ECJ-0EB1A104K [QORVO]
CATV 75 pHEMT Dual RF Amplifier;
| 型号： | ECJ-0EB1A104K |
| 厂家： | 
Qorvo |
| 描述： | CATV 75 pHEMT Dual RF Amplifier 有线电视 |
| 文件： | 总13页 (文件大小：614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
Product Description
The TAT7467E1F is a 75ꢀΩ, fully integrated, single-die
differential RF Amplifier covering medium power
applications in the CATV band. The TAT7467E1F includes
on-chip linearization to improve 3rd order distortion
performance while maintaining low power consumption on
a +5ꢀV supply. It is fabricated using 6 inch GaAs pHEMT
technology to optimize performance and cost.
SOIC-8 Package
Product Features
• 50–1218ꢀMHz Bandwidth
• 75ꢀΩ Impedance
• pHEMT Device Technology
• Meets DOCSIS 3.1 Output Requirements
• +5ꢀV Supply Voltage
Functional Block Diagram
• 380ꢀmA Current Consumption
• On-chip Linearization
• SOIC-8 package
Applications
• Replacement for +5ꢀV SOIC-8 Amplifiers
• Edge QAM Output Stage
• MDU Output
• Distribution Amplifiers
Pin Configuration
• Transmitter Driver Amplifier
Pin No.
1
Label
RFIN A
2
LIN A
LIN B
3
4
RFIN B
5
RFOUTB / VDD
Bias 2
6
7
Bias 1
8
RFOUTA / VDD
RF/DC GND
Ordering Information
Backside Pad
Part No.
Description
TAT7467E1F
TAT7467E1F–EB
75 Ω Dual pHEMT Amplifier
Amplifier Evaluation Board
Standard T/R size = 1000 pieces on a 7” reel
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
Absolute Maximum Ratings
Recommended Operating Conditions
Parameter
Rating
Parameter
Min Typ
+5.0
Max Units
Supply Voltage (VDD)
Storage Temperature
Operating Temperature
+10ꢀV
VDD
V
−60 to +150ꢀ°C
−40 to +85ꢀ°C
IDD (Total EVB current)
Tj for >106 hours MTTF
380
mA
+145
°C
Operation of this device outside the parameter ranges given
above may cause permanent damage.
Electrical performance is measured under conditions noted in
the electrical specifications table. Specifications are not
guaranteed over all recommended operating conditions.
Electrical Specifications
Parameter
Conditions
Min
Typ
Max
Units
MHz
dB
Operational Frequency Range
Gain
50
1218
18
Peak deviation from straight line across full
band.
Gain Flatness
0.75
dB
Noise Figure
4.7
15
16
dB
dB
dB
Input Return Loss
Output Return Loss
EQAM Output Out-of-band
Spurious and Noise for single
channel on a single portꢀ
VOUT = 62ꢀdBmV / ch adjacent,
See Notes 2, 3, and 4
−62
dBc
P1dB
+25
+43
dBm
dBm
dBc
V
OIP3
POUT=+12ꢀdBm / tone, ∆f=10ꢀMHz
Equivalent Harmonics
VDD
See Note 5
-63
5
+5
IDD (Total current of Test Circuit) See Note 7
Bias 2 (Vset range to adjust IDD)
380
mA
V
4
Thermal Resistance θjc
(jct. to case)
14.5
°C/W
Notes:
1. Test conditions unless otherwise noted: 75 Ω impedance, VDD = +5ꢀV, IDD = 380ꢀmA fixed by Vsetꢀ7 from +4ꢀV to +4.7ꢀV, TA = +25°ꢀC
2. Production tested at 66ꢀMHz, 330ꢀMHz, and 990ꢀMHz.
3. Adjacent channel 1 (750ꢀkHz from channel block edge to 6ꢀMHz from channel block edge).
4. Adjacent channel 2 (6ꢀMHz from channel block edge to 12ꢀMHz from channel block edge).
5. Spurious and noise levels in channels coinciding with 2nd harmonic or 3rd harmonic.
6. Recommended application circuit uses active bias described on page 6.
7. Test Circuit, page 3, can be used for evaluation with some variation in IDD when Vset is a fixed voltage between +4 to +4.7ꢀV adjusted by R21.
Variation to IDD may change some performance parameters.
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
TAT7467E1F–EB Evaluation Board (Test Circuit)
L1
R15
+5V
IDD = 380mA
C14
C1
C2
VX
R21
Vset
Adj for IDD = 380mA
C8
L2
C4
C13
Vset
C15
C9
RF INPUT
U1
C5
C18
8
1
C21
L5
R12
Isense
7
2
T2
T1
1
R22
1
2
3
4
5
6
1
2
3
1
2
3
4
5
6
1
2
L
I
N
2
3
C6
B1
B2
R13
R23
6
1
2
3
Vset
Iset=approx 70mA
L4
R14
C7
RF OUTPUT
5
4
C19
C16
9
C10
C3
Backside Paddle
L3
VX
C17
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
Bill of Material–TAT7467E1F
Reference Designator Description
Manufacturer
Part Number
Sil Pad for Heatsink
various
PAD
HEATSINK
BLOCK
Qorvo
U1
TAT7467E1F
PCB
TAT7467E1F Application Board
Panasonic Corp of North America
Panasonic Corp of North America
Panasonic Corp of North America
Murata
C1, C2
CAP, 0402, 0.1uF, 10%, 10V
CAP, 0402, 270 pF, 10%, 50V
ECJ-0EB1A104K
C18, C19
ECJ-0EB1H271K
C5, C6, C7, C13, C14, C17 CAP, 0402, 0.01uF, 10%, 16V, XR7
ECJ-0EB1C103K
C3, C4, C10, C15, C16
CAP, 0402, 0.5pF +/-0.25pF, 50V
RES, 0402, 1.21KꢀΩ, 1%, 1/16W
RES, 0402, 1.5ꢀΩ, 1%, 1/16W
RES, 0402, 750ꢀΩ, 1%, 1/16W
RES, 1206, 1ꢀΩ, 5%
GRM1555C1HR50CZ01D
ERJ-2RKF1211X
Panasonic Corp of North America
Yaego
R12, R13
R22, R23
R14
RC0402FR-071R5L
CRCW0402750RFKED
VISHAY-DALE
R15
Panasonic Corp of North America ERJ-8GEYJ1R0V
Panasonic Corp of North America ERJ-8GEYJ120V
R21
RES, 1206, 12ꢀΩ, 5%, 1/4W
L4
IND, 0402, 5.6nH, 5%, W/W
IND, 0402, 2.7nH, 5%, W/W
IND, 1008, 0.9uH, 10%, 1.3A, Ferrite
IND, 1206, 500nH, 10%, 260mA, Ferrite
Coilcraft, Inc.
Coilcraft, Inc.
0402CS-5N6XJLW
0402CS-2N7XJLW
1008AF-901XKL
L5
L1
Coilcraft, Inc.
Murata
L2, L3
B1, B2
T1, T2
J3
LQH31HNR50K03
BLM15AG601SN1D
TC1-33-75G2+
Bead, Chip Ferrite, 0402, 600ꢀΩ, 300mA Murata
XFMR, SMT, 75ꢀΩ, CD542, 1:1
Header Pin, 2 POS, 0.1”, RA, SMT
Conn, 75ꢀΩ, Edge Launch F
Mini-Circuits
Molex
022-28-8021
J1, J2
Lighthorse Technologies
LTI-FSF55MGT-P-10A-X7
Screw, 4-40, ¼”, Phillips, Pan HD,
SEMS
S1, S2, S3, S4, S5, S6
C8, C9, C21
McMaster-Carr Supply Company 90403A106
Dummy Part
Not Populated Item
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
TAT7467E1F–EB Evaluation Board
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
Application Circuit with Active Bias
L1
R6
+5V
380mA
1
1 VCC
C1
C2
R7
VX
C8
VCC
R15
No Load
5
R8
MMBT2907A
3
E
1.24V
Vcc
-
1
4
3
B
3
Q1
1
+
Vee
2
C
2
1
U3
R10
U1 R11
2
VDRIVE
C13
1
R9
Dual Op Amp
Rail-Rail
C11
LMV431
SOT23-5
C12
ISENSE
C14
C15
C18
RF
INPUT
ACTIVE BIAS
L2
C4
C9
C5
OUTPUT A
1
8
INPUT A
TAT 7467H
U2
L5
C21
T2
T1
1
R12
C6
ISENSE
7
LINA
2
+
-
R22
1
2
3
4
-
1
BIAS1
2
1
L
I
1
2
3
4
2
1
2
B1
N
+
3
6
R23
VDRIVE
C19
TC1-33-75G2+
2
1
LINB
BIAS2
TC1-33-75G2+
R13
B2
C7
L4
4
5
SOIC-8
INPUT B
OUTPUT B
R14
BACKSIDE
PADDLE
C3
C16
C17
L3
RF
OUTPUT
C10
VX
Notes:
1. EVB Nominal IDD current is 380 mA
Bill of Material: Active Bias Section
Reference Designator
U1
Description
Rail-Rail Op-Amp
Manufacturer
On Semi
TI
Part Number
LM7301
U3
Adjustable shunt voltage regulator
General purpose transistor (pnp)
CAP, 0402, 0.1uF, 16V, 10%
CAP, 0402, 10.01uF, 6V, 10%
RES, thick film, 1206, 1ꢀΩ, 5%
LM431
Q1
Various
Various
Various
Various
Various
Various
Various
C1, C2, C8
C11, C12, C13, C14, C15
R6
R7, R8, R9
R10
RES, thick film, 0402, 10.0kꢀΩ, 1/16 W, 1%
RES, thick film, 0402, 5.6kꢀΩ, 1/16 W, 1%
RES, thick film, 0402, 100ꢀΩ, 5%
No Load
R11
R15
L1
IND, High Current, 1008, 0.9uH, 10%
Coilcraft
1008AF-901XKL
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
Performance Plots
Gain
Isolation
24
20
16
12
8
-20
-30
-40
-50
-60
+85°C
+25°C
−40°C
4
0
0
0
250
250
250
500
750
1000
1000
1000
1250
1250
1250
0
250
500
750
1000
1250
Frequency (MHz)
Frequency (MHz)
Input Return Loss
Output Return Loss
0
-10
-20
-30
-40
-50
0
-10
-20
-30
-40
-50
+85°C
+25°C
−40°C
+85°C
+25°C
−40°C
500
750
0
250
500
750
1000
1250
Frequency (MHz)
Frequency (MHz)
Noise Figure
ACPR vs Frequency at Docsis+2
10
8
-60
-64
-68
-72
-76
ACPR1
ACPR2
ACPR3
+85°C
+25°C
−40°C
6
4
2
0
500
750
0
250
500
750
1000
1250
Frequency (MHz)
Frequency (MHz)
Notes:
1. VDD = +5
ꢀV, IDD= 380ꢀmA, TA= +25°ꢀC
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
Typical Performance Plots (cont.)
Harmonics at Docsis+2
OIP3
-60
48
-70
-80
46
44
42
40
-90
-40C
25C
85C
-100
0
200
400
600
800
1000
1200
0
250
500
750
1000
1250
Frequency (MHz)
Frequency (MHz)
P1dB
ACPR1 vs Temperature at Docsis+2
27
26
25
24
23
-62
-66
-70
-74
+85°C
+25°C
−40°C
0
250
500
750
1000
1250
0
200
400
600
800
1000
Frequency (MHz)
Frequency (MHz)
Notes:
1. VDD = +5ꢀV, IDD= 380ꢀmA, TA= +25°ꢀC
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
Pin Configuration and Description
Pin 1 Reference Mark
1
2
3
4
8
7
6
5
RFOUT A/VDD
Bias 1
RFIN
A
LIN A
LIN B
RFIN B
Bias 2
RFOUT B/VDD
Backside pad – RF/DC GND
Pin No.
Label
Description
1
RFINA
RF Input A. DC blocking capacitor required.
Linearizer A. Recommend using 1.21K resistors to ground for optimal on-
chip linearizer current setting.
2
3
LIN A
Linearizer B. Recommend using 1.21K resistors to ground for optimal on-
chip linearizer current setting.
LIN B
4
RFINB
RF Input B. DC blocking capacitor required.
RF Output B. DC blocking capacitor required.
IDD adjust. Set for 380mA, approx. Pin 6 draws approx. 70mA
Output stage common source node. Current sense line for active bias.
RF Output A. DC blocking capacitor required.
Ground Slug
5
RFOUTB / VDD
Bias 2
6
7
Bias 1
8
RFOUTA / VDD
RF/DC GND
Backside Pad
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
Detailed Device Description
The TAT7467E1F is a flexible +5ꢀV differential amplifier for medium power CATV applications. The amplifier of the
TAT7467E1F was specifically designed to work with on-chip linearization to provide 3rd order distortion improvement over
a wide range of RF power levels and across the full CATV bandwidth. Operation of the linearizer will not affect overall gain
by more than 0.7ꢀdB.
For any amplifier bias current, output 3rd order distortion may be improved by adjusting a small bias current of the on-chip
linearization circuit. The Application Schematic shows resistors setting the linearizer currents. Alternate linearizer drive
circuitry is possible; consult Qorvo for discussion.
Bias current may be adjusted with changes to external components making the TAT7467E1F ideal for both input and output
gain stages in an EdgeQAM amplifier line-up. For output stage applications, bias currents of between 300ꢀmA to 400ꢀmA
are recommended. For input stage applications, bias currents of 230ꢀmA to 280ꢀmA are recommended. Active bias circuits,
like the one shown on page 6 of this datasheet, may be used to achieve greater control over the bias current.
The TAT7467E1F is built using a single die, which significantly improves its resulting circuit balance and corresponding 2nd
order distortion performance. For best 2nd order performance, an input balun using a 3rd wire construction may be used to
improve the input phase balance going into the TAT7467E1F.
The TAT7467E1F is packaged in an industry standard SOIC-8 package with a large exposed paddle to enable good heat
flow to a backside heatsink. At the maximum recommended bias current of 400ꢀmA the power consumption will be 2ꢀW. The
TAT7467E1F is fabricated using a mature pHEMT process that has demonstrated outstanding reliability performance on
other Qorvo products. Please use contact information section to consult Qorvo for further information.
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
Package Marking and Dimensions
θ2
θ1
θ2
θ1
PCB Mounting Pattern
Notes:
1. All dimensions are in millimeters. Angles are in degrees.
2. Use 1 oz. copper minimum for top and bottom layer metal.
3. Vias are required under the backside paddle of this device for proper RF/DC grounding and thermal dissipation.
4. We recommend a 0.35mm (#80/.0135") diameter bit for drilling via holes and a final plated thru diameter of 0.25 mm (0.010”).
5. Ensure good package backside paddle solder attach for reliable operation and best electrical performance.
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
TAT7467E1F
CATV 75ꢀΩ pHEMT Dual RF Amplifier
Handling Precautions
Parameter
ESDꢀ–ꢀHuman Body Model (HBM)
Rating Standard
Class 1B
ESDAꢁ/JEDEC JS-001-2012
JEDEC JESD22-C101F
IPC/JEDEC J-STD-020
Caution!
ESD-Sensitive Device
ESDꢀ–ꢀCharged Device Model (HBM) Class C3
MSLꢀ–ꢀMoisture Sensitivity Level
Level 3
Solderability
Compatible with both lead-free (260ꢁ°C maximum reflow temperature) and tin/lead (245ꢁ°C maximum reflow temperature)
soldering processes.
Contact plating: Ni, Pd, & Au
RoHS Compliance
This part is compliant with EU 2002/95/EC RoHS directive (Restrictions on the Use of Certain Hazardous Substances in
Electrical and Electronic Equipment).
•
•
•
•
•
•
Lead Free
Halogen Free (Chlorine, Bromine)
Antimony Free
TBBP-A (C15H12Br402) Free
PFOS Free
SVHC Free
Contact Information
For the latest specifications, additional product information, worldwide sales and distribution locations:
Tel: 1-844-890-8163
Web: www.qorvo.com
Email: customer.support@qorvo.com
Important Notice
The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained
herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained
herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for
Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any
patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by
such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED
HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER
EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical,
life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal
injury or death.
Copyright 2017 © Qorvo, Inc. | Qorvo is a registered trademark of Qorvo, Inc.
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Data Sheet-Rev E, June 5, 2017 | Subject to change without notice
DAT.TAT7467E1F Rev. E
Page 1 of 1
TAT7467E1F Product Datasheet
Revision History
WEBMASTER POSTING
INSTRUCTIONS TO PUBLIC
WEBSITE
ECN#
(Hillsboro
Only)
Rev.
Date
Description of Change
Email*
Info Link 1st page Full Data
Only
only
Sheet
Answer YES in one column
only OR NO** all 3 columns
A
B
12-11-14
02-02-15
90048
90832
Original Documentation (A.Sardar)
No
No
No
No
Yes
Yes
Added active bias circuit and associated BOM, added Pin
Configuration section, updated functional block diagram.
(A. Sardar, C. Blum)
Declare test condition to IDD=380mA for Electrical specs,
limit Vset control range from 4 to 6V for Idd to a 4 to 4.7V
(5V max) to be compatible with 5V active bias application
circuit, referenced test circuit on page 3 to Electrical specs.
Added test conditions to all performance plots, declared
them as typical. Updated package marking & dimensions
per OUT.308, added PCB mounting pattern (T. Cummings)
C
02-23-15
91275
No
No
Yes
Updated data sheet to dual branding. Update package
dimensions and marking. Corrected pin description table.
Pin 1 mislabeled. Added C21 to EVB BOM. Corrected
Functional Block Diagram. Pin 1 mislabeled. Corrected
typos.
D
E
10-08-15
96531
No
No
No
No
Yes
Yes
06-05-17 17-16773 Updated to Qorvo format. Updated EVB BOM. (D.Fun)
CONTROLLED DISTRIBUTION: 03
(Hillsboro Only)
Printed copy of this document is considered an uncontrolled copy; unless control copy designator is identified.
Qorvo, Inc. – Confidential & Proprietary Information Template: FOR-000469 Rev D
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