QPL6216QPCK-01 [QORVO]
High-Linearity SDARS LNA;
| 型号： | QPL6216QPCK-01 |
| 厂家： | 
Qorvo |
| 描述： | High-Linearity SDARS LNA |
| 文件： | 总7页 (文件大小：542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QPL6216Q
®
High-Linearity SDARS LNA
Product Description
The QPL6216Q is a high linearity, ultra-low noise gain block
amplifier in a small 2x2 mm surface-mount package. At 2332
MHz, the amplifier typically provides +36 dBm OIP3. The
amplifier does not require any negative supplies for operation
and can be biased from positive supply rails from 3.3 to 5.25 V.
The device is housed in a lead- free/green/RoHS-compliant
industry-standard 2x2 mm package.
The QPL6216Q uses a high performance E-pHEMT process.
The low noise amplifier contains an internal active bias to
maintain high performance over temperature.
Package: DFN, 8-pin
2.0mm x 2.0mm x 0.85mm
Feature Overview
Tested in accordance with AEC-Q100 Grade 2
High Gain device – Typical value 15.1dB
Ultra-low noise figure, 0.45 dB NF at 2332 MHz
High linearity, +36 dBm Output IP3
Functional Block Diagram
Unconditionally stable
Externally controlled Icq with Vbias
Integrated shutdown control pin
3.3-5.25 V positive supply voltage: −Vgg not required
Applications
SDARS Active Antenna
Ordering Information
PART NUMBER
QPL6216QSB
QPL6216QSQ
QPL6216QSR
QPL6216QTR7
DESCRIPTION
5 PIECE SAMPLE BAG
25 PIECE SAMPLE BAG
100 PIECE 7” REEL
2500 PIECE 7” REEL
QPL6216QPCK-01 EVALUATION BOARD + 5 PC
SAMPLE BAG
Standard T/R Size = 2500 pieces on a reel
Data Sheet REV D
Subject to change without notice
1 of 7
www.qorvo.com
QPL6216Q
®
High-Linearity SDARS LNA
Absolute Maximum Ratings
PARAMETER
RATING
-65 to 150°
+7
UNITS
C
Storage Temperature
Supply Voltage (VDD
)
V
RF Input Power, CW, 50Ω, T = 25°C
+22
dBm
Recommended Operating Conditions
PARAMETER
Supply Voltage (VDD
MIN
TYP
MAX
UNITS
)
+3.3
+3.3
−40
+4.5
+3.6
+5.25
+5.25
+105
+190
V
V
Bias Voltage (Vbias
)
T
°C
°C
CASE
6
T
J
(for >10 hours MTTF)
Electrical Specifications at +25˚C
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operational Frequency Range
Test Frequency
Gain
2320
2332
2330
15.1
9
2345
MHz
MHz
dB
14.3
15.6
Input Return Loss
Output Return Loss
Output P1dB
dB
15
dB
+18.0
+30
+22.5
dBm
Output IP3
Pout=+2 dBm/tone, Δf=1 MHz
+36
dBm
dB
Noise Figure1
0.45
0.65
On state
0
0.63
VDD
V
V
Power Shutdown Control (Pin 6)
Off state (Power down)
1.17
1.8
On state
45
60
3
75
5
mA
mA
µA
2
Current, IDD
Off state (Power down)
Shutdown pin current, I
V
≥ 1.17 V
140
SD
PD
Thermal Resistance, θ
jc
channel to case
62
°C/W
Test conditions unless otherwise noted: VDD = +4.5V, Vbias = +3.6V, Temp =+25°C, 50 Ω system
Note: 1) Noise Figure data has input trace loss de-embedded
2) Icq set by external 2.75K resistor
Data Sheet REV D
Subject to change without notice
2 of 7
www.qorvo.com
QPL6216Q
®
High-Linearity SDARS LNA
Application Schematic
Vbias=3.6V
Vdd=4.5V
Icq
R3
40mA
5.5K
50mA
3.7K
60mA
2.75K
70mA
2.13K
80mA
1.73K
Data Sheet REV D
Subject to change without notice
3 of 7
www.qorvo.com
QPL6216Q
®
High-Linearity SDARS LNA
Pin Configuration and Description
Pin No.
Label
Description
1
Vbias
Sets the Icq bias point for the device.
2
6
RF In
RF Input pin. A DC Block is required.
A high voltage (>1.17V) turns off the device. If the pin is pulled to ground or driven
with a voltage less than 0.63V, then the device will operate under LNA ON state.
Shut Down
RF Output pin. DC bias will also need to be injected through a RF bias
choke/inductor for operation.
7
RF Out / DCBias
3, 4, 5, 8
No electrical connection. Provide grounded land pads for PCB mounting integrity.
NC
RF/DCground. Userecommended via pattern to minimize inductance and
thermal resistance; see PCB Mounting Pattern for suggested footprint.
Backside Paddle
RF/DC GND
Data Sheet REV D
Subject to change without notice
4 of 7
www.qorvo.com
QPL6216Q
®
High-Linearity SDARS LNA
Mechanical Information
Marking: Part number – 6216Q
Trace Code – XXXX
NOTES:
1. All dimensions are in millimeters. Angles are in degrees.
2. Except where noted, this part outline conforms to JEDEC standard MO-220, Issue E (Variation VGGC) for thermally enhanced
plastic very thin fine pitch quad flat no lead package (QFN).
3. Dimension and tolerance formats conform to ASME Y14.4M-1994.
4. The terminal #1 identifier and terminal numbering conform to JESD 95-1 SPP-012.
Data Sheet REV D
Subject to change without notice
5 of 7
www.qorvo.com
QPL6216Q
®
High-Linearity SDARS LNA
PCB Mounting Pattern
NOTES:
1. All dimensions are in millimeters. Angles are in degrees.
2. Use 1 oz. copper minimum for top and bottom layer metal.
3. Vias are required under the backside paddle of this device for proper RF/DC grounding and thermal dissipation. We
recommend a 0.35mm (#80/.0135") diameter bit for drilling via holes and a final plated thru diameter of 0.25 mm (0.10”).
4. Ensure good package backside paddle solder attach for reliable operation and best electrical performance.
Data Sheet REV D
Subject to change without notice
6 of 7
www.qorvo.com
QPL6216Q
®
Product Compliance Information
ESD Sensitivity Ratings
High-Linearity SDARS LNA
Solderability
Compatible with both lead-free (260 °C max. reflow
temperature) and tin/lead (245 °C max. reflow
temperature) soldering processes.
Caution! ESD-Sensitive Device
Package contact plating: NiPdAu
ESD Rating: Class 1B
Value:
Test:
Standard:
Passes ≥ 500 V to < 1000V
Human Body Model (HBM)
JEDEC Standard JESD22-A114
This part is compliant with EU 2002/95/EC RoHS
directive (Restrictions on the Use of Certain
Hazardous Substances in Electrical and Electronic
Equipment).
ESD Rating: Class C3
Value:
Test:
Standard:
Passes ≥1000 V
Charged Device Model (CDM)
JEDEC Standard JESD22-C101
RoHs Compliance
This product also has the following attributes:
Lead Free
Halogen Free (Chlorine, Bromine)
Antimony Free
PFOS Free
SVHC Free
MSL Rating
MSL Rating: Level 1
TBBP-A (C15H12Br402) Free
Test:
Standard:
260°C convection reflow
JEDEC Standard IPC/JEDEC J-STD-020
Contact Information
For the latest specifications, additional product information, worldwide sales and distribution locations:
Tel: 1-844-890-8163
Web: www.qorvo.com
Email: customer.support@qorvo.com
Important Notice
The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes
no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without
notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or
any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether
with regard to such information itself or anything described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH
RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO
SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR
OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or
life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death.
Copyright 2016 © Qorvo, Inc. | Qorvo is a registered trademark of Qorvo, Inc.
Data Sheet REV D
Subject to change without notice
7 of 7
www.qorvo.com
相关型号：
©2020 ICPDF网 联系我们和版权申明