QPL9065 [QORVO]
Ultra Low-Noise 2-Stage Bypass LNA;
| 型号： | QPL9065 |
| 厂家： | 
Qorvo |
| 描述： | Ultra Low-Noise 2-Stage Bypass LNA |
| 文件： | 总12页 (文件大小：3257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Ultra Low-Noise 2-Stage Bypass LNA
Product Description
The QPL9065 is a high-linearity, ultra-low noise 2-stage
gain block amplifier module with a bypass mode
functionality integrated to the second stage in the product.
At 1.95ꢀGHz, the amplifier, under high gain mode, typically
provides 37.5 dB gain, +36 dBm OIP3, and 0.55 dB noise
figure while drawing 160 mA current from a +5ꢀV supply.
The component also provides high performance in the low
gain mode with 17.5 dB gain, 0.55dB noise figure and +33
dBm OIP3 while drawing 70 mA current.
16 Pin 3.5ꢀXꢀ3.5 mm Leadless SMT Package
Product Features
0.45 – 3.8 GHz Operational bandwidth
2nd stage LNA with integrated bypass mode
Ability to turn LNA and bypass mode OFF
Ultra low noise, 0.55 dB at 1.95ꢀGHz
37.5 dB Gain at 1.95ꢀGHz, 17.5 dB in Low Gain Mode
+36 dBm Output IP3 in High Gain Mode
+33 dBm Output IP3 in Low Gain Mode
Positive supply only, +3.3 to +5ꢀV
The QPL9065 uses a high performance E-pHEMT process.
This low noise amplifier contains an internal active bias to
maintain high performance over temperature.
The QPL9065 covers the 0.45ꢀ–ꢀ3.8 GHz frequency band
and is targeted for wireless infrastructure. The QPL9065 is
housed in a 3.5ꢀxꢀ3.5ꢀmm SMT package.
1.8V CMOS TTL logic compatible on pins 5 & 8
Functional Block Diagram
Applications
Base Station Receivers
Tower Mount Amplifiers
Repeaters
Pin 1 Reference Mark
VDD1 GND GND
VDD2
13
16
15
14
FDD-LTE, TDD-LTE, WCDMA
General Purpose Wireless
GND
RF IN
GND
GND
1
2
3
4
GND
12
11
10
9
RF
OUT
GND
GND
5
6
7
8
VPD
NC
GND VBYP
Backside Paddle - RF/DC GND
Ordering Information
Part No.
Description
QPL9065SR
QPL9065TR13
QPL9065PCB401
100 pieces on a 7” reel
2500 pieces on a 13” reel
1.7-2.7GHz Tuned Evaluation Board
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®
Ultra Low-Noise 2-Stage Bypass LNA
Absolute Maximum Ratings
Recommended Operating Conditions
Parameter
Storage Temperature
Rangeꢀ/ꢀValue
−65 to 150
+7
Units
°C
Parameter
Supply Voltage
TCASE
Min
+3.3
−40
Typ
+5.0
Max
+5.25
+105
+169
Units
V
Drain Voltage (VDD
Input Power (CW)
)
V
°C
+22
dBm
Tj at TCASE = 125°C
°C
Electrical specifications are measured under bias, signal and temperature
conditions as specified. Specifications are not guaranteed over all
recommended operating conditions.
Exceeding any one or a combination of the Absolute Maximum
Rating conditions may cause permanent damage to the device.
Extended application of Absolute Maximum Rating conditions to
the device may reduce device reliability.
Electrical Specifications
Test conditions unless otherwise noted: VDD = +5 V, Temp. = +25°C.
Parameter
Operational Frequency Range
Test Frequency
Gain
Conditions
Min
Typ
Max
Units
MHz
MHz
dB
450
3800
1950
37.5
12.5
15
LNAs ON, Bypass OFF
LNAs ON, Bypass OFF
LNAs ON, Bypass OFF
LNAs ON, Bypass OFF
LNAs ON, Bypass OFF
35.5
39.5
0.8
Input Return Loss
Output Return Loss
Noise Figure
dB
dB
0.55
+20.8
dB
Output P1dB
+17.5(1)
+32
dBm
LNAs ON, Bypass OFF,
Pout=+5 dBm/tone, Δf=1 MHz
Output IP3
+36
dBm
LNA1 ON, Bypass ON
LNA1 ON, Bypass ON
LNA1 ON, Bypass ON
LNA1 ON, Bypass ON
LNA1 ON, Bypass ON
Gain
16.2
17.5
11.5
12
19.2
0.8
dB
dB
Input Return Loss
Output Return Loss
Noise Figure
Output P1dB
dB
0.55
+18
dB
+15.8(1)
+30
dBm
LNA1 ON, Bypass ON,
Pout=+5 dBm/tone, Δf=1 MHz
Output IP3
+33
dBm
VIH
1.17
0
3.3
0.63
200
98
V
V
Control Voltage, VPD, VBYP
VIL
LNAs ON, Bypass OFF
LNA1 ON, LNA2 OFF, Bypass ON
LNAs OFF, Bypass OFF
High gain Mode (Channel to case)
Low gain Mode (Channel to case)
80
43
160
70
5
mA
mA
mA
°C/W
°C/W
Current, ID
42
70
Thermal Resistance, θjc
Notes:
1.
P1dB is not measured in production test. This min spec is calculated based on design confidence.
Control Truth Table
VPD VBYP
State
1
0
0
1
0
0
1
1
LNA1 OFF, LNA2 OFF, Bypass OFF
LNA1 ON, LNA2 ON, Bypass OFF
LNA1 ON, LNA2 OFF, Bypass ON
LNA1 OFF, LNA2 OFF, Bypass ON
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®
Ultra Low-Noise 2-Stage Bypass LNA
Typical Performance
Test conditions unless otherwise noted: VDD=+5 V, Temp=+25°C
Typical Values
Units
MHz
dB
Parameter
Frequency
Conditions
900
47.5
17.5
12.5
0.7
1950
37.5
12.7
15.7
0.55
+20.8
2600
3600
28.8
12
Gain
High Gain Mode
High Gain Mode
High Gain Mode
High Gain Mode
High Gain Mode
33
Input Return Loss
Output Return Loss
13.5
12.5
0.65
+20.2
dB
8.2
dB
Noise Figure
Output P1dB
1.1
dBm
dBm
+21.2
+19.7
Pout=+3 dBm/tone, ∆f=1 MHz
Output IP3
+35.6
+36
+34.3
+36
dBm
High Gain Mode
Gain
Low Gain Mode
Low Gain Mode
Low Gain Mode
Low Gain Mode
Low Gain Mode
23.2
14
17.5
11.5
12
15
13.7
25
11.3
12
dB
dB
Input Return Loss
Output Return Loss
Noise Figure
Output P1dB
12
10
dB
0.7
+20
0.55
+18
0.65
+17.3
1.1
dB
+14.5
dBm
Pout=+0 dBm/tone, ∆f=1 MHz
Output IP3
+33
+33
+34.5
+30
dBm
Low Gain Mode
Note: 1) Noise figure data has input trace loss de-embedded.
Switching Speed (1)
VPD VBYP
State
50% of Vctrl to 90% of RF 50% of Vctrl to 10% of RF
Units
-40ꢀ°C
25ꢀ°C 105ꢀ°C -40ꢀ°C
25ꢀ°C 105ꢀ°C
0
0 LNA1 ON, LNA2 ON, Bypass OFF
1 LNA1 OFF, LNA2 OFF, Bypass ON
0 LNA1 ON, LNA2 ON, Bypass OFF
1 LNA1 ON, LNA2 OFF, Bypass ON
1 LNA1 OFF, LNA2 OFF, Bypass ON
1 LNA1 ON, LNA2 OFF, Bypass ON
730
400
292
190
360
300
176
880
780
303
730
740
275
640
690
256
1
0
ns
276
214
0
1
0
Note:
1. To achieve the fast switching speed listed, placement of R10 and C9 are critical. Refer to pg. 4 for EVB schematic and BOM.
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®
Ultra Low-Noise 2-Stage Bypass LNA
QPL9065 Evaluation Board (1.7 – 2.7 GHz tuned)
J3 VDD
R1
0
C6
C12
(0603)
J8 GND
0.1 uF
C5
J3 VDD
R2
0
C12
C8
C7
C8
C7
100 pF
U1
C6
C5
0.1 uF
100 pF
L2
L5
L5
C2
R9
J2
J1
L3
U1
16
15
14
13
VDD1
VDD2
1
12
L1
C9
C2
R9
C11
J1
RFOUT
11
J2
RFIN
2
C10
R5
RF
Input
RF
Output
10pF
3
4
10
9
C1
R10
R7
L4
VPD1
5
VPD2
6
VBYP
8
7
R3
0
J5 VBYP
R7
0
J4 VPD
C3
C4
J6
J7
R5
0
C10
10 pF
C11
10 pF
See Evaluation Board PCB Information section for PCB material and stack-up.
Bill of Material – QPL9065 Evaluation Board
Reference Des.
Value Description
n/a
Manuf.
Qorvo
Part Number
1123139
n/a
PCB
U1
n/a
2-Stage Bypass LNA
RES, 0402, +/-5%, 1/16W
RES, 0402, +/-5%, 1/16W
CAP, 0402, +/-0.1pF, 50V, C0G
RES, 0402, +/-5%, 1/16W
IND, 0402, +/-0.1nH, 1000mA
IND, 0402, +/-2%, 700mA
CAP, 0402, +/-5%, 50V
CAP, 0402, 20%, 16V, Y5V
CAP, 0201, 2%, 50V
Qorvo
QPL9065
R1, 2, 3, 5, 7
0 Ω
Various
Various
Murata
various
Murata
Murata
Various
Various
Murata
Various
various
Murata
Coilcraft
R10
39K
C1
0.5 pF
5.1 Ω
1.5 nH
6.8 nH
100 pF
0.1 uF
10 pF
4.7 uF
10 pF
2.2 nH
18 nH
GJM1555C1HR50BB01D
R9
L1
LQP15MN1N5B02D
LQG15HS6N8J02
L4
C2, 3, 4, 5, 7
C6, 8
C9
GRM0335C1H100GA01
C12
CAP, 0603, 20%, 10V, Y5V
CAP, 0402, 2%, 50V
C10, 11
L2
IND, 0402, +/-0.2nH, 1000mA
IND, 0603, 5%
LQW15AN2N2C10
0603CS-18NXJL
L5
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®
Ultra Low-Noise 2-Stage Bypass LNA
Performance Plots
Test conditions unless otherwise noted: VDD = +5 V, Temp.=ꢁ+25ꢁ°C
Gain vs. Frequency
Input Return Loss vs. Frequency
High Gain Mode
Output Return Loss vs. Frequency
High Gain Mode
50
45
40
35
30
25
20
15
10
0
0
-5
High Gain Mode
-5
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
-10
-15
-20
-10
-15
-20
−40ꢀ°C
+25ꢀ°C
+105ꢀ°C
1000
2000
3000
4000
5000
5000
5000
1000
2000
3000
Frequency (MHz)
4000
5000
1000
2000
3000
Frequency (MHz)
4000
5000
5000
2700
Frequency (MHz)
|S12| vs. Frequency
Gain vs. Frequency
Input Return Loss vs. Frequency
-40
-50
-60
-70
-80
-90
20
15
10
5
0
-5
Low Gain Mode
High Gain Mode
Low Gain Mode
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
-10
-15
-20
−40ꢀ°C
+25ꢀ°C
+105ꢀ°C
-40degC
+25degC
+105degC
0
1000
1000
2000
3000
4000
2000
3000
4000
5000
1000
2000
3000
Frequency (MHz)
4000
Frequency (MHz)
Frequency (MHz)
Output Return Loss vs. Frequency
|S12| vs. Frequency
OIP3 vs. Frequency
0
-5
-20
-25
-30
-35
-40
-45
-50
38
37
36
35
34
33
32
31
30
Low Gain Mode
Low Gain Mode
High Gain Mode
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
-10
-15
-20
-40degC
+25degC
+105degC
1000
2000
3000
4000
1000
2000
3000
4000
5000
1700
1900
2100
2300
2500
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
OIP3 vs. Frequency
P1dB vs. Frequency
40
37
34
31
28
25
24
23
22
21
20
19
18
17
16
15
High Gain Mode
Low Gain Mode
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
25
1700
1900
2100
2300
2500
2700
1700
1900
2100
2300
2500
2700
Frequency (MHz)
Frequency (MHz)
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®
Ultra Low-Noise 2-Stage Bypass LNA
Performance Plots
Test conditions unless otherwise noted: VDD = +5 V, Temp.=ꢁ+25ꢁ°C
P1dB vs. Frequency
Noise Figure vs Frequency
High Gain Mode
Noise Figure vs Frequency
Low Gain Mode
20
19
18
17
16
15
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Low Gain Mode
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
1700
1900
2100
2300
2500
2700
1700
1900
2100
2300
2500
2700
1700
1900
2100
2300
2500
2700
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
K-factor vs Frequency
10
9
8
7
6
5
4
3
2
1
0
High Gain Mode
Low Gain Mode
0
1
2
3
4
5
6
7
8 9
Frequency (GHz)
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®
Ultra Low-Noise 2-Stage Bypass LNA
Performance Plots (VDD = 3.3V)
Test conditions unless otherwise noted: VDD = +3.3 V, IDD(high gain mode) = 98mA, IDD(low gain mode) = 55mA, Temp.=ꢁ+25ꢁ°C
Gain vs. Frequency
Input Return Loss vs. Frequency
High Gain Mode
Output Return Loss vs. Frequency
High Gain Mode
50
45
40
35
30
25
20
15
10
0
-5
0
High Gain Mode
-5
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
+105ꢀ°C
-10
-15
-20
-10
-15
-20
+25ꢀ°C
−40ꢀ°C
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
1000
2000
3000
4000
5000
1000
2000
3000
4000
5000
5000
2700
2700
1000
2000
3000
4000
5000
5000
2700
2700
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
Gain vs. Frequency
Input Return Loss vs. Frequency
Output Return Loss vs. Frequency
20
15
10
5
0
-5
0
-5
Low Gain Mode
Low gain Mode
Low Gain mode
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
-10
-15
-20
-10
-15
-20
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
0
1000
2000
3000
4000
5000
1000
2000
3000
4000
1000
2000
3000
Frequency (MHz)
4000
Frequency (MHz)
Frequency (MHz)
OIP3 vs Frequency
OIP3 vs Frequency
P1dB vs Frequency
35
34
33
32
31
30
29
28
30
29
28
27
26
25
24
23
22
18
17
16
15
14
High Gain Mode
High Gain Mode
Low Gain Mode
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
+105ꢀ°C
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
+25ꢀ°C
−40ꢀ°C
1500
1700
1900
2100
2300
2500
2700
1500
1700
1900
2100
2300
2500
1500
1700
1900
2100
2300
2500
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
P1dB vs Frequency
Noise Figure vs Frequency
Noise Figure vs Frequency
15
14
13
12
11
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
High Gain Mode
Low Gain Mode
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
Low Gain Mode
+105ꢀ°C
+105ꢀ°C
+25ꢀ°C
−40ꢀ°C
+25ꢀ°C
−40ꢀ°C
1500
1700
1900
2100
2300
2500
2700
1500
1800
2100
2400
1500
1800
2100
2400
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
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®
Ultra Low-Noise 2-Stage Bypass LNA
QPL9065 Evaluation Board (2.7 – 3.7 GHz Reference Design)
J3 VDD
R1
0
C6
C12
(0603)
J8 GND
0.1 uF
C5
J3 VDD
R2
C12
0
C8
C7
C8
C7
C6
C5
100 pF
U1
0.1 uF
100 pF
L2
L5
L5
C2
C9
J2
J1
L1
U1
16
15
14
13
VDD1
VDD2
C11
1
12
J1
L3
RFOUT
11
J2
RFIN
R9
C2
C10
2
3
4
RF
Input
27 pF
C13
0.7 pF
RF
Output
10
9
R5
R7
VPD1
5
VPD2
6
VBYP
8
7
R3
0
J5 VBYP
R7
0
J4 VPD
J6
C3
C4
J7
R5
0
C10
10 pF
C11
10 pF
See Evaluation Board PCB Information section for PCB material and stack-up.
Performance Plots – 2.7-3.7 GHz
Test conditions unless otherwise noted: VDD=+5 V, IDD = 65mA, Temp=+25°C. Noise figure data has input trace loss de-embedded.
Gain vs. Frequency
Return Loss vs. Frequency
OIP3 vs. Pout/tone
40
35
30
25
20
15
10
5
0
-5
42
40
38
36
34
32
High Gain Mode
-10
-15
-20
Input Return Loss (High Gain Mode)
2700 MHz
2900 MHz
3500 MHz
3700 MHz
Input Return Loss (Low Gain Mode)
Output Return Loss (High Gain Mode)
Output return Loss (Low Gain Mode)
Low Gain Mode
High Gain Mode
0
2700
2900
3100
3300
3500
3700
2700
2900
3100
3300
3500
3700
3
4
5
6
7
Frequency (MHz)
Frequency (MHz)
Pout/Tone (dBm)
OIP3 vs. Pout/tone
P1dB vs Frequency
Noise Figure vs Frequency
35
33
31
29
27
25
23
21
19
17
15
13
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Low Gain Mode
2.7 GHz
2.9 GHz
3.2 GHz
3.4 GHz
3.5 GHz
3.6 GHz
3.7 GHz
High Gain Mode
Low Gain Mode
0
1
2
3
2700
2900
3100
3300
3500
3700
2700
2900
3100
3300
3500
3700
Pout/Tone (dBm)
Frequency (MHz)
Frequency (MHz)
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®
Ultra Low-Noise 2-Stage Bypass LNA
QPL9065 Evaluation Board (700 – 1000 MHz Reference Design)
J3 VDD
R1
0
C6
C12
(0603)
J8 GND
0.1 uF
C5
J3 VDD
R2
0
C12
C8
C7
C8
C7
100 pF
U1
C6
C5
0.1 uF
100 pF
L2
18nH
L5
18nH
L5
C2
R9
J2
J1
C14
L6
U1
16
15
14
13
VDD1
VDD2
C2
C11
1
12
100pF
L6
J1
C14
R9
RFOUT
11
J2
RFIN
C9
0
2
3
4
C10
3.3 nH
RF
Input
100pF
5.1
RF
10
9
L7
10 nH
R10
39K
Output
R5
R7
VPD1
5
VPD2
6
VBYP
8
7
R3
0
J5 VBYP
R7
0
J4 VPD
C3
J6
C4
J7
R5
0
C10
10 pF
C11
10 pF
See Evaluation Board PCB Information section for PCB material and stack-up.
Performance Plots – 700 – 1000 MHz Reference Design
Test conditions unless otherwise noted: VDD=+5 V, IDD = 65mA, Temp=+25°C.
Gain vs. Frequency
Input Return Loss vs. Frequency
Output Return Loss vs. Frequency
50
45
40
35
30
25
20
0
-5
0
-5
-10
-15
-20
-10
-15
-20
Low Gain Mode
High Gain Mode
Low Gain Mode
High Gain Mode
Low Gain Mode
High Gain Mode
700
750
800
850
900
950
1000
700
750
800
850
900
950
1000
700
750
800
850
900
950
1000
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
OIP3 vs. Pout/tone
P1dB vs Frequency
Noise Figure vs Frequency
38
36
34
32
30
28
26
23
22
21
20
19
18
17
1.0
0.8
0.6
0.4
0.2
0.0
700 MHz High Gain Mode
700 MHz Low Gain Mode
800 MHz High Gain Mode
800 MHz Low Gain Mode
900 MHz High Gain Mode
900 MHz Low Gain Mode
1000 MHz High Gain Mode
1000 MHz Low Gain Mode
High Gain Mode
Low Gain Mode
High Gain Mode
Low Gain Mode
-1
0
1
2
3
4
5
700
800
900
1000
700
800
900
1000
Pout/Tone (dBm)
Frequency (MHz)
Frequency (MHz)
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®
Ultra Low-Noise 2-Stage Bypass LNA
Pin Configuration and Description
Pin 1 Reference Mark
VDD1 GND GND
VDD2
13
16
15
14
GND
RF IN
GND
GND
1
2
3
4
GND
12
11
10
9
RF
OUT
GND
GND
5
6
7
8
VPD
NC
GND VBYP
Backside Paddle - RF/DC GND
Pin No.
1,3,4,7,9,10,12,14,15
Label
GND
Description
RF/DC Ground pin.
2
RFin
RF input pin. Internally DC blocked.
Power Down control for LNAs. Refer to truth table on pg. 2. Voltage should not
exceed 3V. Recommended that VDD1 is applied before the control voltage.
No internal connection but can be grounded for mounting integrity.
5
6
8
VPD
NC
Bypass mode enable pin for LNA2. Refer to truth table on pg. 2. Voltage should
not exceed 3V. Recommended that VDD1 is applied before the control voltage.
VBYP
11
13
16
RFout
VDD2
RF output pin. External DC block required.
Supply voltage pin for LNA2.
VDD1
Supply voltage pin for LNA1.
RF/DC Ground. Follow recommended via pattern and ensure good solder
attach for best thermal and electrical performance.
Backside Paddle
RF/DC GND
Evaluation Board PCB Information
Qorvo PCB 1123139 Material and Stack-up
1 oz. Cu top layer
Rogers 4350B
0.010"
1 oz. Cu inner layer
0.062" ± 0.006"
Finished Board
Thickness
Rogers 4450F
Rogers 4350B
1 oz. Cu inner layer
1 oz. Cu bottom layer
0.010"
50 ohm line dimensions: width = .020”, spacing = .032”
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®
Ultra Low-Noise 2-Stage Bypass LNA
Package Marking and Dimensions
QPL9065
Trace Code
Notes:
1. All dimensions are in millimeters. Angles are in degrees.
2. Dimension and tolerance formats conform to ASME Y14.4M-1994.
3. The terminal #1 identifier and terminal numbering conform to JESD 95-1 SPP-012.
PCB Mounting Pattern
3.85 REF
1.66
0.05 typ
0.75
PIN1
(16X) 0.53 x 0.25
0.25
1.69
0.30 x45°
0.75
0.25
2.20
3.85 REF
0.18
2.20
RECOMMENDED
LAND PATTERN
RECOMMENDED
LAND PATTERN MASK
Notes:
1. All dimensions are in millimeters. Angles are in degrees.
2. Use 1 oz. copper minimum for top and bottom layer metal.
3. Vias are required under the backside paddle of this device for proper RF/DC grounding and thermal dissipation.
4. Do not remove or minimize via hole structure in the PCB. Thermal and RF grounding is critical.
5. We recommend a 0.35mm (#80/.0135") diameter bit for drilling via holes and a final plated thru diameter of 0.25 mm (0.10”).
6. Ensure good package backside paddle solder attach for reliable operation and best electrical performance.
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®
Ultra Low-Noise 2-Stage Bypass LNA
Handling Precautions
Parameter
Rating
Standard
ESDꢀ–ꢀHuman Body Model (HBM)
Class 1C
ESDAꢁ/ꢁJEDEC JS-001-2012
JEDEC JESD22-C101F
IPC/JEDEC J-STD-020
Caution!
ESD-Sensitive Device
ESDꢀ–ꢀCharged Device Model (CDM) Class C3
MSLꢀ–ꢀMoisture Sensitivity Level
Level 3
Solderability
Compatible with both lead-free (260°C max. reflow temp.) and tin/lead (245°C max. reflow temp.) soldering processes.
Solder profiles available upon request.
Contact plating: Electrolytic Plated Au over Ni
RoHS Compliance
This part is compliant with the 2011/65/EU RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and
Electronic Equipment) as amended by Directive 2015/863/EU. This product also has the following attributes:
Product uses RoHS Exemption 7c-I to meet RoHS Compliance requirements.
Halogen Free (Chlorine, Bromine)
Antimony Free
TBBP-A (C15H12Br402) Free
PFOS Free
SVHC Free
Contact Information
For the latest specifications, additional product information, worldwide sales and distribution locations:
Web: www.qorvo.com
Tel: 1-844-890-8163
Email: customer.support@qorvo.com
For technical questions and application information:
Email: appsupport@qorvo.com
Important Notice
The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained
herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained
herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for
Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any
patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by
such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED
HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER
EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical,
life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal
injury or death.
Copyright 2017 © Qorvo, Inc. | Qorvo is a registered trademark of Qorvo, Inc.
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