FM24C04A-GTR [RAMTRON]
Memory Circuit, 512X8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8;
| 型号： | FM24C04A-GTR |
| 厂家： | 
RAMTRON INTERNATIONAL CORPORATION |
| 描述： | Memory Circuit, 512X8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8 光电二极管 |
| 文件： | 总12页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FM24C04A
4Kb FRAM Serial Memory
Features
4K bit Ferroelectric Nonvolatile RAM
Low Power Operation
•
5V operation
•
•
•
•
•
Organized as 512 x 8 bits
•
•
150 µA Active Current (100 kHz)
10 µA Standby Current
High Endurance 1012 Read/Writes
45 Year Data Retention
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Industry Standard Configuration
•
•
Industrial Temperature -40° C to +85° C
8-pin “Green”/RoHS SOIC (-G)
Fast Two-wire Serial Interface
•
•
Up to 1 MHz maximum bus frequency
Direct hardware replacement for EEPROM
Description
Pin Configuration
The FM24C04A is a 4-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 45 years
while eliminating the complexities, overhead, and
system level reliability problems caused by EEPROM
and other nonvolatile memories.
1
8
7
6
5
NC
A1
A2
VDD
WP
2
3
4
SCL
SDA
VSS
Unlike serial EEPROMs, the FM24C04A performs
write operations at bus speed. No write delays are
incurred. Data is written to the memory array in the
cycle after it has been successfully transferred to the
device. The next bus cycle may commence
immediately.
Pin Names
A1-A2
SDA
Function
Device Select Address 1 and 2
Serial Data/Address
Serial Clock
These capabilities make the FM24C04A ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with reduced overhead for the system.
SCL
WP
Write Protect
VSS
Ground
VDD
Supply Voltage 5V
Ordering Information
The FM24C04A provides substantial benefits to users
of serial EEPROM, yet these benefits are available in
a hardware drop-in replacement. The FM24C04A is
available in industry standard 8-pin packages using a
two-wire protocol. The specifications are guaranteed
over an industrial temperature range of -40°C to
+85°C.
FM24C04A-G
“Green”/RoHS 8-pin SOIC
FM24C04A-GTR
“Green”/RoHS 8-pin SOIC,
Tape & Reel
FM24C04A-S *
FM24C04A-STR * 8-pin SOIC, Tape & Reel
* End of life. Last time buy June 2009.
8-pin SOIC
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Rev. 3.2
Feb. 2011
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FM24C04A
Address
Latch
128 x 32
FRAM Array
Counter
8
Serial to Parallel
Converter
SDA
SCL
Data Latch
WP
A1
Control Logic
A2
Figure 1. Block Diagram
Pin Description
Pin Name
I/O
Pin Description
A1-A2
Input
Address 1-2: The address pins set the device select address. The device address value
in the 2-wire slave address must match the setting of these two pins. These pins are
internally pulled down.
SDA
I/O
Serial Data/Address: This is a bi-directional pin used to shift serial data and addresses
for the two-wire interface. It employs an open-drain output and is intended to be wire-
OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt
trigger for noise immunity and the output driver includes slope control for falling
edges. A pull-up resistor is required.
SCL
WP
Input
Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of
the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL
input also incorporates a Schmitt trigger input for improved noise immunity.
Write Protect: When WP is high, the entire array is write-protected. When WP is low,
all addresses may be written. This pin is internally pulled down.
Input
-
NC
VDD
VSS
No connect
Supply Supply Voltage: 5V
Supply Ground
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Feb. 2011
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FM24C04A
Overview
Two-wire Interface
The FM24C04A is a serial FRAM memory. The
memory array is logically organized as 512 x 8 and is
accessed using an industry standard two-wire
interface. Functional operation of the FRAM is
similar to serial EEPROMs. The major difference
between the FM24C04A and a serial EEPROM with
the same pinout relates to its superior write
performance.
The FM24C04A employs a bi-directional two-wire
bus protocol using few pins and little board space.
Figure 2 illustrates a typical system configuration
using the FM24C04A in a microcontroller-based
system. The industry standard two-wire bus is
familiar to many users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24C04A is always a slave device.
Memory Architecture
When accessing the FM24C04A, the user addresses
512 locations each with 8 data bits. These data bits
are shifted serially. The 512 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish other devices), a page address,
and a word address. The word address consists of 8-
bits that specify one of 256 addresses. The page
address is 1-bit and so there are 2 pages each of 256
locations. The complete address of 9-bits specifies
each byte address uniquely.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions:
Start, Stop, Data bit, and Acknowledge. Figure 3
illustrates the signal conditions that specify the four
states. Detailed timing diagrams are shown in the
Electrical Specifications section.
Most functions of the FM24C04A either are
controlled by the two-wire interface or are handled
automatically by on-board circuitry. The memory is
read or written at the speed of the two-wire bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation will be
complete. This is explained in more detail in the
interface section below.
VDD
Rmin = 1.8 K
Rmax = tR/Cbus
Ω
Microcontroller
SDA SCL
FM24C04A
A1 A2
SDA SCL
FM24C64
A0 A1 A2
Users can expect several obvious system benefits
from the FM24C04A due to its fast write cycle and
high endurance as compared with EEPROM.
However there are less obvious benefits as well. For
example in a high noise environment, the fast-write
operation is less susceptible to corruption than an
EEPROM since it is completed quickly. By contrast
an EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Figure 2. Typical System Configuration
Note that the FM24C04A contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to ensure
that VDD is within data sheet tolerances to prevent
incorrect operation.
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FM24C04A
Figure 3. Data Transfer Protocol
not acknowledge the data to deliberately end an
operation. For example, during a read operation, the
FM24C04A will continue to place data onto the bus
as long as the receiver sends acknowledges (and
clocks). When a read operation is complete and no
more data is needed, the receiver must not
acknowledge the last byte. If the receiver
acknowledges the last byte, this will cause the
FM24C04A to attempt to drive the bus on the next
clock while the master is sending a new command
such as a Stop command.
Stop Condition
A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations must end with a Stop condition.
If an operation is pending when a stop is asserted, the
operation will be aborted. The master must have
control of SDA (not a memory read) in order to assert
a Stop condition.
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
ready the FM24C04A for a new operation.
Slave Address
The first byte that the FM24C04A expects after a
start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the device select, the page of memory to be
accessed, and a bit that specifies if the transaction is
a read or a write.
If during operation the power supply drops below the
specified VDD minimum, the system should issue a
Start condition prior to performing another operation.
Bits 7-4 are the device type and should be set to
1010b for the FM24C04A. The device type allows
other types of functions to reside on the 2-wire bus
within an identical address range. Bits 3-2 are the
device address. If bit 3 matches the A2 pin and bit 2
matches the A1 pin, the device will be selected. Bit
1 is the page select. It specifies the 256-byte block
of memory that is targeted for the current operation.
Bit 0 is the read/write bit. A 0 indicates a write
operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change state while SCL is high.
Acknowledge
The Acknowledge takes place after the 8th data bit has
been transferred in any transaction. During this state
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
No-Acknowledge and the operation is aborted.
Word Address
After the FM24C04A (as receiver) acknowledges
the slave ID, the master will place the word address
on the bus for a write operation. The word address is
the lower 8-bits of the address to be combined with
the 1-bit page select to specify exactly the byte to be
written. The complete 9-bit address is latched
internally.
The receiver could fail to acknowledge for two
distinct reasons. First, if a byte transfer fails, the No-
Acknowledge ends the current operation so that the
device can be addressed again. This allows the last
byte to be recovered in the event of a communication
error. Second and most common, the receiver does
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Feb. 2011
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FM24C04A
Memory Operation
The FM24C04A is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24C04A and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Figure 4. Slave Address
No word address occurs for a read operation. Reads
always use the lower 8-bits that are held internally in
the address latch and the 9th address bit is part of the
slave address. Reads always begin at the address
following the previous access. A random read address
can be loaded by doing a write operation as explained
below.
Write Operation
All writes begin with a slave address then a word
address. The bus master indicates a write operation
by setting the LSB of the Slave address to a 0. After
addressing, the bus master sends each byte of data to
the memory and the memory generates an
acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
from 1FFh to 000h.
After transmission of each data byte, just prior to the
acknowledge, the FM24C04A increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (1FFh) is reached, the address latch will
roll over to 000h. There is no limit to the number of
bytes that can be accessed with a single read or write
operation.
Unlike other nonvolatile memory technologies, there
is no write delay with FRAM. The entire memory
cycle occurs in less time than a single bus clock.
Therefore any operation including read or write can
begin immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write is complete is unnecessary and
will always return a done condition.
Data Transfer
After all address information has been transmitted,
data transfer between the bus master and the
FM24C04A can begin. For a read operation the
FM24C04A will place 8 data bits on the bus then wait
for an acknowledge. If the acknowledge occurs, the
next sequential byte will be transferred. If the
acknowledge is not sent, the read operation is
concluded. For a write operation, the FM24C04A will
accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most
significant bit) first.
An actual memory array write occurs after the 8th
data bit is transferred. It will be complete before the
acknowledge is sent. Therefore if the user desires to
abort a write without altering the memory contents,
this should be done using a start or stop condition
prior to the 8th data bit. The FM24C04A needs no
page buffering.
Pulling write protect high will disable writes to the
entire array. The FM24C04A will not acknowledge
data bytes that are applied to the device when write
protect is asserted. In addition, the address counter
will not increment if writes are attempted. Pulling
WP low (VSS) will deactivate this feature.
Figures 5 and 6 illustrate single-byte and multiple-
byte writes.
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FM24C04A
Start
S
Address & Data
Word Address
Stop
By Master
Slave Address
0
A
A
Data Byte
A
P
By FM24C04A
Acknowledge
Figure 5. Byte Write
Start
S
Address & Data
Stop
By Master
Slave Address
0
A
Word Address
A
Data Byte
A
Data Byte
A
P
By FM24C04A
Acknowledge
Figure 6. Multiple Byte Write
attempts to read out additional data onto the bus. The
four valid methods are as follows.
Read Operation
There are two basic types of read operations. They are
current address read and selective address read. For
current address reads, the FM24C04A uses the internal
address latch to supply the lower 8 address bits. In a
selective read, the user performs a procedure to set
these lower address bits to a specific value.
1. The bus master issues a no-acknowledge in the
9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
the preferred method.
2. The bus master issues a no-acknowledge in the
9th clock cycle and a start in the 10th.
3. The bus master issues a stop in the 9th clock
cycle. Bus contention may result.
Current Address & Sequential Read
The FM24C04A uses an internal latch to supply the
lower 8 address bits for a read operation. A current
address read uses the existing value in the address
latch as a starting place for the read operation. This is
the address immediately following that of the last
operation.
4. The bus master issues a start in the 9th clock
cycle. Bus contention may result.
If the internal address reaches 1FFh, it will wrap
around to 000h on the next read cycle. Figures 7 and
8 show the proper operation for current address and
sequential reads.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. The page
select bit in the slave address specifies the block of
memory that is used for the read operation. After the
acknowledge, the FM24C04A will begin shifting out
data from the current address. The current address is
the bit from the slave address combined with the 8 bits
that were in the internal address latch.
Selective (Random) Read
A simple technique allows a user to select a random
address location as the starting point for a read
operation. This involves using the first two bytes of
a write operation to set the internal address byte
followed by subsequent read operations.
To perform a selective read, the bus master sends
out the slave address with the LSB set to 0. This
specifies a write operation. According to the write
protocol, the bus master then sends the word address
byte that is loaded into the internal address latch.
After the FM24C04A acknowledges the word
address, the bus master issues a start condition. This
simultaneously aborts the write operation and allows
the read command to be issued with the slave
address LSB set to a 1. The operation is now a
current address read. See Figure 9.
Beginning with the current address, the bus master can
read any number of bytes. Thus, a sequential read is
simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented. Each time the bus master
acknowledges
a
byte, this indicates that the
FM24C04A should read out the next sequential byte.
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
most likely create a bus contention as the FM24C04A
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FM24C04A
No
Start
S
Address
Acknowledge
By Master
Stop
Slave Address
1
A
Data Byte
Data
1
P
By FM24C04A
Acknowledge
Figure 7. Current Address Read
No
Acknowledge
Start
S
Address
Acknowledge
By Master
Stop
Slave Address
1
A
Data Byte
A
Data Byte
1
P
By FM24C04A
Acknowledge
Data
Figure 8. Sequential Read
No
Address
Acknowledge
Start
Start
S
Address
Acknowledge
A
By Master
Stop
S
Slave Address
0
A
Word Address
A
Slave Address
1
A
Data Byte
Data Byte
1 P
By FM24C04A
Acknowledge
Data
Figure 9. Selective (Random) Read
defined by A8-A2. Each access causes an endurance
cycle for a row. Endurance is virtually unlimited. At
3000 accesses per second to the same segment, it will
take more than 10 years to reach the endurance limit.
Endurance
Internally, a FRAM operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for each read or write cycle. The FRAM architecture
is based on an array of rows and columns. Rows are
Rev. 3.2
Feb. 2011
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FM24C04A
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
Ratings
-1.0V to +7.0V
-1.0V to +7.0V
and VIN < VDD+1.0V *
-55°C to + 125°C
300° C
VDD
VIN
Power Supply Voltage with respect to VSS
Voltage on any signal pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (JEDEC Std JESD22-A114-B)
- Machine Model (JEDEC Std JESD22-A115-A)
Package Moisture Sensitivity Level
3kV
300V
MSL-1
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of
this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device
reliability.
DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified)
Symbol
VDD
IDD
Parameter
Main Power Supply
VDD Supply Current
@ SCL = 100 kHz
@ SCL = 400 kHz
@ SCL = 1000 kHz
Min
Typ
Max
Units
Notes
4.5
5.0
5.5
V
1
115
400
800
150
500
µA
µA
µA
µA
µA
µA
V
1000
ISB
ILI
ILO
VIL
VIH
VOL
Standby Current
1
10
2
3
3
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
@ IOL = 3 mA
±1
±1
0.3 VDD
VDD + 0.5
-0.3
0.7 VDD
V
0.4
V
RIN
Input Resistance (WP, A2,A1)
For VIN = VIL (max)
For VIN = VIH (min)
50
1
5
4
KΩ
MΩ
V
VHYS
Input Hysteresis
0.05 VDD
Notes
1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.
3.
VIN or VOUT = VSS to VDD. Does not apply to WP, A2, A1 pins.
4. This parameter is periodically sampled and not 100% tested.
5. The input pull-down circuit is strong (50KΩ) when the input voltage is below VIL and much weaker (1MΩ)
when the input voltage is above VIH.
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FM24C04A
AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V, CL = 100 pF unless otherwise specified)
Symbol Parameter Min Max Min Max Min Max Units Notes
fSCL
tLOW
tHIGH
tAA
SCL Clock Frequency
0
4.7
4.0
100
0
1.3
0.6
400
0
0.6
0.4
1000
kHz
Clock Low Period
µs
Clock High Period
SCL Low to SDA Data Out Valid
µs
µs
3
0.9
0.55
tBUF
Bus Free Before New
Transmission
4.7
1.3
0.5
µs
tHD:STA
tSU:STA
Start Condition Hold Time
Start Condition Setup for Repeated
Start
4.0
4.7
0.6
0.6
0.25
0.25
µs
µs
tHD:DAT
tSU:DAT
tR
Data In Hold
0
250
0
100
0
100
ns
ns
ns
ns
µs
ns
Data In Setup
Input Rise Time
1000
300
300
300
300
100
1
1
tF
Input Fall Time
tSU:STO
Stop Condition Setup
Data Output Hold
(from SCL @ VIL)
Noise Suppression Time Constant
on SCL, SDA
4.0
0
0.6
0
0.25
0
tDH
tSP
50
50
50
ns
Notes : All SCL specifications as well as Start and Stop conditions apply to both read and write operations.
This parameter is periodically sampled and not 100% tested.
1
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5V)
Symbol
CI/O
Parameter
Input/output capacitance (SDA)
Input capacitance
Max
8
6
Units
pF
pF
Notes
1
1
CIN
Notes
This parameter is periodically sampled and not 100% tested.
1
AC Test Conditions
Input Pulse Levels
0.1 VDD to 0.9 VDD
10 ns
Input rise and fall times
Input and output timing levels
0.5 VDD
Equivalent AC Load Circuit
5.5V
1700
Ω
Output
100 pF
Rev. 3.2
Feb. 2011
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FM24C04A
Diagram Notes
All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read
and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional
relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.
Read Bus Timing
tHIGH
tR
tSP
tF
tSP
tLOW
SCL
SDA
1/fSCL
tSU:SDA
tHD:DAT
tSU:DAT
tBUF
tDH
tAA
Stop Start
Acknowledge
Start
Write Bus Timing
tHD:DAT
SCL
tSU:DAT
tAA
tHD:STA
tSU:STO
SDA
Stop Start
Acknowledge
Start
Data Retention (VDD = 4.5V to 5.5V, +85° C)
Parameter
Data Retention
Min
45
Units
Years
Notes
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Feb. 2011
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FM24C04A
Mechanical Drawing
8-pin SOIC (JEDEC Standard MS-012 variation AA)
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
Legend:
XXXX= part number, P= package type
LLLLLLL= lot code
XXXXXXX-P
LLLLLLL
RICYYWW
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM24C04A, “Green” SOIC package, Year 2004, Work Week 39
FM24C04A-G
A40003G1
RIC0439
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Feb. 2011
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FM24C04A
Revision History
Revision
1.0
Date
Summary
7/26/02
7/31/03
3/17/04
3/9/05
Preliminary
2.0
Changed to Production status.
2.1
3.0
Added “green” packaging option. Changed input leakage spec to 1uA.
Changed Data Retention spec. Added ESD and package MSL ratings.
Modified note 3 (input leakage) in DC table. Updated package drawing.
Updated rev numbering and footer. Removed applications section.
Added tape and reel ordering information. Added last time buy notice on –S
ordering number.
3.1
3.2
5/14/2009
2/18/2011
Not Recommended for New Designs. Alternative: FM24C04B.
Rev. 3.2
Feb. 2011
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