SM16M72ALDT-7.5 [RAMTRON]
Synchronous DRAM Module, 16MX72, 4.5ns, CMOS, DIMM-168;
| 型号： | SM16M72ALDT-7.5 |
| 厂家： | 
RAMTRON INTERNATIONAL CORPORATION |
| 描述： | Synchronous DRAM Module, 16MX72, 4.5ns, CMOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总15页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
168-pin Low Profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
Features
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
•
•
JEDEC Standard 168-pin SDRAM DIMM
Low Latency 166 MHz Modules (2:2:2)
1
Vss
DQ0
DQ1
DQ2
DQ3
Vdd
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Vss
DNU
S2#
85
86
Vss
DQ32
DQ33
DQ34
DQ35
Vdd
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Vss
CKE0
S3#
2
•
•
•
CAS Latency = 2
RAS to CAS Delay = 2
Precharge Delay = 2
3
87
4
DQMB2
DQMB3
DNU
Vdd
88
DQMB6
DQMB7
RFU
Vdd
5
89
•
Sustained Random Burst Reads (same bank access)
6
90
•
•
1-1-1-1 at 66MHz (CL = 1)
2-1-1-1 at 166MHz (CL = 2)
7
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
91
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
•
•
•
•
•
•
•
Early Auto-Precharge and Pipelined Row Activation
Hidden Auto-Refresh (4K, 64ms)
Fully Synchronous Operation
On-board Serial Presence Detect (SPD)
Unbuffered 168-pin DIMM
8
NC
92
NC
9
NC
93
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB2
94
CB6
CB3
95
CB7
Vss
96
Vss
Single 3.3V ± 0.3V Power Supply
Low Profile for IU Rack Mount Systems
DQ9
DQ10
DQ11
DQ12
DQ13
Vdd
DQ16
DQ17
DQ18
DQ19
Vdd
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vdd
DQ48
DQ49
DQ50
DQ51
Vdd
98
99
Description
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
The Enhanced SDRAM (ESDRAM) DIMMs are low
latency, high performance memory modules of 32, 64, and
128 MByte capacities, and are organized x64 or x72 bits
wide. These DIMMs are 100% pin, function, and timing
compatible with JEDEC standard 168-pin SDRAM DIMMs.
The 32 MByte and 64 MByte DIMMs employ a single
physical bank of memory while the 128 MByte DIMMs are
built as two physical banks. Within each physical bank of
memory are four logical banks, which are accessed through
the use of BA0 and BA1 (pins 122 and 39). All control,
access, and data input signals are registered into each of the
ESDRAM components through use of an external clock,
CK0-CK3.
DQ20
NC
DQ52
NC
DQ14
DQ15
CB0
CB1
Vss
DQ46
DQ47
CB4
NC
NC
CKE1
Vss
NC
CB5
Vss
DQ21
DQ22
DQ23
Vss
Vss
DQ53
DQ54
DQ55
Vss
NC
NC
NC
NC
Vdd
Vdd
WE#
DQMB0
DQMB1
S0#
DQ24
DQ25
DQ26
DQ27
Vdd
CAS#
DQMB4
DQMB5
S1#
DQ56
DQ57
DQ58
DQ59
Vdd
ESDRAM DIMMs provide pipeline burst SRAM
performance up to 66 MHz and nearly the same at bus
speeds up to 166 MHz. This performance is achieved using
JEDEC superset features including early auto-precharge and
pipelined row activation. The ESDRAM also supports
hidden auto-refresh.
DNU
Vss
RAS#
Vss
DQ28
DQ29
DQ30
DQ31
Vss
DQ60
DQ61
DQ62
DQ63
Vss
A0
A1
All ESDRAM DIMMs operate from a 3.3V power supply,
and all inputs and outputs are LVTTL compatible. The
DIMM has a low 1.15-inch height to support IU rack mount
system requirements. See the ESDRAM component data
sheet for
specifications and functional operation.
A2
A3
A4
A5
A6
A7
A8
CK2
A9
CK3
a more detailed discussion of ESDRAM
A10/AP
BA1
Vdd
NC
BA0
NC
WP
A11
SA0
SDA
SCL
Vdd
SA1
Vdd
CK1
SA2
CK0
Vdd
RFU
Vdd
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 1 of 15
168-pin Low profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
Pin Descriptions
Symbol
CK(0:3)
Type
Input
Input
Function
Clocks: All SDRAM input signals are sampled on the positive edge of CK.
CKE(0:1)
Clock Enables: CKE activate (high) or deactivate (low) the CK signals. Deactivating the clock initiates the
Power-Down and Self-Refresh operations (all banks idle), or Clock Suspend operation. CKE is synchronous until
the device enters Power-Down and Self-Refresh modes where it is asynchronous until the mode is exited.
S(0:3)#
Input
Input
Chip Select: S# enables (low) or disables (high) the command decoder. When the command decoder is
disabled, new commands are ignored but previous operations continue.
RAS#, CAS#,
WE#
Command Inputs: Sampled on the rising edge of CK, these inputs define the command to be executed.
Bank Addresses: These inputs define to which of the 4 banks a given command is being applied.
BA(0:1)
A(0:11)
Input
Input
Address Inputs: A0-A11 define the row address during the Bank Activate command. A0-A8 define the column
address during Read and Write commands. A10/AP invokes the Auto-precharge operation. During manual
Precharge commands, A10/AP low specifies a single bank precharge while A10/AP high precharges all banks.
The address inputs are also used to program the Mode Register.
DQ(0:63)
Input/
Output
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these pins and must be set-up
and held relative to the rising edge of clock. For Read cycles, the device drives output data on these pins after
the CAS latency is satisfied.
DQMB(0:7)
CB(0:7)
Input
Data I/O Mask Inputs: DQMB0-7 inputs mask write data (zero latency) and acts as a synchronous output enable
(2-cycle latency) for read data.
Input/
Output
Supply
ECC Check Bits
VDD
VSS
Power Supply: +3.3 V
Ground
Supply
SDA
Input/
Output
Serial Presence-Detect Data: SDA is a bi-directional pin used to transfer addresses and data into
and data out of the presence-detect portion of the module.
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize the presence detect data transfer to
and from the module
SA(0:2)
WP
Input
Input
Presence-Detect Address Inputs: These pins are used to configure the presence detect device.
Serial Presence Detect Write Protect: Active high inhibits writes to the SPD EEPROM. WP must be driven low
for normal read/write operations.
RFU
DNU
NC
-
-
-
Reserved for Future Use: These pins should be left unconnected.
Do not use.
No connect - open pin.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 2 of 15
Revision 1.0
168-pin Low Profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
32MB DIMM Functional Block Diagram – SM4M64ALDT
S0#
Clock Wiring
CK0
CK1
CK2
CK3
2 SDRAM+15 pf
Termination
2 SDRAM+15 pf
Termination
DQMB0
U0
U2
DQMB1
DQ(15:0)
10
CK0,2
SDRAMs
DQMB4
DQMB5
Clock Termination
10
DQ(47:32)
CK1,3
10 pf
S2#
DQMB2
DQMB3
SCL
SA0-2
SDA
U1
U3
Serial PD
WP
47K
DQ(31:16)
DQMB6
DQMB7
BA0
BA1
BA0 SDRAM U0-3
BA1 SDRAM U0-3
A0-A11 SDRAM U0-3
Vdd SDRAM U0-3
Vss SDRAM U0-3
DQ(63:48)
A0-A11
Vdd
Vss
RAS#
CAS#
WE#
RAS# SDRAM U0-3
CAS# SDRAM U0-3
WE# SDRAM U0-3
CKE0 SDRAM U0-3
CKE0
Note:
All DQ resistor values are 10 ohms.
All CK resistor values are 10 ohms.
U0-U3 are SM2604T.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 3 of 15
168-pin Low profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
64MB DIMM Functional Block Diagram – SM8M64ALDT
S0#
Clock Wiring
CK0
4 SDRAM+3.3 pf
Termination
4 SDRAM+3.3 pf
Termination
DQMB0
DQ(7:0)
DQMB4
DQ(39:32)
CK1
CK2
CK3
U0
U1
U4
U5
10
CK0,2
SDRAMs
DQMB1
DQ(15:8)
DQMB5
DQ(47:40)
Clock Termination
10
CK1,3
10 pf
S2#
DQMB2
DQMB6
DQ(55:48)
U2
U3
U6
U7
SCL
SA0-2
SDA
DQ(23:16)
Serial PD
WP
47K
DQMB3
DQ(31:24)
DQMB7
DQ(63:56)
BA0
BA1
BA0 SDRAM U0-7
BA1 SDRAM U0-7
A0-A11 SDRAM U0-7
Vdd SDRAM U0-7
Vss SDRAM U0-7
A0-A11
Vdd
Vss
RAS#
CAS#
WE#
RAS# SDRAM U0-7
CAS# SDRAM U0-7
WE# SDRAM U0-7
CKE SDRAM U0-7
CKE0
Note:
All DQ resistor values are 10 ohms.
All CK resistor values are 10 ohms.
U0-U7 are SM2603T.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 4 of 15
Revision 1.0
168-pin Low Profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
64MB ECC DIMM Functional Block Diagram – SM8M72ALDT
S0#
Clock Wiring
CK0
CK1
CK2
CK3
5 SDRAM
DQMB0
DQ(7:0)
DQMB4
DQ(39:32)
Termination
4 SDRAM+3.3 pf
Termination
U0
U1
U2
U5
U6
10
CK0,2
SDRAMs
DQMB1
DQMB5
DQ(47:40)
DQ(15:8)
Clock Termination
10
CK1,3
10 pf
CB(7:0)
SCL
SA0-2
SDA
Serial PD
WP
47K
S2#
DQMB2
DQMB6
DQ(55:48)
U3
U4
U7
U8
DQ(23:16)
BA0
BA1
BA0 SDRAM U0-8
BA1 SDRAM U0-8
A0-A11 SDRAM U0-8
Vdd SDRAM U0-8
Vss SDRAM U0-8
A0-A11
Vdd
DQMB3
DQ(31:24)
DQMB7
DQ(63:56)
Vss
RAS#
CAS#
WE#
RAS# SDRAM U0-8
CAS# SDRAM U0-8
WE# SDRAM U0-8
CKE SDRAM U0-8
CKE0
Note:
All DQ resistor values are 10 ohms.
All CK resistor values are 10 ohms.
U0-U8 are SM2603T.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 5 of 15
168-pin Low profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
128MB DIMM Functional Block Diagram – SM16M64ALDT
S0#
S1#
Clock Wiring
CK0
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
CK1
CK2
CK3
DQMB0
DQ(7:0)
DQMB4
DQ(39:32)
U0
U1
U8
U9
U4
U5
U12
U13
10
CK(0:3)
SDRAMs
DQMB1
DQ(15:8)
DQMB5
DQ(47:40)
SCL
SDA
Serial PD
SA0-2
WP
47K
S2#
S3#
BA0
BA1
BA0 SDRAM U0-15
BA1 SDRAM U0-15
A0-A11 SDRAM U0-15
Vdd SDRAM U0-15
Vss SDRAM U0-15
DQMB2
DQMB6
DQ(55:48)
U2
U3
U10
U11
U6
U7
U14
U15
DQ(23:16)
A0-A11
Vdd
Vss
DQMB3
DQ(31:24)
DQMB7
DQ(63:56)
RAS#
CAS#
WE#
RAS# SDRAM U0-15
CAS# SDRAM U0-15
WE# SDRAM U0-15
CKE0
CKE1
CKE SDRAM U0-7
CKE SDRAM U8-15
Note:
All DQ resistor values are 10 ohms.
All CK resistor values are 10 ohms.
U0-U15 are SM2603T.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 6 of 15
Revision 1.0
168-pin Low Profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
128MB ECC DIMM Functional Block Diagram – SM16M72ALDT
S0#
S1#
Clock Wiring
CK0
CK1
CK2
CK3
5 SDRAM
5 SDRAM
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
DQMB0
DQ(7:0)
DQMB4
DQ(39:32)
U0
U1
U2
U9
U5
U6
U14
U15
10
CK(0:3)
SDRAMs
DQMB1
DQMB5
U10
U11
DQ(15:8)
DQ(47:40)
SCL
SDA
Serial PD
SA0-2
WP
47K
Note:
DQ(15:8)
SDRAM U11 DQM input
is wired to DQMB5.
BA0
BA1
BA0 SDRAM U0-17
BA1 SDRAM U0-17
A0-A11 SDRAM U0-17
Vdd SDRAM U0-17
Vss SDRAM U0-17
S2#
S3#
A0-A11
Vdd
Vss
DQMB2
DQMB6
U3
U4
U12
U13
U7
U8
U16
U17
DQ(23:16)
DQ(55:48)
RAS#
CAS#
WE#
RAS# SDRAM U0-17
CAS# SDRAM U0-17
WE# SDRAM U0-17
DQMB3
DQ(31:24)
DQMB7
CKE0
CKE1
CKE SDRAM U0-8
CKE SDRAM U9-17
DQ(63:56)
Note:
All DQ resistor values are 10 ohms.
All CK resistor values are 10 ohms.
U0-U17 are SM2603T.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 7 of 15
168-pin Low profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
Electrical Characteristics
Absolute Maximum Ratings
Description
Symbol
VDD
Value
Power Supply Voltage
-1V to +4.6V
Voltage on any Pin with Respect to Ground
Operating Temperature (ambient)
Storage Temperature
VIN, VOUT
TA
-0.5V to +4.6V
0°C to +70°C
-55°C to +125°C
TBD
Tstg
Power Dissipation
PD
DC Output Current (I/O pins)
IOUT
50mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these, or any other conditions above those listed in the operational section of the
specification, is not implied. Exposure to conditions at absolute maximum ratings for extended periods may affect device reliability.
DC Operating Conditions (TA = 0°C to 70°C)
Symbol
VDD
VIH
Parameter
Supply Voltage
Min
3.0
2.0
-0.3
-
Typical
Max
3.6
Units
V
Notes
3.3
Input High Voltage
3.3
VDD + 0.3
0.8
V
VIL
Input Low Voltage
0.0
V
II(L)
Input Leakage Current
-
-
-
-
±1
µA
µA
V
IO(L)
VOH
VOL
Output Leakage Current
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = +4mA)
-
±1
2.4
0.0
VDD
0.4
V
Capacitance (TA = 25°C, f = 1MHz, VDD = 3.3V ±0.3V, not 100% tested)
Symbol
Parameter
32MB
non-ECC
32
64MB
non-ECC
128MB
non-ECC
Units
pF
ECC
57
ECC
CIn1
Input Capacitance (BA1, BA0, A0-
11, RAS, CAS,WE)
52
92
102
CIn2
CIn3
CIn4
CIn5
CIn6
CI/O1
CI/O2
Input Capacitance (S0 - S3)
Input Capacitance (CK0 - CK3)
Input Capacitance (CKE0, CKE1)
Input Capacitance (DQMB0-7)
Input Capacitance (SCL, SA0-2)
I/O Capacitance (SDA)
18
30
32
14
14
14
10
27
33
52
14
14
14
10
32
36
57
14
14
14
10
27
33
52
19
14
14
16
32
36
57
19
14
14
16
pF
pF
pF
pF
pF
pF
pF
I/O Capacitance (DQ0-63, CB0-7)
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 8 of 15
Revision 1.0
168-pin Low Profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
AC Characteristics (TA = 0°C to 70°C)
1. An initial pause of 200µs is required after power-up, then a Precharge All Banks command must be given followed by a minimum
of eight Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the VTT = 1.4V crossover point.
VTT
tT
VIH
VTT
VIL
Clock
RT = 50 ohm
tSETUP tHOLD
Z0 = 50 ohm
Output
Input
CLOAD = 50pF
tOH
tAC
tLZ
VTT
Output
AC Output Load Circuit
3. The transition time is measured between VIH and VIL (or between VIH and VIL).
4. AC measurements assume tT = 1ns.
5. In addition to meeting the transition rate specification, the clock and CKE must transition VIH and VIL (or between VIH and VIL) in
a monotonic manner.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 9 of 15
168-pin Low profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
AC Operating Conditions (TA = 0°C to 70°C)
Clock and Clock Enable Parameters
Symbol
Parameter
-6
-7.5
Units
Notes
Min
6.0
12
2.4
5
Max
Min
7.5
15
2.8
6
Max
tCK2
tCK1
Clock Cycle Time, CL = 2, 3
Clock Cycle Time, CL = 1
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tCKH2, tCKL2 Clock High & Low Times, CL=2, 3
tCKH1, tCKL1 Clock High & Low Times, CL=1
-
-
1
1
-
-
tCKES
tCKEH
tCKSP
Clock Enable Set-Up Time
1.5
0.8
1.5
-
-
1.5
0.8
1.5
-
-
Clock Enable Hold Time
-
-
CKE Set-Up Time (Power down mode)
Transition Time (Rise and Fall)
-
-
tT
2
3
Notes:
1. Assumes clock rise and fall times are equal to 1ns. If rise or fall time exceeds 1ns, other AC timing parameters must be compensated by an
additional [(trise+tfall)/2-1] ns.
Common Parameters
Symbol
Parameter
-6
-7.5
Units
Notes
Min
1.5
0.8
12
30
18
12
12
6
Max
Min
1.5
0.8
15
Max
tCS
Command and Address Set-Up Time
Command and Address Hold Time
RAS to CAS Delay Time
-
-
ns
ns
tCH
-
-
tRCD
tRC
tRAS
tRP
-
-
ns
Bank Cycle Time
-
37.5
22.5
15
-
ns
Bank Active Time
120K
120K
ns
Precharge Time
-
-
-
-
-
-
-
-
ns
tRRD
tCCD
tMRD
Bank to Bank Delay Time (Alt. Bank)
CAS to CAS Delay Time (Same Bank)
Mode Register Set to Active Delay
15
ns
7.5
2
ns
2
CLK
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 10 of 15
Revision 1.0
168-pin Low Profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
Read and Write Parameters
Symbol
Parameter
-6
-7.5
Units
Notes
Min
-
Max
Min
-
Max
tAC3
tAC2
tAC1
tOH3
tOH2
tOH1
tLZ
Clock Access Time, CL = 3
Clock Access Time, CL = 2
Clock Access Time, CL = 1
Data Output Hold Time (CL=3)
Data Output Hold Time (CL=2)
Data Output Hold Time (CL=1)
Data Output to Low-Z Time
Data Output to High-Z Time (CL=2, 3)
Data Output to High-Z Time (CL=1)
DQM Data Output Disable Time
Data Input Set-Up Time
4.3
4.5
ns
ns
1,2
1,2
1,2
-
4.6
-
4.8
-
10.5
-
11
ns
2.0
2.3
3.0
0
-
2.0
2.3
3.0
0
-
ns
-
-
ns
-
-
ns
-
-
ns
tHZ2
tHZ1
tDQZ
tDS
-
4.6
-
4.8
ns
3
3
-
7.0
-
7.5
ns
2
-
-
-
-
-
-
2
-
-
-
-
-
-
CLK
ns
1.5
0.8
6.0
20.0
0
1.5
0.8
7.5
22.5
0
tDH
Data Input Hold Time
ns
tDPL
tDAL
Data Input to Precharge
ns
Data Input to ACTV/Refresh
Data Write Mask Latency
ns
tDQW
CLK
Notes:
1. Access time is measured at 1.4V (LVTTL) at max clock rate for the CAS latency specified. See AC Test Load.
2. Access time is based on a clock rise time of 1ns. If clock rise time is longer than 1ns, then (trise/2-0.5) ns must be added to the access time.
3. Referenced to the time at which the output achieves an open circuit condition.
Refresh Parameters
Symbol
Parameter
-6
-7.5
Units
Notes
Min
-
Max
64
Min
-
Max
64
-
tREF
Refresh Period
Self Refresh Exit Time
ms
ns
1,2
3
tSREX
2CLK+tRC
2CLK+tRC
Notes:
1. 4096 cycles.
2. Any time that the refresh period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to “wake up” the device.
3. Self-Refresh exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self-Refresh Exit is not
completed until tRC is satisfied once the Self-Refresh Exit command is registered.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 11 of 15
168-pin Low profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
Serial Presence Detect (SPD) for ESDRAM DIMMs
32MB
64MB
128MB
32MB
64MB
128MB
Byte Description
** Hex Code **
0
1
2
3
4
5
6
Number of bytes written into EEPROM
128
256
SDRAM
12
8
1
x64
128
256
SDRAM
12
9
1
x64
x72
128
256
SDRAM
12
9
2
x64
x72
80
08
04
0C
08
01
40
80
80
08
04
0C
09
02
40
48
00
01
60
43
00
02
80
08
00
08
01
8F
04
07
01
01
00
07
60
46
30
2A
0C
0C
0C
12
10
15
08
15
08
00
01
12
46
58
Total number of SPD bytes
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of Module Banks
Module Data Width
08
04
0C
09
01
40
48
00
01
60
43
00
02
80
08
00
08
01
8F
04
07
01
01
00
07
60
46
30
2A
0C
0C
0C
x64
x72
7
8
Module Data Width (cont’d)
Voltage Interface Levels
0
0
0
00
01
60
43
00
LVTTL
6.0 ns
4.3 ns
LVTTL
6.0 ns
4.3 ns
--- Non-parity ---
--- ECC ---
--- 15.625us / Self ---
LVTTL
6.0 ns
4.3 ns
9
10
11
Cycle Time at max CAS Latency
SDRAM Clock Access Time
DIMM config (non-parity, parity, ECC)
12
13
14
Refresh Rate and Type
Primary SDRAM Width
Error Checking Data Width
80
10
00
x16
N/A
x8
N/A
x8
1 clk
x8
N/A
x8
x64
x72
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Min. CAS-to-CAS Delay (tCCD)
Burst Lengths Supported
Number of Banks on SDRAM Device
CAS Latencies Supported
CS Latency
1 clk
1 clk
01
8F
04
07
01
01
00
07
60
46
30
2A
0C
0C
0C
12
08
15
08
15
08
00
01
12
44
--- 1,2,4,8,Full Pg ---
4
1,2,3
0
4
4
1,2,3
0
1,2,3
0
0
Write Latency
0
0
SDRAM Module Attributes
SDRAM Device Attributes
Min. Clock Cycle Time at CL=2
Clock Access Time at CL=2 (tAC2)
Min. Clock Cycle Time at CL=1
Clock Access Time at CL=1 (tAC1)
Min. Row Precharge Time (tRP)
Min. Row-to-Row Delay (tRRD)
Min. RAS-to-CAS Delay (tRCD)
Min. RAS Pulse Width (tRAS)
Density of each bank on module
Cmd/Addr input set-up time
Cmd/Addr input hold time
Data input set-up time
--- Unbuffered ---
+/-10% Vdd, Precharge All
6 ns
6 ns
4.6 ns
12 ns
10.5 ns
12 ns
12 ns
12 ns
18 ns
32MB
6 ns
4.6 ns
12 ns
10.5 ns
12 ns
12 ns
12 ns
18 ns
64MB
1.5 ns
0.8 ns
1.5 ns
0.8 ns
-
4.6 ns
12 ns
10.5 ns
12 ns
12 ns
12 ns
18 ns
64MB
12
10
15
08
15
08
00
01
Data input hold time
36-60 Superset Information
-
-
61
62
63
Superset Information (cont’d)
SPD Rev.
Checksum for bytes 0-62
ESDRAM defined for Code=01
1.2
-
12
45
57
non-ECC
ECC
-
-
-
-
64-71 JEDEC ID code
Enhanced Memory Systems
-
7F32FFFFFFFFFFFF
72
Manufacturing Location
xxxx
xxxx
xxxx
xxxx
xxxx
rrrr
yyww
ssss
00
xxxx
xxxx
xxxx
rrrr
yyww
ssss
00
73-90 Manufacturer's Part #
x64
x72
SM4M64ALDT SM8M64ALDT SM16M64ALDT
SM8M72ALDT SM16M72ALDT
91,92 PCB Rev. Code
93,94 Manufacturing Date
95-98 Assembly Serial #
99-125 Manufacturer's Specific Data
126 Intel specification frequency
-
rrrr
yyww
ssss
00
yyww code
serial number
open
100MHz
64
64
64
127 Intel specification CL and clock support
128-255 Open for Customer Use
-
-
-
-
-
-
AF
00
AF
00
FF
00
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 12 of 15
Revision 1.0
168-pin Low Profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
Mechanical Drawing
168 - pin
Low Profile DIMM
FRONT VIEW
5.250 (133.35)
TYP
0.090 (2.29) TYP
0.050 (1.27) R (2X)
+
.079 (2.00) R
(2x)
0.130 (3.30) TYP
+
+
1.158 (29.41)
0.118 (3.00)
(2X)
TYP
0.700 (17.78)
TYP
0.118 (3.00) TYP
0.250 (6.35) TYP
1.660 (42.16)
0.128 (3.25)
0.118 (3.00)
.050 (1.27)
TYP pitch
.040 (1.02)
TYP pad width
(2X)
0.118 (3.00)
TYP
pin 1 (pin 85 on backside)
pin 84 (pin 168 on backside)
0.039 (1.00)R
(2X)
2.625 (66.68)
4.550 (115.57)
0.097 (2.47) MAX
0.144 (3.67) MAX
Dimensions: inches (mm)
0.055 (1.40)
0.045 (1.14)
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 13 of 15
168-pin Low profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
Revision Log
Revision
Date
Summary of Changes
1.0
3/16/01
First Draft
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 14 of 15
Revision 1.0
168-pin Low Profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
Ordering Information
Maximum
Power
Supply
Operating
Frequency
(MHz)
Part Number
Capacity
I/O Width
I/O Type
Package
SM4M64ALDT-6
SM4M64ALDT-7.5
SM8M64ALDT-6
SM8M64ALDT-7.5
SM8M72ALDT-6
SM8M72ALDT-7.5
SM16M64ALDT-6
SM16M64ALDT-7.5
SM16M72ALDT-6
SM16M72ALDT-7.5
32 MB
32 MB
64 MB
64 MB
64 MB
64 MB
128 MB
128 MB
128 MB
128 MB
x64
x64
x64
x64
x72
x72
x64
x64
x72
x72
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
168-pin DIMM
168-pin DIMM
168-pin DIMM
168-pin DIMM
168-pin DIMM
168-pin DIMM
168-pin DIMM
168-pin DIMM
168-pin DIMM
168-pin DIMM
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
166
133
166
133
166
133
166
133
166
133
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 15 of 15
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