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SM3603T-7.5 [RAMTRON]

Synchronous DRAM, 8MX8, 4.6ns, CMOS, PDSO54, TSOP2-54;
SM3603T-7.5
型号： SM3603T-7.5
厂家： RAMTRON INTERNATIONAL CORPORATION    RAMTRON INTERNATIONAL CORPORATION
描述：

Synchronous DRAM, 8MX8, 4.6ns, CMOS, PDSO54, TSOP2-54

时钟 动态存储器 光电二极管 内存集成电路
文件： 总10页 (文件大小：108K)
中文：  中文翻译
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64Mbit – High Speed SDRAM  
Data Sheet  
8Mx8, 4Mx16 HSDRAM  
Features  
Description  
•
•
•
•
JEDEC Standard PC-133 SDRAM  
Fast 4.6 ns CL3 Clock Access Time  
Fast 13.75 ns CL1 Clock Access Time (-7.5F)  
Low Latency Operation (3:2:2 @ 133 MHz)  
The Enhanced Memory Systems SM3603 and SM3604 High-  
Speed SDRAM (HSDRAM) devices are high performance  
versions of the proposed JEDEC PC-133 SDRAM. While  
compatible with standard SDRAM, they provide the faster  
clock access time (4.6 ns), shorter random access latency  
(34.6 ns), and fast bank cycle time (52.5 ns) needed to  
improve system stability, capacity, and performance in  
systems operating at 133 MHz and higher bus speeds. The  
HSDRAM is ideal for any high performance system  
including PCs, workstations, servers, communications  
switches, DSP systems, 3-D graphics, and embedded  
computers.  
•
•
•
CAS Latency = 3  
RAS to CAS Delay = 2  
Precharge Delay = 2  
•
•
•
•
•
Fast Random Access Time (34.6 ns)  
Fast Random Cycle time (52.5 ns)  
Programmable Burst length (1, 2, 4, 8, full page)  
Programmable CAS Latency (1, 2, 3)  
Low Power suspend, Self Refresh, and Power  
Down Modes Supported  
•
•
•
4K Refresh / 64 ms  
Single 3.3V ± 5% Power Supply  
54-pin TSOP-II (0.8mm pin pitch)  
Block Diagram (4Mx16 shown)  
BANK A  
BANK B  
BANK C  
BANK D  
BA1  
BA0  
A(11:0)  
4K rows x  
256 col x  
16 bits  
4K rows x  
256 col x  
16 bits  
4K rows x  
256 col x  
16 bits  
4K rows x  
256 col x  
16 bits  
SENSE AMPLIFIERS  
COLUMN DECODER  
SENSE AMPLIFIERS  
COLUMN DECODER  
SENSE AMPLIFIERS  
COLUMN DECODER  
SENSE AMPLIFIERS  
COLUMN DECODER  
Data I/O Buffers  
DQ(15:0)  
CLK  
CKE  
/CS  
/RAS  
/CAS  
/WE  
COMMAND  
DECODER  
and  
TIMING  
GENERATOR  
UDQM,  
LDQM  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Revision 1.1  
Page 1 of 10  
64Mbit – High Speed SDRAM  
8Mx8, 4Mx16 HSDRAM  
Data Sheet  
Pin Assignments (Top View)  
8Mx8  
4Mx16  
VDD  
DQ0  
VDD  
NC  
VDD  
DQ0  
VDD  
DQ1  
DQ2  
VSS  
DQ3  
DQ4  
VDD  
DQ5  
DQ6  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
VSS  
VSS  
2
DQ15 DQ7  
3
VSS  
VSS  
NC  
4
DQ14  
DQ1  
VSS  
5
DQ13 DQ6  
6
VDD  
VDD  
NC  
NC  
DQ2  
VDD  
NC  
7
DQ12  
8
DQ11 DQ5  
9
VSS  
VSS  
NC  
54 PIN TSOP-II  
400 x 875 mils  
0.8 mm pitch  
10  
11  
DQ10  
DQ9  
DQ3  
DQ4  
VSS  
NC  
VSS  
DQ7  
12  
13  
43  
42  
VDD  
DQ8  
VDD  
NC  
VDD  
VDD  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
VSS  
NC  
VSS  
NC  
NC LDQM  
/WE  
/CAS  
/RAS  
/CS  
/WE  
/CAS  
/RAS  
/CS  
UDQM DQM  
CLK  
CKE  
NC  
A11  
A9  
CLK  
CKE  
NC  
A11  
A9  
BA0  
BA1  
BA0  
BA1  
A10/AP A10/AP  
A8  
A8  
A0  
A1  
A0  
A1  
A7  
A7  
A6  
A6  
A2  
A2  
A5  
A5  
A3  
A3  
A4  
A4  
VDD  
VDD  
VSS  
VSS  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Page 2 of 10  
Revision 1.1  
64Mbit – High Speed SDRAM  
Data Sheet  
8Mx8, 4Mx16 HSDRAM  
Pin Descriptions  
Symbol  
CLK  
Type  
Function  
Input  
Input  
Clocks: All SDRAM input signals are sampled on the positive edge of CLK.  
CKE  
Clock Enable: CKE activate (high) or deactivate (low) the CLK signals. Deactivating the  
clock initiates the Power-Down and Self-Refresh operations (all banks idle), or Clock  
Suspend operation. CKE is synchronous until the device enters Power-Down and Self-  
Refresh modes where it is asynchronous until the mode is exited.  
CS#  
Input  
Chip Select: CS# enables (low) or disables (high) the command decoder. When the  
command decoder is disabled, new commands are ignored but previous operations  
continue.  
RAS#, CAS#,  
WE#  
Input  
Input  
Input  
Command Inputs: Sampled on the rising edge of CLK, these inputs define the command  
to be executed.  
BA1, BA0  
Bank Addresses: These inputs define to which of the 4 banks a given command is being  
applied.  
A0-A11  
Address Inputs: A0-A11 define the row address during the Bank Activate command. A0-  
A8 define the column address during Read and Write commands. A10/AP invokes the  
Auto-precharge operation. During manual Precharge commands, A10/AP low specifies a  
single bank precharge while A10/AP high precharges all banks. The address inputs are  
also used to program the Mode Register.  
DQ0-DQ15  
Input/  
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these  
pins and must be set-up and held relative to the rising edge of clock. For Read cycles, the  
device drives output data on these pins after the CAS latency is satisfied.  
Output  
DQM,  
UDQM,  
LDQM  
Input  
Data I/O Mask Inputs: DQM inputs mask write data (zero latency) and acts as a  
synchronous output enable (2-cycle latency) for read data.  
VDD  
VSS  
NC  
Supply  
Supply  
-
Power Supply: +3.3 V  
Ground  
No connect - open pin.  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Revision 1.1  
Page 3 of 10  
64Mbit – High Speed SDRAM  
8Mx8, 4Mx16 HSDRAM  
Data Sheet  
Electrical Characteristics  
Absolute Maximum Ratings  
Description  
Symbol  
VDD  
Value  
-1V to +4.6V  
-0.5V to +4.6V  
0°C to +70°C  
-55°C to +125°C  
1.0 W  
Power Supply Voltage  
Voltage on any Pin with Respect to Ground  
Operating Temperature (ambient)  
Storage Temperature  
VIN, VOUT  
TA  
Tstg  
Power Dissipation  
PD  
DC Output Current (I/O pins)  
IOUT  
50mA  
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a  
stress rating only, and the functional operation of the device at these, or any other conditions above those listed in the  
operational section of the specification, is not implied. Exposure to conditions at absolute maximum ratings for extended  
periods may affect device reliability.  
DC Operating Conditions (TA = 0°C to 70°C)  
Symbol  
VDD  
VIH  
Parameter  
Min  
3.135  
2.0  
-0.3  
-
Typical  
Max  
3.465  
VDD + 0.3  
0.8  
Units  
V
Notes  
Supply Voltage  
3.3  
Input High Voltage  
3.3  
V
VIL  
Input Low Voltage  
0.0  
V
II(L)  
Input Leakage Current  
-
-
-
-
±1  
µA  
µA  
V
IO(L)  
VOH  
VOL  
Output Leakage Current  
Output High Voltage (IOUT = -4mA)  
Output Low Voltage (IOUT = +4mA)  
-
±1  
2.4  
0.0  
VDD  
0.4  
V
Capacitance (TA = 25°C, f = 1MHz, VDD = 3.3V ± 5%, not 100% tested)  
Symbol  
CIn1  
Parameter  
Min  
2.5  
2.5  
3.5  
Typical  
3.3  
Max  
4.0  
4.0  
5.5  
Units  
pF  
Notes  
Input Capacitance (BA1, BA0, A0-11)  
Input Capacitance (all control inputs)  
I/O Capacitance (DQ0-15)  
CIn2  
3.3  
pF  
CI/O  
4.5  
pF  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Page 4 of 10  
Revision 1.1  
64Mbit – High Speed SDRAM  
Data Sheet  
8Mx8, 4Mx16 HSDRAM  
AC Characteristics (TA = 0°C to 70°C)  
1. An initial pause of 200µs is required after power-up, then a Precharge All Banks command must be given followed by  
a minimum of eight Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.  
2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the VTT = 1.4V crossover point.  
VTT  
tT  
VIH  
VTT  
VIL  
Clock  
RT = 50 ohm  
tSETUP tHOLD  
Z0 = 50 ohm  
Output  
Input  
CLOAD = 50pF  
tOH  
tAC  
tLZ  
VTT  
Output  
AC Output Load Circuit  
3. The transition time is measured between VIH and VIL (or between VIH and VIL).  
4. AC measurements assume tT = 1ns.  
5. In addition to meeting the transition rate specification, the clock and CKE must transition VIH and VIL (or between VIH  
and VIL) in a monotonic manner.  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Revision 1.1  
Page 5 of 10  
64Mbit – High Speed SDRAM  
8Mx8, 4Mx16 HSDRAM  
Data Sheet  
AC Operating Conditions (TA = 0°C to 70°C)  
Symbol  
Parameter  
-7.5  
Units  
Notes  
Min  
Max  
Clock and Clock Enable Parameters  
tCK3  
Clock Cycle Time, CL = 3  
7.5  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK2  
Clock Cycle Time, CL = 2  
tCK1  
Clock Cycle Time, CL = 1  
20  
tCKH3, tCKL3  
tCKH2, tCKL2  
tCKH1, tCKL1  
tCKES  
Clock High & Low Times, CL=3  
Clock High & Low Times, CL=2  
Clock High & Low Times, CL=1  
Clock Enable Set-Up Time  
Clock Enable Hold Time  
2.5  
3.5  
4.5  
1.5  
0.8  
1.5  
-
-
-
1
1
1
-
-
tCKEH  
-
tCKSP  
CKE Set-Up Time (Power down mode)  
Transition Time (Rise and Fall)  
-
tT  
4
Common Parameters  
tCS  
Command and Address Set-Up Time  
1.5  
0.8  
15  
-
ns  
ns  
tCH  
Command and Address Hold Time  
RAS to CAS Delay Time  
-
tRCD  
tRC  
tRAS  
tRP  
-
ns  
Bank Cycle Time  
52.5  
37.5  
15  
120K  
ns  
Bank Active Time  
120K  
ns  
Precharge Time  
-
-
-
-
ns  
tRRD  
tCCD  
tMRD  
Bank to Bank Delay Time (Alt. Bank)  
CAS to CAS Delay Time (Same Bank)  
Mode Register Set to Active Delay  
15  
ns  
7.5  
2
ns  
CLK  
Notes:  
1. Assumes clock rise and fall times are equal to 1ns. If rise or fall time exceeds 1ns, other AC timing parameters must be compensated by an  
additional [(trise+tfall)/2-1] ns.  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Page 6 of 10  
Revision 1.1  
64Mbit – High Speed SDRAM  
Data Sheet  
8Mx8, 4Mx16 HSDRAM  
Symbol  
Parameter  
-7.5  
Units  
Notes  
Min  
Max  
Read and Write Parameters  
tAC3  
tAC2  
tAC1  
Clock Access Time, CL = 3  
-
-
-
4.6  
6.0  
ns  
ns  
ns  
1,2,8  
1,2  
Clock Access Time, CL = 2  
Clock Access Time, CL = 1 (-7.5 device)  
Clock Access Time, CL = 1 (-7.5F device)  
15.0  
13.75  
1,2  
tOH3  
tOH2  
tOH1  
tLZ  
Data Output Hold Time (CL=3)  
Data Output Hold Time (CL=2)  
Data Output Hold Time (CL=1)  
Data Output to Low-Z Time  
Data Output to High-Z Time (CL=2, 3)  
Data Output to High-Z Time (CL=1)  
DQM Data Output Disable Time  
Data Input Set-Up Time  
2.7  
3.0  
3.5  
1
-
ns  
ns  
-
-
ns  
-
ns  
tHZ2  
tHZ1  
tDQZ  
tDS  
-
4.6  
ns  
3
3
-
7.0  
ns  
2
-
-
-
-
-
-
CLK  
ns  
1.5  
0.8  
15  
30  
0
tDH  
Data Input Hold Time  
ns  
tDPL  
tDAL  
tDQW  
Data Input to Precharge  
ns  
Data Input to ACTV/Refresh  
Data Write Mask Latency  
ns  
4
CLK  
Refresh Parameters  
tREF  
Refresh Period  
Self Refresh Exit Time  
-
64  
-
ms  
ns  
5, 6  
7
tSREX  
2CLK+tRC  
Notes:  
1. Access time is measured at 1.4V (LVTTL) at max clock rate for the CAS latency specified. See AC Test Load.  
2. Access time is based on a clock rise time of 1ns. If clock rise time is longer than 1ns, then (trise/2-0.5) ns must be added to the access time.  
3. Referenced to the time at which the output achieves an open circuit condition.  
4. tDAL is equal to tDPL + tRP.  
5. 4096 cycles.  
6. Any time that the refresh period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to “wake up” the device.  
7. Self-Refresh exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self-Refresh Exit is not  
completed until tRC is satisfied once the Self-Refresh Exit command is registered.  
8. For 4Mx16 devices, the Clock Access Time (CL=3) is 5.0 ns.  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Revision 1.1  
Page 7 of 10  
64Mbit – High Speed SDRAM  
8Mx8, 4Mx16 HSDRAM  
Data Sheet  
Operating Currents (TA = 0°C to 70°C)  
Parameter  
Operating Current  
Symbol  
ICC1A  
Test Condition  
Value  
120  
Units Notes  
BL = 1, CL = 3, Read or Write,  
CKE • VIH(min), tRC = min., tCK = 7.5ns  
mA  
mA  
mA  
1
(One Bank Active)  
Standby Current in Power Down  
Mode (DRAM Precharged)  
ICC2P  
2.5  
2.0  
CKE ” VIL, tCK = 7.5ns,  
Input Change Every Two Cycles  
ICC2PS  
CKE ” VIL, tCK = Infinity,  
No Input Change  
Standby Current in Non-Power  
Down Mode (DRAM Precharged)  
ICC2N  
ICC2NS  
ICC3N  
30  
10  
65  
mA  
mA  
mA  
CKE • VIH, tCK = 7.5ns  
CKE • VIH, tCK = Infinity  
Device Deselected (DRAM  
Active)  
CKE • VIH, tCK = 7.5ns,  
Input Change Every Two Cycles  
ICC3P  
3
mA  
CKE ” VIL, tCK = 7.5ns,  
Input Change Every Two Cycles  
Burst Operating Current  
(Both Banks Active)  
ICC4A  
ICC4B  
BL = Full Page, CL = 1, Read or Write,  
70  
mA  
mA  
1,2  
1,2  
t
RC = Infinity, tCK = min.  
BL = Full Page, CL = 2,3, Read or Write,  
RC = Infinity, tCK = min.  
130  
t
Auto (CBR) Refresh Current  
Self Refresh Current  
Notes:  
ICC5F  
ICC5D  
ICC6  
CL = 3, tCK = 7.5ns, tRC = tRC(min).  
CL = 3, tCK = 7.5ns, tRC = 15.625 µs  
CKE ”ꢀꢁꢂꢃ9ꢄꢀ1Rꢀ,QSXWꢀ&KDQJH  
170  
30  
4
mA  
mA  
mA  
3,4,5  
3,4,5  
1. The specified value is obtained with the outputs open.  
2. The specified value is obtained when the programmed burst length is executed to completion without intereuption by a subsequent burst read or  
burst write cycle.  
3. The specified value is valid when addresses are changed no more than once during tCK(min).  
4. The specified value is valid when No Operation commands are registered on every rising clock edge during tRC(min).  
5. The specified value is valid when data inputs (DQs) are stable during tRC(min).  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Page 8 of 10  
Revision 1.1  
64Mbit – High Speed SDRAM  
Data Sheet  
8Mx8, 4Mx16 HSDRAM  
Revision Log  
Revision  
1.0  
Date  
-
Summary of Changes  
First release of document.  
Added –7.5F versions of this device. Added Revision Log.  
1.1  
4/17/00  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Revision 1.1  
Page 9 of 10  
64Mbit – High Speed SDRAM  
8Mx8, 4Mx16 HSDRAM  
Data Sheet  
Ordering Information  
Maximum  
Operating  
Frequency  
(MHz)  
Part Number  
CAS  
Latencies  
I/O Width  
I/O Type  
Package  
Power  
Supply  
SM3603T-7.5  
SM3604T-7.5  
SM3603T-7.5F  
SM3604T-7.5F  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
x8  
x16  
x8  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
3.3V  
3.3V  
3.3V  
3.3V  
133  
133  
133  
133  
x16  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Page 10 of 10  
Revision 1.1  

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