ALC269_09_07 [REALTEK]
HIGH DEFINITION AUDIO CODEC WITH EMBEDDED CLASS-D SPEAKER AMPLIFIER;
| 型号： | ALC269_09_07 |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | HIGH DEFINITION AUDIO CODEC WITH EMBEDDED CLASS-D SPEAKER AMPLIFIER 放大器 |
| 文件： | 总79页 (文件大小：1296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC269
(ALC269Q-GR, ALC269QSRS-GR, ALC269W-GR)
HIGH DEFINITION AUDIO CODEC WITH
EMBEDDED CLASS-D SPEAKER AMPLIFIER
DATASHEET
Rev. 1.5
20 July 2009
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
ALC269
Datasheet
COPYRIGHT
©2009 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC269 codec IC.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
Release Date Summary
1.0
2008/04/15
2008/04/25
First Release
1.1
Revised Figure 1 Block Diagram, page 5.
Revised Table 84 Analog Performance, page 64 (DAC/ADC Full-Scale Input Voltage).
Updated analog performance in section 9.3, page 64.
Revised Table 77, page 59, Note 2.
1.2
1.3
1.4
1.5
2008/12/24
2009/01/21
2009/02/25
2009/07/20
Added ALC269W-GR part number in section 12, page 71.
Revised electrical characteristic in section 9.1, page 59 and section 9.2, page 61.
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Datasheet
Table of Contents
1.
2.
GENERAL DESCRIPTION ..............................................................................................................................................1
FEATURES .........................................................................................................................................................................2
2.1.
2.2.
HARDWARE FEATURES .................................................................................................................................................2
SOFTWARE FEATURES ..................................................................................................................................................3
3.
4.
SYSTEM APPLICATIONS ...............................................................................................................................................4
BLOCK DIAGRAM...........................................................................................................................................................5
4.1.
ANALOG INPUT/OUTPUT UNIT .....................................................................................................................................6
5.
6.
PIN ASSIGNMENTS..........................................................................................................................................................7
5.1.
GREEN PACKAGE AND VERSION IDENTIFICATION.........................................................................................................7
PIN DESCRIPTIONS.........................................................................................................................................................8
6.1.
DIGITAL I/O PINS .........................................................................................................................................................8
ANALOG I/O PINS ........................................................................................................................................................8
FILTER/REFERENCE......................................................................................................................................................9
POWER/GROUND..........................................................................................................................................................9
6.2.
6.3.
6.4.
7.
HIGH DEFINITION AUDIO LINK PROTOCOL........................................................................................................10
7.1.
LINK SIGNALS............................................................................................................................................................10
7.1.1. Signal Definitions.................................................................................................................................................11
7.1.2. Signaling Topology...............................................................................................................................................12
7.2.
FRAME COMPOSITION ................................................................................................................................................13
7.2.1. Outbound Frame – Single SDO............................................................................................................................13
7.2.2. Outbound Frame – Multiple SDO ........................................................................................................................14
7.2.3. Inbound Frame – Single SDI................................................................................................................................15
7.2.4. Inbound Frame – Multiple SDI ............................................................................................................................16
7.2.5. Variable Sample Rates..........................................................................................................................................16
7.3.
RESET AND INITIALIZATION........................................................................................................................................19
7.3.1. Link Reset .............................................................................................................................................................19
7.3.2. Codec Reset..........................................................................................................................................................20
7.3.3. Codec Initialization Sequence ..............................................................................................................................21
7.4.
VERB AND RESPONSE FORMAT...................................................................................................................................22
7.4.1. Command Verb Format ........................................................................................................................................22
7.4.2. Response Format..................................................................................................................................................22
7.5.
POWER MANAGEMENT...............................................................................................................................................23
8.
SUPPORTED VERBS AND PARAMETERS ................................................................................................................24
8.1.
VERB – GET PARAMETERS (VERB ID=F00H) .............................................................................................................24
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................24
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................24
8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................25
8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)...........................................................25
8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................25
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................26
8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................27
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................28
8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................28
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8.1.10.
8.1.11.
8.1.12.
8.1.13.
8.1.14.
8.1.15.
8.1.16.
Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)...........................29
Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h).........................29
Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)........................................................30
Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)..................................................30
Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..................................................30
Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)...........................................................31
Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)...............................................31
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ................................................................................32
VERB – SET CONNECTION SELECT (VERB ID=701H) .................................................................................................32
VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H)..........................................................................................33
VERB – GET PROCESSING STATE (VERB ID=F03H)....................................................................................................35
VERB – SET PROCESSING STATE (VERB ID=703H).....................................................................................................35
VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................36
VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................36
VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................37
VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................37
VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................38
VERB – SET AMPLIFIER GAIN (VERB ID=3H).............................................................................................................40
VERB – GET CONVERTER FORMAT (VERB ID=AH) ....................................................................................................41
VERB – SET CONVERTER FORMAT (VERB ID=2H)......................................................................................................42
VERB – GET POWER STATE (VERB ID=F05H) ............................................................................................................43
VERB – SET POWER STATE (VERB ID=705H) .............................................................................................................43
VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................44
VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ................................................................................44
VERB – GET PIN WIDGET CONTROL (VERB ID=F07H)...............................................................................................45
VERB – SET PIN WIDGET CONTROL (VERB ID=707H)................................................................................................45
VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................46
VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ............................................................................46
VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................47
VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................47
VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) ........................................................................................48
VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) .48
VERB – GET BEEP GENERATOR (VERB ID=F0AH)....................................................................................................49
VERB – SET BEEP GENERATOR (VERB ID=70AH).....................................................................................................49
VERB – GET GPIO DATA (VERB ID=F15H)................................................................................................................50
VERB – SET GPIO DATA (VERB ID=715H).................................................................................................................50
VERB – GET GPIO ENABLE MASK (VERB ID=F16H).................................................................................................51
VERB – SET GPIO ENABLE MASK (VERB ID=716H)..................................................................................................51
VERB – GET GPIO DIRECTION (VERB ID=F17H).......................................................................................................52
VERB – SET GPIO DIRECTION (VERB ID=717H)........................................................................................................52
VERB – GET GPIO WAKE ENABLE MASK(VERB ID=F18H).......................................................................................53
VERB-SET GPIO WAKE ENABLE MASK(VERB ID=718H)..........................................................................................53
VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).........................................................54
VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................54
VERB – FUNCTION RESET (VERB ID=7FFH) ..............................................................................................................55
VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=F0DH, F0EH) ...........................................55
VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH).............................................56
GET/SET VOLUME KNOB WIDGET (VERB ID=F0FH/70FH)........................................................................................57
GET/SET SUBSYSTEM ID [31:0] (VERB ID=F20H/723H~720H TO SET BIT[31:0]).....................................................57
GET/SET EAPD ENABLE (VERB ID= F0CH/70CH) ....................................................................................................58
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.23.
8.24.
8.25.
8.26.
8.27.
8.28.
8.29.
8.30.
8.31.
8.32.
8.33.
8.34.
8.35.
8.36.
8.37.
8.38.
8.39.
8.40.
8.41.
8.42.
8.43.
8.44.
9.
ELECTRICAL CHARACTERISTICS...........................................................................................................................59
9.1.
DC CHARACTERISTICS...............................................................................................................................................59
9.1.1. Absolute Maximum Ratings..................................................................................................................................59
9.1.2. Threshold Voltage.................................................................................................................................................59
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9.1.3. Digital Filter Characteristics...............................................................................................................................60
9.1.4. S/PDIF Output Characteristics ............................................................................................................................60
9.2.
AC CHARACTERISTICS...............................................................................................................................................61
9.2.1. Link Reset and Initialization Timing.....................................................................................................................61
9.2.2. Link Timing Parameters at the Codec ..................................................................................................................62
9.2.3. S/PDIF Output Timing..........................................................................................................................................63
9.2.4. Test Mode..............................................................................................................................................................63
9.3.
9.4.
ANALOG PERFORMANCE............................................................................................................................................64
CLASS-D POWER AMPLIFIER PERFORMANCE .............................................................................................................65
10.
APPLICATION CIRCUITS .......................................................................................................................................66
10.1.
10.2.
10.3.
FILTER CONNECTION..................................................................................................................................................66
POWER AND JACK CONNECTION.................................................................................................................................67
S/PDIF-OUT CONNECTION .......................................................................................................................................68
11.
MECHANICAL DIMENSIONS.................................................................................................................................69
MECHANICAL DIMENSIONS NOTES ............................................................................................................................70
ORDERING INFORMATION ...................................................................................................................................71
11.1.
12.
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Class-D Speaker Amplifier
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Datasheet
List of Tables
TABLE 1. DIGITAL I/O PINS .........................................................................................................................................................8
TABLE 2. ANALOG I/O PINS.........................................................................................................................................................8
TABLE 3. FILTER/REFERENCE ......................................................................................................................................................9
TABLE 4. POWER/GROUND..........................................................................................................................................................9
TABLE 5. LINK SIGNAL DEFINITIONS.........................................................................................................................................11
TABLE 6. HDASIGNAL DEFINITIONS ........................................................................................................................................11
TABLE 7. DEFINED SAMPLE RATE AND TRANSMISSION RATE ....................................................................................................17
TABLE 8. 48KHZ VARIABLE RATE OF DELIVERY TIMING ...........................................................................................................17
TABLE 9. 44.1KHZ VARIABLE RATE OF DELIVERY TIMING ........................................................................................................18
TABLE 10. 40-BIT COMMANDS IN 4-BIT VERB FORMAT..............................................................................................................22
TABLE 11. 40-BIT COMMANDS IN 12-BIT VERB FORMAT............................................................................................................22
TABLE 12. SOLICITED RESPONSE FORMAT ..................................................................................................................................22
TABLE 13. UNSOLICITED RESPONSE FORMAT .............................................................................................................................22
TABLE 14. SYSTEM POWER STATE DEFINITIONS .........................................................................................................................23
TABLE 15. POWER CONTROLS IN NID=01H ................................................................................................................................23
TABLE 16. POWERED DOWN CONDITIONS...................................................................................................................................23
TABLE 17. VERB – GET PARAMETERS (VERB ID=F00H).............................................................................................................24
TABLE 18. PARAMETER – VENDOR ID (VERB ID=F00H, PARAMETER ID=00H)..........................................................................24
TABLE 19. PARAMETER – REVISION ID (VERB ID=F00H, PARAMETER ID=02H) ........................................................................24
TABLE 20. PARAMETER – SUBORDINATE NODE COUNT (VERB ID=F00H, PARAMETER ID=04H)................................................25
TABLE 21. PARAMETER – FUNCTION GROUP TYPE (VERB ID=F00H, PARAMETER ID=05H).......................................................25
TABLE 22. PARAMETER – AUDIO FUNCTION CAPABILITIES (VERB ID=F00H, PARAMETER ID=08H) ..........................................25
TABLE 23. PARAMETER – AUDIO WIDGET CAPABILITIES (VERB ID=F00H, PARAMETER ID=09H)..............................................26
TABLE 24. PARAMETER – SUPPORTED PCM SIZE, RATES (VERB ID=F00H, PARAMETER ID=0AH) ............................................27
TABLE 25. PARAMETER – SUPPORTED STREAM FORMATS (VERB ID=F00H, PARAMETER ID=0BH)............................................28
TABLE 26. PARAMETER – PIN CAPABILITIES (VERB ID=F00H, PARAMETER ID=0CH) ................................................................28
TABLE 27. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, INPUT AMPLIFIER PARAMETER ID=0DH)........................29
TABLE 28. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, OUTPUT AMPLIFIER PARAMETER ID=12H) .....................29
TABLE 29. PARAMETER – CONNECT LIST LENGTH (VERB ID=F00H, PARAMETER ID=0EH).......................................................30
TABLE 30. PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH) .................................................30
TABLE 31. PARAMETER – PROCESSING CAPABILITIES (VERB ID=F00H, PARAMETER ID=10H)...................................................30
TABLE 32. PARAMETER – GPIO CAPABILITIES (VERB ID=F00H, PARAMETER ID=11H) .............................................................31
TABLE 33. PARAMETER – VOLUME KNOB CAPABILITIES (VERB ID=F00H, PARAMETER ID=13H)..............................................31
TABLE 34. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H)................................................................................32
TABLE 35. VERB – SET CONNECTION SELECT (VERB ID=701H).................................................................................................32
TABLE 36. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................33
TABLE 37. VERB – GET PROCESSING STATE (VERB ID=F03H)....................................................................................................35
TABLE 38. VERB – SET PROCESSING STATE (VERB ID=703H).....................................................................................................35
TABLE 39. VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................36
TABLE 40. VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................36
TABLE 41. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................37
TABLE 42. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................37
TABLE 43. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................38
TABLE 44. VERB – SET AMPLIFIER GAIN (VERB ID=3H) ............................................................................................................40
TABLE 45. VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................41
TABLE 46. VERB – SET CONVERTER FORMAT (VERB ID=2H) .....................................................................................................42
TABLE 47. VERB – GET POWER STATE (VERB ID=F05H)............................................................................................................43
TABLE 48. VERB – SET POWER STATE (VERB ID=705H).............................................................................................................43
TABLE 49. VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................44
TABLE 50. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H)................................................................................44
TABLE 51. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................45
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TABLE 52. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................45
TABLE 53. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H)...........................................................................46
TABLE 54. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H)............................................................................46
TABLE 55. VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................47
TABLE 56. VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................47
TABLE 57. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH)........................................................................................48
TABLE 58. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3)48
TABLE 59. VERB – GET BEEP GENERATOR (VERB ID=F0AH) ...................................................................................................49
TABLE 60. VERB – SET BEEP GENERATOR (VERB ID=70AH) ....................................................................................................49
TABLE 61. VERB – GET GPIO DATA (VERB ID=F15H) ...............................................................................................................50
TABLE 62. VERB – SET GPIO DATA (VERB ID=715H) ................................................................................................................50
TABLE 63. VERB – GET GPIO ENABLE MASK (VERB ID=F16H) ................................................................................................51
TABLE 64. VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................51
TABLE 65. VERB – GET GPIO DIRECTION (VERB ID=F17H) ......................................................................................................52
TABLE 66. VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................52
TABLE 67. VERB – GET GPIO WAKE ENABLE MASK (VERB ID=F18H)......................................................................................53
TABLE 68. VERB – SET GPIO WAKE ENABLE MASK (VERB ID=718H).......................................................................................53
TABLE 69. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).........................................................54
TABLE 70. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................54
TABLE 71. VERB – FUNCTION RESET (VERB ID=7FFH)..............................................................................................................55
TABLE 72. VERB –GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=F0DH, F0EH) ............................................55
TABLE 73. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH).............................................56
TABLE 74. GET/SET VOLUME KNOB WIDGET (VERB ID=F0FH/70FH) .......................................................................................57
TABLE 75. GET/SET SUBSYSTEM ID [31:0] (VERB ID=F20H / 723H~720H TO SET BIT[31:0])....................................................57
TABLE 76. GET/SET EAPD ENABLE (VERB ID=F0CH / 70CH ) ..................................................................................................58
TABLE 77. ABSOLUTE MAXIMUM RATINGS.................................................................................................................................59
TABLE 78. THRESHOLD VOLTAGE ...............................................................................................................................................59
TABLE 79. DIGITAL FILTER CHARACTERISTICS ...........................................................................................................................60
TABLE 80. S/PDIF INPUT/OUTPUT CHARACTERISTICS................................................................................................................60
TABLE 81. LINK RESET AND INITIALIZATION TIMING..................................................................................................................61
TABLE 82. LINK TIMING PARAMETERS AT THE CODEC ................................................................................................................62
TABLE 83. S/PDIF OUTPUT TIMING............................................................................................................................................63
TABLE 84. ANALOG PERFORMANCE............................................................................................................................................64
TABLE 85. CLASS-D POWER AMPLIFIER PERFORMANCE.............................................................................................................65
TABLE 86. ORDERING INFORMATION ..........................................................................................................................................71
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Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................5
FIGURE 2. ANALOG INPUT/OUTPUT UNIT....................................................................................................................................6
FIGURE 3. PIN ASSIGNMENTS - ALC269 (QFN-48).....................................................................................................................7
FIGURE 4. HDALINK PROTOCOL ..............................................................................................................................................10
FIGURE 5. BIT TIMING...............................................................................................................................................................11
FIGURE 6. SIGNALING TOPOLOGY .............................................................................................................................................12
FIGURE 7. SDO OUTBOUND FRAME..........................................................................................................................................13
FIGURE 8. SDO STREAM TAG IS INDICATED IN SYNC...............................................................................................................14
FIGURE 9. STRIPED STREAM ON MULTIPLE SDOS.....................................................................................................................14
FIGURE 10. SDI INBOUND STREAM.............................................................................................................................................15
FIGURE 11. SDI STREAM TAG AND DATA ....................................................................................................................................15
FIGURE 12. CODEC TRANSMITS DATA OVER MULTIPLE SDIS .....................................................................................................16
FIGURE 13. LINK RESET TIMING .................................................................................................................................................20
FIGURE 14. CODEC INITIALIZATION SEQUENCE ..........................................................................................................................21
FIGURE 15. LINK RESET AND INITIALIZATION TIMING ................................................................................................................61
FIGURE 16. LINK SIGNALS TIMING .............................................................................................................................................62
FIGURE 17. OUTPUT TIMING .......................................................................................................................................................63
FIGURE 18. FILTER CONNECTION................................................................................................................................................66
FIGURE 19. POWER AND JACK CONNECTION...............................................................................................................................67
FIGURE 20. S/PDIF-OUT CONNECTION......................................................................................................................................68
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Datasheet
1. General Description
The ALC269 is a High Definition Audio Codec that integrates a 2+2-channel DAC, a 4-channel ADC,
and a Class-D Speaker Amplifier.
The 2+2-channel DAC supports two independent stereo sound outputs simultaneously. The 4-channel
ADC integrates two stereo and independent analog sound inputs (multiple streaming).
The ALC269 incorporates Realtek converter technology to achieve a 98dB dynamic range playback
quality and a 98dB dynamic range recording quality. It meets the current WLP3.10 (Windows Logo
Program) and future WLP requirements.
The ALC269 also supports stereo digital microphone channels (microphone array) with Acoustic Echo
Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology simultaneously,
significantly improving voice quality for PC VoIP applications.
As well as basic audio functions, the ALC269 has two independent S/PDIF outputs; one could be used to
connect a PC to high-quality consumer electronic products such as digital decoders and speakers, the
other could provide a dedicated digital output to a HDMI transmitter (common in high end PCs).
There are three integrated power amplifiers. The first is a linear headphone amplifier at port C. The
second headphone amplifier at port A removes the need for external DC blocking capacitors, eliminating
pop noise caused by these capacitors. The third is an integrated stereo Class-D amplifier to directly drive
a mini-speaker. The Class-D amplifier is designed to drive speakers with as low as 4Ω impedance. Its
maximum output power is 2.3W per channel at 5V power supply. The advantage of an integrated Class-D
amplifier in the ALC269 is high efficiency with low power consumption.
The ALC269 integrates five hardware equalizer bands composed of one low-pass filter, one high-pass
filter, and three band-pass filters to compensate for mini-speaker frequency response. All the equalizer
filters are programmable via the BIOS, allowing the equalizer to function without the need to customize
the audio driver.
The ALC269 conforms to Intel’s Audio Codec low power state white paper and is ECR compliant.
Note: ALC269 version differences are listed in section 12 Ordering Information, page 71.
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ALC269
Datasheet
2. Features
2.1. Hardware Features
98dB Signal-to-Noise Ratio (A-weighting) for DAC output
98dB Signal-to-Noise Ratio (A-weighting) for ADC input
Meets WLP (Windows Logo Program) 3.10 and future WLP requirements
2+2-channel DAC supports 16/20/24-bit PCM format for independent two stereo channel audio
playback
4-channel ADC supports 16/20/24-bit PCM format for independent two stereo channel audio inputs
All DACs supports 44.1/48/96/192kHz sample rate
All ADCs support 44.1/48/96kHz sample rate
S/PDIF-OUT support 16/20/24-bit format and 32/44.1/48/88.2/96/192kHz rate
Supports MONO line level output
Supports external PCBEEP input and built-in digital BEEP generator
Software selectable 2.5V/3.2V/4.2V VREFOUT as bias voltage for analog microphone input
Two jack detection pins each designed to detect up to 4 jacks
1dB resolution of input and output volume control
Programmable +10/+20/+30dB boost gain for analog microphone input
Built-in headphone amplifiers for port-A and port-C.
2 GPIOs are supported for customized applications (pin shared with digital microphone interface)
EAPD (External Amplifier Power Down) is supported (pin shared with secondary S/PDIF-OUT)
Supports Anti-pop mode when analog power AVDD is on and digital power is off
Power support: 3.3V digital core power; 1.5V~3.3V digital IO power for HDA link; 3.3V~5.0V
analog power; 3.3V~5.0V power stage voltage
Enhanced power management features
Secondary S/PDIF-OUT supports 16/20/24-bit format and 32k/44.1k/48k/88.2k/96k/192kHz rate
High Definition Audio Codec with Embedded
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Datasheet
Supports stereo digital microphone input
Programmable boost gain and volume control for digital microphone input
Headphone amplifier for port-A does not require DC blocking capacitors
Stereo Bridge-Tied Load Class-D amplifier at port-D has 2Watt (rms)/4Ω per channel output
Short circuit and thermal overload protection for Class-D amplifier
Supports digital PWM output at port-D which system integrator can easily connect the output to
external power amplifier receives digital audio stream
Five band hardware equalizer designed for BTL output (port-D) to compensate for frequency
response while driving the mini-speaker
Intel low power ECR compliant: supports power status control, jack detection, and wake-up event in
D3 mode
48-pin QFN ‘Green’ package
2.2. Software Features
Compatible with Windows Logo Program 3.10 and future requirements
WaveRT-based audio function driver for Windows Vista
EAX™ 1.0 & 2.0 compatible
Direct Sound 3D™ compatible
A3D™ compatible
I3DL2 compatible
HRTF 3D Positional Audio (Windows XP only)
Emulation of 26 sound environments to enhance gaming experience
Multi-band software equalizer and tools
Voice Cancellation and Key Shifting in Karaoke mode
Dynamic range control (expander, compressor, and limiter) with adjustable parameters
Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience
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Datasheet
Provides 10-foot GUI for Windows Media Center
Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)
technology for voice application
Smart multiple streaming operation
HDMI audio driver for AMD platform
Dolby® PCEE program™ (optional software feature)
SRS® TrueSurround HD (optional software feature)
Fortemedia® SAM™ technology for voice processing (Beam Forming and Acoustic Echo
Cancellation) (optional software feature)
MaxxAudio technologies from Waves (optional software feature, ALC269W only)
3. System Applications
Windows Vista premium desktop and laptop PCs
Information Appliances (IA) with High Definition Audio Controller
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Datasheet
4. Block Diagram
Figure 1. Block Diagram
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Datasheet
4.1. Analog Input/Output Unit
Pin widgets NID=18h, 19h, 1Ah, and 1Bh are re-tasking IO supporting input units. NID=15h and 1Ah
support amplifier units.
Left
A
R
EN_OBUF
EN_AMP
Right
R
Output_Signal_Left
Output_Signal_Right
Input_Signal_Left
EN_OBUF
EN_IBUF
Input_Signal_Right
Figure 2. Analog Input/Output Unit
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Datasheet
5. Pin Assignments
36
34 33
31
27
30 29 28 26 25
35
32
24 LINE1-R
23 LINE1- L
AVSS2
AVDD2
37
38
39
40
41
42
43
44
45
46
47
48
MIC1- R
MIC1- L
22
21
20
19
18
17
16
15
14
13
PVDD1
SPK-OUT- L +
MONO - OUT
JDREF
SPK-OUT- L-
PVSS1
ALC269
PVSS2
Sense B
SPK- OUT- R-
SPK- OUT- R+
PVDD2
MIC2- R
MIC2- L
LLLLLLL TXXXVV
LINE 2- R
LINE 2- L
EAPD/SPDIFO2
SPDIFO
Sense A
1
3
6
10
9 11 12
2
5
7 8
4
Figure 3. Pin Assignments - ALC269 (QFN-48)
5.1. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3. The version number is shown
in the location marked ‘VV’.
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Class-D Speaker Amplifier
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Datasheet
6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Characteristic Definition
Name
Type Pin Description
RESET#
SYNC
I
I
11 H/W Reset Control
10 Sample Sync (48kHz)
Vt=0.5*DVDD
Vt=0.5*DVDD
BCLK
I
6
5
8
24MHz Bit Clock Input
Serial TDM Data Input
Serial TDM Data Output
Vt=0.5*DVDD
SDATA-OUT
SDATA-IN
EAPD/
SPDIFO2
SPDIFO
GPIO0/
DMIC-DATA
GPIO1/
DMIC-CLK
PD#
I
Vt=0.5*DVDD
O
O
VOH=0.9*DVDD, VOL=0.1*DVDD
Output to mute/un-mute external amplifier
Output has 12 mA@75Ω driving capability.
Output has 12mA@75Ω driving capability.
47 Signal to power down ext. amp
Secondary S/PDIF output
48 S/PDIF Output
O
IO
2
3
4
General Purpose Input/Output 0 Input Vt=(1/2)*DVDD, output VOH=DVDD,
VOL=DVSS, internal pulled up by 50KΩ
Data input from digital MIC1&2
General Purpose Input/Output 1 Input Vt=(1/2)*DVDD, output VOH=DVDD,
IO
I
VOL=DVSS, Default 2.048MHz clock output
Clock output for digital MIC
Low to Power Down Speaker
(BTL) Output
Input Vt=(1/2)*DVDD, internal pulled up by 50KΩ
Total: 10 pins
6.2. Analog I/O Pins
Table 2. Analog I/O Pins
Name
Type Pin Description
Characteristic Definition
PCBEEP
LINE2-L
LINE2-R
MIC2-L
MIC2-R
MONO-OUT
MIC1-L
I
12 External PCBEEP Input
Analog input, 1.6Vrms of full-scale input
Analog input/output, default is input (JACK-E)
Analog input/output, default is input (JACK-E)
IO 14 2nd Line Input Left Channel
IO 15 2nd Line Input Right Channel
IO 16 2nd Stereo Microphone Input Left Channel Analog input/output, default is input (JACK-F)
IO 17 2nd Stereo Microphone Input Right Channel Analog input/output, default is input (JACK-F)
O
20 MONO Output
Analog mono output is summation of (L+R)/2.
IO 21 1st Stereo Microphone Input Left Channel
Analog input/output, default is input
(JACK-B)
MIC1-R
LINE1-L
LINE1-R
IO 22 1st Stereo Microphone Input Right Channel Analog input/output, default is input
(JACK-B)
IO 23 1st Line Input Left Channel
Analog input/output, default is input
(JACK-C)
IO 24 1st Line Input Right Channel
Analog input/output, default is input
(JACK-C)
SPK-OUT-L+
SPK-OUT-L-
SPK-OUT-R-
O
O
O
40 BTL Mode Positive Left Channel
41 BTL Mode Negative Left Channel
44 BTL Mode Negative Right Channel
Pulse width modulation output (JACK-D)
Pulse width modulation output (JACK-D)
Pulse width modulation output (JACK-D)
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Datasheet
Name
Type Pin Description
Characteristic Definition
SPK-OUT-R+
HP-OUT-L
HP-OUT-R
Sense A
O
O
O
I
45 BTL Mode Positive Right Channel
Pulse width modulation output (JACK-D)
Analog output (JACK-A)
32 First Out Left Channel
33 First Out Right Channel
13 Jack Detect Pin L
Analog output (JACK-A)
Resistor (5.1K, 10K, 20K, 39.2K) w/ 1%
accuracy
Sense B
I
18 Jack Detect Pin 2
Resistor (5.1K, 10K, 20K, 39.2K) w/ 1%
accuracy
Total: 18 pins
6.3. Filter/Reference
Table 3. Filter/Reference
Name
Type Pin Description
Characteristic Definition
JDREF
-
19 Ref. Resistor for Jack Detect
20K, 1% accuracy resistor to analog ground
1µf capacitor to analog ground
2.5V/3.2V/4.2V reference voltage
2.5V/3.2V/4.2V reference voltage
VREF
-
27 2.5V Reference Voltage
28 Bias Voltage for MIC1 Jack
29 Bias Voltage for MIC2 Jack
MIC1-VREFO-L
MIC2-VREFO
MIC1-VREFO-R
CPVREF
CBN
O
O
O
30 Secondary Bias voltage for MIC1 jack 2.5V/3.2V/4.2V reference voltage
31 0V Reference Voltage
35 Reference Capacitor
36 Reference Capacitor
Analog ground
-
-
2.2µf capacitor to CBP
2.2µf capacitor to CBN
Total: 8 pins
CBP
6.4. Power/Ground
Table 4. Power/Ground
Name
Type Pin Description
Characteristic Definition
AVDD1
AVSS1
AVDD2
AVSS2
DVDD
DVDD-IO
DVSS
P
G
P
25 Analog VDD (5.0V or 3.3V)
Analog power for mixer and amplifier
Analog ground for mixer and amplifier
Analog power for DACs and ADCs
Analog ground for DACs and ADCs
Digital core power for core logic
Digital I/O power for HDA link
Digital ground
26 Analog GND
38 Analog VDD (5.0V or 3.3V)
37 Analog GND
G
P
1
9
7
Digital VDD (3.3V)
Digital VDD (3.3V or 1.5V)
Digital GND
P
G
P
PVDD1
PVSS1
PVSS2
PVDD2
CPVEE
39 Power Stage VDD 5.0V
42 Power Stage GND
Power supply for full-bridge left channel
Ground for full-bridge left channel
Ground for full-bridge right channel
Power supply for full-bridge right channel
2.2µf capacitor to analog ground
Total: 12 pins
G
G
P
43 Power Stage GND
46 Power Stage VDD 5.0V
34 Reference Voltage Output
P
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Datasheet
7. High Definition Audio Link Protocol
7.1. Link Signals
The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol.
Figure 4. HDA Link Protocol
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Datasheet
7.1.1.
Signal Definitions
Table 5. Link Signal Definitions
Item
Description
BCLK
SYNC
24.0MHz bit clock sourced from the HDA controller and connected to all codecs.
48kHz signal used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
SDO
Serial Data Output signal driven by the HDA controller to all codecs. Commands and data streams are
carried on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec
samples data present on SDO with respect to each edge of BCLK. The HDA controller must support at
least one SDO. To extend outbound bandwidth, multiple SDOs may be supported.
SDI
Serial Data Input signal driven by the codec. It is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be
supported. SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at
each rising edge of BCLK. SDI can be driven by the controller to initialize the codec’s ID.
RST#
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs.
Table 6. HDA Signal Definitions
Signal Name
BCLK
SYNC
SDO
Source
Controller
Controller Type Description
Output
Output
Global 24.0MHz Bit Clock.
Controller
Global 48kHz Frame Sync and outbound tag signal.
Serial Data Output from Controller.
Controller
Output
SDI
Codec/Controller
Input/Output
Serial Data Input from codec. Weakly pulled down by the
controller.
RST#
Controller
Output
Global Active Low Reset Signal.
BCLK
SYNC
8-Bit Frame SYNC
Start of Frame
7
6
5
4
3
2
1
0 999 998 997 996 995 994 993 992 991 990
SDO
SDI
3
2
1
0
499 498 497 496 495 494
Codec samples SDO at both rising and falling edge of BCLK
Controller samples SDI at rising edge of BCLK
Figure 5. Bit Timing
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Datasheet
7.1.2.
Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0 and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.
Figure 6 shows the possible connections between the HDA controller and codecs:
• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
• Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
• Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 13 describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 6 can be implemented concurrently in an HDA system. The ALC269 is
designed to receive a single SDO stream.
Figure 6. Signaling Topology
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Datasheet
7.2. Frame Composition
7.2.1.
Outbound Frame – Single SDO
An outbound frame is composed of one 32-Bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be 2 blocks in the same stream to carry
96kHz samples (Figure 7).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-Bit preamble and 4-Bit stream ID (Figure 8).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
A 48kHz Frame is composed of Command stream and multiple Data streams
Previous Frame
Next Frame
Frame SYNC
Stream 'A' Tag
(Here 'A' = 5)
Stream 'X' Tag
(Here 'X' = 6)
SYNC
SDO
Command Stream
0s
Stream 'A' Data
Stream 'X' Data
Padded at the
end of Frame
Null Field
One or multiple blocks in a stream
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block1 includes (N)th time of samples, Block2
includes (N+1)th time of samples
..
.
Block 1
Block 2
Block Y
..
.
Sample 1 Sample 2
Sample Z
Z channels of PCM Sample
...
msb first in a sample
msb
lsb
Figure 7. SDO Outbound Frame
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Datasheet
BCLK
SYNC
Stream Tag
msb lsb
1 0 1 0
Stream=10
(4-Bit)
Preamble
(4-Bit)
Data of Stream 10
7 6 5 4 3 2 1 0
Previous Stream
SDO
Figure 8. SDO Stream Tag is Indicated in SYNC
7.2.2.
Outbound Frame – Multiple SDO
The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission
in less time to get more bandwidth. If software determines the target codec supports multiple SDO
capability, it enables the stripe control bit in the controller’s Output Stream Control Register to initiate a
specific stream (Stream ‘A’ in Figure 9) to be transmitted on multiple SDOs. In this case, the MSB of
stream data is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to
SDO0.
To guarantee all codecs can determine their corresponding stream, the command stream is not striped. It
is always transmitted on SDO0, and copied on SDO1.
Figure 9. Striped Stream on Multiple SDOs
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Datasheet
7.2.3.
Inbound Frame – Single SDI
An Inbound Frame – Single SDI is composed of one 36-Bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each
rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 10).
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-Bit stream tag, one 6-Bit data length, and n-Bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte
length (Figure 11).
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams
Previous Frame
Frame SYNC
Next Frame
SYNC
SDI
0s
Stream 'X'
Response Stream
Stream 'A'
Null Field
Padded at the end of Frame
Stream Tag
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples
Block 1
...
Block Y Null Pad
Block 2
Sample 1 Sample 2
msb ...
...
Sample Z Z channels of PCM Sample
lsb
msb first in a sample
Figure 10. SDI Inbound Stream
BCLK
SDI
n-Bit Sample Block
Null Pad
Next Stream
Stream Tag
Data Length in Bytes
B
B
B
B
B
B
D
D
0
0
B
B
B
B
D
0
0
0
8
7
6
5
4
3
2
1
0
n-1 n-2
9
(Data Length in Bytes *8)-Bit
A Complete Stream
Figure 11. SDI Stream Tag and Data
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Datasheet
7.2.4.
Inbound Frame – Multiple SDI
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data onto separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
SYNC
Frame SYNC
Stream 'A'
SDI
Tag A
Data A
Response Stream
Stream 'X'
0s
Stream 'Y'
0s
0
Stream 'B'
Data B
SDI
Response Stream
Tag B
1
Stream A, B, X, and Y are independent and have separate IDs
Codec drives SDI0 and SDI1
Figure 12. Codec Transmits Data Over Multiple SDIs
7.2.5.
Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table 7, page 17, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, page 17, shows the delivery cadence
of variable rates based on 48kHz.
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames.
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Datasheet
The cadence ‘12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)’interleaves 13 frames containing no
sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery
rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence AND interleave n empty frames.
Rates in multiples (n) of 44.1kHz applying this cadence contain n sample blocks in the non-empty frame
AND interleave an empty frame between non-empty frames (Table 9, page 18).
Table 7. Defined Sample Rate and Transmission Rate
(Sub) Multiple 48kHz Base
44.1kHz Base
1/6
1/4
1/3
1/2
2/3
1
8kHz (1 sample block every 6 frames)
-
12kHz (1 sample block every 4 frames)
16kHz (1 sample block every 3 frames)
-
11.025kHz (1 sample block every 4 frames)
-
22.05kHz (1 sample block every 2 frames)
-
32kHz (2 sample blocks every 3 frames)
48kHz (1 sample block per frame)
96kHz (2 sample blocks per frame)
192kHz (4 sample blocks per frame)
44.1kHz (1 sample block per frame)
88.2kHz (2 sample blocks per frame)
176.4kHz (4 sample blocks per frame)
2
4
Table 8. 48kHz Variable Rate of Delivery Timing
Rate
8kHz
Delivery Cadence
YNNNNN (repeat)
YNNN (repeat)
YNN (repeat)
Y2NN (repeat)
Y (repeat)
Description
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 4 frames
One sample block is transmitted in every 3 frames
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 6 frames
Two sample blocks are transmitted in each frame
Four sample blocks are transmitted in each frame
Yx: X sample blocks in a frame.
12kHz
16kHz
32kHz
48kHz
96kHz
192kHz
Y2 (repeat)
Y4 (repeat)
N: No sample block in a frame.
Y: One sample block in a frame.
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Datasheet
Table 9. 44.1kHz Variable Rate of Delivery Timing
Delivery Cadence
Rate
11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
22.05kHz
{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
44.1kHz
88.2kHz
174.4kHz
12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)
124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{ - }=NNNN
22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN
{11}=YNYNYNYNYNYNYNYNYNYNYN
{ - }=NN
44.1kHz: 12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with no
sample block.
88.2kHz: 122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with no
sample block.
176.4kHz: 124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with no
sample block.
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Datasheet
7.3. Reset and Initialization
There are two types of reset within an HDA link:
• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default
state
An initialization sequence is requested after any of the following three events:
1. Link Reset
2. Codec Reset
3. Codec changes its power state (For example, hot docking a codec to an HDA system)
7.3.1.
Link Reset
A link reset may be caused by 3 events:
1. The HDA controller asserts RST# for any reason (power up, or PCI reset)
2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
3. Software initiates power management sequences. Figure 13, page 20, shows the ‘Link Reset’ timing
including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)
Enter ‘Link Reset’:
n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
link reset
o As the controller completes the current frame, it does not signal the normal 8-Bit frame SYNC at the
end of the frame
p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state
r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
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Exit from ‘Link Reset’:
s If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
t Software is responsible for de-asserting RST# after a minimum of 100µsec BCLK running time (the
100µsec provides time for the codec PLL to stabilize)
u Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
v When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
last bit of frame SYNC, it means the codec requests an initialization sequence)
>=100 usec >= 4 BCLK
Initialization Sequence
Previous Frame
4 BCLK
4 BCLK
Link in Reset
BCLK
SYNC
SDOs
SDIs
Normal Frame
SYNC
Normal Frame
SYNC is absent
Driven Low
Pulled Low
2
8
Driven Low
Driven Low
Pulled Low
Pulled Low
Wake Event
9
RST#
Pulled Low
1
3
4
5
6
7
Figure 13. Link Reset Timing
7.3.2.
Codec Reset
A ‘Codec Reset’ is initiated via the Codec RESET command verb. It results in the target codec being
reset to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
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7.3.3.
Codec Initialization Sequence
n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller
o The codec will stop driving the SDI during this turnaround period
pqrs The controller drives SDI to assign a CAD to the codec
t The controller releases the SDI after the CAD has been assigned
u Normal operation state
Figure 14. Codec Initialization Sequence
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7.4. Verb and Response Format
7.4.1.
Command Verb Format
There are two types of verbs: one with 4-Bit identifiers (4-Bit verbs) and 16-Bits of data, the other with
12-Bit identifiers (12-Bit verbs) and 8-Bits of data. Table 10 shows the 4-Bit verb structure of a command
stream sent from the controller to operate the codec. Table 11 is the 12-Bit verb structure that gets and
controls parameters in the codec.
Table 10. 40-Bit Commands in 4-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Bit [15:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
Table 11. 40-Bit Commands in 12-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Bit [7:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
7.4.2.
Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-Bit Response is interpreted by
software, opaque to the controller.
Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Table 12. Solicited Response Format
Bit [35]
Bit [34]
Bit [33:32]
Bit [31:0]
Valid
Unsol=0
Reserved
Response
Table 13. Unsolicited Response Format
Bit [35]
Valid
Bit [34]
Unsol=1
Bit [33:32]
Bit [31:28]
Tag
Bit [27:0]
Response
Reserved
Note: The response stream in the link protocol is 36-Bits wide. The response is placed in the lower 32-bit
field. Bit-35 is a ‘Valid’ bit to indicate the response is ‘Ready’. Bit-34 is set to indicate that an unsolicited
response was sent.
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7.5. Power Management
All power management state changes in widgets are driven by software. Table 14 shows the System
Power State Definitions.
In the ALC269, all the widgets include output/input converters support power control. Software may have
various power states depending on system configuration.
Table 15 indicates those nodes that support power management. To simplify power control, software can
configure whole codec power states through the audio function (NID=01h). Output converters (DACs)
and input converters (ADCs) have no individual power control to supply fine-grained power control.
Table 14. System Power State Definitions
Power States Definitions
D0
D1
All power on. Individual DACs and ADCs can be powered up or down as required.
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog
reference stays up.
D2
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog
reference off (D1 + analog reference off).
D3 (Hot)
Power still supplied. The codec stops the internal clock. State is maintained.
All power removed. State lost.
D3 (Cold)
Table 15. Power Controls in NID=01h
Description
Audio Function LINK Response
D0
D1
D2
Normal
PD
D3 (Hot/Cold)
Link Reset
PD
Normal
Normal
Normal
Normal
Normal
Normal
Normal
PD
PD
PD
PD
PD
PD
PD
(NID=01h)
DACs
PD
ADCs
PD
PD
PD
All Headphone Drivers
All Mixers
Normal
Normal
Normal
PD
Normal
Normal
Normal
PD
All Reference
PD
Note: PD=Powered Down
Table 16. Powered Down Conditions
Condition
Description
LINK Response powered down
Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with pulled low
47K resistors internally. Detection of ‘Link Reset Entry’ and ‘Link Reset Exit’
sequences are supported. All states are maintained if DVDD is supplied.
DAC powered down
Analog block and digital filter are powered down.
ADC powered down
Analog block and digital filter are powered down. The data on SDATA-IN is quiet.
All headphone drivers are powered down.
Headphone Driver powered down
Mixers powered down
All internal mixer widgets are powered down. The DC reference and VREFOUTx
at individual pin complexes are still alive.
Reference power down
All internal references, DC reference, and VREFOUTx at individual pin complexes
are off.
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8. Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC269. If a verb is
not supported by the addressed widget, it will respond with 32 bits of ‘0’.
8.1. Verb – Get Parameters (Verb ID=F00h)
The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. Refer to section 7.4.1 Command Verb Format, page 22, to get
detailed information about supported parameters.
Table 17. Verb – Get Parameters (Verb ID=F00h)
Get Parameter Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Cad=X
Node ID=00h
Verb ID=F00h
Parameter ID[7:0]
32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.
8.1.1.
Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Codec Response Format
Bit
31:16
15:0
Description
Vendor ID=10ECh (Realtek’s PCI vendor ID).
Device ID=0269h.
Note: The Root Node (NID=00h) supports this parameter.
8.1.2.
Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Codec Response Format
Bit
Description
31:24
23:20
19:16
15:8
Reserved. Read as 0’s.
MajRev. The major version number (in decimal) of the HDA Spec to which the ALC269 is fully compliant.
MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC269 is fully compliant.
Revision ID. The vendor’s revision number.
00h is for the first silicon version A, 01h is for the second version B, etc.
7:0
Stepping ID. The vendor’s stepping number within the given Revision ID.
Note: The Root Node (NID=00h in the ALC269) supports this parameter.
For example, Revision ID=00h and Stepping ID=01h indicates the silicon is the A1 version.
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8.1.3.
Parameter – Subordinate Node Count
(Verb ID=F00h, Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node. For function group nodes, it provides the total number of widgets
associated with this function node.
Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Codec Response Format
Bit
31:24
23:16
15:8
7:0
Description
Reserved. Read as 0’s.
Starting Node Number. The starting node number in the sequential widgets.
Reserved. Read as 0’s.
Total Number of Nodes. For a root node, the total number of function groups in the root node.
For a function group, the total number of widget nodes in the function group.
8.1.4.
Parameter – Function Group Type
(Verb ID=F00h, Parameter ID=05h)
Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)
Codec Response Format
Bit
31:9
8
Description
Reserved. Read as 0’s.
UnSol Capable.
0: Unsolicited response is not supported by this function group
1: Unsolicited response is supported by this function group
7:0
Function Group Type.
00h: Reserved
01h: Audio Function
02h: Modem Function
03h~7Fh: Reserved
80h~FFh: Vendor Defined Function.
Note: The Audio Function Group (NID=01h) supports this parameter.
8.1.5.
Parameter – Audio Function Capabilities
(Verb ID=F00h, Parameter ID=08h)
Table 22. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Codec Response Format
Bit
31:17
16
Description
Reserved. Read as 0’s.
Beep Generator.
A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group.
15:12
11:8
7:4
Reserved. Read as 0’s.
Input Delay.
Reserved. Read as 0’s.
Output Delay.
3:0
Note: The Audio Function Group (NID=01h) supports this parameter.
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8.1.6.
Parameter – Audio Widget Capabilities
(Verb ID=F00h, Parameter ID=09h)
Table 23. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s.
Widget Type.
0h: Audio Output
3h: Selector
6h: Volume Knob Widget
1h: Audio Input
4h: Pin Complex
7h~Eh: Reserved
2h: Mixer
5h: Power Widget
Fh: Vendor defined audio widget
19:16
15:11
10
Delay. Samples delayed between the HDA link and widgets.
Reserved. Read as 0’s.
Power Control.
0: Power state control is not supported on this widget
1: Power state is supported on this widget
Digital.
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (S/PDIF, I2S, etc.)
ConnList. Connection List.
0: Connected to HDA link. No Connection List Entry should be queried
1: Connection List Entry must be queried
UnsolCap. Unsolicited Capable.
0: Unsolicited response is not supported
1: Unsolicited response is supported
ProcWidget. Processing Widget.
0: No processing control
9
8
7
6
1: Processing control is supported
Reserved. Read as 0.
5
4
3
2
1
0
Format Override.
AmpParOvr. AMP Param Override.
OutAmpPre. Out AMP Present.
InAmpPre. In AMP Present.
Stereo.
0: Mono Widget
1: Stereo Widget
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8.1.7.
Parameter – Supported PCM Size, Rates
(Verb ID=F00h, Parameter ID=0Ah)
Parameter in audio function provides default information about formats. Individual converters have their
own parameters to provide supported formats if their ‘Format Override’ bit is set.
Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Codec Response Format
Bit
31:21
20
Description
Reserved. Read as 0’s.
B32. Indicates whether 32-Bit audio format is supported.
0: Not supported
B24. Indicates whether 24-Bit audio format is supported.
0: Not supported 1: Supported
B20. Indicates whether 20-Bit audio format is supported.
0: Not supported 1: Supported
B16. Indicates whether 16-Bit audio format is supported.
0: Not supported 1: Supported
B8. Indicates whether 8-Bit audio format is supported.
1: Supported
19
18
17
16
0: Not supported
1: Supported
15:12
11
Reserved. Read as 0’s.
R12. Indicates whether 384kHz (=8*48kHz) rate is supported.
0: Not supported 1: Supported
R11. Indicates whether 192kHz (=4*48kHz) rate is supported.
0: Not supported 1: Supported
R10. Indicates whether 176.4kHz (=4*44.1kHz) rate is supported.
0: Not supported 1: Supported
R9. Indicates whether 96kHz (=2*48kHz) rate is supported.
0: Not supported 1: Supported
R8. Indicates whether 88.2kHz (=2*44.1kHz) rate is supported.
0: Not supported 1: Supported
10
9
8
7
6
5
4
3
2
1
0
R7. Indicates whether 48kHz rate is supported.
0: Not supported 1: Supported
R6. Indicates whether 44.1kHz rate is supported.
0: Not supported
R5. Indicates whether 32kHz (=2/3*48kHz) rate is supported.
0: Not supported 1: Supported
R4. Indicates whether 22.05kHz (=1/2*44.1kHz) rate is supported.
0: Not supported 1: Supported
R3. Indicates whether 16kHz (=1/3*48kHz) rate is supported.
0: Not supported 1: Supported
R2. Indicates whether 11.025kHz (=1/4*44.1kHz) rate is supported.
0: Not supported 1: Supported
R1. Indicates whether 8kHz (=1/6*48kHz) rate is supported.
0: Not supported 1: Supported
1: Supported
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8.1.8.
Parameter – Supported Stream Formats
(Verb ID=F00h, Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the ‘Format Override’ bit is set.
Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Codec Response Format
Bit
31:3
2
Description
Reserved. Read as 0’s.
AC3.
0: Not supported
Float32.
0: Not supported
PCM.
1: Supported
1: Supported
1: Supported
1
0
0: Not supported
Note: Input converters and output converters support this parameter.
8.1.9.
Parameter – Pin Capabilities
(Verb ID=F00h, Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 26. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
Codec Response Format
Bit
31:16
15:8
Description
Reserved. Read as 0’s.
VREF Control Capability.
‘1’ in corresponding bit field indicates signal levels of associated Vrefout are specified as a percentage of
AVDD.
7:6
5
4
3
2
1
0
Reserved
100%
80%
Reserved
Ground
50%
Hi-Z
7
6
5
4
3
2
1
0
L-R Swap. Indicates the capability of swapping the left and rights.
Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins.
Input Capable. ‘1’ indicates this pin complex supports input.
Output Capable. ‘1’ indicates this pin complex supports output.
Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone.
Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in.
Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement.
Impedance Sense Capable. ‘1’ indicates this pin complex can perform analog sense on the attached
device to determine its type.
Note: Only Pin Complex widgets support this parameter.
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8.1.10. Parameter – Amplifier Capabilities
(Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 27. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Codec Response Format
Bit
31
Description
(Input) Mute Capable.
30:23
22:16
Reserved. Read as 0.
Step Size.
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB.
Reserved. Read as 0.
15
14:8
7
Number of Steps. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.
Reserved. Read as 0.
6:0
Offset. Indicates which step is 0dB.
8.1.11. Parameter – Amplifier Capabilities
(Verb ID=F00h, Output Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 28. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Codec Response Format
Bit
31
Description
(Output) Mute Capable.
30:23
22:16
Reserved. Read as 0.
Step Size.
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB.
Reserved. Read as 0.
15
14:8
7
Number of Steps. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.
Reserved. Read as 0.
6:0
Offset. Indicates which step is 0dB.
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8.1.12. Parameter – Connect List Length
(Verb ID=F00h, Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Codec Response Format
Bit
31:8
7
Description
Reserved. Read as 0.
Short Form.
0: Short Form
1: Long Form
6:0
Connect List Length.
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one
input, and there is no Connection Select Control (Not a MUX widget).
8.1.13. Parameter – Supported Power States
(Verb ID=F00h, Parameter ID=0Fh)
Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Codec Response Format
Bit
31:4
3
Description
Reserved. Read as 0’s.
D3Sup.
1: Power state D3 is supported.
D2Sup.
1: Power state D2 is supported.
D1Sup.
1: Power state D1 is supported.
D0Sup
2
1
0
1: Power state D0 is supported.
8.1.14. Parameter – Processing Capabilities
(Verb ID=F00h, Parameter ID=10h)
Table 31. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Codec Response Format
Bit
31:16
15:8
7:1
Description
Reserved. Read as 0’s.
NumCoeff. Number of Coefficient.
Reserved. Read as 0’s.
0
Benign.
0: Processing unit is not linear and time invariant
1: Processing unit is linear and time invariant
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8.1.15. Parameter – GPIO Capabilities
(Verb ID=F00h, Parameter ID=11h)
Table 32. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Codec Response Format
Bit
Description
31
GPIWake=0.
The ALC269 does not support GPIO wake up function.
GPIUnsol=1.
30
The ALC269 supports GPIO unsolicited response.
Reserved. Read as 0’s.
NumGPIs=00h.
29:24
23:16
No GPI pin is supported.
NumGPOs=00h.
No GPO pin is supported.
NumGPIOs=02h.
15:8
7:0
Two GPIO pins are supported.
8.1.16. Parameter – Volume Knob Capabilities
(Verb ID=F00h, Parameter ID=13h)
Table 33. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Codec Response Format
Bit
31:8
7
Description
Reserved. Read as 0’s.
Delta.
0: Software cannot modify the Volume Control Knob volume
1: Software can write a base volume to the Volume Control Knob
NumSteps.
6:0
The number of steps in the range of the Volume Control Knob.
Note: The ALC269 does not support volume control knob.
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8.2. Verb – Get Connection Select Control (Verb ID=F01h)
Table 34. Verb – Get Connection Select Control (Verb ID=F01h)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Verb ID=F01h
0’s
Bit[7:0] are Connection Index
Codec Response for Multiplexer Widget NID=14h~15h, 18h~1Bh
Bit
31:8
7:0
Description
0’s.
Connection Index currently Set (Default value is 00h).
00h: Pin Widget NID=0Ch
01h: Pin Widget NID=0Dh
Other: Reserved
Codec Response for Multiplexer Widget NID=23h
Bit
31:8
7:0
Description
0’s.
Connection Index Currently Set (Default value is 00h).
00h: Pin Widget NID=18h
02h: Pin Widget NID=1Ah
04h: Pin Widget NID=1Dh
06h: Mixer Widget NID=0Bh
01h: Pin Widget NID=19h
03h: Pin Widget NID=1Bh
05h: Pin Widget NID=12h
Other: Reserved
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.3. Verb – Set Connection Select (Verb ID=701h)
Table 35. Verb – Set Connection Select (Verb ID=701h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Verb ID=701h
Select Index [7:0]
0’s for all nodes
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8.4. Verb – Get Connection List Entry (Verb ID=F02h)
Table 36. Verb – Get Connection List Entry (Verb ID=F02h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh Verb ID=F02h
Offset Index – N[7:0]
32-bit Response
Returns 00h for N>3.
Returns 00h for N>3.
Codec Response for NID=07h ADC
Bit
Description
31:8
Connection List Entry (N+3), (N+2), (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 24h (Sum Widget) for N=0~3.
Codec Response for NID=08h ADC
Bit
Description
31:8
Connection List Entry (N+3), (N+2), (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 23h (Sum Widget) for N=0~3.
Codec Response for NID=0Ch
Bit
Description
31:16
Connection List Entry (N+3), (N+2).
Returns 0000h.
15:8
7:0
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 02h (LOUT1 DAC) for N=0~3.
Codec Response for NID=0Dh
Bit
Description
31:16
Connection List Entry (N+3), (N+2).
Returns 0000h.
15:8
7:0
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 03h (LOUT2 DAC) for N=0~3.
Codec Response for NID=0Eh
Bit
Description
31:16
Connection List Entry (N+3), (N+2).
Returns 0000h.
15:8
7:0
Connection List Entry (N+1).
Returns 0Dh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 0Ch (Mixer) for N=0~3.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
33
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
Codec Response for NID=14h~15h, 18h~1Bh
Bit
Description
31:16
Connection List Entry (N+3), (N+2).
Returns 0000h.
15:8
7:0
Connection List Entry (N+1).
Returns 0Dh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 0Ch (Mixer) for N=0~3.
Codec Response for NID=16h
Bit
Description
31:8
Connection List Entry (N+3), (N+2), (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 0Eh (Mixer) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Returns 00h for N>3.
Codec Response for NID=1Eh)
Bit
Description
31:8
Connection List Entry (N+3, (N+2), (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Return 06h (First S/PDIF-OUT converter) for N=0~3.
Codec Response for NID=11h)
Bit
Description
31:8
Connection List Entry (N+3, (N+2), (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Return 10h (Secondary S/PDIF-OUT converter) for N=0~3.
Codec Response for NID=23h (MUX Widget)
Bit
Description
31:24
Connection List Entry (N+3).
Return 1Bh (Pin Complex - LINE2) for N=0~3.
Return 00h for N>3.
Return 00h for N>7.
Return 00h for N>7.
Return 00h for N>7.
23:16
15:8
7:0
Connection List Entry (N+2).
Return 1Ah (Pin Complex - LINE1) for N=0~3.
Return 0Bh (Mixer Widget) for N=4~7.
Connection List Entry (N+1).
Return 19h (Pin Complex - MIC2) for N=0~3.
Return 12h (Pin Complex – DMIC-DATA) for N=4~7.
Connection List Entry (N).
Return 18h (Pin Complex - MIC1) for N=0~3.
Return 1Dh (Pin Complex - PCBEEP) for N=4~7.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
34
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
Codec Response for NID=24h (Mixer Widget)
Bit
Description
31:24
Connection List Entry (N+3).
Return 1Bh (Pin Complex - LINE2) for N=0~3.
Return 00h for N>3.
Return 00h for N>3.
23:16
15:8
Connection List Entry (N+2).
Return 1Ah (Pin Complex - LINE1) for N=0~3.
Connection List Entry (N+1).
Return 19h (Pin Complex - MIC2) for N=0~3.
Return 0Bh (Mixer Widget) for N=4~7.
Return 00h for N>3.
Return 00h for N>7.
7:0
Connection List Entry (N).
Return 18h (Pin Complex - MIC1) for N=0~3.
Return 1Dh (Pin Complex - PCBEEP) for N=4~7.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.5. Verb – Get Processing State (Verb ID=F03h)
Table 37. Verb – Get Processing State (Verb ID=F03h)
Get Command Format
Codec Response Format
Response [31:0]
32-bit response
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Cad=X
Node ID=Xh Verb ID=F03h
0’s
Codec Response for All NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.6. Verb – Set Processing State (Verb ID=703h)
Table 38. Verb – Set Processing State (Verb ID=703h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh Verb ID=703h
Processing State [7:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
35
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.7. Verb – Get Coefficient Index (Verb ID=Dh)
Table 39. Verb – Get Coefficient Index (Verb ID=Dh)
Get Command Format
Codec Response Format
Response [31:0]
Bit [15:0] are Coefficient Index
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Cad=X
Verb ID=Dh
0’s
Codec Response for NID=20h (Realtek Vendor Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s.
Coefficient Index.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.8. Verb – Set Coefficient Index (Verb ID=5h)
Table 40. Verb – Set Coefficient Index (Verb ID=5h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=5h
Coefficient Index [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
36
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.9. Verb – Get Processing Coefficient (Verb ID=Ch)
Table 41. Verb – Get Processing Coefficient (Verb ID=Ch)
Get Command Format
Codec Response Format
Response [31:0]
Processing Coefficient [15:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Cad=X
Verb ID=Ch
0’s
Codec Response for NID=20h (Realtek Vendor Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s.
Processing Coefficient.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.10. Verb – Set Processing Coefficient (Verb ID=4h)
Table 42. Verb – Set Processing Coefficient (Verb ID=4h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Cad=X
Verb ID=4h
Coefficient [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
37
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.11. Verb – Get Amplifier Gain (Verb ID=Bh)
This verb is used to get gain/attenuation settings from each widget.
Table 43. Verb – Get Amplifier Gain (Verb ID=Bh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=Bh
‘Get’ payload [15:0]
Bit[7:0] are responsible for ‘Get’
‘Get’ Payload in Command Bit[15:0]
Bit
Description
15
Get Input/Output.
0: Input amplifier gain is requested
1: Output amplifier gain is requested
Reserved. Read as 0.
14
13
Get Left/Right.
0: Right amplifier gain is requested
1: Left amplifier gain is requested
Reserved. Read as 0’s.
12:4
3:0
Index[3:0] for Input Source.
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored.
Codec Response for NID=02h (LOUT1 DAC) and 03h (LOUT2 DAC)
Bit
31:8
7
Description
0’s.
Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Mute).
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Gain).
6:0
Payload[15] is 1 in ‘Get Amplifier Gain’: 6-bit control specifying the volume from–63dB~ +1dB in 1dB
step.
Node
Gain[6:0] (Default)
1000000b=3Fh (0dB)
1000000b=3Fh (0dB)
Gain Range
LOUT1 DAC(NID=02h)
LOUT2 DAC (NID=03h)
–63dB~+1dB in 1dB step
–63dB~+1dB in 1dB step
Codec Response for NID=0Ch, 0Dh and 0Eh (Mixer)
Bit
31:8
7
Description
0’s.
Payload[15] is 0 in ‘Get Amplifier Gain’: 1: Mute, 0:Unmute (Input Amplifier Mute).
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Gain).
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Gain).
6:0
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
38
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
Codec Response for NID=18h, 19h, 1Ah and 1Bh (Pin widget: MIC1, MIC2, LINE1 and LINE2)
Bit
31:8
7
Description
0’s.
Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Mute).
Payload[15] is 1 in ‘Get Amplifier Gain’: 1: Mute, 0:Unmute (Output Amplifier Mute, default=1).
6:0
Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
The volume 0dB/10dB/20dB/30dB in 10dB per step (default=0, 0dB).
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
Codec Response for NID=14h, 15h and 16h (Pin widget: SPK-OUT, HP-OUT and MONO-OUT)
Bit
31:8
7
Description
0’s.
Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Mute).
Payload[15] is 1 in ‘Get Amplifier Gain’: 1: Mute, 0:Unmute (Output Amplifier Mute, default=1).
6:0
Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Gain).
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
Codec Response for NID=0Bh (Mixer)
Bit
31:8
7
Description
0’s.
Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. 0: Unmute, 1: Mute (Default for all)
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
6:0
Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
Specifying the volume from -34.5dB~+12dB in 1.5dB step (Default: 17h, 0dB).
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
Index=0
(MIC1)
Index=1
(MIC2)
Index=2
(LINE1)
Index=3
(LINE2)
Index=4
(PCBEEP)
Index>5
(Other)
Mute [7]
Gain [6:0]
Default[7:0]
0/1
0s
0/1
0s
0/1
0s
0/1
0s
0/1
0s
0
0
10010111
10010111
10010111
10010111
10010111
00000000
Codec Response for NID=07h, 08h (ADCs)
Bit
31:8
7
Description
0’s.
Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. 0: Unmute, 1: Mute (Default)
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
6:0
Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
Specifying the volume from –17dB~ 29dB in 1.0dB step.
Node
Gain[6:0] Default
0010001b=11h (0dB)
0010001b=11h (0dB)
Gain Range
MIC ADC(NID=07h)
LINE ADC( NID=08h)
–17dB~29dB in 1.0dB step
–17dB~29dB in 1.0dB step
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
39
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
Codec Response for NID=24h (Mixer)
Bit
31:8
7
Description
0’s.
Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. 0: Unmute, 1: Mute (Default for all)
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
6:0
Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
Index=0
(MIC1)
Index=1
(MIC2)
Index=2
(LINE1)
Index=3
(LINE2)
Index=4
(PCBEEP)
Index=5
(Mixer )
Index>5
(Other)
Mute [7]
Gain [6:0]
Default[7:0]
0/1
0s
0/1
0s
0/1
0s
0/1
0s
0/1
0s
0/1
0s
0
0
10000000
10000000
10000000
10000000
10000000
10000000
00000000
Codec Response to Other NID
Bit
Description
Not Supported (returns 00000000h).
31:0
8.12. Verb – Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 44. Verb – Set Amplifier Gain (Verb ID=3h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Cad=X
Node ID=Xh
Verb ID=3h
‘Set’ payload [7:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
15
Description
Set Output Amp. 1 indicates output amplifier gain will be set.
Set Input Amp. 1 indicates input amplifier gain will be set.
Set Left Amp. 1 indicates left amplifier gain will be set.
14
13
12
Set Right Amp. 1 indicates right amplifier gain will be set.
Index Offset (for input amplifiers on Sum widgets and Selector Widgets).
11:8
5 bits index offset in connection list is used to select which input gain will be set on a mixer or a
multiplexer widget. The index is ignored if the node is not a mixer or a multiplexer widget, or the ‘Set
Input Amp’ bit is not set.
7
Mute.
0: Unmute
1: Mute (-∞gain)
6:0
Gain[6:0]. A 7-bit step value specifying the amplifier gain.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
40
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.13. Verb – Get Converter Format (Verb ID=Ah)
Table 45. Verb – Get Converter Format (Verb ID=Ah)
Get Command Format
Codec Response Format
Response [31:0]
Bit[15:0] are converter format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Cad=X
Verb ID=Ah
0’s
Codec Response for NID=02h, 03h, 06h, 10h (Output Converters: LOUT1 DAC, LOUT2 DAC, S/PDIF-OUT,
S/PDIF-OUT2). Codec Response for NID=07h, 08h (Input Converters: MIC ADC, LINE ADC)
Bit
31:16
15
Description
Reserved. Read as 0.
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
10:8
Sample Base Rate Multiple (MULT).
000b: *1
001b: *2
010b: *3
011b: *4
011b: /4
100b~111b: Reserved.
100b: /5
Sample Base Rate Divisor (DIV).
000b: /1
101b: /6
001b: /2
110b: /7
010b: /3
111b: /8
The ALC269 does not support Divisor. Always read as 000b.
7
Reserved. Read as 0.
6:4
Bits per Sample (BITS).
000b: 8 bits
101b~111b: Reserved
Number of Channels.
0: 1 channel
001b: 16 bits
010b: 20 bits
2: 3 channels
011b: 24 bits
.........
100b: 32 bits
3:0
1: 2 channels
15: 16 channels
BASE MULT
DIV
BITS
Sample Rate
48K, 96K,192K
44.1K
48K, 96K,192K
44.1K
NID=02h (LOUT1 DAC)
NID=03h (LOUT2 DAC)
NID=06h (S/PDIF-OUT)
0
1
0
1
0
1
0
0
1
0
0
1
0
1
000b, 001b, 011b
000b
000b, 001b, 011b
000b
000b, 001b, 011b
000b, 001b
001b
000b, 001b, 011b
000b, 001b
001b
000b
000b
000b
000b
000b
000b
010b
000b
000b
010b
000b
000b
000b
000b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b, 100b 48K, 96K, 192K
001b, 010b, 011b, 100b 44.1K, 88.2K
001,010b, 011b
001b, 010b, 011b, 100b 48K, 96K, 192K
001b, 010b, 011b, 100b 44.1K, 88.2K
001,010b, 011b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b
32K
NID=10h (S/PDIF-OUT2)
32K
48K, 96K
44.1K
48K, 96K
44.1K
NID=07h (MIC ADC)
NID=08h (LINE ADC)
000b, 001b
000b
000b, 001b
000b
Codec Response for other NID
Bit
31:0
Description
Not Supported (returns 00000000h).
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
41
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.14. Verb – Set Converter Format (Verb ID=2h)
Table 46. Verb – Set Converter Format (Verb ID=2h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Cad=X
Verb ID=2h
Set format [15:0]
‘Set’ Payload in Command Bit[15:0]
Bit
31:16
15
Description
Reserved. Read as 0.
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
Sample Base Rate Multiple (MULT).
000b: *1
011b: *4
001b: *2
100b~111b: Reserved.
010b: *3
10:8
Sample Base Rate Divisor (DIV).
000b: /1
011b: /4
110b: /7
001b: /2
100b: /5
111b: /8
010b: /3
101b: /6
7
Reserved. Read as 0.
6:4
Bits per Sample (BITS).
000b: 8 bits
001b: 16 bits
010b: 20 bits
011b: 24 bits
Number of Channels.
0: 1 channel
.........
100b: 32 bits
1: 2 channels
101b~111b: Reserved
3:0
2: 3 channels
15: 16 channels
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
42
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.15. Verb – Get Power State (Verb ID=F05h)
Table 47. Verb – Get Power State (Verb ID=F05h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=F05h
0’s
Power State [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:6
5:4
Description
Reserved. Read as 0’s.
PS-Act. Actual Power State [1:0].
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set.
3:2
1:0
Reserved. Read as 0’s.
PS-Set, Set Power State [1:0].
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Set controls the current power setting of the referenced node.
Note: Specific blocks will be powered down in each power state. Refer to section 7.5 Power Management, page 23.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.16. Verb – Set Power State (Verb ID=705h)
Table 48. Verb – Set Power State (Verb ID=705h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Cad=X
Node ID=Xh
Verb ID=705h
Power State [7:0]
0’s for all nodes
‘Power State’ in Command Bit[7:0]
Bit
7:6
5:4
Description
Reserved. Read as 0’s.
PS-Act. Actual Power State [1:0].
00: Power state is D0
PS-Act indicates the actual power state of the referenced node.
Reserved. Read as 0’s.
01: Power state is D1
10: Power state is D2
11: Power state is D3
11: Power state is D3
3:2
1:0
PS-Set. Set Power State [1:0].
00: Power state is D0
01: Power state is D1
10: Power state is D2
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
43
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.17. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh Verb ID=F06h
0’s
Stream & Channel [7:0]
Codec Response for NID=02h, 03h, 06h, 10h (Output Converters: LOUT1 DAC, LOUT2 DAC, S/PDIF-OUT, and
S/PDIF-OUT2).
Codec Response for NID=07h, 08h (Input Converters: MIC ADC, LINE ADC)
Bit
31:8
7:4
Description
Reserved. Read as 0’s.
Stream[3:0].
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Channel[3:0].
3:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for
its left and right channel.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.18. Verb – Set Converter Stream, Channel (Verb ID=706h)
Table 50. Verb – Set Converter Stream, Channel (Verb ID=706h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh Verb ID=706h Stream & Channel [7:0]
0’s for all nodes
‘Stream and Channel’ in Command Bit[7:0]
Bit
31:8
7:4
Description
Reserved. Read as 0’s.
Set Stream[3:0].
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Set Channel[3:0].
1:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for
its left and right channel.
Note: This verb assigns stream and channel for output converters (NID=02h, 03h, 06h, 10h) and input converters
(NID=07h, 08h). Other widgets will ignore this verb.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
44
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.19. Verb – Get Pin Widget Control (Verb ID=F07h)
Table 51. Verb – Get Pin Widget Control (Verb ID=F07h)
Get Command Format
Codec Response Format
Response [31:0]
Pin Control [7:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Verb ID=F07h
Payload Bit [7:0]
Cad=X
0’s
Codec Response for pin widget NID=12h, 14h, 15h, 16h, 18h~1Bh, 1Dh, 1Eh and 11h. (Pin Complex: DMIC-DATA,
SPK-OUT, HP-OUT, MONO-OUT, MIC1, MIC2, LINE1, LINE2, PCBEEP, S/PDIF_OUT, and S/PDIF-OUT2).
Bit
31:1
7
Description
Reserved. Read as 0’s.
H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O unit).
0: Disabled
Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit).
0: Disabled 1: Enabled.
In Enable (Input Buffer Enable, EN_IBUF for an I/O unit).
1: Enabled.
6
5
0: Disabled
1: Enabled.
4:3
2:0
Reserved.
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled)
010b: Ground 0V
100b: 80% of AVDD
001b: 50% of AVDD
011b: Reserved
101b: 100% of AVDD
110b~111b: Reserved
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.20. Verb – Set Pin Widget Control (Verb ID=707h)
Table 52. Verb – Set Pin Widget Control (Verb ID=707h)
Set Command Format
Codec Response Format
Bit [31:28]
Cad=X
Bit [27:20]
Node ID=Xh
Bit [19:8]
Verb ID=707h
Payload Bit [7:0]
Pin Control [7:0]
Response [31:0]
0’s for all nodes
‘Pin Control’ in command [7:0]: pin widget NID=12h, 14h, 15h, 16h, 18h~1Bh, 1Dh, 1Eh and 11h. (Pin Complex:
DMIC-DATA, SPK-OUT, HP-OUT, MONO-OUT, MIC1, MIC2, LINE1, LINE2, PCBEEP, S/PDIF_OUT, and
S/PDIF-OUT2).
Bit
31:1
7
Description
Reserved. Read as 0’s.
H-Phn Enable.
0: Disabled
1: Enabled
1: Enabled
6
5
Out Enable.
0: Disabled
In Enable (Input Buffer Enable, EN_IBUF for an I/O unit).
0: Disabled
1: Enabled
4:
Reserved.
2:0
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled)
010b: Ground 0V
001b: 50% of AVDD
011b: Reserved
100b: 80% of AVDD)
101b: 100% of AVDD
110b~111b: Reserved
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
45
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.21. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real time event.
Table 53. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Verb ID=F08h
0’s
32-bit Response
Codec Response for NID=01h (GPIO in Audio Function Group), 14h~16h (port jack detect), 18h~1Bh (port jack detect)
Bit
31:8
7
Description
Reserved. Read as 0’s.
Unsolicited Response is Enabled.
0: Disabled
1: Enabled
6:4
3:0
Reserved. Read as 0’s.
Assigned Tag for Unsolicited Response.
The tag[3:0] is assigned by software to determine which widget generates unsolicited responses.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.22. Verb – Set Unsolicited Response Control (Verb ID=708h)
Enable a widget to generate an unsolicited response.
Table 54. Verb – Set Unsolicited Response Control (Verb ID=708h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Verb ID=708h
EnableUnsol [7:0]
0’s for all nodes
‘EnableUnsol’ in Command Bit[7:0]
For NID=01h (GPIO in Audio Function Group), 15h, 18h~1Bh (port jack detect)
Bit
31:8
7
Description
Reserved. Read as 0’s.
Enable Unsolicited Response.
0: Disable
1: Enable
6:4
3:0
Reserved. Read as 0’s.
Tag for Unsolicited Response.
Tag[3:0] is defined by software to assign a 4-bit tag for nodes that are enabled to generate unsolicited
responses.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.23. Verb – Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 55. Verb – Get Pin Sense (Verb ID=F09h)
Get Command Format
Codec Response Format
Response [31:0]
32-bit Response
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Cad=X
Verb ID=F09h
0’s
Codec Response: Pin widget 15h (HP-OUT), 18h (MIC1), 19h (MIC2), 1Ah (LINE1), 1Bh (LINE2)
Bit
Description
31
Presence Detect Status.
0: No device is attached to the pin
1: Device is attached to the pin
Measured Impedance.
30:0
Note: The ALC269 does not support impedance sensing. Read as 0’s.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.24. Verb – Execute Pin Sense (Verb ID=709h)
Table 56. Verb – Execute Pin Sense (Verb ID=709h)
Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=709h
Right Channel[0]
0’s for all nodes
‘Payload’ in Command Bit[7:0]
Bit
7:1
0
Description
Reserved. Read as 0’s.
Right (Ring) Channel Select.
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)
Note: The ALC269 does not support ‘Execute Pin Sense’and will ignore this verb and respond with 0’s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
47
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.25. Verb – Get Configuration Default (Verb ID=F1Ch)
Read the 32-bit sticky register for each Pin Widget configured by software.
Table 57. Verb – Get Configuration Default (Verb ID=F1Ch)
Get Command Format
Codec Response Format
Response [31:0]
32-bit Response
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Cad=X
Verb ID=F1Ch
0’s
Codec Response for Pin Widget: NID=12h (Digital MIC), 14h (SPK-OUT), 15h (HP-OUT), 16h (MONO-OUT), 18h
(MIC1), 19h (MIC2), 1Ah (LINE1), 1Bh (LINE2), 1Dh (PCBEEP), 1Eh (S/PDIF-OUT), 11h (S/PDIF-OUT2)
Bit
Description
31:0
32-bit configuration information for each pin widget.
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).
8.26. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and
1Eh~1Fh such as placement and expected default device.
Table 58. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Verb ID=71Ch,
Label [7:0]
0’s for all nodes
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=12h (Digital MIC), 14h (SPK-OUT), 15h (HP-OUT), 16h (MONO-OUT), 18h
(MIC1), 19h (MIC2), 1Ah (LINE1), 1Bh (LINE2), 1Dh (PCBEEP), 1Eh (S/PDIF-OUT), 11h (S/PDIF-OUT2)
Codec Response for All NID
Bit
Description
31:0
0’s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
48
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.27. Verb – Get BEEP Generator (Verb ID=F0Ah)
Table 59. Verb – Get BEEP Generator (Verb ID=F0Ah)
Get Command Format
Codec Response Format
Response [31:0]
Divider [7:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Cad=X
Verb ID=F0Ah
0’s
‘Response’ for NID=01h (Audio Function Group)
Bit
31:8
7:0
Description
Reserved.
Frequency Divider, F[7:0].
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0].
The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz.
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.28. Verb – Set BEEP Generator (Verb ID=70Ah)
Table 60. Verb – Set BEEP Generator (Verb ID=70Ah)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Verb ID=70Ah
Divider [7:0]
0’s for all nodes
‘Divider’ in Set Command
Bit
31:8
7:0
Description
Reserved.
Frequency Divider, F[7:0].
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0].
The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz.
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
49
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.29. Verb – Get GPIO Data (Verb ID=F15h)
Table 61. Verb – Get GPIO Data (Verb ID=F15h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=01h
Verb ID=F15h
0’s
32-bit Response
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved.
GPIO[7:2] Data. Not supported in the ALC269.
GPIO[1:0] Data.
1:0
The value written (output) or sensed (input) on the corresponding pin if it is enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.30. Verb – Set GPIO Data (Verb ID=715h)
Table 62. Verb – Set GPIO Data (Verb ID=715h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Cad=X
Node ID=01h
Verb ID=715h
Data [7:0]
0’s for all nodes
‘Data’ in Set command for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved.
GPIO[7:2] Output Data. Not supported in the ALC269.
GPIO[1:0] Output Data.
1:0
The value written determines the value driven on a pin that is configured as an output pin.
Codec Response for All NID
Bit
Description
31:0
0’s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
50
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.31. Verb – Get GPIO Enable Mask (Verb ID=F16h)
Table 63. Verb – Get GPIO Enable Mask (Verb ID=F16h)
Get Command Format
Codec Response Format
Response [31:0]
EnableMask [7:0]
Bit [31:28]
Bit [27:20]
Node ID=01h
Bit [19:8]
Payload Bit [7:0]
Cad=X
Verb ID=F16h
0’s
Codec Response for NID=01h (Audio Function Group)
Bit
31:2
1:0
Description
Reserved.
GPIO[1:0] Enable Mask.
0: The corresponding GPIO pin is disabled and is in Hi-Z state.
1: The corresponding GPIO pin is enabled. It’s behavior is determined by the GPIO direction control.
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.32. Verb – Set GPIO Enable Mask (Verb ID=716h)
Table 64. Verb – Set GPIO Enable Mask (Verb ID=716h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=01h
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Verb ID=716h Enable Mask [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved.
GPIO[7:2] Enable Mask. Not supported in the ALC269.
GPIO[1:0] Enable Mask.
1:0
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. It’s behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
51
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.33. Verb – Get GPIO Direction (Verb ID=F17h)
Table 65. Verb – Get GPIO Direction (Verb ID=F17h)
Get Command Format
Codec Response Format
Response [31:0]
Direction [7:0]
Bit [31:28]
Bit [27:20]
Node ID=01h
Bit [19:8]
Payload Bit [7:0]
Cad=X
Verb ID=F17h
0’s
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved.
GPIO[7:2] Direction Control. Not supported in the ALC269.
GPIO[1:0] Direction Control.
1:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.34. Verb – Set GPIO Direction (Verb ID=717h)
Table 66. Verb – Set GPIO Direction (Verb ID=717h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=01h
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Verb ID=717h
Direction [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved.
GPIO[7:2] Direction Control. Not supported in the ALC269.
GPIO[1:0] Direction Control.
1:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
52
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.35. Verb – Get GPIO Wake Enable Mask(Verb ID=F18h)
Table 67. Verb – Get GPIO Wake Enable Mask (Verb ID=F18h)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Node ID=01h
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Verb ID=F18h
0’s
WakeEnalbeMask [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved.
GPIO[7:2] Wake Enable Mask. Not supported in the ALC269.
GPIO[1:0] Wake Enable Mask.
1:0
0: The corresponding GPIO pin will not generate a wake-up event
1: The corresponding GPIO pin will generate a wake-up event
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.36. Verb-Set GPIO Wake Enable Mask(Verb ID=718h)
Table 68. Verb – Set GPIO Wake Enable Mask (Verb ID=718h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=01h Verb ID=718h WakeEnalbeMask [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved.
GPIO[7:2] Wake Enable Mask. Not supported in the ALC269
GPIO[1:0] Wake Enable Mask.
1:0
0: The corresponding GPIO pin will not generate a wake-up event
1: The corresponding GPIO pin will generate a wake-up event
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
53
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.37. Verb – Get GPIO Unsolicited Response Enable Mask
(Verb ID=F19h)
Table 69. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Get Command Format
Codec Response Format
Response [31:0]
UnsolEnable [7:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Cad=X
Node ID=01h
Verb ID=F19h
0’s
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved.
GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC269.
1:0
GPIO[1:0] Unsolicited Enable Mask.
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.38. Verb – Set GPIO Unsolicited Response Enable Mask
(Verb ID=719h)
Table 70. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=01h
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Verb ID=719h
UnsolEnable [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved.
GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC269
1:0
GPIO[1:0] Unsolicited Enable Mask.
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Note 2: The unsolicited response of corresponding GPIO is enabled when it’s ‘Enable Mask’and Verb-‘Unsolicited
Response’for NID=01h are enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
54
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.39. Verb – Function Reset (Verb ID=7FFh)
Table 71. Verb – Function Reset (Verb ID=7FFh)
Command Format (NID=01H)
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=01h
Verb ID=7FFh
0’s
0’s
Codec Response
Bit
Description
31:0
Reserved. Read as 0’s.
Note: The Function Reset command causes all widgets in the ALC269 to return to their power-on default state.
8.40. Verb – Get Digital Converter Control 1 & Control 2
(Verb ID=F0Dh, F0Eh)
Table 72. Verb –Get Digital Converter Control 1 & Control 2 (Verb ID=F0Dh, F0Eh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh Verb ID=F0Dh/F0Eh
0’s
Bit[31:16]=0’s, Bit[15:0] are SIC bit
NID=06h, 10h (S/PDIF-OUT, S/PDIF-OUT2) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0]).
NID=06h, 10h (S/PDIF-OUT, S/PDIF-OUT2) Response to ‘Get verb’ – F0Eh (Control 2 for SIC bit[15:0])
Bit
31:16
15
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Read as 0’s.
Reserved. Read as 0’s.
14:8
7
6
CC[6:0] (Category Code).
LEVEL (Generation Level).
PRO (Professional or Consumer Format).
0: Consumer format
/AUDIO (Non-Audio Data type).
0: PCM data
COPY (Copyright).
0: Asserted
1: Professional format
5
4
3
1: AC3 or other digital non-audio data
1: Not asserted
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
1
0
VCFG for Validity Control (control V bit and data in Sub-Frame).
V for Validity Control (control V bit and data in Sub-Frame).
Digital Enable. DigEn.
0: OFF
1: ON
Codec Response for Other NID
Bit
Description
31:0
0’s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
55
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.41. Verb – Set Digital Converter Control 1 & Control 2
(Verb ID=70Dh, 70Eh)
Table 73. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Set Command Format (Verb ID=70Dh, Set Control 1)
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=70Dh
SIC [7:0]
0’s
Set Command Format (Verb ID=70Eh, Set Control 2)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Cad=X
Node ID=Xh
Verb ID=70Eh
SIC [15:8]
‘Payload’ in Set Control 1 for NID=06h (S/PDIF-OUT), 10h (S/PDIF-OUT2)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
LEVEL (Generation Level).
PRO (Professional or Consumer Format).
0: Consumer format
6
1: Professional format
5
4
3
/AUDIO (Non-Audio Data Type).
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright).
0: Asserted
1: Not asserted
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
VCFG for Validity Control (control V bit and data in Sub-Frame).
V for Validity Control (control V bit and data in Sub-Frame).
Digital Enable. DigEn.
2
1
0
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=06h (S/PDIF-OUT), 10h (S/PDIF-OUT2)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved. Read as 0’s.
6:0
CC[6:0] (Category Code).
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.42. Get/Set Volume Knob Widget (Verb ID=F0Fh/70Fh)
Table 74. Get/Set Volume Knob Widget (Verb ID=F0Fh/70Fh)
Get Command Format
Codec Response Format
Bit [31:28]
Cad=X
Bit [27:20]
Node ID=Xh
Bit [19:8]
Verb ID=F0Fh
Payload Bit [7:0]
Response [31:0]
Bit[31:8]=0’s, Bit[7:0] is volume
0’s
Codec Response for Volume Knob Widget
Bit
31:8
7
Description
Reserved.
Direct.
0: The volume generated by an external HW volume control will be sent by unsolicited response.
Software is responsible for programming the amplifier appropriately
1: The volume generated by an external HW volume control will directly affect amplifier volume
Volume in Steps.
6:0
Note: The ALC269 does not support volume knob widget and will ignore this verb and respond with 0’s.
Set Command Format (Verb ID=70Fh)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Cad=X
Node ID=Xh Verb ID=70Fh Bit[7] is ‘Direct’ control
‘Payload’ in Set Command for Volume Knob Widget
Bit
31:8
7
Description
Reserved.
Direct.
0: The volume generated by an external HW volume control will be sent by unsolicited response.
Software is responsible for programming the amplifier appropriately
1: The volume generated by an external HW volume control will directly affect amplifier volume
Reserved.
6:0
Note: The ALC269 does not support volume knob widget and will ignore this verb and respond with 0’s.
8.43. Get/Set Subsystem ID [31:0]
(Verb ID=F20h/723h~720h to Set Bit[31:0])
Table 75. Get/Set Subsystem ID [31:0] (Verb ID=F20h / 723h~720h to Set Bit[31:0])
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Verb ID=F20h
Payload Bit [7:0]
Cad=X
0’s
32 bits response
Codec Response for NID=01h (Audio Function Group)
Bit
31:16
15:8
7:0
Description
Subsystem ID[23:8] (Default=10Ech).
Subsystem ID[7:0] (Default=02h).
Assembly ID[7:0] (Default=69h).
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
57
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
8.44. Get/Set EAPD Enable (Verb ID= F0Ch/70Ch)
Table 76. Get/Set EAPD Enable (Verb ID=F0Ch / 70Ch )
Get Command Format
Codec Response Format
Response [31:0]
Bit[1] is EAPD Control
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Cad=X
Verb ID=F0Ch
0’s
Codec response in Get Command for NID=14h (LINE-OUT Pin Widget), 15h (HP-OUT Pin Widget)
Bit
31:3
2
Description
Reserved.
L-R Swap.
The ALC269 does not support swapping left and right channel, it is read as 0.
EAPD Value.
0: EAPD pin state is low potential to power down external amplifier in all power state of AFG.
1: EAPD pin state is high potential to power up external amplifier in all power state of AFG.
BTL Enable.
1
0
The ALC269 does not support BTL output, it is read as 0.
Codec Response in Get Command for other NID
Bit
Description
31:0
0s.
Set Command Format
Codec Response Format
Response [31:0]
0s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd = X
Node ID=Xh Verb ID=70Ch Bit[1] is EAPD Control
Payload in Set Command for NID=14h (SPK-OUT Pin Widget), 15h (HP-OUT Pin Widget)
Bit
7:3
2
Description
Reserved.
L-R Swap.
The ALC269 does not support swapping left and right channel, it is read as 0.
EAPD Value (Default=0).
0: EAPD pin state is low potential to power down external amplifier in all power state of AFG.
1: EAPD pin state is high potential to power up external amplifier in power state of AFG.
BTL Enable.
1
0
The ALC269 does not support BTL output, it is read as 0.
Codec Response in Set Command for all NID
Bit
Description
31:0
0s.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
58
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1.
Absolute Maximum Ratings
Table 77. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Typical
Maximum
Units
Power Supplies
Digital Power for Core
Digital Power for Link*1
Analog Power*2
DVDD
DVDD-IO
AVDD1, AVDD2
PVDD1, PVDD2
3.0
1.425
3.3
3.3
3.3
5.0
5.0
3.6
3.6
5.25
5.25
V
V
V
V
BTL Analog Power*2, *3
3.3
Ambient Operating Temperature
Storage Temperature
Ta
Ts
0
-
-
-
+70
oC
oC
+125
ESD (Electrostatic Discharge)
Susceptibility Voltage
4000V
All Pins Except PVDD1, PVDD2
PVDD1 (Pin39), PVDD2 (Pin 46)
3500V
Note1: DVDD-IO must be lower than DVDD.
Note2: PVDD must be greater than AVDD, and keep PVDD-AVDD ≤ 0.8V for best performance.
When (PVDD ≥ AVDD + 1V), THD+N will be degraded when playing at full power output.
Note3: When the Class-D amplifier is operating, surges of PVDD > 7V duration for 0.1ms may damage the amplifier. To
suppress such surges, 10µF tantalum capacitors are required at PVDD1 and PVDD2.
9.1.2.
Threshold Voltage
DVDD-IO=3.3V±5%, Tambient=25°C, with 50pF external load.
Table 78. Threshold Voltage
Parameter
Symbol
Vin
Minimum
Typical
Maximum
DVDD+0.30
0.35*DVDDIO
Units
V
Input Voltage Range
-0.30
-
-
-
Low Level Input Voltage
VIL
V
(BCLK, RST#, SDO, SYNC, SDI)
High Level Input Voltage
(BCLK, RST#, SDO, SYNC, SDI)
VIH
VIL
VIH
0.65*DVDDIO
-
-
-
-
V
V
V
Low Level Input Voltage
( GPIOs)
-
0.44*DVDD
-
High Level Input Voltage
( GPIOs)
0.56*DVDD
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
VOH
0.9*DVDD
-
-
V
V
VOL
-
-10
-10
-
-
-
0.1*DVDD
-
-
-
-
10
10
-
µA
µA
mA
Ω
Output Leakage Current (Hi-Z)
Output Buffer Drive Current
Internal Pull Up Resistance
-
5
-
50k
-
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
9.1.3.
Digital Filter Characteristics
Table 79. Digital Filter Characteristics
Filter
Symbol
Minimum
Typical
Maximum
Units
kHz
kHz
dB
ADC Lowpass Filter
Passband
0
-
-
0.454*Fs (-1dB)
Stopband
28.8
-
Stopband Rejection
Passband Ripple
Passband
-
-76.0
±0.02
-
-
-
-
dB
DAC Lowpass Filter
0
0.454*Fs (-1dB)
kHz
kHz
dB
Stopband
28.8
-
-
-
-
Stopband Rejection
Passband Ripple
-
-
-78.5
±0.02
dB
9.1.4.
S/PDIF Output Characteristics
DVDD=3.3V, Tambient=25°C, with 75Ω external load.
Table 80. S/PDIF Input/Output Characteristics
Parameter
Symbol
VOH
Minimum
Typical
Maximum
Units
V
S/PDIF-OUT High Level Output
S/PDIF-OUT Low Level Output
3.0
-
3.3
0
-
VOL
0.3
V
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
60
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
9.2. AC Characteristics
9.2.1.
Link Reset and Initialization Timing
Table 81. Link Reset and Initialization Timing
Parameter
Symbol
TRST
Minimum
100.167
100
Typical
Maximum
Units
µs
RESET# Active Low Pulse Width
RESET# Inactive to BCLK
-
-
-
-
TPLL
µs
Startup Delay for PLL Ready Time
SDI Initialization Request
TFRAME
-
-
25
Frame Time
Initialization Sequence
>= 4 BCLK
4 BCLK
4 BCLK
BCLK
Normal Frame
SYNC
SYNC
SDO
SDI
Initialization Request
RESET#
T
RST
T
T
PLL
FRAME
Figure 15. Link Reset and Initialization Timing
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
9.2.2.
Link Timing Parameters at the Codec (DVDDIO=3.3V)
Table 82. Link Timing Parameters at the Codec (DVDDIO=3.3V)
Parameter
Symbol
Minimum
23.9976
41.163
-
Typical
Maximum
24.0024
42.171
Units
MHz
ns
BCLK Frequency
BCLK Period
24.0
-
Tcycle
41.67
BCLK Jitter
Tjitter
Thigh
Tlow
150
500
ps
BCLK High Pulse Width
BCLK Low Pulse Width
17.5 (42%)
17.5 (42%)
5
-
-
-
24.16 (58%)
24.16 (58%)
-
ns (%)
ns (%)
ns
SDO Setup Time at Both Rising
and Falling Edge of BCLK
Tsetup
SDO Hold Time at Both Rising and
Falling Edge of BCLK
Thold
Ttco
5
3
0
-
-
-
-
11
7
ns
ns
ns
SDI Valid Time After Rising Edge
of BCLK (1:50pF external load)
SDI Flight Time
Tflight
Figure 16. Link Signals Timing
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
62
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
9.2.3.
S/PDIF Output Timing
Table 83. S/PDIF Output Timing
Parameter
Symbol
-
Minimum
Typical
3.072
Maximum
Units
MHz
ns
S/PDIF-OUT Frequency*1
S/PDIF-OUT Period*1
-
-
Tcycle
Tjitter
THigh
TLow
Trise
-
325.6
-
S/PDIF-OUT Jitter
-
-
4
ns
S/PDIF-OUT High Level Width*1
S/PDIF-OUT Low Level Width*1
S/PDIF-OUT Rising Time
S/PDIF-OUT Falling Time
156.2 (48%)
162.8 (50%)
162.8 (50%)
2.0
169.2 (52%)
ns (%)
ns (%)
ns
156.2 (48%)
169.2 (52%)
-
-
-
-
Tfall
2.0
ns
*1: Bit parameters for 48kHz sample rate of S/PDIF-OUT.
Figure 17. Output Timing
9.2.4.
Test Mode
The ALC269 does not support codec test mode or Automatic Test Equipment (ATE) mode.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
9.3. Analog Performance
• Tambient=25oC, DVDD-CORE=3.3V ±5%, AVDD=5.0V±5%
• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
Standard Test Conditions
• 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz
Table 84. Analog Performance
Parameter
Min
Typ
1.5
Max
Units
Vrms
Vrms
Full-Scale Input Voltage
All ADC (Gain=0dB)
-
-
-
-
Full-Scale Output Voltage
All DAC (Gain=+1dB)
Dynamic Range with 1kHz Tone, DR (A Weighted)
ADC
1.5
-
-
-
98
98
95
-
-
-
dB FSA
dB FSA
dB FSA
DAC
Headphone Out @32Ω Load
Total Harmonic Distortion Plus Noise, THD+N
ADC
-
-
-
-85
-90
-70
-
-
-
dB FS
dB FS
dB FS
DAC
Headphone Out @32Ω Load
Frequency Response
ADC (-3dB lower edge, -1dB higher edge)
DAC (-3dB lower edge, -1dB higher edge)
Power Supply Rejection Ratio
Total Out-of-Band Noise (28.8kHz~100kHz)
Amplifier Gain Step
10
10
-
-
-
0.454*Fs
0.454*Fs
Hz
Hz
dB
dB
-60
-60
-
-
-
ADC
DAC
-
-
-
-
1.0
1.0
-80
32
-
-
-
-
dB
dB
Crosstalk Between Input Channels
Input Impedance (Gain=0dB)
Output Impedance
dB
KΩ
Amplified Output
Non-Amplified Output
-
-
1
200
-
-
Ω
Ω
Digital Power Supply Current (Normal Operation)
DVDD=3.3V, DVDD-IO=3.3V
-
-
-
-
50
-
-
-
-
mA
Digital Power Supply Current (Power Down Mode)
DVDD=3.3V, DVDD-IO=3.3V
2
mA
mA
mA
Analog Power Supply Current (Normal Operation)
AVDD1, AVDD2=5.0V
48
7
Analog Power Supply Current (Power Down Mode)
AVDD1, AVDD2=5.0V
VREFOUTx Output Voltage
0
2.50
5
4.20
-
V
VREFOUTx Output Current
-
mA
Note: FSA=Full-Scale with A-weighting filter.
FS=Full-Scale.
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
64
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
9.4. Class-D Power Amplifier Performance
Table 85. Class-D Power Amplifier Performance
Parameter
Min
Typ
3.07
1.3
Max
Units
Vrms
A
Output Voltage @ BTL Mode (Vrms)
Maximum Output Peak Current @ BTL Mode
Maximum Output Power @ BTL Mode
Power Efficiencyη@ BTL Mode into 4ohm
-
-
-
-
-
-
2.0
2.3
-
W
80
%
-
-
-
-
84
88
-
-
-
-
%
%
Power Efficiencyη@ BTL Mode into 4ohm with Filter
Power Efficiencyη@ BTL Mode into 8ohm
92
%
Power Efficiencyη@ BTL Mode into 8ohm with Filter
Full-Scale Output Voltage @ BTL Mode
PCM/PWM Converter
+/-4.34
Vpeak
S/N (A weighted) @ BTL Mode
PCM/PWM Converter
-
-
90
-75
-60
-
-
dB FSA
dB FS
dB FS
Hz
THD+N @ BTL Mode at test signal 997Hz~3dB sine wave
PCM/PWM Converter
-
-
THD+N @ BTL Mode at test signal around 20Hz~22KHz
PCM/PWM Converter
-
Frequency Response @ BTL Mode
PCM/PWM Converter
20
22K
Total Quiescent Current (Iq)
-
-
-
-
-
-
-
-
-
-
-
-
1.25
150
250
384K
0
-
-
-
-
-
-
-
-
-
-
-
-
nA
mΩ
mΩ
Hz
P-Type MOS Output Impendence (Rds)
N-Type MOS Output Impendence (Rds)
PWM Frequency
Dead Time (Shoot)
nS
Modulation Index
0.8896
150
65.4
32.4
50
N/A
nS
Minimum Pulse Width
LQFP-48 Package Thermal Characteristic, ӨJA
QFN-48 Package Thermal Characteristic, ӨJA
Output Voltage Noise(Vn) at Mute Condition
Output Short Circuit Protection Limit
Class-D Output RMS Current, IL
(BTL 4Ω Load, PVDD = 5.0V, Full Power Output)
Class-D Output RMS Current, IL
(BTL 4Ω Load, PVDD = 5.0V, Power Down)
°C/W
°C/W
µV
2.5
A
0.6
A
-
0
-
mA
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
10. Application Circuits
10.1. Filter Connection
MIC1-VREFO_R
MIC2-VREFO
C1
2.2u
+
MIC1-VREFO-L
10u
C2
+
+5VA
C9
C4
+
C3
+
10u
0.1u
2.2u
U2
+5VA
C7
C8
+
10u
0.1u
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
LINE1-R
LINE1-L
MIC1-R
AVSS2
AVDD2
PVDD1
SPK-L+
SPK-L-
PVSS1
PVSS2
SPK-R-
SPK-R+
PVDD2
LINE1-R
LINE1-L
MIC1-R
AGND
PVDD1
C39
+
C10
SPKL+
SPKL-
MIC1-L
MIC1-L
10u
0.1u
MONO-OUT
MONO-OUT
JDREF
RJ1
19
18
17
16
15
14
13
PGND
39.2K,1%
20K,1%
ALC269
PGND
RJ2
LINE2-JD
Sense-B
MIC2-R
Tantalum capacitor is
required for C39, C40
RJ3
RJ4
20K,1%
10K,1%
5.1K,1%
SPKR-
SPKR+
MIC2-R
MIC2-L
MIC2-JD
MONO-OUT-JD
SPDIF-OUT2-JD
MIC2-L
RJ5
PVDD2
LINE2-R
LINE2-L
Sense A
C12
0.1u
C40
10u
+
SPDIFO2/EAPD
SPDIFO
RJ6
39.2K, 1%
20K,1%
HPOUT-JD
RJ7
RJ8
RJ9
MIC1-JD
PGND
10K,1%
5.1K,1%
LINE1-JD
S/PDIF-OUT2 or EAPD
S/PDIF-OUT
SPDIF-OUT-JD
Pin 47 (EAPD):
Output to control external amplifier
R1
47k
J1
Pin 47 (Secondary S/PDIF-OUT):
C16
1u
+3.3VD
1
2
C19 C17
GND
Optional digital output to HDMI Tx
+
C21
R3
10K
PCBEEP
0.1u 10u
R4
10
22p
RESET#
SYNC
C22
100P
GPIO0, or DATA for digital MIC
GPIO1, or CLK for digital MIC
R7
10
C24
22p
Power down speaker amplifier
(internal pulled high)
PD#
+3.3VD
0V: Power down speaker amplifier
3.3V: Power up speaker amplifier
C29 C28
R8
R9
R10 10
10
SDIN
+
10
BCLK
0.1u 10u
SDOUT
C30 C31
22p 22p
speaker
amplifier ground
digital_ground
Analog_ground
digital_ground
GND
PGND
AGND
GND
Tied at one point only under the codec or near the codec
Figure 18. Filter Connection
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
66
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
10.2. Power and Jack Connection
Power for Speaker Amplifier
PH1
U1
HPOUT-JD
CN
CS
1
3
4
L1
L2
FERB
FERB
PVDD2
PVDD1
AC1085-50/3A
+12V
HPOUT-R
HPOUT-L
2
3
OUT
IN
5
C6
+
C5
+
HP-OUT (Port-A)
100u
100u
speaker
amplifier ground
PH2
PGND
LINE1-JD
CN
CS
1
L3
L4
FERB
1u
1u
C11
C13
LINE1-R
LINE1-L
FERB
3
4
5
Standby +5V
+12V
C14
C15
LINE-IN(Port-C)
100P
100P
For Standby mode De-pop purpose
D1
D2
B130LAW/1N5817
1N4148
MIC1-VREFO-L
MIC1-VREFO-R
LM7805CT/200mA
OUT IN
L5 FERB
R6
3
1
R5
2.2K
1u
1u
+5VA
2.2K
PH3
C18
R2
MIC1-JD
CN
CS
1
+
10
L6
L7
FERB
FERB
C23
C25
C20
MIC1-R
MIC1-L
+
+10u
3
4
5
+100u
C26
100P
C27
MIC-IN (Port-B)
100P
To reduce background noise
when boosting Microphone
MIC2-VREFO
D3
1N5817
D4
1N5817
SPKL+
SPKL-
SPK1
INTERNAL SPEAKER (Port-D Lef t)
R11
2.2K
R12
2.2K
J2
1u
1u
C32
C33
SPKR+
SPKR-
MIC2-R
MIC2-L
1
2
SPK2
INTERNAL SPEAKER (Port-D Right)
INTERNAL MIC (Port-F)
C34 C35
100P 100P
Configuation: (Standard case for Laptop)
Pin/Port Assignment
Location
Chassis
Chassis
Chassis
Functions
HP-OUT (pin-32,33)/Port-A
MIC1 (pin-21,22)/Port-B
LINE1 (pin-23,24)/Port-C
Headphone output
Mic-In for external microphone
Line-In for external line input
MIC2 (pin-16,17)/Port-F
Internal
Internal
Mic-In for internal analog microphone
Amplifier output for internal speaker
SPK-OUT (pin-40,41,44,45)/Port-D
Figure 19. Power and Jack Connection
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
67
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
10.3. S/PDIF-OUT Connection
S/PDIF module option 1: Optical
S/PDIF module option 2: Coaxial
U4
S/PDIF OUTPUT
J3
Optical Transmitter
TOTX178
1
R14 200
S/PDIF-OUT
C37 0.01u
C38
5
4
N.C
N.C
R15
100
100P
C36
0.1u
R13 10
S/PDIF-OUT
+5VD
Figure 20. S/PDIF-OUT Connection
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
68
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
11. Mechanical Dimensions
0.129mm
0.28mm
(mm)
Optional support bar does not appear
in the ALC269Q package
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
11.1. Mechanical Dimensions Notes
SYMBOL
MILLIMETER
TYPICAL
0.85
INCH
TYPICAL
0.034
MIN.
0.75
0.00
0.55
MAX.
1.00
MIN.
0.030
0.000
0.022
MAX
0.039
0.002
0.032
A
A1
A2
A3
b
0.02
0.05
0.001
0.65
0.80
0.026
0.20 REF
0.25
0.008 REF
0.010
0.18
4.80
4.80
0.30
5.30
5.30
0.007
0.189
0.189
0.012
0.209
0.209
D
7.00 BSC
6.75 BSC
5.05
0.276 BSC
0.266 BSC
0.199
D1
D2
E
7.00 BSC
6.75 BSC
5.05
0.276 BSC
0.266 BSC
0.199
E1
E2
e
0.50 BSC
0.40
0.020 BSC
0.016
L
0.30
0o
0.50
14o
0.012
0o
0.020
14o
θ
-
-
R
0.09
0.20
-
-
-
0.004
0.008
-
-
-
K
-
-
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
70
Track ID: JATR-1076-21 Rev. 1.5
ALC269
Datasheet
12. Ordering Information
Table 86. Ordering Information
Part Number
ALC269Q-GR
Description
Status
QFN-48 ‘Green’ Package
Production
Production
Production
ALC269QSRS-GR
ALC269W-GR
ALC269Q-GR + SRS Audio Software
ALC269Q-GR + Waves MaxxAudio (software feature)
Note: See page 7 for ‘Green’package and version identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
High Definition Audio Codec with Embedded
Class-D Speaker Amplifier
71
Track ID: JATR-1076-21 Rev. 1.5
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