ALC5629 [REALTEK]
I2S/PCM AUDIO DAC;
| 型号： | ALC5629 |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | I2S/PCM AUDIO DAC PC |
| 文件： | 总38页 (文件大小：717K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC5629
I2S/PCM AUDIO DAC
DATASHEET
Rev. 1.0
26 June 2009
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
ALC5629
Datasheet
COPYRIGHT
©2009 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC5629 Audio DAC IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
Release Date
Summary
1.0
2009/06/26
First release.
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Datasheet
Table of Contents
1.
2.
3.
4.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
SYSTEM APPLICATIONS...............................................................................................................................................3
BLOCK DIAGRAM...........................................................................................................................................................4
4.1.
4.2.
FUNCTION BLOCK ........................................................................................................................................................4
AUDIO MIXER PATH.....................................................................................................................................................5
5.
6.
PIN ASSIGNMENTS .........................................................................................................................................................6
5.1.
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................6
PIN DESCRIPTIONS.........................................................................................................................................................7
6.1.
DIGITAL I/O.................................................................................................................................................................7
ANALOG I/O.................................................................................................................................................................7
FILTER/REFERENCE......................................................................................................................................................7
POWER/GROUND..........................................................................................................................................................8
NOT CONNECTED (NC)................................................................................................................................................8
6.2.
6.3.
6.4.
6.5.
7.
FUNCTIONAL DESCRIPTION.......................................................................................................................................9
7.1.
7.2.
POWER .........................................................................................................................................................................9
RESET ..........................................................................................................................................................................9
7.2.1. Power-On Reset (POR) ..........................................................................................................................................9
7.3.
7.4.
CLOCKING..................................................................................................................................................................10
I2C CONTROL INTERFACE ..........................................................................................................................................11
7.4.1. Addressing Setting................................................................................................................................................11
7.4.2. Complete Data Transfer.......................................................................................................................................11
7.4.3. Odd-Addressed Register Access ...........................................................................................................................12
7.5.
DIGITAL DATA INTERFACE ........................................................................................................................................12
7.5.1. I2S/PCM Interface ................................................................................................................................................12
7.6.
ANALOG SIGNAL PATH ..............................................................................................................................................14
7.6.1. Line Output...........................................................................................................................................................14
7.6.2. Stereo DAC...........................................................................................................................................................14
7.7.
7.8.
7.9.
POWER MANAGEMENT...............................................................................................................................................15
LINE OUTPUT DEPOP..................................................................................................................................................15
ZERO CROSS ..............................................................................................................................................................15
8.
REGISTER DESCRIPTIONS.........................................................................................................................................16
8.1.
REG-00H: SOFTWARE RESET......................................................................................................................................16
REG-04H: LINE OUTPUT VOLUME..............................................................................................................................16
REG-0C: STEREO DAC DIGITAL VOLUME .................................................................................................................16
REG-16H: SOFT DELAY VOLUME CONTROL TIME......................................................................................................17
REG-1CH: OUTPUT MIXER CONTROL ........................................................................................................................17
REG-34H: STEREO AUDIO SERIAL DATA PORT CONTROL ..........................................................................................18
REG-38H: STEREO DAC CLOCK CONTROL ................................................................................................................18
REG-3AH: POWER MANAGEMENT ADDITION 1..........................................................................................................19
REG-3CH: POWER MANAGEMENT ADDITION 2..........................................................................................................20
REG-3EH: POWER MANAGEMENT ADDITION 3 ..........................................................................................................20
REG-40H: GENERAL PURPOSE CONTROL ...................................................................................................................21
REG-42H: GLOBAL CLOCK CONTROL ........................................................................................................................21
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
8.11.
8.12.
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8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
REG-44H: PLL M/N CODE CONTROL.........................................................................................................................22
REG-5CH: MISC1 CONTROL......................................................................................................................................22
REG-5EH: MISC2 CONTROL......................................................................................................................................23
REG-6AH: PRIVATE REGISTER INDEX ........................................................................................................................23
REG-6CH: PRIVATE REGISTER DATA .........................................................................................................................24
PRIVATE-39H: DIGITAL INTERNAL REGISTER ............................................................................................................24
9.
ELECTRICAL CHARACTERISTICS ..........................................................................................................................25
9.1.
DC CHARACTERISTICS...............................................................................................................................................25
9.1.1. Absolute Maximum Ratings..................................................................................................................................25
9.1.2. Recommended Operating Conditions...................................................................................................................25
9.1.3. Static Characteristics ...........................................................................................................................................25
9.2.
9.3.
ANALOG PERFORMANCE CHARACTERISTICS..............................................................................................................26
AC TIMING CHARACTERISTICS ..................................................................................................................................27
9.3.1. I2C Control Interface............................................................................................................................................27
9.3.2. I2S/PCM Interface Master Mode ..........................................................................................................................28
9.3.3. I2S/PCM Interface Slave Mode.............................................................................................................................29
10.
11.
12.
APPLICATION CIRCUITS .......................................................................................................................................30
MECHANICAL DIMENSIONS.................................................................................................................................31
ORDERING INFORMATION...................................................................................................................................32
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List of Tables
TABLE 1. DIGITAL I/O PINS.........................................................................................................................................................7
TABLE 2. ANALOG I/O PINS ........................................................................................................................................................7
TABLE 3. FILTER/REFERENCE PINS .............................................................................................................................................7
TABLE 4. POWER/GROUND PINS .................................................................................................................................................8
TABLE 5. NOT CONNECTED (NC) PINS........................................................................................................................................8
TABLE 6. RESET OPERATION.......................................................................................................................................................9
TABLE 7. POWER-ON RESET VOLTAGE .......................................................................................................................................9
TABLE 8. PLL CLOCK SETTING TABLE FOR 48K (UNIT: MHZ).................................................................................................10
TABLE 9. PLL CLOCK SETTING TABLE FOR 44.1K (UNIT: MHZ)..............................................................................................10
TABLE 10. MX00 SOFTWARE RESET ..........................................................................................................................................16
TABLE 11. MX04 LINE OUTPUT VOLUME ..................................................................................................................................16
TABLE 12. MX0C STEREO DAC DIGITAL VOLUME ...................................................................................................................16
TABLE 13. MX16 SOFT DELAY VOLUME CONTROL TIME ..........................................................................................................17
TABLE 14. MX1C OUTPUT MIXER CONTROL .............................................................................................................................17
TABLE 15. MX34 STEREO AUDIO SERIAL DATA PORT CONTROL...............................................................................................18
TABLE 16. MX38 STEREO DAC CLOCK CONTROL.....................................................................................................................18
TABLE 17. MX3A POWER MANAGEMENT ADDITION 1 ..............................................................................................................19
TABLE 18. LINE_OUT DRIVE ABILITY SELECTION ...................................................................................................................19
TABLE 19. MX3C POWER MANAGEMENT ADDITION 2...............................................................................................................20
TABLE 20. MX3E POWER MANAGEMENT ADDITION 3...............................................................................................................20
TABLE 21. MX40 GENERAL PURPOSE CONTROL ........................................................................................................................21
TABLE 22. MX42 GLOBAL CLOCK CONTROL .............................................................................................................................21
TABLE 23. MX44 PLL M/N CODE CONTROL .............................................................................................................................22
TABLE 24. MX5C MISC1 CONTROL ..........................................................................................................................................22
TABLE 25. MX5E MISC2 CONTROL ..........................................................................................................................................23
TABLE 26. MX6A PRIVATE REGISTER INDEX.............................................................................................................................23
TABLE 27. MX6C PRIVATE REGISTER DATA..............................................................................................................................24
TABLE 28. PR39 DIGITAL INTERNAL REGISTER .........................................................................................................................24
TABLE 29. ABSOLUTE MAXIMUM RATINGS................................................................................................................................25
TABLE 30. RECOMMENDED OPERATING CONDITIONS.................................................................................................................25
TABLE 31. THRESHOLD VOLTAGE ..............................................................................................................................................25
TABLE 32. ANALOG PERFORMANCE CHARACTERISTICS .............................................................................................................26
TABLE 33. I2C CONTROL INTERFACE TIMING .............................................................................................................................27
TABLE 34. I2S MASTER MODE TIMING .......................................................................................................................................28
TABLE 35. I2S SLAVE MODE TIMING ..........................................................................................................................................29
TABLE 36. ORDERING INFORMATION..........................................................................................................................................32
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List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................4
FIGURE 2. AUDIO MIXER PATH ...................................................................................................................................................5
FIGURE 3. PIN ASSIGNMENTS ......................................................................................................................................................6
FIGURE 4. DATA TRANSFER OVER I2C CONTROL INTERFACE ...................................................................................................11
FIGURE 5. WRITE WORD PROTOCOL .......................................................................................................................................11
FIGURE 6. READ WORD PROTOCOL .........................................................................................................................................11
FIGURE 7. PCM STEREO DATA MODE A FORMAT (SEL_I2S_DATA_FORMAT=10’B, CTRL_I2S_BCLK_POLARITY=0’B) ............12
FIGURE 8. PCM STEREO DATA MODE A FORMAT (SEL_I2S_DATA_FORMAT=10’B, CTRL_I2S_BCLK_POLARITY=1’B) ............13
FIGURE 9. PCM STEREO DATA MODE B FORMAT (SEL_I2S_DATA_FORMAT=11’B, CTRL_I2S_BCLK_POLARITY=0’B).............13
FIGURE 10. I2S DATA FORMAT (SEL_I2S_DATA_FORMAT=00’B)................................................................................................13
FIGURE 11. LEFT-JUSTIFIED DATA FORMAT (SEL_I2S_DATA_FORMAT=01’B, CTRL_I2S_BCLK_POLARITY=0’B).......................14
FIGURE 12. ZERO CROSS DISABLED WHEN OUTPUT MUTED.......................................................................................................15
FIGURE 13. ZERO CROSS ENABLED WHEN OUTPUT MUTED........................................................................................................15
FIGURE 14. GLOBAL CLOCK CONTROL.......................................................................................................................................21
FIGURE 15. I2C CONTROL INTERFACE WAVEFORM.....................................................................................................................27
FIGURE 16. I2S MASTER MODE WAVEFORM...............................................................................................................................28
FIGURE 17. I2S SLAVE MODE WAVEFORM..................................................................................................................................29
FIGURE 18. APPLICATION CIRCUITS............................................................................................................................................30
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Datasheet
1. General Description
The ALC5629 is a highly-integrated I2S/PCM interface audio DAC with single-ended stereo LINE_OUT
that can be configured to drive Headphones, and is designed for Multimedia and Communication
handheld devices. It provides a Stereo Hi-Fi DAC for playback via the I2S/PCM interface and is
controlled by the I2C interface.
The ALC5629 AVDD operates at supply voltages from 2.3V to 3.6V. DCVDD and DBVDD operate
from 1.8V to 3.6V. To extend battery life, each section of the device can be powered down individually
under software control. Leakage current in maximum power saving state is less than 10µA.
The ALC5629 is available in a 4x4mm ‘Green’ QFN-24 package, making it ideal for use in handheld
portable systems.
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2. Features
Digital-to-Analog Converter with 100dB SNR and –86dB THD+N at 3.3V
Supports playback soft-mute and digital volume
Supports pop noise suppression with external capacitor
Digital power supplied from 1.8V to 3.6V
Analog power supplied from 2.3V to 3.6V
Stereo LINE_OUT can be configured to drive 45mW Headphone OUT
Power management and enhanced power saving
Internal PLL can receive wide range of clock inputs
Supports crystal oscillator
Supports sampling rate 8KHz ~ 192KHz
Supports I2C control interface
Supports three programmable data interfaces
I2S, left justified, and PCM interface
16/20/24-bit word lengths
Master or Slave clock mode
24-pin QFN 4x4mm package for small footprint
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3. System Applications
Portable media player
MP3 player
Bluetooth A2DP (Advanced Audio Distribution Profile) headsets
Portable Navigation Device (PND)
Multimedia phone
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4. Block Diagram
4.1. Function Block
Figure 1. Block Diagram
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4.2. Audio Mixer Path
Reg1C[1]
Reg1C[9:8]
Figure 2. Audio Mixer Path
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Datasheet
5. Pin Assignments
18
17
16
15
14
13
NC
NC
19
20
21
22
23
24
12
11
10
9
DBVDD
DCVDD
DGND
XTO
REALTEK
ALC5629
LLLLLLL
TXXXV
AVDD
VREF
AGND
8
XTI
LINE_OUT_R
7
SDAC
1
2
3
4
5
6
Figure 3. Pin Assignments
5.1. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3.
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Datasheet
6. Pin Descriptions
6.1. Digital I/O
Table 1. Digital I/O Pins
Pin Name
LRCK
BCLK
SDAC
XTI
Type Pin No Description
Characteristic Definition
IO
IO
I
5
6
Digital Audio Input Frame Sync
Digital Audio Serial Clock
Digital Audio Serial Data Input
Crystal Input
Schmitt Trigger Input, Output
Schmitt Trigger Input, Output
Schmitt Trigger Input
7
I
8
Schmitt Trigger Input
XTO
O
I
9
Crystal Output
Schmitt Trigger Output
Schmitt Trigger Input
SCLK
SDA
13
14
15
I2C: Clock Input
IO
I
I2C: Data Input And Output
Schmitt Trigger Input, Output
OSC_EN
Crystal Oscillator Enable Control, Connect Schmitt Trigger Input
to VDD or GND
VDD: Crystal enabled
GND: Crystal disabled
6.2. Analog I/O
Table 2. Analog I/O Pins
Pin Name
Type Pin No Description
Characteristic Definition
Analog Amplifier Output
Analog Amplifier Output
LINE_OUT_L
LINE_OUT_R
O
O
1
Line Output Left Channel
Line Output Right Channel
24
6.3. Filter/Reference
Table 3. Filter/Reference Pins
Pin Name
Type Pin No Description
Characteristic Definition
Cdepop
IO
16
De-Pop Capacitor, Connect 1µF Capacitor Capacitor to Analog Ground
to Analog GND
VREF
O
22
Reference Voltage Output, Connect 4.7µF Capacitor to Analog Ground
Capacitor to Analog GND
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6.4. Power/Ground
Table 4. Power/Ground Pins
Description
Pin Name
DGND
Type
Pin No
10
Characteristic Definition
P
P
P
P
P
P
Digital GND
-
DCVDD
DBVDD
AGND
11
Digital VDD
1.8V~3.6V (Core)
12
Digital VDD
1.8V~3.6V (IO Buffer)
23
Analog GND
-
AVDD
2, 21
Analog VDD
2.3V~3.6V
-
DGND
Exposed Pad Digital GND
6.5. Not Connected (NC)
Table 5. Not Connected (NC) Pins
Pin Name
Type
Pin No
Description
Characteristic Definition
NC
-
3, 4, 17, 18, 19, 20 Not Connected
-
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7. Functional Description
7.1. Power
The ALC5629 has many power blocks. The power supply limit conditions are DBVDD≥DCVDD and
AVDD≥DCVDD. To prevent pop noise, we suggest that DCVDD is powered on before AVDD.
7.2. Reset
There are two types of reset operation: Power-On-Reset (POR) and Register reset.
Table 6. Reset Operation
Reset Type
Trigger Condition
Codec Response
POR
Monitor Digital Power Supply Voltage Reach
VPOR
Reset all hardware logic and all registers to default
values.
Register Reset
Write Reg00
Reset all registers to default values.
7.2.1. Power-On Reset (POR)
When power is on, DCVDD passes through the VPOR band of the ALC5629 (VPORH~VPORL). A Power-On
Reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip.
Table 7. Power-On Reset Voltage
Symbol
VPOR_ON
VPOR_OFF
Min
1.0
-
Typical
Max
1.6
-
Unit
V
-
1.3
V
Note: The VPOR_OFF must be below VPOR_ON
.
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Datasheet
7.3. Clocking
The ALC5629 supports a Crystal as internal system clock. When the OSC_EN pin is kept high, the audio
system clock can be selected from XTI/XTO or PLL. When a crystal is applied, 256/384/512/768Fs is
required from XTI/XTO. If using internal PLL as audio internal clock, set the PLL output to 512Fs.
A Phase-Lock Loop (PLL) is used to provide a flexible input clock from 2.048MHz (64Fs of 32kHz) to
40MHz. Typical choices are 2.048MHz, 4.096MHz, and 13MHz. The source of the PLL can be set to
XTI or BCLK by setting sel_pll_sour (Reg42[14]). Firmware can setup the PLL to output the desired
frequency for the system clock.
The PLL transmit formula is: FOUT = (XTI*(N+2)) / ((M+2)*(K+2)) (Typical K=2)
Table 8. PLL Clock Setting Table for 48K (Unit: MHz)
XTI
2.048
3.6864
4.096
12
M Code
N Code
94
Fvco
98.304
98.304
98.304
98.25
K Code
Fout
24.576
24.576
24.576
24.5625
24.57812
24.576
24.57143
24.5647
24.6
0
1
2
2
2
2
2
2
2
2
2
78
0
46
14
14
3
129
119
30
13
98.3125
98.304
98.28571
98.25882
98.4
15.36
16
5
41
19.2
19.68
15
0
85
8
Table 9. PLL Clock Setting Table for 44.1K (Unit: MHz)
XTI
2.048
3.6864
4.096
12
M Code
N Code
86
Fvco
K Code
Fout
0
90.112
2
2
2
2
2
2
2
2
2
22.528
0
47
90.3168
90.48436
90.35294
90.23529
90.35294
90.28571
90.35294
90.29647
22.5792
22.62109
22.58824
22.55882
22.58824
22.57143
22.58824
22.57412
9
241
126
116
98
15
15
15
12
15
15
13
15.36
16
77
19.2
19.68
78
76
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Datasheet
7.4. I2C Control Interface
I2C is a 2-wire half-duplex serial communication interface, supporting only slave mode.
7.4.1. Addressing Setting
(MSB)
0
BIT
(LSB)
RW
0
1
1
0
0
0
7.4.2. Complete Data Transfer
Data Transfer over I2C Control Interface
Figure 4. Data Transfer Over I2C Control Interface
Write WORD Protocol
Read WORD Protocol
Figure 5. Write WORD Protocol
S: Start Condition
A: 0 for ACK, 1 for NACK
Data Byte: 16-bit Mixer data
ꢀ: Master-to-Slave
Slave Address: 7-bit Device Address
Wr: 0 for Write Command
Rd: 1 for Read Command
ꢀ: Slave-to-Master
Command Code: 8-bit Register Address
Figure 6. Read WORD Protocol
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7.4.3. Odd-Addressed Register Access
The ALC5629 will return ‘0000h’ when odd-addressed and unimplemented registers are read.
7.5. Digital Data Interface
7.5.1. I2S/PCM Interface
The Digital to Analog Converter (DAC) serial data is input via the SDAC pin. The serial data is shifted in
on the rising edge of BCLK (ctrl_i2s_bclk_polarity=0’b) or the falling edge (ctrl_i2s_bclk_polarity=1’b).
The Left/Right Clock (LRCK) signal is the frame sync signal. Left/Right data can be swapped by
en_dac_lrck_swap.
The ALC5629 I2S/PCM interface can be configured to Master mode or Slave mode. In Master mode
(sel_i2s_mode=0’b), BCLK and LRCK are configured as output. In Slave mode (sel_i2s_mode=1’b),
BCLK and LRCK are configured as input. The XTI provides BCLK synchronized clock externally as
Stereo System Clock.
The ALC5629 supports three independent I2S/PCM interfaces for Stereo Audio data formats:
• PCM/DSP mode
• Left justified mode
• I2S mode
Figure 7. PCM Stereo Data Mode A Format-1 (sel_i2s_data_format=10’b, ctrl_i2s_bclk_polarity=0’b)
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Figure 8. PCM Stereo Data Mode A Format-2 (sel_i2s_data_format=10’b, ctrl_i2s_bclk_polarity=1’b)
Figure 9. PCM Stereo Data Mode B Format (sel_i2s_data_format=11’b, ctrl_i2s_bclk_polarity=0’b)
Figure 10. I2S Data Format (sel_i2s_data_format=00’b)
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Figure 11. Left-Justified Data Format (sel_i2s_data_format=01’b, ctrl_i2s_bclk_polarity=0’b)
7.6. Analog Signal Path
7.6.1. Line Output
LINE_OUT_L/R provides 2-channel single-ended output. The source of LINE_OUT_L/R can be selected
from sel_lo_l_in & sel_lo_r_in, as shown below.
• VMID
• DAC R/L channel
The LINE_OUT_L/R volume and mute are controlled by Reg04. Besides, Reg3E[10]: pow_lo_l_vol and
Reg3E[9]: pow_lo_r_vol can be used to power down the LINE_OUT volume.
LINE_OUT supports ‘Soft Volume Delay Mute’ and ‘Zero-Crossing Detect’ functions which can be
enabled by Reg5C[11]: en_lo_l_dezero, Reg5C[10]: en_lo_l_softvol, Reg5C[9]: en_lo_r_dezero, and
Reg5C[8]: en_lo_r_softvol.
LINE_OUT_L/R source can be selected from DAC Stereo output (Reg1C[1]: en_dac_lo) for high quality
performance playback.
LINE_OUT_L/R can be configured to drive Headphone by setting en_hp_enhance_amp=1.
7.6.2. Stereo DAC
The stereo DAC can be configured to different sample rates by driving 256Fs/384Fs into audio SYSCLK,
and individually set by sel_i2s_bclk_ms (Reg38[12]).
dac_l_vol & dac_r_vol can be used to control the DAC output volume.
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7.7. Power Management
The ALC5629 supports detailed Power Management control registers within Reg3A, 3C, and 3E. Each
particular block will be active only when individual bits of Reg3A, 3C, and 3E are set to enable.
7.8. Line Output Depop
The ALC5629 provides a LINE_OUT depop mechanism in order to eliminate the pop noise of
LINE_OUT when LINE_OUT acts as Headphone output, by setting en_lo_out_amp=1 and
en_lo_enhance_amp=1. An external 1µF Capacitor is required in this application. Refer to the ALC5629
Application Notes (separate document) for details.
7.9. Zero Cross
When Zero-Cross detect is enabled, the ALC5629 will change each output volume or mute only if the
signal swing crosses the zero point. This function can avoid pop noise when volume is changed or muted.
Figure 12. Zero Cross Disabled when Output Muted
Figure 13. Zero Cross Enabled when Output Muted
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Datasheet
8. Register Descriptions
8.1. Reg-00h: Software Reset
Default: 0003’h
Table 10. MX00 Software Reset
Name
id
Bits
15:8
7:0
RW
R
Default Description
00’h
03’h
Chip ID
Reserved
R
Reserved
8.2. Reg-04h: Line Output Volume
Default: 9F9F’h
Table 11. MX04 Line Output Volume
RW Default Description
RW 1’h
Mute Line Output Left Channel
Name
Bits
mute_lo_l
15
0: On
1: Mute (-∞ dB)
Reserved
Reserved
14:13
12:8
7
R
0’h
sel_lo_l_vol
mute_lo_r
RW
RW
1F’h Line Output Left Volume (HPL[4:0]) in 1.5dB Steps
1’h
Mute Line Output Right Channel
0: On
1: Mute (-∞ dB)
Reserved
6:5
4:0
R
0’h
Reserved
sel_lo_r_vol
RW
1F’h Line Output Right Volume (HPR[4:0]) in 1.5dB Steps
Note: For HPR/HPL: 00h: 0dB attenuation.
1Fh: 46.5dB attenuation.
8.3. Reg-0Ch: Stereo DAC Digital Volume
Default: FFFF’h
Table 12. MX0C Stereo DAC Digital Volume
Name
Bits RW Default Description
mute_dacl2hp
15 RW
14 RW
13:8 RW
1’h
Mute DAC Left Channel Digital Volume Output to Headphone Mux Control
0: On
1: Mute (-∞ dB)
mute_dacl2spk
dac_l_vol
1’h
Mute DAC Left Channel Digital Volume Output to Speaker Mixer Control
0: On
1: Mute (-∞ dB)
DAC Left Channel Digital Volume (PLV[5:0]) in 0.75dB Steps
3F’h
I2S/PCM Audio DAC
16
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ALC5629
Datasheet
Name
Bits RW Default Description
mute_dacr2hp
7
RW
1’h
Mute Right Channel DAC Digital Volume Output to Headphone Mux Control
0: On
1: Mute (-∞ dB)
mute_dacr2spk
dac_r_vol
6
RW
1’h
Mute Right Channel DAC Digital Volume Output to Speaker Mixer Control
0: On
1: Mute (-∞ dB)
5:0 RW
3F’h
DAC Right Channel Digital Volume (PRV[5:0]) in 0.75dB Steps
Note: For PRV/PLV: 00h: +12dB gain.
10h: 0dB attenuation.
3Fh: 35.25dB attenuation.
8.4. Reg-16h: Soft Delay Volume Control Time
Default: 0009’h
Table 13. MX16 Soft Delay Volume Control Time
Name
Bits
15:4
3:0
RW
R
Default Description
0’h Reserved
1001’b Soft Volume Change Delay Time (Default=1001b)
Reserved
sel_sync_softvol
RW
0000: 1 SVSYNC
0010: 4 SVSYNC
0100: 16 SVSYNC
0110: 64 SVSYNC
1000: 256 SVSYNC
0001: 2 SVSYNC
0011: 8 SVSYNC
0101: 32 SVSYNC
0111: 128 SVSYNC
1001: 512 SVSYNC
1010: 1024 SVSYNC
Others: Reserved
Note: SVSYNC=1/Fs, Step: -1.5dBFS.
8.5. Reg-1Ch: Output Mixer Control
Default: 8004’h
Table 14. MX1C Output Mixer Control
Default Description
10’h Reserved
Line Out Left Volume Output Source Select
0: VMID (No input) 1: DAC Left Channel
Line Out Right Volume Output Source Select
Name
Bits
15:10
9
RW
R
Reserved
sel_lo_l_in
RW
0’h
0’h
sel_lo_r_in
8
RW
0: VMID (No input)
1: DAC Right Channel
Reserved
7:2
1
R
01’h
0’b
Reserved
en_dac_lo
RW
DAC Direct Output to LINE_OUT Control
0: Normal
Reserved
1: Enable direct output
Reserved
0
R
0’b
I2S/PCM Audio DAC
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ALC5629
Datasheet
8.6. Reg-34h: Stereo Audio Serial Data Port Control
Default: 8000’h
Table 15. MX34 Stereo Audio Serial Data Port Control
Name
Bits
RW
Default Description
sel_i2s_mode
15
RW
1’h
Main Serial Data Port Mode Selection
0: Master
Reserved
1: Slave
Reserved
14:8
7
R
0’h
0’h
ctrl_i2s_bclk_polarity
RW
Stereo I2S BCLK Polarity Control
0: Normal
1: Invert
Reserved
6:5
4
R
0’h
0’h
Reserved
en_dac_lrck_swap
RW
DAC Data L/R Swap
0: DAC data appears at left phase of LRCK
1: DAC data appears at right phase of LRCK
Note: Support to I2S & PCM.
Data Length Selection
sel_i2s_data_len
3:2
1:0
RW
RW
0’h
0’h
00: 16 bits
10: 24 bits
01: 20 bits
11: Reserved
sel_i2s_data_format
Stereo PCM Data Format Selection
00: I2S format
01: Left justified
10: PCM Mode A (LRCK One Plus at Master Mode)
11: PCM Mode B (LRCK One Plus at Master Mode)
8.7. Reg-38h: Stereo DAC Clock Control
Default: 2000’h
Table 16. MX38 Stereo DAC Clock Control
Name
Bits
RW
Default Description
sel_i2s_pre_div
15:13
RW
1’h
I2S Pre-Divider
000b: ÷1
001b: ÷2
011b: ÷8
101b: ÷32
010b: ÷4
100b: ÷16
Others: Reserved
sel_i2s_bclk_ms
12
RW
0’b
Master Mode Clock Relative to BCLK and LRCK
0b: 32bits (64FS)
Reserved
1b: 16bits (32FS)
Reserved
11:3
2
R
0’h
0’b
sel_dac_filter_clk
RW
Stereo DAC Filter Clock Select
0b: 256Fs
Reserved
1b: 384Fs
Reserved
1:0
R
0’h
I2S/PCM Audio DAC
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ALC5629
Datasheet
8.8. Reg-3Ah: Power Management Addition 1
Default: 0000’h
Table 17. MX3A Power Management Addition 1
Name
Bits
RW
Default Description
en_main_i2s
15
RW
0’h
I2S Digital Interface Enable
0: Disable
1: Enable
pow_zcd
14
RW
0’h
All Zero Cross Detect Power Down (Including Digital)
0: Disable
1: Enable
Reserved
13:9
8
R
0’h
0’h
Reserved
pow_softgen
RW
Power on Softgen
1: Power on
0: Power down
Note: When pow_softgen=1, whether the LINE_OUT can be driven
depends on the level on Cdepop (depneds on depop mode
selection)
Reserved
7:6
5
R
0’h
0’h
Reserved
en_lo_out_amp
RW
1: Enable LINE_OUT
0: Disable
en_lo_enhance_amp
Reserved
4
RW
R
0’h
0’h
1: Enable LINE_OUT enhance output amplifier
0: Disable (DPOP mode or normal loading mode)
Reserved
3:0
The following table describes Bit 4 & Bit 5:
Table 18. LINE_OUT Drive Ability Selection
en_lo_enhance_amp Description
en_lo_out_amp
0’b
0’b
1’b
1’b
0’b
1’b
0’b
1’b
LINE Output Off
Not Used
LINE Output for High-Impedance Loading (>KOhm)
LINE Output for Low-Impedance Loading (<100Ohm), acts as
Headphone Amplifier
I2S/PCM Audio DAC
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Datasheet
8.9. Reg-3Ch: Power Management Addition 2
Default: 0000’h
Table 19. MX3C Power Management Addition 2
Name
Bits
15:14
13
RW
R
Default Description
Reserved
pow_vref
0’h
0’h
Reserved
RW
0: Disable
1: Enable VREF for All analog circuit
pow_pll
12
RW
0’h
0: Disable
1: Enable PLL
Reserved
11
10
RW
RW
0’h
0’h
Reserved (Must be Set to ‘0’)
pow_dac_ref
0: Disable
1: Enable DAC reference circuit
pow_dac_l
9
8
RW
RW
RW
RW
RW
RW
R
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0: Disable
1: Enable left STEREO DAC and its filter clock
pow_dac_r
0: Disable
1: Enable right STEREO DAC and its filter clock
pow_dacl2hpmux_direct
pow_dacr2hpmux_direct
pow_lo_l
7
0: Disable
1: Enable left DAC to hpmux and direct path power
0: Disable
1: Enable Right DAC to hpmux and direct path power
6
5
0: Disable
1: Enable left LINE_OUT
0: Disable
1: Enable right LINE_OUT
Reserved
pow_lo_r
4
Reserved
3:0
8.10. Reg-3Eh: Power Management Addition 3
Default: 0000’h
Table 20. MX3E Power Management Addition 3
Name
Bits
RW
Default Description
pow_main_bias
15
RW
0’h
0: Disable
1: Enable Main bias of analog circuit
Reserved
14:11
10
R
0’h
0’h
Reserved
pow_lo_l_vol
RW
0: Disable
1: Enable LINE_OUT_L volume control
0: Disable
1: Enable LINE_OUT_R volume control
Reserved
pow_lo_r_vol
Reserved
9
RW
R
0’h
0’h
8:0
I2S/PCM Audio DAC
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ALC5629
Datasheet
8.11. Reg-40h: General Purpose Control
Default: 0100’h
Table 21. MX40 General Purpose Control
Name
Bits
15:9
8
RW
R
Default Description
Reserved
en_dac_hpf
0’h
1’h
Reserved
RW
STEREO DAC High Pass Filter
0: Disable
1: Enable
Reserved
7:0
R
0’h
Reserved
8.12. Reg-42h: Global Clock Control
Default: 0000’h
Table 22. MX42 Global Clock Control
RW Default Description
0’h Clock Source MUX Control
Name
Bits
sel_sysclk
15
RW
0: XTI
1: PLL
sel_pll_sour
14
RW
0’h
PLL Source Select
0: From XTI
1: From BIT_CLK
Reserved
Reserved
13:3
0
R
0’h
0’b
sel_pll_pre_div
RW
PLL Pre Divider
0b: ÷1
1b: ÷2
Figure 14. Global Clock Control
I2S/PCM Audio DAC
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Datasheet
8.13. Reg-44h: PLL M/N Code Control
Default: 0000’h
Table 23. MX44 PLL M/N Code Control
RW Default Description
RW N[7:0] Code for Analog PLL
Name
Bits
sel_pll_n_code
15:8
00’h
00000000: Div 2
…………
00000001: Div 3
11111111: Div 257
sel_pll_m_bypass
sel_pll_k_code
7
RW
RW
0’h
0’h
Bypass PLL M
0b: No bypass
1b: Bypass
6:4
K[2:0] Code for Analog PLL
000: Div 2
…………
001: Div 3
111: Div 9
sel_pll_m_code
3:0
RW
0’h
M[3:0] Code for Analog PLL
0000: Div 2
…………
0001: Div 3
1111: Div 17
8.14. Reg-5Ch: MISC1 Control
Default: 0000’h
Table 24. MX5C MISC1 Control
Default Description
Name
Bits
15:12
11
RW
R
Reserved
0’h
0’h
Reserved
LINE Out Left Zero Cross Detector Control
0: Disable 1: Enable
LINE Out Left Soft Volume Change Control
0: Disable 1: Enable
LINE Out Right Zero Cross Detector Control
0: Disable 1: Enable
LINE Out Right Soft Volume Control
en_lo_l_dezero
RW
en_lo_l_softvol
en_lo_r_dezero
en_lo_r_softvol
10
9
RW
RW
RW
0’h
0’h
0’h
8
0: Disable
Reserved
1: Enable
Reserved
7:4
3
R
0’h
0’b
en_dac_zc
RW
Enable DAC Digital Volume Zero Crossing Detect
0: Disable 1: Enable
Enable DAC Digital Soft Volume
en_dac_soft_vol
2
RW
0’b
0: Disable
Reserved
1: Enable
Reserved
1:0
R
0’h
Note: When zero cross detector is enabled, change mute volume only on zero crossing or after timeout.
I2S/PCM Audio DAC
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Datasheet
8.15. Reg-5Eh: MISC2 Control
Default: 0000’h
Table 25. MX5E MISC2 Control
Default Description
Name
Bits
RW
en_vref_fastb
15
RW
0’b
Enable Fast Vref (This Bit must be Disabled in Normal Use)
0: Enable fast Vref
Thermal Shut Down Enable
0: Disable
1: Disable fast Vref
en_thermal_shutdown
14
RW
0’b
1: Enable
Reserved
13:10
9
R
0’h
0’h
Reserved
en_dp2_lo
RW
Enable De-Pop Mode 2 of Line Out
0: Disable 1: Enable
Enable De-Pop Mode 1 of Line Out
0: Disable 1: Enable
Enable Line Out Left Mute-Unmute Depop
0: Disable 1: Enable
Enable Line Out Right Mute-Unmute Depop
en_dp1_lo
en_smt_lo_l
en_smt_lo_r
smt_en
8
7
6
5
RW
RW
RW
RW
0’h
0’h
0’h
0’h
0: Disable
1: Enable
Mute-Unmute Depop
0: Disable
1: Enable
Reserved
4
3
R
0’h
0’h
Reserved
mute_dac_l
RW
Mute Main DAC Left Input
0: On
1: Mute (-∞ dB)
mute_dac_r
Reserved
2
RW
R
0’h
0’h
Mute Main DAC Right Input
0: On
1: Mute (-∞ dB)
1:0
Reserved
8.16. Reg-6Ah: Private Register Index
Default: 0000’h
Table 26. MX6A Private Register Index
RW Default Description
0’h Reserved
0’h
Name
Bits
15:7
6:0
Reserved
R
private_reg_index
RW
Private Register Index
I2S/PCM Audio DAC
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Datasheet
8.17. Reg-6Ch: Private Register Data
Default: 0000’h
Table 27. MX6C Private Register Data
Default Description
0’h Private Register Data Port
Name
Bits
RW
private_reg_data
15:0
RW
8.18. Private-39h: Digital Internal Register
Default: 8800’h
Table 28. PR39 Digital Internal Register
Name
Bits
RW
Default Description
sel_pad_drive
15
RW
1’h
Pad Drive Capability
0b: 5mA
Reserved
1b: (5+6) 11mA
Reserved
osc_curr
14:12
11:9
R
0’b
RW
100’b Oscillator Drive Current Control
000: 1x bias current
010: 4x
100: 16x
001: 2x
011: 8x
………..
111: 128x
Note: The oscillator startup current is set to maximum, and
controlled by osc_curr after 512 clocks. The digital clock input is
enabled after 1024 clocks.
Reserved
8:0
R
0’b
Reserved
I2S/PCM Audio DAC
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ALC5629
Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 29. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Typical
Maximum
Units
Power Supplies
Digital Power for Core
Digital Power for IO and PLL
Analog Power
DCVDD
DBVDD
AVDD
Ta
-0.3
-0.3
-0.3
-20
-
-
-
-
-
3.63
3.63
3.63
+85
V
V
V
oC
oC
Ambient Operating Temperature
Storage Temperature
Ts
-40
+125
9.1.2. Recommended Operating Conditions
Table 30. Recommended Operating Conditions
Parameter
Digital IO Buffer
Digital Core
Analog
Symbol
DBVDD
DCVDD
AVDD
Min
1.8
Typ
3.3
3.3
3.3
Max
3.6
Units
V
1.8
3.6
V
2.3
3.6
V
Note: A 1µF Capacitor must be connected from AVDD to AGND, and should be placed as close as possible to the AVDD
pin of the ALC5629.
9.1.3. Static Characteristics
DBVDD= 3.3V, Tambient=25°C, with 25pF external load.
Table 31. Threshold Voltage
Parameter
Symbol
Vin
Minimum
Typical
Maximum
Units
V
Input Voltage Range
-0.30
-
-
-
-
-
-
-
DBVDD +0.30
Low Level Input Voltage
High Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Low Level Input Voltage (JD2)
High Level Input Voltage (JD2)
VIL
-
0.33*DBVDD
V
VIH
0.66*DBVDD
-
V
VOH
VOL
VIL
0.9*DBVDD
-
V
-
0.1*DBVDD
0.33*AVDD
-
V
-
V
VIH
0.66*AVDD
V
I2S/PCM Audio DAC
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Datasheet
9.2. Analog Performance Characteristics
• Tambient=25oC, DBVDD=DCVDD=1.8V, AVDD=3.3V, 1kHz input
Standard Test Conditions
sine wave; Sampling Frequency=48kHz; 0dB=1Vrms, 10KΩ/50pF
load; Test bench Characterization BW: 10Hz~22kHz, 0dB attenuation
Table 32. Analog Performance Characteristics
Parameter
Minimum
Typical
Maximum
Units
Vrms
dBFS
Full-Scale Output Voltage
LINE_OUT Outputs
-
-
1.0
-
-
S/N (A Weighted)
LINE_OUT
95
THD+N
LINE_OUT
-
-
-80
-50
1.5
-80
45
-
-
-
-
-
dBFS
dB
Power Supply Rejection (217Hz)
Amplifier Gain Step
-
dB
Crosstalk Between Input Channels
LINE_OUT Output Power (RL=16Ω) (en_hp_enhance_amp=‘1’)
Digital Power Supply Current (Power Down Mode)
DCVDD=1.8V, DBVDD=1.8V (Include POR Circuit)
Analog Power Supply Current (DAC to Headphone Without Load)
AVDD=DCVDD=DBVDD=3.3V
Analog Power Supply Current (Power Down Mode)
AVDD=3.3V
-
dB
25
mW
-
-
-
10
-
µA
8
mA
-
-
-
-
0.5
-
1
-
µA
AVDD
ms
VREF Output Voltage
VREF Rising Time at Fast Mode (C=4.7µF)
50
I2S/PCM Audio DAC
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ALC5629
Datasheet
9.3. AC Timing Characteristics
9.3.1. I2C Control Interface
Table 33. I2C Control Interface Timing
Parameter
Symbol
tw(9)
tw(10)
f
Minimum
Typical
Maximum
Units
µs
ns
Clock Pulse Duration
Clock Pulse Duration
Clock Frequency
Re-Start Setup Time
Start Hold Time
Data Setup Time
Data Hold Time
Rising Time
1.3
600
0
-
-
-
-
-
-
-
-
-
-
-
-
-
400K*
Hz
ns
tsu(6)
th(5)
tsu(7)
th(6)
tr
600
600
100
-
-
-
ns
-
ns
900
300
300
-
ns
-
ns
Falling Time
tf
-
ns
Stop Setup Time
tsu(8)
tsp
600
0
ns
Pulse Width of Spikes Suppressed
Input Filter
Note: ‘*’indicates the host must provide MCLK higher than 4MHz to the ALC5629 during I2C control interface access.
If MCLK provides 128*8KHz, the I2C clock frequency can only support 100KHz.
50
ns
Figure 15. I2C Control Interface Waveform
I2S/PCM Audio DAC
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ALC5629
Datasheet
9.3.2. I2S/PCM Interface Master Mode
Table 34. I2S Master Mode Timing
Parameter
Symbol
tLRD
Minimum
Typical
Maximum
Units
ns
LRCK Output to BCLK Delay
Data Output to BCLK Delay
Data Input Setup Time
Data Input Hold Time
-
-
-
-
-
30
30
-
tADD
-
ns
tDAS
10
10
ns
tDAH
-
ns
Figure 16. I2S Master Mode Waveform
I2S/PCM Audio DAC
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Datasheet
9.3.3. I2S/PCM Interface Slave Mode
Table 35. I2S Slave Mode Timing
Parameter
Symbol
tBCH
Minimum
Typical
Maximum
Units
ns
BCLK High Pulse Width
BCLK Low Pulse Width
LRCK Input Setup Time
Data Input Setup Time
Data Input Hold Time
20
20
30
10
10
-
-
-
-
-
-
-
-
-
-
tBCL
ns
tLRS
ns
tDAS
ns
tDAH
ns
Figure 17. I2S Slave Mode Waveform
I2S/PCM Audio DAC
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ALC5629
Datasheet
10. Application Circuits
Application circuits are for design reference only. System designers are suggested to visit Realtek’s web
site to download the latest application circuits. To get the best compatibility in hardware design and
software driver, Realtek should confirm modifications of application circuits.
DVDD
DBVDD
DCVDD
C1
C2
1000pF
1uF
U1-1
close to IC
close to IC
AVDD
AVDD
3
4
1
24
LINE_OUT_L
LINE_OUT_R
NC
NC
LINE_OUT_L
LINE_OUT_R
CA1
1uF
CA2
1000pF
BCLK
LRCK
DACDAT
6
5
7
17
18
BCLK
LRCK
SDAC
NC
NC
QFN24
16
22
Cdepop
VREF
Cdepop
VREF
C4
22p
C5 CLK_crystal1
CLK_crystal2
22p
8
9
15
C6
1u
XTI
XTO
OSC_EN
C9
C8
0.1u
RGND1
0
13
14
SCLK
SDA
4.7u
SCLK
SDA
RGND2
BEAD
DBVDD
ALC5629
DGND
AGND
POWER / GND
R33
U2
1M
Crystal CLK
C22 1uF
SPK_AMP_L
LINE_OUT_R
LINE_OUT_L
1
2
CLK_crystal2
CLK_crystal1
C23 1uF
C19
20p
C20
SPK_AMP_R
Crystal 24.576MHz
20p
Figure 18. Application Circuits
I2S/PCM Audio DAC
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Datasheet
11. Mechanical Dimensions
QFN-24 Package; 4x4mm Outline
Symbol
Dimension in mm
Nom
Dimension in inch
Nom
Min
0.75
0.00
-
Max
1.00
0.05
0.70
Min
0.030
0.000
-
Max
0.039
0.002
0.028
A
A1
A2
A3
b
0.85
0.034
0.02
0.001
0.65
0.026
0.20 REF
0.25
0.008 REF
0.010
0.18
2.00
0.30
0.30
2.50
0.50
0.007
0.078
0.012
0.012
0.098
0.020
D/E
D2/E2
e
4.00 BSC
2.25
0.158 BSC
0.088
0.50 BSC
0.40
0.020 BSC
0.016
L
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MO-220.
I2S/PCM Audio DAC
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Datasheet
12. Ordering Information
Table 36. Ordering Information
Part Number
ALC5629-GR
ALC5629-GRT
Package
Status
QFN-24 in ‘Green’ Package (Tray)
Mass Production
Mass Production
QFN-24 in ‘Green’ Package (Tape & Reel)
Note: See page 6 for package and version identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
I2S/PCM Audio DAC
32
Track ID: JATR-1076-21 Rev. 1.0
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