ALC861DTS-GR [REALTEK]
7.1 CHANNEL HIGH DEFINITION AUDIO CODEC;
| 型号： | ALC861DTS-GR |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | 7.1 CHANNEL HIGH DEFINITION AUDIO CODEC |
| 文件： | 总67页 (文件大小：1037K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC861-GR
ALC861DTS-GR
7.1 CHANNEL HIGH DEFINITION AUDIO CODEC
DATASHEET
Rev. 1.3
07 November 2005
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-557-6047
www.realtek.com.tw
ALC861
Datasheet
COPYRIGHT
©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC861 Audio Codec chip.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
Release Date
2005/07/05
2005/08/24
Summary
First release.
1.1
Update Table 29, page 28.
Update section 9.3 Analog Performance, page 56, and Table 61, page 56.
Update section 12 Ordering Information, page 59.
Correct JDREF resistor value to 4.99K. See Table 3, page 6.
1.2
1.3
2005/08/25
2005/11/07
Correct error in section 2.1 Hardware Features, page 2 (input and output
re-tasking).
Correct error in Table 3, page 6.
Correct error in Table 61, page 56 (VREFOUTx Output Voltage).
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Datasheet
Table of Contents
1. General Description .................................................................................................... 1
2. Features ........................................................................................................................ 2
2.1. HARDWARE FEATURES.....................................................................................................................2
2.2. SOFTWARE FEATURES ......................................................................................................................2
3. System Applications .................................................................................................... 2
4. Block Diagram............................................................................................................. 3
5. Pin Assignments........................................................................................................... 4
5.1. PACKAGE AND VERSION IDENTIFICATION ........................................................................................4
6. Pin Descriptions........................................................................................................... 5
6.1. DIGITAL I/O PINS .............................................................................................................................5
6.2. ANALOG I/O PINS.............................................................................................................................5
6.3. FILTER/REFERENCE ..........................................................................................................................6
6.4. POWER/GROUND ..............................................................................................................................6
6.5. NC (NOT CONNECTED) PINS ............................................................................................................6
7. High Definition Audio Link Protocol ........................................................................ 7
7.1. LINK SIGNALS ..................................................................................................................................7
7.1.1.
7.1.2.
Signal Definitions...................................................................................................................................................7
Signaling Topology.................................................................................................................................................8
7.2. FRAME COMPOSITION.......................................................................................................................9
7.2.1.
7.2.2.
7.2.3.
7.2.4.
7.2.5.
Outbound Frame – Single SDO..............................................................................................................................9
Outbound Frame – Multiple SDOs.......................................................................................................................11
Inbound Frame – Single SDI................................................................................................................................12
Inbound Frame – Multiple SDIs...........................................................................................................................13
Variable Sample Rates..........................................................................................................................................13
7.3. RESET AND INITIALIZATION............................................................................................................15
7.3.1.
7.3.2.
7.3.3.
Link Reset .............................................................................................................................................................15
Codec Reset..........................................................................................................................................................17
Codec Initialization Sequence ..............................................................................................................................17
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7.4. VERB AND RESPONSE FORMAT.......................................................................................................18
7.4.1.
7.4.2.
Command Verb Format ........................................................................................................................................18
Response Format..................................................................................................................................................18
8. Supported Verbs and Parameters............................................................................ 19
8.1. VERB – GET PARAMETERS (VERB ID=F00H) .................................................................................19
8.1.1.
8.1.2.
8.1.3.
8.1.4.
8.1.5.
8.1.6.
8.1.7.
8.1.8.
8.1.9.
Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................19
Parameter – Subsystem ID (Verb ID=F00h, Parameter ID=01h) .......................................................................19
Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................20
Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................20
Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)...........................................................21
Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................21
Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................22
Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................23
Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................24
8.1.10. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................25
8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)................................26
8.1.12. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)..............................26
8.1.13. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ............................................................27
8.1.14. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh).......................................................27
8.2. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ....................................................28
8.3. VERB – SET CONNECTION SELECT (VERB ID=701H) .....................................................................28
8.4. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H)..............................................................29
8.5. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...............................................................................35
8.6. VERB – SET AMPLIFIER GAIN (VERB ID=3H).................................................................................37
8.7. VERB – GET CONVERTER FORMAT (VERB ID=AH)........................................................................38
8.8. VERB – SET CONVERTER FORMAT (VERB ID=2H) .........................................................................39
8.9. VERB – GET POWER STATE (VERB ID=F05H)................................................................................40
8.10. VERB – SET POWER STATE (VERB ID=705H).................................................................................41
8.11. VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...................................................41
8.12. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ....................................................42
8.13. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H)...................................................................42
8.14. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...................................................................43
8.15. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...............................................44
8.16. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ................................................45
8.17. VERB – GET PIN SENSE (VERB ID=F09H)......................................................................................45
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8.18. VERB – EXECUTE PIN SENSE (VERB ID=709H)..............................................................................46
8.19. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH/F1DH/F1EH/F1FH).............................46
8.20. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR
BYTES 0, 1, 2, 3).............................................................................................................................47
8.21. VERB – GET BEEP GENERATOR (VERB ID=F0AH) .......................................................................47
8.22. VERB – SET BEEP GENERATOR (VERB ID=70AH) ........................................................................48
8.23. VERB – FUNCTION RESET (VERB ID=7FFH) ..................................................................................48
8.24. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH)..............49
8.25. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ................50
8.26. VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/D22H/F23H) ......................................51
8.27. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR
[15:8], 720H FOR [7:0]) ..................................................................................................................51
9. Electrical Characteristics ......................................................................................... 52
9.1. DC CHARACTERISTICS ...................................................................................................................52
9.1.1.
9.1.2.
9.1.3.
Absolute Maximum Ratings..................................................................................................................................52
Threshold Voltage.................................................................................................................................................52
S/PDIF Output Characteristics ............................................................................................................................53
9.2. AC CHARACTERISTICS ...................................................................................................................53
9.2.1.
9.2.2.
9.2.3.
9.2.4.
Link Reset and Initialization Timing.....................................................................................................................53
Link Timing Parameters at the Codec ..................................................................................................................54
S/PDIF Output Timing..........................................................................................................................................55
Test Mode..............................................................................................................................................................55
9.3. ANALOG PERFORMANCE ................................................................................................................56
10. Application Circuits .................................................................................................. 57
11. Mechanical Dimensions ............................................................................................ 58
11.1. MECHANICAL DIMENSIONS NOTES.................................................................................................59
12. Ordering Information............................................................................................... 59
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List of Tables
Table 1. Digital I/O Pins ...........................................................................................................................5
Table 2. Analog I/O Pins...........................................................................................................................5
Table 3. Filter/Reference...........................................................................................................................6
Table 4. Power/Ground.............................................................................................................................6
Table 5. NC (Not Connected) Pins ...........................................................................................................6
Table 6. Link RESET#..............................................................................................................................7
Table 7. HDA Signal Definitions..............................................................................................................8
Table 8. Defined Sample Rate and Transmission Rate...........................................................................14
Table 9. 48kHz Variable Rate of Delivery Timing .................................................................................14
Table 10. 44.1kHz Variable Rate of Delivery Timing ..............................................................................14
Table 11. 40-Bit Commands in 4-Bit Verb Format...................................................................................18
Table 12. 40-Bit Commands in 12-Bit Verb Format.................................................................................18
Table 13. Solicited Response Format .......................................................................................................18
Table 14. Unsolicited Response Format ...................................................................................................18
Table 15. Verb – Get Parameters (Verb ID=F00h) ...................................................................................19
Table 16. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)...................................................19
Table 17. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ................................................20
Table 18. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)............................20
Table 19. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) .................................21
Table 20. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h).......................21
Table 21. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) .........................22
Table 22. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ......................23
Table 23. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) ........................24
Table 24. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..........................................25
Table 25. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) .....26
Table 26. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ...26
Table 27. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ..................................27
Table 28. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) .............................27
Table 29. Verb – Get Connection Select Control (Verb ID=F01h)...........................................................28
Table 30. Verb – Set Connection Select (Verb ID=701h).........................................................................28
Table 31. Verb – Get Connection List Entry (Verb ID=F02h)..................................................................29
Table 32. Verb – Get Amplifier Gain (Verb ID=Bh) ................................................................................35
Table 33. Verb – Set Amplifier Gain (Verb ID=3h)..................................................................................37
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Table 34. Verb – Get Converter Format (Verb ID=Ah)............................................................................38
Table 35. Verb – Set Converter Format (Verb ID=2h)..............................................................................39
Table 36. Verb – Get Power State (Verb ID=F05h) ..................................................................................40
Table 37. Verb – Set Power State (Verb ID=705h)...................................................................................41
Table 38. Verb – Get Converter Stream, Channel (Verb ID=F06h)..........................................................41
Table 39. Verb – Set Converter Stream, Channel (Verb ID=706h)...........................................................42
Table 40. Verb – Get Pin Widget Control (Verb ID=F07h) ......................................................................42
Table 41. Verb – Set Pin Widget Control (Verb ID=707h).......................................................................43
Table 42. Verb – Get Unsolicited Response Control (Verb ID=F08h) .....................................................44
Table 43. Verb – Set Unsolicited Response Control (Verb ID=708h) ......................................................45
Table 44. Verb – Get Pin Sense (Verb ID=F09h)......................................................................................45
Table 45. Verb – Execute Pin Sense (Verb ID=709h)...............................................................................46
Table 46. Verb – Get Configuration Default (Verb ID=F1Ch/F1Dh/F1Eh/F1Fh)....................................46
Table 47. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3) ............................................................47
Table 48. Verb – Get BEEP Generator (Verb ID= F0Ah).........................................................................47
Table 49. Verb – Set BEEP Generator (Verb ID= 70Ah)..........................................................................48
Table 50. Verb – Function Reset (Verb ID=7FFh)....................................................................................48
Table 51. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)........................49
Table 52. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) ..........................50
Table 53. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)........................................51
Table 54. Verb – Set Subsystem ID [31:0] (Verb ID=723h for [31:24], 722h for [23:16], 721h for
[15:8], 720h for [7:0])...............................................................................................................51
Table 55. Absolute Maximum Ratings .....................................................................................................52
Table 56. Threshold Voltage .....................................................................................................................52
Table 57. S/PDIF Output Characteristics..................................................................................................53
Table 58. Link Reset and Initialization Timing ........................................................................................53
Table 59. Link Timing Parameters at the Codec.......................................................................................54
Table 60. S/PDIF Output Timing..............................................................................................................55
Table 61. Analog Performance .................................................................................................................56
Table 62. Ordering Information................................................................................................................59
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Datasheet
List of Figures
Figure 1. Block Diagram ..........................................................................................................................3
Figure 2. Pin Assignments........................................................................................................................4
Figure 3. HDA Link Protocol ...................................................................................................................7
Figure 4. Bit Timing .................................................................................................................................8
Figure 5. Signaling Topology ...................................................................................................................9
Figure 6. SDO Outbound Frame.............................................................................................................10
Figure 7. SDO Stream Tag is Indicated in SYNC ..................................................................................10
Figure 8. Stripped Stream on Multiple SDO ..........................................................................................11
Figure 9. SDI Inbound Stream................................................................................................................12
Figure 10. SDI Stream Tag and Data........................................................................................................12
Figure 11. Codec Transmits Data Over Multiple SDI ..............................................................................13
Figure 12. Link Reset Timing...................................................................................................................16
Figure 13. Codec Initialization Sequence.................................................................................................17
Figure 14. Link Reset and Initialization Timing.......................................................................................53
Figure 15. Link Signal Timing..................................................................................................................54
Figure 16. Output Timing .........................................................................................................................55
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1. General Description
The ALC861 7.1 Channel High Definition Audio codec with UAA (Universal Audio Architecture),
features four stereo DACs and one stereo ADC. The ALC861 is designed for multimedia PC systems.
The ALC861 provides 7.1 output channels, along with mixing, mute, and gain control functions to
provide an integrated audio solution for PCs.
Parts of analog IO are input and output capable, and three headphone amplifiers are also integrated to
drive earphones on front and rear panels.
The ALC861 supports S/PDIF output function and a sampling rate of up to 96kHz, offering easy connection
of PCs to high-quality consumer electronic products such as AC-3 decoders/speakers, and mini disk
devices.
The ALC861 supports host/soft audio from the Intel ICH chipset, and also from any other HDA
compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and software
utilities like Karaoke mode, environment emulation, software equalizer, and HRTF 3D positional audio,
the ALC861 provides an excellent entertainment package and game experience for PC users.
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2. Features
2.1. Hardware Features
Four Stereo DACs support 16/20/24-bit PCM format for 7.1 channel audio solution
One stereo ADC supports 16-bit PCM format
Front/Surround/Cen/LFE/Side Surround-DACs support independent 48KHz/96KHz sample rate
ADC supports 48K/96K sample rate
MIC1 (port-B) LINE1 (port-C), LINE2 (port-E) and MIC2 (port-F) are stereo input and output
re-tasking
High-quality differential CD input
Two jack detection pins: each supports detection of up to 4 jacks
Supports 48KHz/96KHz S/PDIF output
Supports analog PCBEEP input
Integrates digital BEEP generator
Power support: Digital: 3.3V; Analog: 5.0V
48-pin LQFP ‘Green’ package
2.2. Software Features
Meets Microsoft WHQL/WLP 2.0 audio requirements
EAX™ 1.0 & 2.0 compatible
Direct Sound 3D™ compatible
A3D™ compatible
I3DL2 compatible
HRTF 3D Positional Audio
Emulation of 26 sound environments to enhance gaming experience
10 Software Equalizer Bands
Voice Cancellation and Key Shifting in Karaoke mode
ALC861DTS-GR features optional DTS® CONNECT™ software
3. System Applications
Multimedia PCs
3D PC Games
Information Appliances (IA)
Voice Recognition
Audio Conferencing
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Datasheet
4. Block Diagram
Figure 1. Block Diagram
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5. Pin Assignments
Figure 2. Pin Assignments
5.1. Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2. The version number is shown
in the location marked ‘V’.
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6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Type Pin No. Description Characteristic Definition
Name
RESET#
SYNC
I
I
11
10
6
H/W reset
Schmitt trigger input, VIL=1.0V, VIH=2.0V
Schmitt trigger input, VIL=1.0V, VIH=2.0V
Schmitt trigger input, VIL=1.0V, VIH=2.0V
Schmitt trigger input, VIL=1.0V, VIH=2.0V
Sample Sync (48kHz)
24MHz Bit clock input
Serial TDM data input
Serial TDM data output
BCLK
I
SDATA-OUT
SDATA-IN
I
5
O
8
Schmitt output, VOH=0.9*DVDD,
VOL=0.1*DVDD
SPDIFO
O
48
S/PDIF output
TTL output has 12mA@75Ω driving capability
Total: 6 Pins
6.2. Analog I/O Pins
Table 2. Analog I/O Pins
Name
Type Pin No. Description
Characteristic Definition
LINE2-L
LINE2-R
MIC2-L
IO
IO
IO
14
15
16
2nd line input left channel
Analog input/output. Default is input (JACK-E)
2nd line input right channel Analog input/output. Default is input (JACK -E)
2
nd stereo microphone input Analog input/output. Default is input (JACK -F)
left channel
2
nd stereo microphone input Analog input/output. Default is input (JACK -F)
MIC2-R
IO
17
right channel
CD-L
I
I
18
19
20
21
CD input left channel
Analog input. 1.6Vrms of full scale input
CD-GND
CD-R
CD input reference ground Analog input. 1.6Vrms of full scale input
I
CD input right channel
Analog input. 1.6Vrms of full scale input
MIC1-L
IO
1st stereo microphone input Analog input/output. Default is input (JACK -B)
left channel
MIC1-R
IO
22
1st stereo microphone input Analog input/output. Default is input (JACK -B)
right channel
LINE1-L
LINE1-R
PCBEEP
FRONT-
IO
IO
I
23
24
12
35
1st line input left channel
1st line input right channel
External PCBEEP input
Front output left channel
Analog input/output. Default is input (JACK -C)
Analog input/output. Default is input (JACK -C)
Analog input. 1.6Vrms of full scale input
Analog output (JACK -D)
IO
OUT-L
FRONT-
OUT-R
IO
36
Front output right channel
Surround out left channel
Analog output (JACK -D)
Analog output (JACK -A)
SURR-OUT-L
SURR-OUT-R
CEN-OUT
LFE-OUT
IO
IO
O
39
41
43
44
Surround out right channel Analog output (JACK -A)
Center output
Analog output (JACK -G)
Analog output (JACK -G)
O
Low Frequency output
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Name
Type Pin No. Description
Characteristic Definition
SIDESURR-
OUT-L
O
45
Side Surround output left
channel
Analog output (JACK -H)
SIDESURR-
OUT-R
O
46
Side Surround output right Analog output (JACK -H)
channel
Sense A
I
I
13
34
Jack Detect pin l
Jack Detect pin 2
Jack resistor network input 1
Jack resistor network input 2
Total: 22 Pins
Sense B
6.3. Filter/Reference
Table 3. Filter/Reference
Type Pin No. Description Characteristic Definition
Name
VREF
-
27
28
30
31
32
Reference voltage
Typical 2.25V,10uf capacitor to analog ground
3.2V reference voltage
MIC1-VREFO-L
MIC2-VREFO
LINE2-VREFO
MIC1-
O
O
O
O
Bias voltage for MIC1 jack
Bias voltage for MIC2 jack
Bias voltage for LINE2 jack
Bias voltage for MIC1 jack
3.2V reference voltage
3.2V reference voltage
3.2V reference voltage
VREFO-R
JDREF
-
40
Reference resistor for Jack
detection
4.99K, 1% external resistor to analog ground
Total: 6 Pins
6.4. Power/Ground
Table 4. Power/Ground
Type Pin No Description Characteristic Definition
Analog VDD (5V or 3.3V) Analog power for mixer and amplifier
Analog GND Analog ground for mixer and amplifier
Analog VDD (5V or 3.3V) Analog power for DACs and ADCs
Name
AVDD1
AVSS1
AVDD2
AVSS2
DVDD
DVSS
I
I
I
I
I
I
I
I
25
26
38
42
1
Analog GND
Analog ground for DACs and ADCs
Digital power
Digital VDD (3.3V)
Digital GND
4
Digital ground
DVDD
DVSS
9
Digital VDD (3.3V)
Digital GND
Digital power
7
Digital ground
Total: 8 Pins
6.5. NC (Not Connected) Pins
Table 5. NC (Not Connected) Pins
Symbol
Type
Pin No
Description
Not Connected.
Total: 6 Pins
NC
2, 3, 29, 33, 37, 47
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Datasheet
7. High Definition Audio Link Protocol
7.1. Link Signals
The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 3 shows the basic concept of the HDA link protocol.
T
= 20.833 µs (48KHz)
frame_sync
Previous Frame
BCLK
Next Frame
Frame SYNC= 8 BCLK
Stream 'A' Tag
(Here 'A' = 5)
Stream 'B' Tag
(Here 'B' = 6)
SYNC
SDO
SDI
Command Stream
(40-bit data)
Stream 'B' Data
Stream 'A' Data
Stream
'C' Tag
Stream 'C' Data
Response Stream
(36-bit data)
(n bytes + 10-bit data)
RST#
Figure 3. HDA Link Protocol
Table 6. Link RESET#
7.1.1. Signal Definitions
Item
BCLK
SYNC
Description
24.0MHz bit clock sourced from the HDA controller and connecting to all codecs.
A 48kHz signal used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
SDO
Serial Data Output signal driven by the HDA controller to all codecs. Commands and data streams are
carried on SDO. The data rate is double-pumped; the controller drives data onto the SDO, the codec samples
data present on SDO with respect to each edge of BCLK. The HDA controller must support at least one
SDO. To extend outbound bandwidth, multiple SDOs may be supported.
SDI
Serial Data Input signal driven by the codec. This is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI. Up to a maximum of 15 SDI’s can be supported.
SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of
BCLK. SDI can be driven by the controller to initialize the codec’s ID.
RESET# Active low reset signal. Asserted to reset the codec to default power-on state. RESET# is sourced from the
HDA controller and connects to all codecs.
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Datasheet
Table 7. HDA Signal Definitions
Signal Name
BCLK
SYNC
SDO
Source
Controller
Type for Controller Description
Output
Output
Global 24.0MHz bit clock.
Controller
Global 48kHz Frame Sync and outbound tag signal.
Serial data output from controller.
Controller
Output
SDI
Codec/Controller
Input/Output
Serial data input from codec. Weakly pulled down by the
controller.
RESET#
Controller
Output
Global active low reset signal.
BCLK
8-Bit Frame SYNC
SYNC
Start of Frame
7
6
5
4
3
2
1
0
999 998 997 996995 994 993 992 991 990
SDO
SDI
3
2
1
0
499
498
497
496
495
494
Codec samples SDO at both rising and falling edge of BCLK
Controller samples SDI at rising edge of BCLK
Figure 4. Bit Timing
7.1.2. Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RESET#, BCLK, SYNC, SDO0 and SDO1 are driven by the controller to codecs. Each codec drives its
own point-to-point SDI signal(s) to the controller.
Figure 5, on page 9, shows the possible connections between the HDA controller and codecs:
• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
• Codec 1 has two SDOs for doubled outbound rate, and a single SDI for normal inbound rate
• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
• Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 9, describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 5 can be implemented concurrently in an HDA system. The ALC861 is
designed to receive a single SDO stream.
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Datasheet
SDI14
.
.
.
.
.
.
SDI13
SDI2
HDA
SDI1
Controller
SDI0
SDO1
SDO0
SYNC
BCLK
RST#
. . .
Codec 0
Codec 1
Codec 2
Codec N
Single SDO
Single SDI
Two SDOs
Single SDI
Single SDO
Two SDIs
Two SDOs
Multiple SDIs
Figure 5. Signaling Topology
7.2. Frame Composition
7.2.1. Outbound Frame – Single SDO
An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be 2 blocks in the same stream to carry
96kHz samples (Figure 6).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 7).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
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Datasheet
A 48kHz Frame is composed of Command stream and multiple Data streams
Previous Frame
Next Frame
Frame SYNC
Stream 'A' Tag
(Here 'A' = 5)
Stream 'X' Tag
(Here 'X' = 6)
SYNC
SDO
Command Stream
0s
Stream 'A' Data
Stream 'X' Data
Padded at the
end of Frame
Null Field
One or multiple blocks in a stream
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block1 includes (N)th time of samples, Block2
includes (N+1)th time of samples
..
.
Block 1
Block 2
Block Y
..
.
Sample 1 Sample 2
Sample Z
Z channels of PCM sample
...
msb first in a sample
msb
lsb
Figure 6. SDO Outbound Frame
BCLK
SYNC
Stream Tag
msb lsb
1 0 1 0
Stream=10
(4-Bit)
Preamble
(4-Bit)
Data of Stream 10
7 6 5 4 3 2 1 0
SDO
Previous Stream
Figure 7. SDO Stream Tag is Indicated in SYNC
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Datasheet
7.2.2. Outbound Frame – Multiple SDOs
The HDA controller allows two SDO signals to be used to strip outbound data, completing transmission
in less time to get more bandwidth. If software determines that the target codec supports multiple SDO
capability, it enables the ‘Strip Control’ bit in the controller’s Output Stream Control Register to initiate a
specific stream (Stream ‘A’ in Figure 8) to be transmitted on multiple SDOs. In this case, the MSB of
stream data is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a stripped stream. The codec does not support multiple SDOs connected to
SDO0.
To ensure that all codecs can determine their corresponding stream, the command stream is not stripped.
It is always transmitted on SDO0, and copied on SDO1.
Stream 'A' Tag
Stream 'X' Tag
Stream 'Y' Tag
SYNC
Frame SYNC
Command Stream
Stream 'A' to Codec A
. .
.
SDO
0
Stream 'X' to Codec X
Stream 'Y' to Codec Y
D
D
n
n-2
. .
.
SDO
1
0s
Command Stream
0s
. .
.
D
D
n-3
n-1
Stream A is "bit-stripped" on SDO0 and SDO1
Command stream is unchanged, not stripped
Figure 8. Stripped Stream on Multiple SDO
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Datasheet
7.2.3. Inbound Frame – Single SDI
An Inbound Frame – Single SDI is composed of one 36-bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each
rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 9).
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte length
(Figure 10).
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams
Previous Frame
Frame SYNC
Next Frame
SYNC
SDI
0s
Stream 'X'
Response Stream
Stream 'A'
Null Field
Padded at the end of Frame
Stream Tag
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples
Block 1
...
Block Y Null Pad
Block 2
Sample 1 Sample 2
msb ...
...
Sample Z Z channels of PCM sample
lsb msb first in a sample
Figure 9. SDI Inbound Stream
BCLK
SDI
n-Bit Sample Block
Null Pad
Next Stream
Stream Tag
Data Length in Bytes
B5 B4 B3 B2 B1
B8
Dn-1 Dn-2
0
0
B9
B7 B6
B0
D0
0
0
(Data Length in Bytes *8)-Bit
A Complete Stream
Figure 10. SDI Stream Tag and Data
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Datasheet
7.2.4. Inbound Frame – Multiple SDIs
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data onto separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
SYNC
Frame SYNC
Stream 'A'
SDI
Tag A
Data A
Response Stream
Stream 'X'
0s
Stream 'Y'
0s
0
Stream 'B'
Data B
SDI
Tag B
Response Stream
1
Stream A, B, X, and Y are independent and have separate IDs
Codec drives SDI0 and SDI1
Figure 11. Codec Transmits Data Over Multiple SDI
7.2.5. Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable sample rates are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table 8, page 14, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 9, page 14, shows the delivery cadence
of variable rates based on 48kHz.
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames. The cadence
“12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)”
interleaves 13 frames containing no sample blocks in every 160 frames. It provides a low long-term
frequency drift for 44.1kHz of delivery rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this
cadence AND interleave n empty frames. Rates in multiples (n) of 44.1kHz applying this cadence contain
n sample blocks in the non-empty frame AND interleave an empty frame between non-empty
frames (Table 10, page 14).
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Datasheet
Table 8. Defined Sample Rate and Transmission Rate
(Sub) Multiple 48kHz Base 44.1kHz Base
1/6
1/4
1/3
1/2
2/3
1
8kHz (1 sample block every 6 frames)
12kHz (1 sample block every 4 frames)
16kHz (1 sample block every 3 frames)
11.025kHz (1 sample block every 4 frames)
22.05kHz (1 sample block every 2 frames)
32kHz (2 sample blocks every 3 frames)
48kHz (1 sample block per frame)
96kHz (2 sample blocks per frame)
192kHz (4 sample blocks per frame)
44.1kHz (1 sample block per frame)
88.2kHz (2 sample blocks per frame)
176.4kHz (4 sample blocks per frame)
2
4
Table 9. 48kHz Variable Rate of Delivery Timing
Rate
8kHz
Delivery Cadence
YNNNNN (repeat)
YNNN (repeat)
YNN (repeat)
Y2NN (repeat)
Y (repeat)
Description
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 4 frames
One sample block is transmitted in every 3 frames
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 6 frames
Two sample blocks are transmitted in each frame
Four sample blocks are transmitted in each frame
12kHz
16kHz
32kHz
48kHz
96kHz
192kHz
Y2 (repeat)
Y4 (repeat)
N: No sample block in a frame
Y: One sample block in a frame
Yx: X sample blocks in a frame
Table 10. 44.1kHz Variable Rate of Delivery Timing
Delivery Cadence
Rate
11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)
174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{-} =NNNN
22.05kHz:
{12}=YNYNYNYNYNYNYNYNYNYNYNYN
{11}=YNYNYNYNYNYNYNYNYNYNYN
{-} =NN
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Datasheet
44.1kHz
88.2kHz
174.4kHz
12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with
no sample block.
122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with
no sample block.
124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with
no sample block.
7.3. Reset and Initialization
There are two types of reset within an HDA link:
• Link Reset.
Generated by assertion of the RESET# signal. All codecs return to their power-on state
• Codec Reset.
Generated by software directing a command to reset a specific codec back to its default state
An initialization sequence is requested after any of the following three events:
1. Link Reset
2. Codec Reset
3. Codec changes its power state, e.g., hot docking a codec to an HDA system
7.3.1. Link Reset
A link reset may be caused by any of the following three events:
1. The HDA controller asserts RESET# for any reason (power up, or PCI reset)
2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
3. Software initiates power management sequences. Figure 12, page 16, shows the ‘Link Reset’ timing
including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)
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Datasheet
Enter ‘Link Reset’:
n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
link reset
o As the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the
end of the frame
p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
q The controller asserts the RESET# signal to low, and enters the ‘Link Reset’ state
r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
Exit from ‘Link Reset’:
s If BCLK is re-started for any reason (codec, wake-up event, power management, etc.)
t Software is responsible for de-asserting RESET# after a minimum of 100µs BCLK running time (the
100µsec provides time for the codec PLL to stabilize)
u Minimum of 4 BCLKs after RESET# is de-asserted, the controller starts to signal normal frame SYNC
v The codec drives its SDI to request an initialization sequence (when the SDI is driven high at the last
bit of frame SYNC)
>=100 usec >= 4 BCLK
Initialization Sequence
Previous Frame
4 BCLK
4 BCLK
Link in Reset
BCLK
SYNC
SDOs
SDIs
Normal Frame
SYNC
Normal Frame
SYNC is absent
Driven Low
Pulled Low
2
8
Driven Low
Driven Low
Pulled Low
Pulled Low
Wake Event
9
RST#
Pulled Low
1
3
4
5
6
7
Figure 12. Link Reset Timing
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Datasheet
7.3.2. Codec Reset
A ‘Codec Reset’ is initiated via the Codec RESET command verb. It results in the target codec being
reset to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
7.3.3. Codec Initialization Sequence
n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller
o The codec stops driving the SDI during this turnaround period
pqrs The controller drives SDI to assign a CAD to the codec
t The controller releases the SDI after the CAD has been assigned
u Normal operation state
Turnaround Frame
(Non-48kHz Frame)
Address Frame
(Non-48kHz Frame)
Exit from Reset Connection Frame
Normal Operation
BCLK
Frame SYNC
SYNC
Frame SYNC
Frame SYNC
5
4
6
Response
SDIx
SD14
SD0 SD1
3
1
2
7
8
RST#
Codec
Drives SDIx
Codec
Controller Drives SDIx
Controller
Codec Drives SDIx
Turnaround
(477 BCLK
Max.)
Turnaround
(477 BCLK
Max.)
Figure 13. Codec Initialization Sequence
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Datasheet
7.4. Verb and Response Format
7.4.1. Command Verb Format
There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with
12-bit identifiers (12-bit verbs) and 8-bits of data. Table 11 shows the 4-bit verb structure of a command
stream sent from the controller to operate the codec. Table 12 is the 12-bit verb structure that gets and
controls parameters in the codec.
Table 11. 40-Bit Commands in 4-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Bit [15:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
Table 12. 40-Bit Commands in 12-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Bit [7:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
7.4.2. Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-bit response is interpreted by
software, opaque to the controller.
Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Table 13. Solicited Response Format
Bit [35]
Bit [34]
Bit [33:32]
Bit [31:0]
Valid
Unsol=0
Reserved
Response
Table 14. Unsolicited Response Format
Bit [35]
Valid
Bit [34]
Unsol=1
Bit [33:32]
Bit [31:28]
Tag
Bit [27:0]
Response
Reserved
Note: The response stream in the link protocol is 36-bits wide. The response is placed in the
lower 32-bit field. Bit-35 is a ‘Valid’bit to indicate the response is ‘Ready’. Bit-34 is set to
indicate that an unsolicited response was sent.
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8. Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC861. If a verb is
not supported by the addressed widget, it will respond with 32 bits of ‘0’.
8.1. Verb – Get Parameters (Verb ID=F00h)
The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget,
some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format,
page 18, for detailed information about supported parameters.
Table 15. Verb – Get Parameters (Verb ID=F00h)
Get Parameter Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=00h Verb ID=F00h
Parameter ID[7:0]
32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 16. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Codec Response Format
Bit
31:16
15:0
Description
Vendor ID=10ECh (Realtek’s PCI vendor ID)
Device ID=0861h
Note: The Root Node (NID=00h) supports this parameter.
8.1.2. Parameter – Subsystem ID (Verb ID=F00h, Parameter ID=01h)
This parameter was removed from the HDA 1.0 specification. The ALC861 will respond with 0s to this
command.
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8.1.3. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 17. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Codec Response Format
Bit
Description
31:24
23:20
19:16
15:8
Reserved. Read as 0’s
MajRev=1h. The major version number (in decimal) of the HDA Specification
MinRev=0h. The minor version number (in decimal) of the HDA Specification
Revision ID. The vendor’s revision number
00h is for the first silicon version, 01h is for the second version, etc.
Stepping ID. The vendor’s stepping number within the given Revision ID
7:0
Note: The Root Node (NID=00h) supports this parameter.
8.1.4. Parameter – Subordinate Node Count (Verb ID=F00h,
Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node.
For function group nodes, it provides the total number of widgets associated with this function node.
Table 18. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Codec Response Format
Bit
Description
31:24
23:16
Reserved. Read as 0’s
Starting Node Number
The starting node number in the sequential widgets
Reserved. Read as 0’s.
15:8
7:0
Total Number of Nodes
For a root node, this is the total number of function groups in the root node
For a function group, this is the total number of widget nodes in the function group
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Datasheet
8.1.5. Parameter – Function Group Type (Verb ID=F00h,
Parameter ID=05h)
Table 19. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)
Codec Response Format
Bit
31:9
8
Description
Reserved. Read as 0’s
UnSol Capable
0: Unsolicited response is not supported by this function group
1: Unsolicited response is supported by this function group
Function Group Type
7:0
00h: Reserved
01h: Audio Function
02h: Modem Function
03h~7Fh: Reserved
80h~FFh: Vendor Defined Function
8.1.6. Parameter – Audio Function Capabilities (Verb ID=F00h,
Parameter ID=08h)
Table 20. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Codec Response Format
Bit
31:17
16
Description
Reserved. Read as 0’s
Beep Generator
A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group
15:12
11:8
Reserved. Read as 0’s
Input Delay
Number of samples delay from analog input to HDA link
Reserved. Read as 0’s
7:4
3:0
Output Delay
Number of samples delay from HDA link to analog output
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8.1.7. Parameter – Audio Widget Capabilities (Verb ID=F00h,
Parameter ID=09h)
Table 21. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s
Widget Type
0h: Audio Output 1h: Audio Input 2h: Mixer 3h: Selector 4h: Pin Complex
5h: Power Widget 6h: Volume Knob Widget
7h~Eh: Reserved
Fh: Vendor defined audio widget
19:16
15:12
11:
Delay. Samples delayed between the HDA link and widgets
Reserved. Read as 0’s
L-R Swap
0: Left channel and right channel swapping is not supported
1: Left channel and right channel swapping is supported
Power Control
0: Power control is not supported on this widget
1: Power control is supported on this widget
Digital
10
9
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (S/PDIF, I2S, etc.)
ConnList. Connection List
8
0: Connected to HDA link. No Connection List Entry will be queried
1: Connection List Entry must be queried
UnsolCap. Unsolicited Capable
7
0: Unsolicited response is not supported
1: Unsolicited response is supported
ProcWidget. Processing Widget
6
0: No processing control
1: Processing control is supported
5
4
Reserved. Read as 0
Format Override
The ALC861 DACs support 16/20/24-bit with a 48KHz and 96KHz sample rate. The format (parameter
ID=0Ah) must be queried
3
AmpParOvr (AMP Param Override)
Override amplifier parameters (Gain Control) in individual output Pin Complexes, ADCs, and Mixer
widgets
2
1
OutAmpPre (Out AMP Present)
InAmpPre (In AMP Present)
There are amplifiers (Gain Control) in individual ADCs and Mixer widgets
0
Stereo
0: Mono Widget
1: Stereo Widget
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Datasheet
8.1.8. Parameter – Supported PCM Size, Rates (Verb ID=F00h,
Parameter ID=0Ah)
Parameters in audio functions provide default information about formats. Individual converters have their
own parameters to provide supported formats if their ‘Format Override’ bit is set.
Table 22. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Codec Response Format
Bit
31:21
20
Description
Reserved. Read as 0’s
B32. 32-bit audio format support
0: Not supported
1: Supported
19
18
17
16
B24. 24-bit audio format support
0: Not supported
1: Supported
B20. 20-bit audio format support
0: Not supported
1: Supported
B16. 16-bit audio format support
0: Not supported
1: Supported
B8. 8-bit audio format support
0: Not supported
1: Supported
15:12
11
Reserved. Read as 0’s
R12. 384kHz (=8*48kHz) rate support
0: Not supported
1: Supported
10
9
R11. 192kHz (=4*48kHz) rate support
0: Not supported
1: Supported
R10. 176.4Hz (=4*44.1kHz) rate support
0: Not supported
1: Supported
8
R9. 96kHz (=2*48kHz) rate support
0: Not supported
1: Supported
7
R8. 88.2kHz (=2*44.1kHz) rate support
0: Not supported
1: Supported
6
R7. 48kHz rate support
0: Not supported
1: Supported
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Datasheet
Codec Response Format
Bit
Description
5
R6. 44.1kHz rate support
0: Not supported
1: Supported
4
3
2
1
0
R5. 32kHz (=2/3*48kHz) rate support
0: Not supported
1: Supported
R4. 22.05kHz (=1/2*44.1kHz) rate support
0: Not supported
1: Supported
R3. 16kHz (=1/3*48kHz) rate support
0: Not supported
1: Supported
R2. 11.025kHz (=1/4*44.1kHz) rate support
0: Not supported
1: Supported
R1. 8kHz (=1/6*48kHz) rate support
0: Not supported
1: Supported
8.1.9. Parameter – Supported Stream Formats (Verb ID=F00h,
Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the ‘Format Override’ bit is set.
Table 23. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Codec Response Format
Bit
31:3
2
Description
Reserved. Read as 0’s
AC3
0: Not supported
1: Supported
Float32
0: Not supported
1: Supported
PCM
1
0
0: Not supported
1: Supported
Note: Input converters and output converters support this parameter.
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Datasheet
8.1.10. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 24. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
Codec Response Format
Bit
31:16
15:8
Description
Reserved. Read as 0’s
VREF Control Capability
‘1’ in corresponding bit field indicates signal levels of associated Vrefout are specified as a percentage of
AVDD.
7:6
5
4
3
2
1
0
Reserved
100%
80%
Reserved
Ground
50%
Hi-Z
7
6
Reserved
Balanced I/O Pin
‘1’ indicates this pin complex has balanced pins
Input Capable
‘1’ indicates this pin complex supports input
Output Capable
‘1’ indicates this pin complex supports output
Headphone Drive Capable
‘1’ indicates this pin complex has an amplifier to drive a headphone
Presence Detect Capable
‘1’ indicates this pin complex can detect whether there is a device plugged in
Trigger Required
‘1’ indicates whether a software trigger is required for an impedance measurement
Impedance Sense Capable
5
4
3
2
1
0
‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type
Note: Only Pin Complex widgets support this parameter.
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Datasheet
8.1.11. Parameter – Amplifier Capabilities
(Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 25. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Codec Response Format
Bit
31
Description
(Input) Mute Capable
30:23
22:16
Reserved. Read as 0
Step Size
Indicates the size of each step in the gain range
15
Reserved. Read as 0
14:8
Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
7
Reserved. Read as 0
Offset
6:0
Indicates which step is 0dB
8.1.12. Parameter – Amplifier Capabilities (Verb ID=F00h, Output
Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 26. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Codec Response Format
Bit
31
Description
(Output) Mute Capable
Reserved. Read as 0
Step Size
30:23
22:16
Indicates the size of each step in the gain range. Each individual step may be 0~32dB, specified in
0.25dB steps. ‘0’ indicates 0.25dB steps. ‘127’ indicates 32dB steps.
15
Reserved. Read as 0
14:8
Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
Reserved. Read as 0
7
6:0
Offset. Indicates which step is 0dB
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Datasheet
8.1.13. Parameter – Connect List Length (Verb ID=F00h,
Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 27. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Codec Response Format
Bit
31:8
7
Description
Reserved. Read as 0
Short Form
0: Short Form
1: Long Form
6:0
Connect List Length
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one
input, and there is no Connection Select Control (Not a MUX widget)
8.1.14. Parameter – Supported Power States (Verb ID=F00h,
Parameter ID=0Fh)
Table 28. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Codec Response Format
Bit
31:4
3
Description
Reserved. Read as 0’s
D3Sup
1: Power state D3 is supported
D2Sup
1: Power state D2 is supported
D1Sup
1: Power state D1 is supported
D0Sup
2
1
0
1: Power state D0 is supported
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Datasheet
8.2. Verb – Get Connection Select Control (Verb ID=F01h)
Table 29. Verb – Get Connection Select Control (Verb ID=F01h)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F01h
0’s
Bit[7:0] are Connection Index
Codec Response for NID=08h (ADC)
Bit
31:8
7:0
Description
0’s
Connection Index currently Set (Default value is 00h)
00h: Port-B (NID=0Dh) - MIC1
01h: Port-C (NID=0Ch) - LINE1
02h: Port-E (NID=0Fh) - LINE2
03h: Port-F (NID=10h) - MIC2
04h: NID=11h - analog CD
05h: Mixer (NID=15h)
Other: Reserved.
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.3. Verb – Set Connection Select (Verb ID=701h)
Table 30. Verb – Set Connection Select (Verb ID=701h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=701h
Select Index [7:0]
0’s for all nodes
Note: See 8.2 Verb – Get Connection Select Control (Verb ID=F01h), page 28 for detailed select items for widget support
connection selection.
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Datasheet
8.4. Verb – Get Connection List Entry (Verb ID=F02h)
Table 31. Verb – Get Connection List Entry (Verb ID=F02h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F02h
Offset Index - N[7:0]
32-bit Response
Codec Response for NID=08h (ADC)
Bit
Description
31:24
Connection List Entry (N+3)
Returns 10h (Port-F: MIC2) for N=0~3
Returns 00h for N>3
23:16
15:8
Connection List Entry (N+2)
Returns 0Fh (Port-E: LINE2) for N=0~3
Return 00h for N >3.
Connection List Entry (N+1)
Returns 0Ch (Port-C: LINE1) for N=0~3
Returns 15h (Mixer) for N=4~7
Returns 00h for N>7.
7:0
Connection List Entry (N)
Returns 0Dh (Port-B: MIC1) for N =0~3
Returns 11h (CD) for N =4~7
Returns 00h for N >7.
Codec Response for NID=14h (Mic Mixer)
Bit
Description
31:24
Connection List Entry (N+3)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 10h (Port-F: MIC2) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 0Dh (Port-B: MIC1) for N=0~3
Returns 00h for N>3
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Datasheet
Codec Response for NID=15h (Stereo Mixer)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 14h (MIC Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 11h (Analog CD) for N=0~3
Returns 00h for N>3
Codec Response for NID=16h (Mixer, to Port-D:Surr-Out)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 15h (Stereo Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 03h (front DAC) for N=0~3
Returns 00h for N>3
Codec Response for NID = 17h (Mixer, to Port-H:Side-Surr Out)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 15h (Stereo Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 04h (Side-Surr DAC) for N=0~3
Returns 00h for N>3
7.1 Channel High Definition Audio Codec
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Datasheet
Codec Response for NID=18h (Mixer, to Port-G:Cen/Lfe Out)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 15h (Stereo Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 05h (Side-Surr DAC) for N=0~3
Returns 00h for N>3
Codec Response for NID=19h (Mixer, to Port-A:Surr Out)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 15h (Stereo Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 06h (Surr DAC) for N=0~3
Returns 00h for N>3
Codec Response for NID=1Ah (Mixer, to Port-E:LINE2)
Bit
Description
31:24
Connection List Entry (N)
Returns 04h (SideSurr DAC) for N=0~3
Returns 00h
23:16
15:8
7:0
Connection List Entry (N+2)
Returns 15h (Stereo Mixer) for N=0~3
Returns 00h
Connection List Entry (N+1)
Returns 06h (Surr DAC) for N=0~3
Returns 00h for N>3
Connection List Entry (N)
Returns 03h (Front DAC) for N=0~3
Returns 00h for N>3
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Datasheet
Codec Response for NID=1Bh (Mixer, to Port-F: MIC2)
Bit
Description
31:24
Connection List Entry (N)
Returns 04h (SideSurr DAC) for N=0~3
Returns 00h
23:16
15:8
7:0
Connection List Entry (N+2)
Returns 15h (Stereo Mixer) for N=0~3
Returns 00h
Connection List Entry (N+1)
Returns 06h (Surr DAC) for N=0~3
Returns 00h for N>3
Connection List Entry (N)
Returns 03h (Front DAC) for N=0~3
Returns 00h for N>3
Codec Response for NID=1Ch (LINE Mixer)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Fh (Port-E: LINE2) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 0Ch (Port-C: LINE1) for N=0~3
Returns 00h for N>3
Codec Response for NID=0Bh (Port-D: FRONT-OUT)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h.
7:0
Connection List Entry (N)
Returns 16h (Mixer 16h) for N=0~3
Returns 00h for N>3
Codec Response for NID=0Ch (Port-C: LINE1)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h.
7:0
Connection List Entry (N)
Returns 19h (Mixer 19h) for N=0~3
Returns 00h for N>3
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Datasheet
Codec Response for NID=0Dh (Port-B: MIC1)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 18h (Mixer 18h) for N=0~3
Returns 00h for N>3
Codec Response for NID=0Eh (Port-A: SURR-OUT)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 19h (Mixer 19h) for N=0~3
Returns 00h for N>3
Codec Response for NID= 0Fh (Port-E: LINE2)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 1Ah (Mixer 1Ah) for N=0~3
Returns 00h for N>3
Codec Response for NID=10h (Port-F: MIC2)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 1Bh (Mixer 1Bh) for N=0~3
Returns 00h for N>3
7.1 Channel High Definition Audio Codec
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Datasheet
Codec Response for NID= 1Fh (Port-G: CEN/LFE-OUT)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 18h (Mixer 18h) for N=0~3
Returns 00h for N>3
Codec Response for NID= 20h (Port-H: SIDE-SURR-OUT)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 17h (Mixer 17h) for N=0~3
Returns 00h for N>3
Codec Response for NID=12h (Pin Widget: S/PDIF-OUT)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 07h (S/PDIF-OUT Converter) for N=0~3
Returns 00h for N>3
Codec Response for Other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1 Channel High Definition Audio Codec
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Datasheet
8.5. Verb – Get Amplifier Gain (Verb ID=Bh)
This verb is used to get gain/attenuation settings from each widget.
Table 32. Verb – Get Amplifier Gain (Verb ID=Bh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=Bh
‘Get’ payload [15:0]
Bit[7:0] are responsible for ‘Get’
‘Get’ Payload in Command Bit[15:0]
Bit
Description
15
Get Input/Output
0: Input amplifier gain is requested
1: Output amplifier gain is requested
Reserved. Read as 0
14
13
Get Left/Right
0: Right amplifier gain is requested
1: Left amplifier gain is requested
Reserved. Read as 0’s
12:4
3:0
Index[3:0] for Input Source
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored.
Codec Response for NID=03h, 04h, 05h, 06h (DAC) and 07h (S/PDIF-OUT Converter)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute)
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute, 0: Unmute, 1: Mute (Default)
Read as 0’s (No volume control for DAC and S/PDIF-OUT converter)
6:0
Codec Response for NID=08h (ADC)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute, 0: Unmute 1: Mute (Default ).
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute)
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0]
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute)
6:0
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Datasheet
Codec Response for NID=14h, 1Ch (MIXER 14h and 1Ch)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute, 0: Unmute 1: Mute (Default).
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute)
Read as 0’s (No volume control)
6:0
Codec Response for NID=15h (Stereo MIXER 15h)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute: 0: Unmute 1: Mute (Default for all Index)
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute: 0: Unmute 1: Mute (Default)
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
6:0
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0].
Codec Response for NID=16h~1Bh (Mixers)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute: 0: Unmute 1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute)
Read as 0’s (No volume control for Input and Output Amplifier Gain)
6:0
Codec Response for NID=23h (Internal BEEP Generator)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0. (No Input Amplifier Mute)
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute: 0: Unmute
1: Mute (Default)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No volume control for input)
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0].
Codec Response to Other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1 Channel High Definition Audio Codec
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Datasheet
8.6. Verb – Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 33. Verb – Set Amplifier Gain (Verb ID=3h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=3h
‘Set’ payload [7:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
Description
15
Set Output Amp
1: indicates output amplifier gain will be set
Set Input Amp
1 indicates input amplifier gain will be set
Set Left Amp
14
13
1 indicates left amplifier gain will be set
Set Right Amp
12
1 indicates right amplifier gain will be set
Index Offset (for input amplifiers on Sum widgets and Selector Widgets)
11:8
5-bit index offset in connection list is used to select the input gain that will be set on a Sum or a Selector
widget. The index is ignored if the node is not a Sum or a Selector widget, or the ‘Set Input Amp’ bit is
not set
7
Mute
0: Unmute
1: Mute (-∞ gain)
6:0
Gain[6:0]
A 7-bit step value specifying the amplifier gain
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Datasheet
8.7. Verb – Get Converter Format (Verb ID=Ah)
Table 34. Verb – Get Converter Format (Verb ID=Ah)
Get Command Format
Codec Response Format
Response [31:0]
Bit[15:0] are converter format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Ah
0’s
Codec Response for NID=03h~06h (Output Converters: Front, Surr, Cen/Lfe, Side-Surr DAC, and S/PDIF-OUT).
Codec Response for NID=08h (Input Converters: ADC)
Bit
31:16
15
Description
Reserved. Read as 0
Stream Type (TYPE)
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE)
0: 48kHz
1: 44.1kHz
13:11
10:8
Sample Base Rate Multiple (MULT)
000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved
Sample Base Rate Divisor (DIV)
000b: /1 001b: /2 010b: /3 011b: /4 100b: /5
Not supported. Always read as 000b
Reserved. Read as 0
101b: /6 110b: /7 111b: /8
7
6:4
Bits per Sample (BITS)
000b: 8 bits
001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved
3:0
Number of Channels.
0: 1 channel 1: 2 channels 2: 3 channels ….. 15: 16 channels
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1 Channel High Definition Audio Codec
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Datasheet
8.8. Verb – Set Converter Format (Verb ID=2h)
Table 35. Verb – Set Converter Format (Verb ID=2h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=2h
Set format [15:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
31:16
15
Description
Reserved. Read as 0
Stream Type (TYPE)
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE)
0: 48kHz
1: 44.1kHz
13:11
10:8
Sample Base Rate Multiple (MULT)
000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved
Sample Base Rate Divisor (DIV)
000b: /1 001b: /2 010b: /3 011b: /4 100b: /5
Reserved. Read as 0
101b: /6 110b: /7 111b: /8
7
6:4
Bits per Sample (BITS)
000b: 8 bits
001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved
3:0
Number of Channels
0: 1 channel 1: 2 channels 2: 3 channels …..… 15: 16 channels
7.1 Channel High Definition Audio Codec
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ALC861
Datasheet
8.9. Verb – Get Power State (Verb ID=F05h)
Table 36. Verb – Get Power State (Verb ID=F05h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F05h
0’s
Power State [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:6
5:4
Description
Reserved. Read as 0’s.
PS-Act. Actual Power State [1:0].
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set.
3:2
1:0
Reserved. Read as 0’s.
PS-Set. Set Power State [1:0].
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Set controls the current power setting of the referenced node.
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC861
Datasheet
8.10. Verb – Set Power State (Verb ID=705h)
Table 37. Verb – Set Power State (Verb ID=705h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=705h
Power State [7:0]
0’s for all nodes
‘Power State’ in Command Bit[7:0]
Bit
7:6
5:4
Description
Reserved. Read as 0’s
PS-Act. Actual Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Act indicates the actual power state of the referenced node
Reserved. Read as 0’s
3:2
1:0
PS-Set. Set Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
8.11. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Table 38. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F06h
0’s
Stream & Channel [7:0]
Codec Response for NID=03h~06h, 07h (Output Converters: Front, Surr, Cen/Lfe, Side-Surr DAC and S/PDIF-OUT)
Codec Response for NID=08h (Input Converters: ADC)
Bit
31:8
7:4
Description
Reserved. Read as 0’s
Stream[3:0]
The link stream used by the converter. 0000b is unused, 0001b is stream 1, etc.
Channel[3:0]
3:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1
for its left and right channel
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC861
Datasheet
8.12. Verb – Set Converter Stream, Channel (Verb ID=706h)
Table 39. Verb – Set Converter Stream, Channel (Verb ID=706h)
Codec Response Format
Set Command Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=706h
Stream & Channel [7:0]
0’s for all nodes
‘Stream and Channel’ in Command Bit[7:0]
Bit
31:8
7:4
Description
Reserved. Read as 0’s
Set Stream[3:0]
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Set Channel[3:0]
1:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1
for its left and right channel
8.13. Verb – Get Pin Widget Control (Verb ID=F07h)
Table 40. Verb – Get Pin Widget Control (Verb ID=F07h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F07h
0’s
Pin Control [7:0]
Codec Response for NID=0Bh~0Fh, 10h, 1Fh, 20h
(Pin Complex: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, and LINE2)
Bit
31:7
6
Description
Reserved. Read as 0’s
Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit)
0: Disabled
1: Enabled
5
In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
0: Disabled
1: Enabled
4:3
2:0
Reserved
VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled, default for all)
001b: 50% of AVDD
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD
101b: 100% of AVDD
110b~111b: Reserved
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Datasheet
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.14. Verb – Set Pin Widget Control (Verb ID=707h)
Table 41. Verb – Set Pin Widget Control (Verb ID=707h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=707h
Pin Control [7:0]
‘Pin Control’ in command [7:0]: (Pin: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, and LINE2)
Bit
31:7
6
Description
Reserved. Read as 0’s
Out Enable
0: Disabled
1: Enabled
5
In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
0: Disabled
1: Enabled
4:3
2:0
Reserved
VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled, default for all)
001b: 50% of AVDD
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD
101b: 100% of AVDD
110b~111b: Reserved
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Datasheet
8.15. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real time event.
Table 42. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F08h
0’s
32-bit Response
Codec Response for NID= 0Bh~0Fh, 10h, 1Fh, 20h (Analog I/O Port)
Bit
31:8
7
Description
Reserved. Read as 0’s
Unsolicited Response
0: Disabled
1: Enabled
6
Reserved. Read as 0’s
Assigned Tag for Unsolicited Responses
5:0
The tag [5:0] is assigned by software to determine which widget generates unsolicited responses
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1 Channel High Definition Audio Codec
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Datasheet
8.16. Verb – Set Unsolicited Response Control (Verb ID=708h)
Enable a widget to generate an unsolicited response.
Table 43. Verb – Set Unsolicited Response Control (Verb ID=708h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=708h
EnableUnsol [7:0]
0’s for all nodes
‘EnableUnsol’ in Command Bit [7:0]
Bit
31:8
7
Description
Reserved. Read as 0’s
Unsolicited Response
0: Disable
1: Enable
6
Reserved. Read as 0’s
Tag for Unsolicited Responses.
5:0
Tag[5:0] is defined by software to assign a 6-bit tag for nodes that are enabled to generate unsolicited
responses.
8.17. Verb – Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 44. Verb – Get Pin Sense (Verb ID=F09h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F09h
0’s
32-bit Response
Codec Response for NID=0Bh~0Fh, 10h, 11h, 1Fh and 20h (Analog I/O Port)
Bit
Description
31
Presence Detect Status
0: No device is attached to the pin
1: Device is attached to the pin
Measured Impedance
30:0
0x7FFFFFFF or 0xFFFFFFFF: Valid sense is not available or busy
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC861
Datasheet
8.18. Verb – Execute Pin Sense (Verb ID=709h)
Table 45. Verb – Execute Pin Sense (Verb ID=709h)
Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= 709h
Right Channel[0]
0’s for all nodes
‘Payload’ in Command Bit[7:0]
Bit
7:1
0
Description
Reserved. Read as 0’s
Right (Ring) Channel Select
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)
8.19. Verb – Get Configuration Default
(Verb ID=F1Ch/F1Dh/F1Eh/F1Fh)
Read the 32-bit sticky register for each Pin Widget configured by software.
Table 46. Verb – Get Configuration Default (Verb ID=F1Ch/F1Dh/F1Eh/F1Fh)
Get Command Format Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F1Ch
0’s
32-bit Response
Codec Response for NID=0B~0Fh, 10h, 11h, 1Fh, 20h and 12h
Bit
Description
31:0
32-bit configuration information for each pin widget
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).
7.1 Channel High Definition Audio Codec
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Datasheet
8.20. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions (e.g., placement and expected default
device) for the Pin Widgets NID=0B~0Fh, 10h, 11h, 1Fh, 20h, and 12h.
Table 47. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=71Ch,
Label [7:0]
0’s for all nodes
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=0B~0Fh, 10h, 11h, 1Fh, 20h, and 12h. Other widgets will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s
8.21. Verb – Get BEEP Generator (Verb ID=F0Ah)
Table 48. Verb – Get BEEP Generator (Verb ID= F0Ah)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F1Bh
0’s
Divider [7:0]
‘Response’ for NID=23h
Bit Description
31:8
7:0
Reserved
Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
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Datasheet
8.22. Verb – Set BEEP Generator (Verb ID=70Ah)
Table 49. Verb – Set BEEP Generator (Verb ID= 70Ah)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=23h Verb ID=71Bh
Divider [7:0]
‘Divider’ in Set Command
Bit
31:8
7:0
Description
Reserved
Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input
Note: All nodes except BEEP generator (NID=23h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s
8.23. Verb – Function Reset (Verb ID=7FFh)
Table 50. Verb – Function Reset (Verb ID=7FFh)
Command Format (NID=01H)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=7FFh
0’s
Codec Response
Bit
Description
31:0
Reserved. Read as 0’s
Note: The Function Reset command causes all widgets to return to their power-on default state.
7.1 Channel High Definition Audio Codec
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Datasheet
8.24. Verb – Get Digital Converter Control 1 & Control 2
(Verb ID= F0Dh, F0Eh)
Table 51. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F0Dh/
F0Eh
0’s
Bit[31:16]=0’s, Bit[15:0] are SIC bit
NID=07h (S/PDIF-OUT Converter) Response to ‘Get verb’ – F0Dh (Control for SIC bit[15:0])
Bit
31:16
15
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Read as 0’s
Reserved. Read as 0’s
14:8
7
CC[6:0] (Category Code)
LEVEL (Generation Level)
PRO (Professional or Consumer format)
0: Consumer format
6
1: Professional format
5
4
3
/AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright)
0: Asserted
1: Not asserted
PRE (Pre-emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
VCFG for Validity Control (control V bit and data in Sub-Frame)
V for Validity Control (control V bit and data in Sub-Frame)
Digital Enable. DigEn
2
1
0
0: OFF
1: ON
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1 Channel High Definition Audio Codec
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Datasheet
8.25. Verb – Set Digital Converter Control 1 & Control 2
(Verb ID=70Dh, 70Eh)
Table 52. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Set Command Format (Verb ID=70Dh, Set Control 1)
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=70Dh
SIC [7:0]
0’s
Set Command Format (Verb ID=70Eh, Set Control 2)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh
Verb ID=70Eh
SIC [15:8]
‘Payload’ in Set Control 1 for NID=07h (S/PDIF-OUT Converter)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
LEVEL (Generation Level)
PRO (Professional or Consumer format)
0: Consumer format
6
1: Professional format
5
4
3
/AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright)
0: Asserted
1: Not asserted
PRE (Pre-emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
VCFG for Validity Control (control V bit and data in Sub-Frame)
V for Validity Control (control V bit and data in Sub-Frame)
Digital Enable. DigEn
2
1
0
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=07h (S/PDIF-OUT Converter)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved. Read as 0’s
6:0
CC[6:0] (Category Code)
7.1 Channel High Definition Audio Codec
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Datasheet
8.26. Verb – Get Subsystem ID [31:0]
(Verb ID=F20h/F21h/D22h/F23h)
32-bit Read/Write register for Audio Function Group (NID=01h)
Table 53. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)
Get Command Format Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd = X
Node ID=01h Verb ID=F20h
0s
32-bit Response
Codec Response for NID=01h
Bit
31:8
7:0
Description
Subsystem ID= 086100h
Assembly ID. Read as 0
8.27. Verb – Set Subsystem ID [31:0]
(Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8],
720h for [7:0])
Table 54. Verb – Set Subsystem ID [31:0]
(Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0])
Set Command Format
Codec Response Format
Bit [31:28] Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd = X Node ID=01h Verb ID=723h,
Label [7:0]
0s for all nodes
722h, 721h,
720h
Codec Response for all NID
Bit
Description
0s
31:0
7.1 Channel High Definition Audio Codec
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Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 55. Absolute Maximum Ratings
Parameter
Power Supply:
Digital
Symbol
Minimum
Typical
Maximum
Units
DVDD
AVDD
Ta
3.0
3.0
0
3.3
5.0
-
3.6
5.5
V
V
oC
Analog
Ambient Operating
Temperature
+70
Storage Temperature
All Pins
Ts
+125
oC
ESD (Electrostatic Discharge)
Susceptibility Voltage
4000V
9.1.2. Threshold Voltage
DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load.
Table 56. Threshold Voltage
Parameter
Symbol
Vin
Minimum
Typical
Maximum
Units
V
Input Voltage Range
-0.30
-
-
-
DVDD +0.30
0.30*DVDD
(1.00)
Low Level Input Voltage
(BCLK, RESET#, SDO, SYNC, SDI)
High Level Input Voltage
(BCLK, RESET#, SDO, SYNC, SDI)
Low Level Input Voltage
(S/PDIF-OUT)
VIL
V
VIH
VIL
VIH
0.65* DVDD
-
-
-
-
V
V
V
(2.00)
-
0.44*DVDD
(1.45)
-
High Level Input Voltage
(S/PDIF-OUT)
0.56* DVDD
(1.85)
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
VOH
0.9*DVDD
-
V
V
VOL
-
-10
-10
-
-
-
0.1*DVDD
-
-
-
-
10
10
µA
µA
mA
Ω
Output Leakage Current (Hi-Z)
Output Buffer Drive Current
Internal Pull Up Resistance
-
5
-
-
50k
100k
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Datasheet
9.1.3. S/PDIF Output Characteristics
DVDD= 3.3V, Tambient=25°C, with 75Ω external load.
Table 57. S/PDIF Output Characteristics
Parameter
Symbol
VOH
Minimum
Typical
Maximum
Units
V
S/PDIF-OUT High Level Output
S/PDIF-OUT Low Level Output
3.0
-
3.3
0
-
VOL
0.3
V
9.2. AC Characteristics
9.2.1. Link Reset and Initialization Timing
Table 58. Link Reset and Initialization Timing
Parameter
Symbol
TRST
Minimum
Typical
Maximum
Units
µs
RESET# Active Low Pulse Width
RESET# Inactive to BCLK
Startup delay for PLL ready time
SDI Initialization Request
1.0
20
-
-
-
-
TPLL
µs
TFRAME
-
-
1
Frame Time
Initialization
Sequence
>= 4 BCLK
4 BCLK
4 BCLK
BCLK
SYNC
Normal Frame
SYNC
SDO
SDI
Initialization
Request
RESET#
TRST
TPLL
TFRAME
Figure 14. Link Reset and Initialization Timing
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Datasheet
9.2.2. Link Timing Parameters at the Codec
Table 59. Link Timing Parameters at the Codec
Parameter
Symbol
Minimum
Typical
Maximum
Units
MHz
ns
BCLK Frequency
BCLK Period
-
24.0
-
Tcycle
Tjitter
Thigh
-
41.67
-
BCLK Jitter
-
-
-
2.0
ns
BCLK High Pulse Width
18.75
(45%)
18.75
(45%)
2.1
22.91
(55%)
22.91
(55%)
-
ns
(%)
ns
(%)
ns
BCLK Low Pulse Width
Tlow
-
SDO Setup Time at Both Rising
and Falling Edge of BCLK
Tsetup
Thold
Ttco
-
SDO Hold Time at Both Rising and
Falling Edge of BCLK
2.1
-
-
8.0
-
ns
ns
ns
SDI Valid Time After Rising Edge
of BCLK (1: 50pF external load)
-
-
7.5
2.0
SDI Flight Time
Tflight
T_cycle
T_high
V
IH
BCLK
SDO
V
V
T
IL
T_low
T_setup T_hold
T_tco
V
OH
SDI
V
OL
T_flight
Figure 15. Link Signal Timing
7.1 Channel High Definition Audio Codec
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ALC861
Datasheet
9.2.3. S/PDIF Output Timing
Table 60. S/PDIF Output Timing
Parameter
Symbol
-
Minimum
Typical
6.144
Maximum
Units
MHz
ns
S/PDIF-OUT Frequency
S/PDIF-OUT Period
-
-
Tcycle
Tjitter
THigh
TLow
Trise
-
162.8
-
S/PDIF-OUT Jitter
-
-
4
ns
S/PDIF-OUT High Level Width
S/PDIF-OUT Low Level Width
S/PDIF-OUT Rising Time
S/PDIF-OUT Falling Time
78.1 (48%)
81.4 (50%)
81.4 (50%)
2.0
84.6 (52%)
ns (%)
ns (%)
ns
78.1 (48%)
84.6 (52%)
-
-
-
-
Tfall
2.0
ns
T
cycle
T
T
low
high
V
OH
V
IH
V
t
V
IL
V
OL
T
T
rise
fall
Figure 16. Output Timing
9.2.4. Test Mode
Codec test mode and Automatic Test Equipment (ATE) mode is not supported.
7.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC861
Datasheet
9.3. Analog Performance
• Tambient=25 oC, DVDD= 3.3V ±5%, AVDD=5.0V±5%
Standard Test Conditions
• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW: 10Hz~22kHz,
0dB attenuation
Table 61. Analog Performance
Parameter
Min
Typ
Max
Units
Full Scale Input Voltage
All Inputs (gain=0dB)
All ADC
-
-
1.6
1.2
-
-
Vrms
Vrms
Full Scale Output Voltage
All DAC
-
1.1
-
Vrms
S/N (A Weighted)
Analog Inputs to Outputs
All ADC
-
-
-
94
82
90
-
-
-
dB FSA
dB FSA
dB FSA
All DAC
THD+N
Analog Inputs to Outputs
ADC
All DAC
-
-
-
-90
-72
-73
-
-
-
dB FS
dB FS
dB FS
Frequency Response
Mixers
10
16
-
-
22,000
19,200
Hz
Hz
dB
dB
dB
dB
KΩ
ADC, DAC
Power Supply Rejection Ratio
Total Out-of-Band Noise (28.8kHz~100kHz)
20dB Gain is Selected
Crosstalk Between Input Channels
Input Impedance (gain=0dB)
Output Impedance
Line Output
-40
-60
20
-80
47
-
18
-
-
22
100
-
Ω
Ω
Amplified Output
2
-
Power Supply Current (normal operation)
VA=5V / VD=3.3V
-
46 / 16
mA
Power Supply Current (power down mode)
VA=5V / VD=3.3V
-
-
5 / 12
3.2
5
-
-
uA
V
VREFOUTx Output Voltage
VREFOUTx Output Current
mA
7.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC861
Datasheet
10. Application Circuits
Designers are suggested to contact Realtek to get the latest application circuits. To get the best
compatibility in hardware design and software driver, any modifications of application circuits should be
confirmed by Realtek. Realtek may update the latest application circuits onto our web site
(www.realtek.com.tw) without modifying this data sheet.
7.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC861
Datasheet
11. Mechanical Dimensions
L
L1
See the Mechanical Dimensions notes on the next page.
7.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC861
Datasheet
11.1. Mechanical Dimensions Notes
MILLIMETER
INCH
SYMBOL
MIN. TYP MAX. MIN. TYP MAX
A
A1
A2
c
1.60
0.15 0.002
0.063
0.006
0.05
TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING,
FOOTPRINT 2.0mm
1.35 1.40 1.45 0.053 0.055 0.057
0.09 0.20 0.004 0.008
0.354 BSC
D
9.00 BSC
7.00 BSC
5.50
LEADFRAME MATERIAL
D1
D2
E
E1
E2
b
0.276 BSC
0.217
0.354 BSC
0.276 BSC
0.217
APPROVE
CHECK
DOC. NO.
VERSION 02
DWG NO. PKGC-065
DATE
9.00 BSC
7.00BSC
5.50
REALTEK SEMICONDUCTOR CORP.
0.17 0.20 0.27 0.007 0.008 0.011
e
TH
L
0.50 BSC
0.0196 BSC
0o
3.5o
7o
0o
3.5o 7o
0.45 0.60 0.75 0.018 0.0236 0.030
1.00 0.0393
L1
12. Ordering Information
Table 62. Ordering Information
Package
Part Number
Status
Sample
Sample
ALC861-GR
LQFP-48 ‘Green’ package
ALC861-GR + DTS CONNECT™ (software feature)
ALC861DTS-GR
Note 1: See page 4 for Green package and version identification.
Note 2: Above parts are tested under AVDD =5.0V. If customers have lower AVDD request, please contact
Realtek sales representatives or agents.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-557-6047
www.realtek.com.tw
7.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
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