ALC888S-VD_11_05 [REALTEK]
7.12 CHANNEL HD AUDIO CODEC;
| 型号： | ALC888S-VD_11_05 |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | 7.12 CHANNEL HD AUDIO CODEC |
| 文件： | 总92页 (文件大小：1421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC888S-VD
(PN: ALC888S-VD2-GR)
7.1+2 CHANNEL HD AUDIO CODEC
WITH TWO INDEPENDENT SPDIF OUTPUTS
DATASHEET
Rev. 1.2
31 May 2011
Track ID: JATR-2265-11
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
ALC888S-VD
Datasheet
COPYRIGHT
©2011 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC888S-VD IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
Release Date
2011/03/18
2011/03/31
2011/05/31
Summary
1.0
First release.
1.1
Corrected minor typing errors.
1.2
Revised Jack Detection pins from two to three
Revised Table 87, page 76 (Dynamic Range with –60dB Signal parameters).
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
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ALC888S-VD
Datasheet
Table of Contents
1.
2.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
2.1.
2.2.
HARDWARE FEATURES ................................................................................................................................................2
SOFTWARE FEATURES..................................................................................................................................................3
3.
4.
SYSTEM APPLICATIONS...............................................................................................................................................4
BLOCK DIAGRAM...........................................................................................................................................................5
4.1.
ANALOG INPUT/OUTPUT UNIT .....................................................................................................................................6
5.
6.
PIN ASSIGNMENTS .........................................................................................................................................................7
5.1.
PACKAGE AND VERSION IDENTIFICATION....................................................................................................................7
PIN DESCRIPTIONS.........................................................................................................................................................8
6.1.
6.2.
PIN DESCRIPTION TABLE..............................................................................................................................................8
PIN DIFFERENCES: ALC888S-VD VS. ALC888S-VC................................................................................................10
7.
HIGH DEFINITION AUDIO LINK PROTOCOL .......................................................................................................11
7.1.
LINK SIGNALS............................................................................................................................................................11
7.1.1. Link Signal Definitions.........................................................................................................................................12
7.1.2. Signaling Topology...............................................................................................................................................13
7.2.
FRAME COMPOSITION ................................................................................................................................................14
7.2.1. Outbound Frame – Single SDO............................................................................................................................14
7.2.2. Outbound Frame – Multiple SDOs.......................................................................................................................15
7.2.3. Inbound Frame – Single SDI................................................................................................................................16
7.2.4. Inbound Frame – Multiple SDIs...........................................................................................................................17
7.2.5. Variable Sample Rates .........................................................................................................................................17
7.3.
RESET AND INITIALIZATION .......................................................................................................................................20
7.3.1. Link Reset .............................................................................................................................................................20
7.3.2. Codec Reset..........................................................................................................................................................21
7.3.3. Codec Initialization Sequence ..............................................................................................................................22
7.4.
VERB AND RESPONSE FORMAT ..................................................................................................................................22
7.4.1. Command Verb Format........................................................................................................................................22
7.4.2. Response Format..................................................................................................................................................25
7.5.
POWER MANAGEMENT...............................................................................................................................................25
7.5.1. System Power State Definitions............................................................................................................................25
7.5.2. Power Controls in NID 01h..................................................................................................................................26
7.5.3. Powered Down Conditions...................................................................................................................................26
8.
SUPPORTED VERBS AND PARAMETERS................................................................................................................27
8.1.
VERB – GET PARAMETERS (VERB ID=F00H).............................................................................................................27
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)............................................................................27
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)..........................................................................27
8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h).....................................................28
8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) ..........................................................28
8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) ...............................................29
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ..................................................29
8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ................................................30
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh).................................................31
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8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..................................................................31
8.1.10.
8.1.11.
8.1.12.
8.1.13.
8.1.14.
8.1.15.
8.1.16.
Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) ..........................32
Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ........................32
Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) .......................................................33
Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) .................................................33
Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)..................................................34
Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)..........................................................34
Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) ...........................................34
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H)................................................................................35
VERB – SET CONNECTION SELECT (VERB ID=701H).................................................................................................35
VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................36
VERB – GET PROCESSING STATE (VERB ID=F03H) ...................................................................................................42
VERB – SET PROCESSING STATE (VERB ID=703H) ....................................................................................................43
VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................43
VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................43
VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................44
VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................44
VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................45
VERB – SET AMPLIFIER GAIN (VERB ID=3H) ............................................................................................................47
VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................48
VERB – SET CONVERTER FORMAT (VERB ID=2H).....................................................................................................49
VERB – GET POWER STATE (VERB ID=F05H)............................................................................................................50
VERB – SET POWER STATE (VERB ID=705H) ............................................................................................................50
VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................51
VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H)................................................................................51
VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................52
VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................53
VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................53
VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H)............................................................................54
VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................54
VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................55
VERB – GET VOLUME KNOB WIDGET (VERB ID=F0FH) ...........................................................................................55
VERB – SET VOLUME KNOB WIDGET (VERB ID=70FH) ............................................................................................56
VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) .......................................................................................57
VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 59
VERB – GET BEEP GENERATOR (VERB ID=F0AH)...................................................................................................59
VERB – SET BEEP GENERATOR (VERB ID=70AH)....................................................................................................60
VERB – GET GPIO DATA (VERB ID=F15H)...............................................................................................................60
VERB – SET GPIO DATA (VERB ID=715H)................................................................................................................61
VERB – GET GPIO ENABLE MASK (VERB ID=F16H).................................................................................................61
VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................62
VERB – GET GPIO DIRECTION (VERB ID=F17H).......................................................................................................62
VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................63
VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) .......................................................63
VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) ........................................................64
VERB – FUNCTION RESET (VERB ID=7FFH)..............................................................................................................64
VERB – GET DIGITAL CONVERTER CONTROL 1, 2, 3, 4 (VERB ID=F0DH, F0EH, F3EH, F3FH) .................................65
VERB – SET DIGITAL CONVERTER CONTROL 1, 2, 3, 4 (VERB ID=70DH, 70EH, 73EH, 73FH)...................................67
VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/F22H/F23H)...................................................................68
VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR
[7:0]) .........................................................................................................................................................................69
VERB – GET EAPD CONTROL (VERB ID=F0CH FOR GET) ........................................................................................69
VERB – SET EAPD CONTROL (VERB ID=70CH FOR SET)..........................................................................................70
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.23.
8.24.
8.25.
8.26.
8.27.
8.28.
8.29.
8.30.
8.31.
8.32.
8.33.
8.34.
8.35.
8.36.
8.37.
8.38.
8.39.
8.40.
8.41.
8.42.
8.43.
8.44.
8.45.
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
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9.
ELECTRICAL CHARACTERISTICS ..........................................................................................................................71
9.1.
DC CHARACTERISTICS...............................................................................................................................................71
9.1.1. Absolute Maximum Ratings..................................................................................................................................71
9.1.2. Threshold Voltage ................................................................................................................................................71
9.1.3. Digital Filter Characteristics...............................................................................................................................72
9.1.4. SPDIF Input/Output Characteristics....................................................................................................................72
9.2.
AC CHARACTERISTICS...............................................................................................................................................73
9.2.1. Link Reset and Initialization Timing.....................................................................................................................73
9.2.2. Link Timing Parameters at the Codec..................................................................................................................74
9.2.3. SPDIF Output and Input Timing ..........................................................................................................................75
9.2.4. Test Mode .............................................................................................................................................................75
9.3.
ANALOG PERFORMANCE............................................................................................................................................76
APPLICATION CIRCUITS .......................................................................................................................................77
DESKTOP SYSTEM......................................................................................................................................................77
APPLICATION SUPPLEMENTS .............................................................................................................................81
10.
10.1.
11.
11.1.
11.2.
STANDBY MODE ........................................................................................................................................................81
DIGITAL MICROPHONE IMPLEMENTATION .................................................................................................................82
12.
13.
MECHANICAL DIMENSIONS.................................................................................................................................83
ORDERING INFORMATION...................................................................................................................................84
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Datasheet
List of Tables
TABLE 1. PIN DESCRIPTIONS ........................................................................................................................................................8
TABLE 2. PIN DIFFERENCES: ALC888S-VD VS. ALC888S-VC.................................................................................................10
TABLE 3. LINK SIGNAL DEFINITIONS .........................................................................................................................................12
TABLE 4. HDA SIGNAL DEFINITIONS.........................................................................................................................................12
TABLE 5. DEFINED SAMPLE RATE AND TRANSMISSION RATE....................................................................................................18
TABLE 6. 48KHZ VARIABLE RATE OF DELIVERY TIMING ..........................................................................................................18
TABLE 7. 44.1KHZ VARIABLE RATE OF DELIVERY TIMING .......................................................................................................19
TABLE 8. 40-BIT COMMANDS IN 4-BIT VERB FORMAT ..............................................................................................................22
TABLE 9. 40-BIT COMMANDS IN 12-BIT VERB FORMAT ............................................................................................................22
TABLE 10. VERBS SUPPORTED BY THE ALC888S-VD (Y=SUPPORTED) .....................................................................................23
TABLE 11. PARAMETERS IN THE ALC888S-VD (Y=SUPPORTED)...............................................................................................24
TABLE 12. SOLICITED RESPONSE FORMAT ..................................................................................................................................25
TABLE 13. UNSOLICITED RESPONSE FORMAT .............................................................................................................................25
TABLE 14. SYSTEM POWER STATE DEFINITIONS .........................................................................................................................25
TABLE 15. POWER CONTROLS IN NID 01H..................................................................................................................................26
TABLE 16. POWERED DOWN CONDITIONS...................................................................................................................................26
TABLE 17. VERB – GET PARAMETERS (VERB ID=F00H).............................................................................................................27
TABLE 18. PARAMETER – VENDOR ID (VERB ID=F00H, PARAMETER ID=00H)..........................................................................27
TABLE 19. PARAMETER – REVISION ID (VERB ID=F00H, PARAMETER ID=02H)........................................................................27
TABLE 20. PARAMETER – SUBORDINATE NODE COUNT (VERB ID=F00H, PARAMETER ID=04H)...............................................28
TABLE 21. PARAMETER – FUNCTION GROUP TYPE (VERB ID=F00H, PARAMETER ID=05H) ......................................................28
TABLE 22. PARAMETER – AUDIO FUNCTION CAPABILITIES (VERB ID=F00H, PARAMETER ID=08H)..........................................29
TABLE 23. PARAMETER – AUDIO WIDGET CAPABILITIES (VERB ID=F00H, PARAMETER ID=09H).............................................29
TABLE 24. PARAMETER – SUPPORTED PCM SIZE, RATES (VERB ID=F00H, PARAMETER ID=0AH) ...........................................30
TABLE 25. PARAMETER – SUPPORTED STREAM FORMATS (VERB ID=F00H, PARAMETER ID=0BH)...........................................31
TABLE 26. PARAMETER – PIN CAPABILITIES (VERB ID=F00H, PARAMETER ID=0CH) ...............................................................31
TABLE 27. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, INPUT AMPLIFIER PARAMETER ID=0DH).......................32
TABLE 28. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, OUTPUT AMPLIFIER PARAMETER ID=12H) ....................32
TABLE 29. PARAMETER – CONNECT LIST LENGTH (VERB ID=F00H, PARAMETER ID=0EH) ......................................................33
TABLE 30. PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH) ................................................33
TABLE 31. PARAMETER – PROCESSING CAPABILITIES (VERB ID=F00H, PARAMETER ID=10H)..................................................34
TABLE 32. PARAMETER – GPIO CAPABILITIES (VERB ID=F00H, PARAMETER ID=11H) ............................................................34
TABLE 33. PARAMETER – VOLUME KNOB CAPABILITIES (VERB ID=F00H, PARAMETER ID=13H).............................................34
TABLE 34. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H)................................................................................35
TABLE 35. VERB – SET CONNECTION SELECT (VERB ID=701H) .................................................................................................35
TABLE 36. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................36
TABLE 37. VERB – GET PROCESSING STATE (VERB ID=F03H) ...................................................................................................42
TABLE 38. VERB – SET PROCESSING STATE (VERB ID=703H) ....................................................................................................43
TABLE 39. VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................43
TABLE 40. VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................43
TABLE 41. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................44
TABLE 42. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................44
TABLE 43. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................45
TABLE 44. VERB – SET AMPLIFIER GAIN (VERB ID=3H).............................................................................................................47
TABLE 45. VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................48
TABLE 46. VERB – SET CONVERTER FORMAT (VERB ID=2H) .....................................................................................................49
TABLE 47. VERB – GET POWER STATE (VERB ID=F05H)............................................................................................................50
TABLE 48. VERB – SET POWER STATE (VERB ID=705H).............................................................................................................50
TABLE 49. VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................51
TABLE 50. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H)................................................................................51
TABLE 51. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................52
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SPDIF Outputs
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TABLE 52. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................53
TABLE 53. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................53
TABLE 54. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ............................................................................54
TABLE 55. VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................54
TABLE 56. VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................55
TABLE 57. VERB – GET VOLUME KNOB (VERB ID=F0FH)..........................................................................................................55
TABLE 58. VERB – SET VOLUME KNOB (VERB ID=70FH) ..........................................................................................................56
TABLE 59. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) .......................................................................................57
TABLE 60. DEFAULT CONFIGURATION IN CHIP (14H~1CH).........................................................................................................58
TABLE 61. DEFAULT CONFIGURATION IN CHIP (1DH~12H) ........................................................................................................58
TABLE 62. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 ...........................................................................................59
TABLE 63. VERB – GET BEEP GENERATOR (VERB ID= F0AH) ..................................................................................................59
TABLE 64. VERB – SET BEEP GENERATOR (VERB ID= 70AH) ...................................................................................................60
TABLE 65. VERB – GET GPIO DATA (VERB ID= F15H)..............................................................................................................60
TABLE 66. VERB – SET GPIO DATA (VERB ID= 715H)...............................................................................................................61
TABLE 67. VERB – GET GPIO ENABLE MASK (VERB ID= F16H)................................................................................................61
TABLE 68. VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................62
TABLE 69. VERB – GET GPIO DIRECTION (VERB ID=F17H).......................................................................................................62
TABLE 70. VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................63
TABLE 71. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).........................................................63
TABLE 72. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................64
TABLE 73. VERB – FUNCTION RESET (VERB ID=7FFH) ..............................................................................................................64
TABLE 74. VERB – GET DIGITAL CONVERTER CONTROL 1, 2, 3, 4 (VERB ID=F0DH, F0EH, F3EH, F3FH) .................................65
TABLE 75. VERB – SET DIGITAL CONVERTER CONTROL 1, 2, 3, 4 (VERB ID=70DH, 70EH, 73EH, 73FH)...................................67
TABLE 76. VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/F22H/F23H)...................................................................68
TABLE 77. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR
[7:0])..........................................................................................................................................................................69
TABLE 78. VERB – GET EAPD CONTROL (VERB ID=F0CH).......................................................................................................69
TABLE 79. VERB – SET EAPD CONTROL (VERB ID=70CH FOR SET)..........................................................................................70
TABLE 80. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................71
TABLE 81. THRESHOLD VOLTAGE...............................................................................................................................................71
TABLE 82. DIGITAL FILTER CHARACTERISTICS...........................................................................................................................72
TABLE 83. SPDIF INPUT/OUTPUT CHARACTERISTICS .................................................................................................................72
TABLE 84. LINK RESET AND INITIALIZATION TIMING..................................................................................................................73
TABLE 85. LINK TIMING PARAMETERS AT THE CODEC ...............................................................................................................74
TABLE 86. SPDIF OUTPUT AND INPUT TIMING ...........................................................................................................................75
TABLE 87. ANALOG PERFORMANCE............................................................................................................................................76
TABLE 88. DESKTOP SYSTEM ......................................................................................................................................................77
TABLE 89. STANDBY MODE ........................................................................................................................................................81
TABLE 90. ORDERING INFORMATION ..........................................................................................................................................84
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Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM ........................................................................................................................................................5
FIGURE 2. ANALOG INPUT/OUTPUT UNIT.....................................................................................................................................6
FIGURE 3. PIN ASSIGNMENTS .......................................................................................................................................................7
FIGURE 4. HDA LINK PROTOCOL...............................................................................................................................................11
FIGURE 5. BIT TIMING................................................................................................................................................................12
FIGURE 6. SIGNALING TOPOLOGY ..............................................................................................................................................13
FIGURE 7. SDO OUTBOUND FRAME...........................................................................................................................................14
FIGURE 8. SDO STREAM TAG IS INDICATED IN SYNC...............................................................................................................14
FIGURE 9. STRIPED STREAM ON MULTIPLE SDOS......................................................................................................................15
FIGURE 10. SDI INBOUND STREAM .............................................................................................................................................16
FIGURE 11. SDI STREAM TAG AND DATA ...................................................................................................................................16
FIGURE 12. CODEC TRANSMITS DATA OVER MULTIPLE SDIS ....................................................................................................17
FIGURE 13. LINK RESET TIMING..................................................................................................................................................21
FIGURE 14. CODEC INITIALIZATION SEQUENCE...........................................................................................................................22
FIGURE 15. LINK RESET AND INITIALIZATION TIMING ................................................................................................................73
FIGURE 16. LINK SIGNALS TIMING ..............................................................................................................................................74
FIGURE 17. OUTPUT AND INPUT TIMING......................................................................................................................................75
FIGURE 18. FILTER CONNECTION ................................................................................................................................................78
FIGURE 19. FRONT PANEL HEADER AND FRONT PANEL MODULE CONNECTION .........................................................................79
FIGURE 20. JACK CONNECTION AT REAR PANEL.........................................................................................................................80
FIGURE 21. SPDIF INPUT/OUTPUT CONNECTION ........................................................................................................................80
FIGURE 22. DIGITAL MICROPHONE IMPLEMENTATION ................................................................................................................82
FIGURE 23. STEREO DIGITAL MICROPHONE CONNECTION ..........................................................................................................82
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SPDIF Outputs
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Datasheet
1. General Description
The ALC888S-VD provides ten DAC channels that simultaneously support 7.1 channel sound playback,
plus 2 channels of independent stereo sound output (multiple streaming) through the front panel stereo
outputs. Two stereo ADCs and one stereo digital microphone converter are integrated and can support a
microphone array with Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise
Suppression (NS) technologies.
All analog I/O are input and output capable, and headphone amplifiers are also integrated at three analog
output ports (port-D/port-E/port-F). All analog I/Os can be re-tasked according to user definitions.
Support for 16/20/24-bit SPDIF input and output with up to 192kHz sample rate offers easy connection of
PCs to consumer electronic products such as digital decoders and speakers. The ALC888S-VD also
features secondary SPDIF-OUT output and converter to transport digital audio output to a High
Definition Media Interface (HDMI) transmitter.
The ALC888S-VD supports host audio from the Intel chipsets, and also from any other HDA compatible
audio controller. With various software utilities like environment sound emulation, multiple-band and
independent software equalizer, dynamic range compressor and expander, optional Dolby PCEE program,
SRS TruSurround HD, SRS Premium Sound, Fortemedia SAM, Creative Host Audio, Synopsys Sonic
Focus, DTS Surround Sensation | UltraPC, and DTS Connect licenses, the ALC888S-VD offers the
highest sound quality, providing an excellent entertainment package and game experience for PC users.
The ALC888S-VD is an upgraded version of the ALC888S-VC, with lower power consumption. It also
features a built-in Low-dropout (LDO) regulator to reduce customer’s external circuit cost.
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
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Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
2. Features
2.1. Hardware Features
DACs with 95dB SNR (A-weighting), ADCs with 90dB SNR (A-weighting)
Ten DAC channels support 16/20/24-bit PCM format for 7.1 channel sound playback, plus 2
channels of concurrent independent stereo sound output (multiple streaming) through the front panel
output
Two stereo ADCs support 16/20/24-bit PCM format, multiple stereo recording
All DACs supports 44.1k/48k/96k/192kHz sample rate
All ADCs supports 44.1k/48k/96k/192kHz sample rate
Primary 16/20/24-bit SPDIF-OUT supports 32k/44.1k/48k/88.2k/96k/192kHz sample rate
Secondary 16/20/24-bit SPDIF-OUT supports 32k/44.1k/48k/88.2k/96k/192kHz sample rate
16/20/24-bit SPDIF-IN supports 44.1k/48k/96k/192kHz sample rate
All analog jacks (port-A to port-G) are stereo input and output re-tasking
Port-D/E/F built-in headphone amplifiers
Port-B/C/E/F with software selectable boost gain (+10/+20/+30dB) for analog microphone input
High-quality analog differential CD input
Supports external PCBEEP input and built-in digital BEEP generator
Software selectable 2.5V/3.2V/4.0V VREFOUT
Up to four channels of microphone array input are supported for AEC/BF applications
Three jack detection pins; each designed to detect up to 4 jacks
Supports legacy analog mixer architecture
Up to two GPIOs (General Purpose Input and Output) for customized applications. GPIO0 and
GPIO1 share pin with DMIC-CLK and DMIC-DATA
Supports mono and stereo digital microphone interface (pins shared with GPIO0 and GPIO1)
Supports anti-pop mode when analog power LDO-IN is on and digital power is off
1dB per step output volume and input volume control
Supports 3.3V digital core power, 1.5V or 3.3V digital I/O power for HD Audio link, and 5.0V
analog power
7.1+2 Channel HD Audio Codec with Two Independent
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Datasheet
Intel low power ECR compliant and power status control for each analog/digital converter and pin
widget
Built-in Low-dropout (LDO) regulator
Ultra low power consumption in anti-pop mode
48-pin LQFP ‘Green’ package
2.2. Software Features
Meets Microsoft WLP 3.x and future WLP audio requirements
WaveRT-based audio function driver for Windows Vista and Windows 7
Direct Sound 3D™ compatible
I3DL2 compatible
7.1+2 channel multi-streaming enables concurrent gaming/VoIP
Emulation of 26 sound environments to enhance gaming experience
Multiband software equalizer and tools provided
Voice Cancellation and Key Shifting effect
Dynamic range control (expander, compressor, and limiter) with adjustable parameters
Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience
Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)
technology for voice applications
Smart multiple streaming operation
HDMI audio driver for AMD platform
Optional Dolby PCEE program, SRS TruSurround HD, SRS Premium Sound, Fortemedia SAM,
Creative Host Audio, Synopsys Sonic Focus, DTS Surround Sensation | UltraPC, and DTS Connect
licenses
7.1+2 Channel HD Audio Codec with Two Independent
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3. System Applications
Desktop multimedia PCs
Notebook PCs
7.1+2 Channel HD Audio Codec with Two Independent
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4. Block Diagram
Figure 1. Block Diagram
7.1+2 Cannel HD Audio Codec with Two Independent
SPDIF utputs
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Datasheet
4.1. Analog Input/Output Unit
Pin Complex widgets NID=14h~1Bh are re-tasking IOs.
Left
A
R
EN_OBUF
EN_AMP
Right
R
Output_Signal_Left
Output_Signal_Right
Input_Signal_Left
Input_Signal_Right
EN_OBUF
EN_IBUF
Figure 2. Analog Input/Output Unit
7.1+2 Channel HD Audio Codec with Two Independent
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Datasheet
5. Pin Assignments
Figure 3. Pin Assignments
5.1. Package and Version Identification
Green package is indicated by the ‘G’ in GXXVS (Figure 3). The silicon version and step numbers are
shown in the location marked ‘V’ and ‘S’.
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Datasheet
6. Pin Descriptions
For a convenient list of ALC888S-VD vs. ALC888S-VC pin differences, see section 6.2, page 10.
6.1. Pin Description Table
Table 1. Pin Descriptions
Name
Type Pin Description
Characteristic Definition
DVDD
P
IO1
1
2
Digital Core Power
Digital VDD (3.3V)
GPIO0/
DMIC-CLK/
SPDIF-OUT2
General Purpose Input/Output/
Digital MIC Clock Output/
Secondary SPDIF Out to HDMI
Transmitter
Digital Input: Schmitt trigger, VIL =0.4×DVDD,
VIH =0.6×DVDD, internal 50K pull up
Digital Output:
VOL <0.1×DVDD, VOH >0.9×DVDD
6mA@75Ω Output driving
REGREF
-
3
4
Reference for Integrated
Regulator
10µF capacitor to digital ground
GPIO1/
IO1
General Purpose Input/Output/
Digital Input: Schmitt trigger, VIL =0.4×DVDD,
DMIC-DATA
Digital MIC Stereo Channel Input VIH =0.6×DVDD, internal 50K pull up
Digital Output: VOL <0.1×DVDD, VOH
>0.9×DVDD
SDATA-OUT
BITCLK
I
I
5
6
Serial TDM Data Input
24MHz Clock
Digital Input: Schmitt trigger,
VIL =0.4×DVDD-IO, VIH =0.6×DVDD-IO
Digital Input: Schmitt trigger,
VIL =0.4×DVDD-IO, VIH =0.6×DVDD-IO
Digital ground
DVSS
G
7
8
Digital Ground
SDATA-IN
IO
Serial TDM Data Output
Digital Input: Schmitt trigger,
VIL =0.4×DVDD-IO, VIH =0.6×DVDD-IO
Digital Output:
V
OL <0.1×DVDD-IO, VOH >0.9×DVDD-IO
DVDD-IO
SYNC
P
I
9
Digital Power for HD Link
Scalable Digital VDD (1.5V~3.3V)
Digital Input: Schmitt trigger,
10 48KHz Frame SYNC Signal
VIL =0.4×DVDD-IO, VIH =0.6×DVDD-IO
Digital Input: Schmitt trigger,
RESET#
I
11 H/W Reset Input
VIL =0.4×DVDD-IO, VIH =0.6×DVDD-IO
Analog Input: 1.6Vrms of full-scale input
BEEP
I
-
12 External PC Beep Input
Sense A
13 Jack Detect for Resistor Network Connector {5.1K, 10K, 20K, 39.2K} with 1%
accuracy
LINE2-L
LINE2-R
MIC2-L
IO
IO
IO
14 Analog Input and Output with
Multiple Function (Left)
Analog I/O (PORT-E-L), default 2nd line input.
Recommended to be re-tasking port at front
panel
Analog I/O (PORT-E-R), default 2nd line input.
Recommended to be re-tasking port at front
panel
Analog I/O (PORT-F-L), default 2nd mic input.
Recommended to be re-tasking port at front
panel
15 Analog Input and Output with
Multiple Function (Right)
16 Analog Input and Output with
Multiple Function (Left)
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Name
Type Pin Description
Characteristic Definition
Analog I/O (PORT-F-R), default 2nd mic input.
MIC2-R
IO
17 Analog Input and Output with
Multiple Function (Right)
Recommended to be re-tasking port at front
panel
CD-L
I
I
18 CD Input Left Channel
19 CD Input Reference Ground
20 CD Input Right Channel
Analog Input: 1.6Vrms of full-scale input
Analog Input: 1.6Vrms of full-scale input
Analog Input: 1.6Vrms of full-scale input
CD-GND
CD-R
I
MIC1-L
IO
21 Analog Input and Output with
Multiple Function (Left)
Analog I/O (PORT-B-L), default 1st mic input.
Recommended to be microphone input at rear
panel
MIC1-R
IO
22 Analog Input and Output with
Multiple Function (Right)
Analog I/O (PORT-B-R), default 1st mic input.
Recommended to be microphone input at rear
panel
LINE1-L
IO
IO
-
23 Analog Input and Output with
Multiple Function (Left)
Analog I/O (PORT-C-L), default 1st line input.
Recommended to be line level input at rear panel
Analog I/O (PORT-C-R), default 1st line input.
Recommended to be line level input at rear panel
LINE1-R
LDO-OUT1
24 Analog Input and Output with
Multiple Function (Right)
25 Built-In LDO Output for Mixer & Needs 10µF capacitor to analog ground, and
Amp short to Pin38
26 Analog Ground for Mixer & Amp Analog GND
AVSS1
VREF
G
-
27 0.5×LDO-OUT1 Reference
Voltage
10µF capacitor to analog ground
MIC1-VREFO-L
O
28 Bias Voltage for MIC1 (Port-B)
Analog Output: 2.5V/3.2V/4.0V reference
voltage
LDO-IN
P
29 Built-In LDO Input
VDD (5V)
MIC2-VREFO
O
30 Bias Voltage for MIC2 (Port-F)
Analog Output: 2.5V/3.2V/4.0V reference
voltage
LINE2-VREFO
MIC1-VREFO-R
Sense C
O
O
-
31 Bias Voltage for LINE2 (Port-E)
Analog Output: 2.5V/3.2V/4.0V reference
voltage
32 Secondary Bias Voltage for MIC1 Analog Output: 2.5V/3.2V/4.0V reference
(Port-B) voltage
33 Jack Detect for Resistor Network Connector {5.1K, 10K, 20K, 39.2K} with 1%
accuracy
Sense B
-
34 Jack Detect for Resistor Network Connector {5.1K, 10K, 20K, 39.2K} with 1%
accuracy
FRONT-L
IO
IO
O
-
35 Analog Input and Output (Left)
Analog I/O (PORT-D-L), default front channel
output
FRONT-R
36 Analog Input and Output (Right) Analog I/O (PORT-D-R), default front channel
output
PIN37-VREFO
LDO-OUT2
SURR-L
37 Bias Voltage
Analog Output: 2.5V/3.2V/4.0V reference
voltage
38 Analog Power for DAC and ADC Needs 10µF capacitor to analog ground, and
short to Pin25
IO
39 Analog Input and Output (Left)
Analog I/O (PORT-A-L), default surround
channel
JDREF
-
40 Reference for Jack Detect
20K, 1% resistor to AGND
SURR-R
IO
41 Analog Input and Output (Right) Analog I/O (PORT-A-R), default surround
channel
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Name
Type Pin Description
Characteristic Definition
42 Analog Ground for DAC & ADC Analog GND
43 Analog Input and Output (Left) Analog I/O (PORT-G-L), default center channel
44 Analog Input and Output (Right) Analog I/O (PORT-G-R), default LFE channel
45 Analog Input and Output (Left) Analog I/O (PORT-H-L), default side channel
46 Analog Input and Output (Right) Analog I/O (PORT-H-R), default side channel
AVSS2
G
CENTER
LFE
IO
IO
IO
IO
IO
SIDE-L
SIDE-R
SPDIF-IN/EAPD
47 SPDIF Input/
External Amplifier Power Down
Digital Input: Schmitt trigger (5V tolerance),
VIL =0.44×DVDD, VIH =0.56×DVDD
Digital Output:
V
OL <0.1×DVDD, VOH >0.9×DVDD
Digital Output:
OL <0.1×DVDD, VOH >0.9×DVDD
SPDIF-OUT
O
48 Primary SPDIF Out
V
10mA@75Ω Output driving
Total: 48 Pins
Note1: Pins 2 and 4 have multiple functions. Their default operation is as GPIOs. They function as digital MIC pins when
the configuration register of the digital MIC pin widget (node ID12h) is enabled, and exclusively function as secondary
SPDIF-OUT when the configuration register of the SPDIF-OUT2 pin widget (node ID 11h) is enabled.
6.2. Pin Differences: ALC888S-VD vs. ALC888S-VC
Table 2. Pin Differences: ALC888S-VD vs. ALC888S-VC
Pin Number
ALC888S-VD
ALC888S-VC
Description for ALC888S-VD
Pin 2
GPIO0/DMIC-CLK
/SPDIF-OUT2
SPDIFO2
Pin 2 is re-designed as a share pin to support secondary
SPDIF-OUT, GPIO, and digital microphone interface.
Pin 3(*)
Pin 25
REGREF
LDO-OUT1
LDO-IN
GPIO0/DMIC-CLK Pin 3 is used as reference for the integrated regulator.
AVDD1
LINE1-VREFO
AVDD2
LDO output1; must be shorted to Pin38
Pin 29 is used as VDD input for the built-in LDO.
LDO output2; must be shorted to Pin25
Pin 29(*)
Pin 38
LDO-OUT2
(*) Please notice external circuit connected to pin3/pin29 if ALC888S-VD is directly mounted on C version layout.
7.1+2 Channel HD Audio Codec with Two Independent
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Datasheet
7. High Definition Audio Link Protocol
7.1. Link Signals
The High Definition Audio (HDA) link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol.
Figure 4. HDA Link Protocol
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7.1.1. Link Signal Definitions
Table 3. Link Signal Definitions
Item
Description
24.0MHz bit clock sourced from the HDA controller and connecting to all codecs
BCLK
SYNC
48kHz signal used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs
SDO
Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are carried
on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec samples data
present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To
extend outbound bandwidth, multiple SDOs may be supported
SDI
Serial data input signal driven by the codec. This is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported.
SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of
BCLK. SDI can be driven by the controller to initialize the codec’s ID
RST#
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the HDA
controller and connects to all codecs
Table 4. HDA Signal Definitions
Signal Name
BCLK
SYNC
SDO
Source
Controller
Type for Controller Description
Output
Output
Global 24.0MHz Bit Clock
Controller
Global 48kHz Frame Sync and Outbound Tag Signal
Serial Data Output from the Controller
Serial Data Input from Codec.
Controller
Output
SDI
Codec/Controller
Input/Output
Weakly pulled down by the controller
Global Active Low Reset Signal
RST#
Controller
Output
BCLK
8-Bit Frame SYNC
SYNC
Start of Frame
7
6
5
4
3
2
1
0
999 998 997 996 995 994 993 992 991 990
SDO
SDI
3
2
1
0
499
498
497
496
495
494
Codec samples SDO at both rising and falling edge of BCLK
Controller samples SDI at rising edge of BCLK
Figure 5. Bit Timing
7.1+2 Channel HD Audio Codec with Two Independent
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Datasheet
7.1.2. Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0, and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.
Figure 6 shows the possible connections between the HDA controller and codecs:
• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
• Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
• Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 14 describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 6 can be implemented concurrently in an HDA system. The
ALC888S-VD is designed to receive a single SDO stream.
SDI14
.
.
.
.
.
.
SDI13
SDI2
HDA
Controller
SDI1
SDI0
SDO1
SDO0
SYNC
BCLK
RST#
. . .
Codec 0
Codec 1
Codec 2
Codec N
Single SDO
Single SDI
Two SDOs
Single SDI
Single SDO
Two SDIs
Two SDOs
Multiple SDIs
Figure 6. Signaling Topology
7.1+2 Channel HD Audio Codec with Two Independent
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Datasheet
7.2. Frame Composition
7.2.1. Outbound Frame – Single SDO
An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be two blocks in the same stream to carry
96kHz samples (Figure 7).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 8).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
A 48kHz Frame is composed of Command stream and multiple Data streams
Previous Frame
Next Frame
Frame SYNC
Stream 'A' Tag
(Here 'A' = 5)
Stream 'X' Tag
(Here 'X' = 6)
SYNC
SDO
Command Stream
0s
Stream 'A' Data
Stream 'X' Data
Padded at the
end of Frame
Null Field
One or multiple blocks in a stream
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block1 includes (N)th time of samples, Block2
includes (N+1)th time of samples
..
.
Block 1
Block 2
Block Y
..
.
Sample 1 Sample 2
Sample Z
Z channels of PCM Sample
...
msb first in a sample
msb
lsb
Figure 7. SDO Outbound Frame
BCLK
SYNC
Stream Tag
msb lsb
1 0 1 0
Stream=10
(4-Bit)
Preamble
(4-Bit)
Data of Stream 10
7 6 5 4 3 2 1 0
Previous Stream
SDO
Figure 8. SDO Stream Tag is Indicated in SYNC
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7.2.2. Outbound Frame – Multiple SDOs
The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission
in less time to get more bandwidth. If software determines the target codec supports multiple SDO
capability, it enables the ‘Stripe Control’ bit in the controller’s Output Stream Control Register to initiate
a specific stream (Stream ‘A’ in Figure 9) to be transmitted on multiple SDOs. In this case, the MSB of
the data stream is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to
SDO0.
To guarantee all codecs can determine their corresponding stream, the command stream is not striped. It
is always transmitted on SDO0, and copied on SDO1.
Figure 9. Striped Stream on Multiple SDOs
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7.2.3. Inbound Frame – Single SDI
An Inbound Frame – A single SDI is composed of one 36-bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), the SDI is driven by the codec at
each rising edge of BCLK. The controller also samples data at the rising edge of BCLK.
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte length (Figure
11).
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams
Previous Frame
Frame SYNC
Next Frame
SYNC
SDI
0s
Stream 'X'
Response Stream
Stream 'A'
Null Field
Padded at the end of Frame
Stream Tag
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples
...
Block Y Null Pad
Block 1
Block 2
Sample 1 Sample 2
msb ...
...
Sample Z Z channels of PCM Sample
lsb msb first in a sample
Figure 10. SDI Inbound Stream
BCLK
SDI
n-Bit Sample Block
Null Pad
Next Stream
Stream Tag
Data Length in Bytes
B5 B4 B3 B2 B1
B8
Dn-1 Dn-2
0
0
B9
B7 B6
B0
D0
0
0
(Data Length in Bytes *8)-Bit
A Complete Stream
Figure 11. SDI Stream Tag and Data
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7.2.4. Inbound Frame – Multiple SDIs
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data into separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
SYNC
Frame SYNC
Stream 'A'
SDI
Tag A
Data A
Response Stream
Stream 'X'
0s
Stream 'Y'
0s
0
Stream 'B'
Data B
SDI
Response Stream Tag B
1
Stream A, B, X, and Y are independent and have separate IDs
Codec drives SDI0 and SDI1
Figure 12. Codec Transmits Data Over Multiple SDIs
7.2.5. Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table 5, page 18, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 6, page 18, shows the delivery cadence
of variable rates based on 48kHz.
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames.
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The cadence ‘12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)’ interleaves 13 frames containing no
sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery
rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence AND interleave n empty frames.
Rates in multiples (n) of 44.1kHz applying this cadence contain n sample blocks in the non-empty frame
AND interleave an empty frame between non-empty frames (Table 7, page 19).
Table 5. Defined Sample Rate and Transmission Rate
(Sub) Multiple 48kHz Base
44.1kHz Base
1/6
1/4
1/3
1/2
2/3
1
8kHz (1 Sample Block Every 6 Frames)
-
12kHz (1 Sample Block Every 4 Frames)
16kHz (1 Sample Block Every 3 Frames)
-
11.025kHz (1 Sample Block Every 4 Frames)
-
22.05kHz (1 Sample Block Every 2 Frames)
-
32kHz (2 Sample Blocks Every 3 Frames)
48kHz (1 Sample Block per Frame)
96kHz (2 Sample Blocks per Frame)
192kHz (4 Sample Blocks per Frame)
44.1kHz (1 Sample Block per Frame)
88.2kHz (2 Sample Blocks per Frame)
176.4kHz (4 Sample Blocks per Frame)
2
4
Table 6. 48kHz Variable Rate of Delivery Timing
Rate
8kHz
Delivery Cadence
YNNNNN (Repeat)
YNNN (Repeat)
YNN (Repeat)
Y2NN (Repeat)
Y (Repeat)
Description
One Sample Block is Transmitted in Every 6 Frames
One Sample Block is Transmitted in Every 4 Frames
One Sample Block is Transmitted in Every 3 Frames
Two Sample Blocks are Transmitted in Every 3 Frames
One Sample Block is Transmitted in Every Frame
Two Sample Blocks are Transmitted in Each Frame
Four Sample Blocks Are Transmitted In Each Frame
12kHz
16kHz
32kHz
48kHz
96kHz
192kHz
Y2 (Repeat)
Y4 (Repeat)
N: No sample block in a frame.
Y: One sample block in a frame.
Yx: X sample blocks in a frame.
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Datasheet
Table 7. 44.1kHz Variable Rate of Delivery Timing
Delivery Cadence
Rate
11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(Repeat)
22.05kHz
{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(Repeat)
44.1kHz
88.2kHz
176.4kHz
12-11-11-12-11-11-12-11-11-12-11-11-11- (Repeat)
122-112-112-122-112-112-122-112-112-122-112-112-112- (Repeat)
124-114-114-124-114-114-124-114-114-124-114-114-114- (Repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{ - }=NNNN
22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN
{11}=YNYNYNYNYNYNYNYNYNYNYN
{ - }=NN
44.1kHz
88.2kHz
176.4kHz
12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with
no sample block.
122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with
no sample block.
124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with
no sample block.
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Datasheet
7.3. Reset and Initialization
There are two types of reset within an HDA link:
• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default
state
An initialization sequence is requested after any of the following three events:
• Link Reset
• Codec Reset
• Codec changes its power state (for example, hot docking a codec to an HDA system)
7.3.1. Link Reset
A link reset may be caused by 3 events:
1. The HDA controller asserts RST# for any reason (power up, or PCI reset)
2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
3. Software initiates power management sequences. Figure 13, shows the ‘Link Reset’ timing including
the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)
Enter ‘Link Reset’:
n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
link reset
o When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at
the end of the frame
p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state
r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
7.1+2 Channel HD Audio Codec with Two Independent
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Datasheet
Exit from ‘Link Reset’:
s If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
t Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the
100µsec provides time for the codec PLL to stabilize)
u Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
v When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
last bit of frame SYNC, it means the codec requests an initialization sequence)
>=100 usec >= 4 BCLK
Initialization Sequence
Previous Frame
4 BCLK
4 BCLK
Link in Reset
BCLK
SYNC
SDOs
SDIs
Normal Frame
SYNC
Normal Frame
SYNC is absent
Driven Low
Driven Low
Driven Low
Pulled Low
2
8
Pulled Low
Pulled Low
Wake Event
9
RST#
Pulled Low
1
3
4
5
6
7
Figure 13. Link Reset Timing
7.3.2. Codec Reset
A ‘Codec Reset’ is initiated via the codec RESET command verb. It results in the target codec being reset
to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
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Datasheet
7.3.3. Codec Initialization Sequence
n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller
o The codec will stop driving the SDI during this turnaround period
pqrs The controller drives SDI to assign a CAD to the codec
t The controller releases the SDI after the CAD has been assigned
u Normal operation state
Turnaround Frame
(Non-48kHz Frame)
Address Frame
(Non-48kHz Frame)
Exit from Reset Connection Frame
Normal Operation
BCLK
Frame SYNC
SYNC
Frame SYNC
Frame SYNC
5
4
6
Response
SDIx
SD14
SD0 SD1
3
1
2
7
8
RST#
Codec
Drives SDIx
Codec
Controller Drives SDIx
Codec Drives SDIx
Controller
Turnaround
(477 BCLK
Max.)
Turnaround
( 477 BCLK
Max.)
Figure 14. Codec Initialization Sequence
7.4. Verb and Response Format
7.4.1. Command Verb Format
There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with
12-bit identifiers (12-bit verbs) and 8-bits of data. Table 8 shows the 4-bit verb structure of a command
stream sent from the controller to operate the codec. Table 9 is the 12-bit verb structure that gets and
controls parameters in the codec.
Table 8. 40-Bit Commands in 4-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Bit [15:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
Table 9. 40-Bit Commands in 12-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Bit [7:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
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Datasheet
Table 10. Verbs Supported by the ALC888S-VD (Y=Supported)
Supported Verb
Get Parameter
F00
F01
F02
F03
D-
-
701
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
-
Y
Y
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
-
Connection Select
Get Connection List Entry
Processing State
Coefficient Index
Processing Coefficient
Amplifier Gain/Mute
Stream Format
-
-
Y
-
-
-
703
5-
-
-
-
-
-
-
-
-
-
-
-
Y
Y
-
C-
4-
-
-
-
-
-
-
-
B-
3-
-
-
Y
Y
Y
Y
Y
Y
-
Y
-
Y
-
-
-
A-
2-
-
Y
Y
Y
Y
Y
-
-
-
-
Digital Converter 1
Digital Converter 2
Digital Converter 3
Digital Converter 4
Power State
F0D 70D
F0D 70E
-
-
-
-
-
-
-
-
-
-
-
-
F3E
F3F
F05
F06
F04
F07
F08
F09
73E
73F
705
706
704
707
708
709
-
-
-
-
-
-
-
-
-
-
-
-
Y
-
-
-
-
-
-
Channel/Stream ID
SDI Select
Y
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
Pin Widget Control
Unsolicited Enable
Pin Sense
-
-
-
Y
Y
Y
Y
-
-
-
-
-
-
-
-
-
Y
-
-
-
-
-
-
-
-
EAPD/BTL Enable
F0C 70C
-
-
-
-
-
-
-
F15~ 715~
All GPIO Control
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
F19
719
Beep Generator Control
Volume Knob Control
Subsystem ID, Byte 0
Subsystem ID, Byte 1
Subsystem ID, Byte 2
Subsystem ID, Byte 3
Config Default, Byte 0
Config Default, Byte 1
Config Default, Byte 2
Config Default, Byte 3
RESET
F0A 70A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
F0F
F20
F20
F20
F20
70F
720
721
722
723
Y
Y
Y
Y
-
-
-
-
-
-
-
-
-
-
-
-
F1C 71C
F1C 71D
F1C 71E
Y
Y
Y
Y
-
-
-
-
-
-
-
-
-
F1C
-
71F
7FF
-
-
-
Y
-
-
*1: The ALC888S-VD does not support Modem Function, HDMI Function, Vendor Defined Groups, and Power Widgets.
7.1+2 Channel HD Audio Codec with Two Independent
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Datasheet
Table 11. Parameters in the ALC888S-VD (Y=Supported)
Supported Parameter
Vendor ID
00
02
04
05
08
09
0A
0B
0C
0D
12
0E
0F
10
11
Y
Y
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Revision ID
Subordinate Node Count
Function Group Type
Audio Function Group Capabilities
Audio Widget Capabilities
Sample Size, Rate
Y
Y
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
Y
Y
-
Y
Y
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
-
Y
Y
-
Stream Formats
-
-
-
-
-
-
-
Pin Capabilities
-
Y
-
-
-
-
-
-
Input Amp Capabilities
Output Amp Capabilities
Connection List Length
Supported Power States
Processing Capabilities
GPIO Count
-
-
-
Y
-
Y
Y
Y
Y
-
Y
-
-
-
-
-
-
-
Y
Y
Y
-
-
-
-
-
-
-
Y
Y
-
Y
Y
-
-
-
-
-
Y
-
Y
-
-
-
Y
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
Volume Knob Capabilities
13
-
-
-
-
-
-
-
Y
-
-
*1: The ALC888S-VD does not support Modem Function, HDMI Function, Vendor Defined Groups, and Power Widgets.
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
24
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
7.4.2. Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-bit Response is interpreted by
software, opaque to the controller.
Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Table 12. Solicited Response Format
Bit [35]
Bit [34]
Bit [33:32]
Bit [31:0]
Valid
Unsol=0
Reserved
Response
Table 13. Unsolicited Response Format
Bit [35]
Valid
Bit [34]
Unsol=1
Bit [33:32]
Bit [31:28]
Tag
Bit [27:0]
Response
Reserved
Note: The response stream in the link protocol is 36-bit wide. The response is placed in the lower 32-bit field. Bit 35 is a
‘Valid’bit to indicate the response is ‘Ready’. Bit 34 is set to indicate that an unsolicited response was sent.
7.5. Power Management
All power management state changes in widgets are driven by software. Table 14 shows the System
Power State Definitions. To simplify power management in the ALC888S-VD, only the Audio Function
(NID=01h) supports power control. Output converters (DACs) and input converters (ADCs) have no
individual power control. Software can configure whole codec power states through the audio function
(NID=01h). Software may have various power states depending on system configuration.
Table 15 indicates those nodes that support power management.
7.5.1. System Power State Definitions
Table 14. System Power State Definitions
Power States Definitions
D0
D1
D2
All Power On. Individual DACs and ADCs can be powered up or down as required.
All Converters (DACs and ADCs) are Powered Down. State maintained, analog reference stays up.
Power is Still Supplied. All amplifiers and converters (DACs and ADCs) are powered down.
Codec stops PLL. State maintained. Jack-detection and GPI are powered down.
Power is Still Supplied. All amplifiers and converters (DACs and ADCs) are powered down.
Codec stops PLL. State maintained. Jack-detection/GPI work.
D3 (Hot)
D3 (Cold)
Power is Still Supplied. All amplifiers and converters (DACs and ADCs) are powered down.
Codec stops PLL. State maintained. Jack-detection/GPI work when internal OSC powers up.
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Datasheet
7.5.2. Power Controls in NID 01h
Table 15. Power Controls in NID 01h
Item
Description
D0
D1
Normal
PD
D2
Normal
PD
D3
Normal
PD
Link Reset
PD
Audio Function
(NID=01h)
HD LINK State
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Front DAC (NID-02h)
Surr DAC (NID-03h)
Cen/Lfe DAC (NID-04h)
Side DAC (NID-05h)
Fout DAC (NID-25h)
LINE ADC (NID-08h)
MIX ADC (NID-09h)
All Headphone Drivers
All Mixers
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Normal
Normal
Normal
Normal
PD
PD
PD
PD
PD
PD
All Reference
Normal
PD
Normal
Normal
Normal
Normal2
Jack Detection with
Unsolicited Response
Note 1: PD=Powered Down.
Note 2: Jack detection with unsolicited response is issued when a Link Reset occurs in D3 state.
7.5.3. Powered Down Conditions
Table 16. Powered Down Conditions
Condition
Description
LINK Response Powered Down
Internal Clock is Stopped.
SDATA-IN and SPDIF-OUT are floated with internally pulled low 47K resistors.
SPDIF-IN is also floated. Detection of ‘Link Reset Entry’ and ‘Link Reset Exit’
sequences is supported. All states are maintained if DVDD is supplied.
FRONT DAC Powered Down
SURR DAC Powered Down
CEN/LFE DAC Powered Down
SIDESURR DAC Powered Down
FOUT DAC Powered Down
LINE ADC Powered Down
Analog Block and Digital Filter are Powered Down.
Analog Block and Digital Filter are Powered Down.
Analog Block and Digital Filter are Powered Down.
Analog Block and Digital Filter are Powered Down.
Analog Block and Digital Filter are Powered Down.
Analog Block and Digital Filter are Powered Down.
Data on SDATA-IN is quiet.
MIX ADC Powered Down
Analog Block and Digital Filter are Powered Down.
Data on SDATA-IN is quiet.
Headphone Driver Powered Down
Mixers Powered Down
All Headphone Drivers are Powered Down.
All Internal Mixer Widgets are Powered Down.
The DC reference and VREFOUTx at individual pin complexes are still alive.
Reference Power Down
All Internal References, DC Reference, and VREFOUTx at Individual Pin
Complexes are Off.
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Datasheet
8. Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC888S-VD. If a
verb is not supported by the addressed widget, it will respond with 32 bits of ‘0’.
8.1. Verb – Get Parameters (Verb ID=F00h)
The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget.
Some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format,
page 22, for detailed information about supported parameters.
Table 17. Verb – Get Parameters (Verb ID=F00h)
Get Parameter Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=00h Verb ID=F00h
Parameter ID[7:0]
32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Codec Response Format
Bit
31:16
15:0
Description
Vendor ID=10ECh (Realtek’s PCI Vendor ID).
Device ID=0888h.
Note: The Root Node (NID=00h) supports this parameter.
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s.
MajRev. The major version number (in decimal) of the HDA Spec to which the ALC888S-VD is fully
compliant. Response=0x1.
19:16
15:8
MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC888S-VD is fully
compliant. Response=0x0.
Revision ID. The vendor’s revision number.
00h is for the first silicon version (A version), 01h is for the second version (B version), etc.
Stepping ID. The vendor’s stepping number within the given Revision ID.
7:0
Note: The Root Node (NID=00h in the ALC888S-VD) supports this parameter.
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Datasheet
8.1.3. Parameter – Subordinate Node Count
(Verb ID=F00h, Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node.
For function group nodes, it provides the total number of widgets associated with this function node.
Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Codec Response Format
Bit
Description
31:24
23:16
Reserved. Read as 0’s.
Starting Node Number.
The starting node number in the sequential widgets.
Reserved. Read as 0’s.
15:8
7:0
Total Number of Nodes.
For a root node, the total number of function groups in the root node.
For a function group, the total number of widget nodes in the function group.
Description
Bits Æ
Reserved
Starting Node
Bit [23:16]
01h
Reserved
Total Fun/Widgets
Bit [31:24]
Bit [15:8]
Bit [7:0]
01h
Root Node
NID=00h
NID=01h
-
-
-
-
Audio Function
Others
02h
25h
Not Supported (Returns 00000000h)
8.1.4. Parameter – Function Group Type
(Verb ID=F00h, Parameter ID=05h)
Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)
Codec Response Format
Bit
31:9
8
Description
Reserved. Read as 0’s.
UnSol Capable. Read as 1.
0: Unsolicited response is not supported by this function group
1: Unsolicited response is supported by this function group
Function Group Type. Read as 01h.
00h: Reserved
7:0
01h: Audio Function
02h: Modem Function
03h~7Fh: Reserved
80h~FFh: Vendor Defined Function
Note: The Audio Function Group (NID=01h) supports this parameter.
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Datasheet
8.1.5. Parameter – Audio Function Capabilities
(Verb ID=F00h, Parameter ID=08h)
Table 22. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Codec Response Format
Bit
31:17
16
Description
Reserved. Read as 0’s.
Beep Generator, Read as 1.
A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group.
15:12
11:8
7:4
Reserved. Read as 0’s.
Input Delay. Read as 0xF.
Reserved. Read as 0’s.
Output Delay. Read as 0xF.
3:0
Note: The Audio Function Group (NID=01h) supports this parameter.
8.1.6. Parameter – Audio Widget Capabilities
(Verb ID=F00h, Parameter ID=09h)
Table 23. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s.
Widget Type.
0h: Audio Output
3h: Selector
6h: Volume Knob Widget
1h: Audio Input
4h: Pin Complex
7h~Eh: Reserved
2h: Mixer
5h: Power Widget
Fh: Vendor defined audio widget
19:16
15:11
10
Delay. Samples delayed between the HDA link and widgets.
Reserved. Read as 0’s.
Power Control.
0: Power state control is not supported on this widget
1: Power state is supported on this widget
Digital.
9
8
7
6
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (SPDIF, I2S, etc.)
ConnList. Connection List.
0: Connected to HDA link. No Connection List Entry should be queried
1: Connection List Entry must be queried
UnsolCap. Unsolicited Capable.
0: Unsolicited response is not supported
1: Unsolicited response is supported
ProcWidget. Processing Widget.
0: No processing control
1: Processing control is supported
5
4
3
2
1
0
Reserved. Read as 0.
Format Override.
AmpParOvr, AMP Param Override.
OutAmpPre. Out AMP Present.
InAmpPre. In AMP Present.
Stereo.
0: Mono Widget
1: Stereo Widget
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8.1.7. Parameter – Supported PCM Size, Rates
(Verb ID=F00h, Parameter ID=0Ah)
Parameters here provide default information about formats. Individual converters have their own
parameters to provide supported formats if their ‘Format Override’ bit is set.
Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Codec Response Format
Bit
31:21
20
Description
Reserved. Read as 0’s.
B32. 32-bit audio format support.
0: Not supported
1: Supported
19
18
17
16
B24. 24-bit audio format support.
0: Not supported
1: Supported
B20. 20-bit audio format support.
0: Not supported
1: Supported
B16. 16-bit audio format support.
0: Not supported
1: Supported
B8. 24-bit audio format support.
0: Not supported
1: Supported
15:12
11
Reserved. Read as 0’s.
R12. 384kHz (=8×48kHz) rate support.
0: Not supported
1: Supported
10
9
8
7
6
5
4
3
2
1
0
R11. 192kHz (=4×48kHz) rate support.
0: Not supported
1: Supported
R10. 176.4kHz (=4×44.1kHz) rate support.
0: Not supported
1: Supported
R9. 96kHz (=2×48kHz) rate support.
0: Not supported
1: Supported
R8. 88.2kHz (=2×44.1kHz) rate support.
0: Not supported
1: Supported
R7. 48kHz rate support.
0: Not supported
1: Supported
1: Supported
R6. 44.1kHz rate support.
0: Not supported
R5. 32kHz (=2/3×48kHz) rate support.
0: Not supported
1: Supported
R4. 22.05kHz (=1/2×44.1kHz) rate support.
0: Not supported
1: Supported
R3. 16kHz (=1/3×48kHz) rate support.
0: Not supported
1: Supported
R2. 11.025kHz (=1/4×44.1kHz) rate support.
0: Not supported
R1. 8kHz (=1/6×48kHz) rate support.
0: Not supported 1: Supported
1: Supported
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Datasheet
8.1.8. Parameter – Supported Stream Formats
(Verb ID=F00h, Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the ‘Format Override’ bit is set.
Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Codec Response Format
Bit
31:3
2
Description
Reserved. Read as 0’s.
AC3.
0: Not supported
Float32.
0: Not supported
PCM.
1: Supported
1: Supported
1: Supported
1
0
0: Not supported
Note: Input converters and output converters support this parameter.
8.1.9. Parameter – Pin Capabilities
(Verb ID=F00h, Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 26. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
Codec Response Format
Bit
31:16
15:8
Description
Reserved. Read as 0’s
VREF Control Capability. ‘1’ in corresponding bit field indicates signal levels of associated Vrefout are
specified as a percentage of LDO-OUT1.
7:6
5
4
3
2
1
0
Reserved
100%
80%
Reserved
Ground
50%
Hi-Z
7
6
5
4
3
2
1
0
L-R Swap. Indicates the capability of swapping the left and right.
Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins.
Input Capable. ‘1’ indicates this pin complex supports input.
Output Capable. ‘1’ indicates this pin complex supports output.
Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone.
Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in.
Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement.
Impedance Sense Capable.
‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type.
Note: Only Pin Complex widgets support this parameter.
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Datasheet
8.1.10. Parameter – Amplifier Capabilities
(Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 27. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Codec Response Format
Bit
31
Description
(Input) Mute Capable.
30:23
22:16
Reserved. Read as 0.
Step Size.
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB.
15
Reserved. Read as 0.
14:8
Number of Steps.
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.
7
Reserved. Read as 0.
Offset.
6:0
Indicates which step is 0dB.
8.1.11. Parameter – Amplifier Capabilities
(Verb ID=F00h, Output Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 28. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Codec Response Format
Bit
31
Description
(Output) Mute Capable.
30:23
22:16
Reserved. Read as 0.
Step Size.
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB.
Reserved. Read as 0.
15
14:8
Number of Steps.
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.
Reserved. Read as 0.
7
6:0
Offset. Indicates which step is 0dB.
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Datasheet
8.1.12. Parameter – Connect List Length
(Verb ID=F00h, Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Codec Response Format
Bit
31:8
7
Description
Reserved. Read as 0.
Short Form.
0: Short form
1: Long form
6:0
Connect List Length.
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one
input, and there is no Connection Select Control (not a MUX widget).
8.1.13. Parameter – Supported Power States
(Verb ID=F00h, Parameter ID=0Fh)
Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Codec Response Format
Bit
Description
31
Extended Power States Supported (EPSS).
1: Extended power states EPSS is supported
30
CLKSTOP.
1: D3 mode operates even there is no BITCLK presents on the link
29:4
3
Reserved. Read as 0’s.
D3Sup.
1: Power state D3 is supported
D2Sup.
1: Power state D2 is supported
D1Sup.
1: Power state D1 is supported
D0Sup.
2
1
0
1: Power state D0 is supported
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Datasheet
8.1.14. Parameter – Processing Capabilities
(Verb ID=F00h, Parameter ID=10h)
Table 31. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Codec Response Format
Bit
31:16
15:8
7:1
Description
Reserved. Read as 0’s.
NumCoeff. Number of Coefficient.
Reserved. Read as 0’s.
0
Benign.
0: Processing unit is not linear and time invariant
1: Processing unit is linear and time invariant
8.1.15. Parameter – GPIO Capabilities
(Verb ID=F00h, Parameter ID=11h)
Table 32. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Codec Response Format
Bit
31
Description
GPIWake=0. The ALC888S-VD does not support GPIO wake up function.
GPIUnsol=1. The ALC888S-VD supports GPIO unsolicited response.
Reserved. Read as 0’s.
30
29:24
23:16
15:8
7:0
NumGPIs=00h. No GPI pin is supported.
NumGPOs=00h. No GPO pin is supported.
NumGPIOs=02h. Two GPIO pins are supported.
8.1.16. Parameter – Volume Knob Capabilities
(Verb ID=F00h, Parameter ID=13h)
Table 33. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Codec Response Format for NID=21h (Volume Control Knob)
Bit
31:8
7
Description
Reserved. Read as 0s.
Delta. Read as 0.
0: Software will not modify the volume in Volume Control Knob
1: Software can write a base volume to the Volume Control Knob
NumSteps.
6:0
The total number of steps in the range of the Volume Control Knob (NID=21h)
Note: The Volume Control knob (NID=21h) supports this parameter.
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Datasheet
8.2. Verb – Get Connection Select Control (Verb ID=F01h)
Table 34. Verb – Get Connection Select Control (Verb ID=F01h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F01h
0’s
Bit[7:0] are Connection Index
Codec Response for Analog Port-B/C/E/F (NID=18h~1Bh)
Bit
31:8
7:0
Description
0’s.
Connection Index Current Settings (Default Value is 00h).
00h: Sum Widget NID=0Ch
02h: Sum Widget NID=0Eh
04h: Sum Widget NID=26h
01h: Sum Widget NID=0Dh
03h: Sum Widget NID=0Fh
Other: Reserved
Codec Response for Digital Pin SPDIF-OUT (NID=1Eh)
Bit
31:8
7:0
Description
0’s.
Connection Index Current Settings (Default Value is 00h).
00h: Digital Converter (SPDIF-OUT) NID=06h
Other: Reserved
Codec Response for Digital Pin SPDIF-OUT2 (NID=11h)
Bit
31:8
7:0
Description
0’s.
Connection Index Current Settings (Default Value is 00h).
00h: Digital Converter (SPDIF-OUT2) NID=10h
Other: Reserved
Codec Response for Other NID
Bit
Description
31:0
Not Supported (Returns 00000000h).
8.3. Verb – Set Connection Select (Verb ID=701h)
Table 35. Verb – Set Connection Select (Verb ID=701h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=701h
Select Index [7:0]
0’s for All Nodes
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Datasheet
8.4. Verb – Get Connection List Entry (Verb ID=F02h)
Table 36. Verb – Get Connection List Entry (Verb ID=F02h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=F02h
Offset Index - N[7:0]
32-bit Response
Codec Response for NID=08h (LINE ADC)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 23h (Sum Widget) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=09h (MIX ADC)
Bit
Description
15:8
Connection List Entry (N+3), (N+2), and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 22h (Sum Widget) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=0Ah (SPDIF-IN Converter)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 1Fh (SPDIF-IN Pin Widget) for N=0~3.
Returns 00h for N>3.
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Codec Response for NID=0Bh (Mixer)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 1Bh (Pin Complex – LINE2) for N=0~3.
Returns 15h (Pin Complex-SURR) for N=4~7.
Returns 00h for N>7.
23:16
15:8
Connection List Entry (N+2).
Returns 1Ah (Pin Complex – LINE1) for N=0~3.
Returns 14h (Pin Complex – FRONT) for N=4~7.
Returns 00h for N>7.
Connection List Entry (N+1).
Returns 19h (Pin Complex – MIC2) for N=0~3.
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7.
Returns 17h (Pin Complex – SIDESURR) for N=8~11.
Returns 00h for N>11.
7:0
Connection List Entry (N).
Returns 18h (Pin Complex – MIC1) for N=0~3.
Returns 1Ch (Pin Complex – CD) for N=4~7.
Returns 16h (Pin Complex – CEN/LFE) for N=8~11.
Returns 00h for N>11.
Codec Response for NID=0Ch (Front Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
7:0
Connection List Entry (N).
Returns 02h (Front DAC) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=0Dh (Surround Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
7:0
Connection List Entry (N).
Returns 03h (Surround DAC) for N=0~3.
Returns 00h for N>3.
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Codec Response for NID=0Eh (Cen/LFE Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
7:0
Connection List Entry (N).
Returns 04h (Cen/LFE DAC) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=0Fh (Side-Surr Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
7:0
Connection List Entry (N).
Returns 05h (Front DAC) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=26h (Fout Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
15:8
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
Returns 00h for N>3.
7:0
Connection List Entry (N).
Returns 25h (Fout1 DAC) for N=0~3.
Returns 00h for N>3.
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Codec Response for NID=14h (Port-D)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 00h.
Connection List Entry (N).
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=15h (Port-A)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 00h.
Connection List Entry (N).
Returns 0Dh (Sum Widget NID=0Dh) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=16h (Port-G)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 00h.
Connection List Entry (N).
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3.
Returns 00h for N>3.
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Datasheet
Codec Response for NID=17h (Port-H)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 00h.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 00h.
Connection List Entry (N+1).
Returns 00h.
Connection List Entry (N).
Returns 0Fh (Sum Widget NID=0Fh) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=18h~1Bh (Port-B/C/E/F)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 0Fh (Sum Widget NID=0Fh) for N=0~3.
Returns 00h for n>3.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3.
Returns 00h for N>3.
Connection List Entry (N+1).
Returns 0Dh (Sum Widget NID=0Dh) for N=0~3.
Returns 00h for N>3.
Connection List Entry (N).
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3.
Returns 26h (Sum Widget NID=26h) for N=4~7.
Returns 00h for N>7.
Codec Response for NID=1Eh (Pin Widget: SPDIF-OUT)
Bit
Description
31:16
Connection List Entry (N+3) and (N+2).
Returns 0000h.
15:8
7:0
Connection List Entry (N+1).
Returns 00h.
Connection List Entry (N).
Returns 06h (SPDIF-OUT converter) for N=0~3.
Returns 00h for N>3.
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Datasheet
Codec Response for NID=11h (Pin Widget: SPDIF-OUT2)
Bit
Description
31:16
Connection List Entry (N+3) and (N+2).
Returns 0000h.
15:8
7:0
Connection List Entry (N+1).
Returns 00h.
Connection List Entry (N).
Returns 10h (SPDIF-OUT2 converter) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=22h (Sum Widget before ADC 09h)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 1Bh (Pin Complex – LINE2) for N=0~3.
Returns 15h (Pin Complex-SURR) for N=4~7.
Returns 12h for N=8~11.
Returns 00h for N>11.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 1Ah (Pin Complex – LINE1) for N=0~3.
Returns 14h (Pin Complex – FRONT) for N=4~7.
Returns 0Bh (Sum Widget) for N=8~11.
Returns 00h for N>11.
Connection List Entry (N+1).
Returns 19h (Pin Complex – MIC2) for N=0~3.
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7.
Returns 17h (Pin Complex – SIDESURR) for N=8~11.
Returns 00h for N>11.
Connection List Entry (N).
Returns 18h (Pin Complex – MIC1) for N=0~3.
Returns 1Ch (Pin Complex – CD) for N=4~7.
Returns 16h (Pin Complex – CEN/LFE) for N=8~11.
Returns 00h for N>11.
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Datasheet
Codec Response for NID=23h (Sum Widget before ADC 08h)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 1Bh (Pin Complex – LINE2) for N=0~3.
Returns 15h (Pin Complex-SURR) for N=4~7.
Returns 00h for N>7.
23:16
15:8
7:0
Connection List Entry (N+2).
Returns 1Ah (Pin Complex – LINE1) for N=0~3.
Returns 14h (Pin Complex – FRONT) for N=4~7.
Returns 0Bh (Sum Widget) for N=8~11.
Returns 00h for N>11.
Connection List Entry (N+1).
Returns 19h (Pin Complex – MIC2) for N=0~3.
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7.
Returns 17h (Pin Complex – SIDESURR) for N=8~11.
Returns 00h for N>11.
Connection List Entry (N).
Returns 18h (Pin Complex – MIC1) for N=0~3.
Returns 1Ch (Pin Complex – CD) for N=4~7.
Returns 16h (Pin Complex – CEN/LFE) for N=8~11.
Returns 00h for N>11.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (Returns 00000000h).
8.5. Verb – Get Processing State (Verb ID=F03h)
Table 37. Verb – Get Processing State (Verb ID=F03h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=F03h
0’s
32-bit Response
Codec Response for All NID
Bit
Description
Not Supported (Returns 00000000h).
31:0
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Datasheet
8.6. Verb – Set Processing State (Verb ID=703h)
Table 38. Verb – Set Processing State (Verb ID=703h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for All Nodes
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=703h
Processing State [7:0]
Codec Response for All NID
Bit
Description
31:0
0’s.
8.7. Verb – Get Coefficient Index (Verb ID=Dh)
Table 39. Verb – Get Coefficient Index (Verb ID=Dh)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=20h
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Dh
0’s
Bit [15:0] are Coefficient Index
Codec Response for NID=20h (Realtek Defined Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s.
Coefficient Index.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (Returns 00000000h).
8.8. Verb – Set Coefficient Index (Verb ID=5h)
Table 40. Verb – Set Coefficient Index (Verb ID=5h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
CAd=X
Node ID=Xh
Verb ID=5h
Coefficient Index [15:0]
0’s for All Nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
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8.9. Verb – Get Processing Coefficient (Verb ID=Ch)
Table 41. Verb – Get Processing Coefficient (Verb ID=Ch)
Get Command Format
Codec Response Format
Response [31:0]
Processing Coefficient [15:0]
Bit [31:28]
Bit [27:20]
Node ID=20h
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Ch
0’s
Codec Response for NID=20h (Realtek Defined Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s.
Processing Coefficient.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (Returns 00000000h).
8.10. Verb – Set Processing Coefficient (Verb ID=4h)
Table 42. Verb – Set Processing Coefficient (Verb ID=4h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Verb ID=4h
Coefficient [15:0]
0’s for All Nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
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8.11. Verb – Get Amplifier Gain (Verb ID=Bh)
This verb is used to get gain/attenuation settings from each widget.
Table 43. Verb – Get Amplifier Gain (Verb ID=Bh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=Bh
‘Get’ Payload [15:0]
Bit[7:0] are Responsible for ‘Get’
‘Get’ Payload in Command Bit[15:0]
Bit
Description
15
Get Input/Output.
0: Input amplifier gain is requested
1: Output amplifier gain is requested
14
13
Reserved. Read as 0.
Get Left/Right.
0: Right amplifier gain is requested
1: Left amplifier gain is requested
12:4
3:0
Reserved. Read as 0’s.
Index[3:0] for Input Source.
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored.
Codec Response for 08h (LINE ADC) and 09h (MIX ADC)
Bit
31:8
7
Description
0’s.
Bit 15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Mute.
0: Unmute
1: Mute
Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute).
6:0
Bit 15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Gain [6:0].
7-bit step value (0~46) specifying the volume from –16dB~+30dB in 1.0dB steps.
Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0’s (No Output Amplifier Mute).
Codec Response for NID=0Bh (MIXER Sum Widget)
Bit
31:8
7
Description
0’s.
Bit 15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Mute.
0: Unmute
1: Mute (Default for all Index)
Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute).
6:0
Bit 15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps.
Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0’s (No Output Amplifier Mute).
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Codec Response for NID=0Ch~0Fh and 26h (Sum Widget: Front, Surr, Cen/LFE, SIDESURR Sum, Fout)
Bit
31:8
7
Description
0’s.
Bit 15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Mute.
0: Unmute
1: Mute
Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute).
6:0
Bit 15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Gain).
Bit 15 is 1 in ‘Get Amplifier Gain’. Output Amplifier Gain [6:0].
7-bit step value (0~64) specifying the volume from –64dB~0dB in 1.0dB steps.
Codec Response for NID=02h ~ 05h and 25h (DAC Widget: Front, Surr, Cen/LFE, SIDESURR, Fout DAC)
Bit
31:8
7
Description
0’s.
Bit 15 is 0 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Mute).
Bit 15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Mute).
Bit 15 is 0 in ‘Get Amplifier Gain. Read as 0’s (No Output Amplifier Mute).
6:0
Bit 15 is 1 in ‘Get Amplifier Gain. Output Amplifier Gain [6:0]. 7-bit step value (0~64) specifying the
volume from –64dB~0dB in 1dB steps.
Codec Response for NID=14h~17h (Pin Complex: Front/Surr/CenLFE/SIDESURR)
Bit
31:8
7
Description
0’s.
Bit 15 is 0 in ‘Get Amplifier Gain’. Read as 0.
Bit 15 is 1 in ‘Get Amplifier Gain’. Output Amplifier Mute.
0: Unmute
1: Mute (NID=14h~17h, Default=1)
6:0
Bit 15 is 0 in ‘Get Amplifier Gain’. Read as 0’s.
Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Gain).
Codec Response for NID=18h~1Bh (Pin Complex: MIC1/MIC2/LINE1/LINE2)
Bit
31:8
7
Description
0’s.
Bit 15 is 0 in ‘Get Amplifier Gain. Read as 0.
Bit 15 is 1 in ‘Get Amplifier Gain.
Output Amplifier Mute:
0: Unmute
1: Mute (NID=18h~1Bh, Default=1)
6:0
Bit 15 is 0 in ‘Get Amplifier Gain. Input Amplifier Gain [6:0]. 7-bit step value (0~3) specifying the
volume from 0dB~30dB in 10dB steps.
Bit 15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Gain).
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Codec Response for NID=22h and 23h (Sum Widget)
Bit
31:8
7
Description
0’s.
Bit 15 is 0 in ‘Get Amplifier Gain. Input Amplifier Mute: 0: Unmute; 1: Mute
Bit 15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Mute).
Bit 15 is 0 in ‘Get Amplifier Gain. Read as 0 (No Input Amplifier Gain).
Bit 15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Input Amplifier Gain).
6:0
Codec Response to Other NID
Bit
Description
31:0
Not Supported (Returns 00000000h).
8.12. Verb – Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 44. Verb – Set Amplifier Gain (Verb ID=3h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=3h
‘Set’ Payload [7:0]
0’s for All Nodes
‘Set’ Payload in Command Bit[15:0]
Bit
Description
15
Set Output Amp.
‘1’ indicates output amplifier gain will be set.
Set Input Amp.
‘1’ indicates input amplifier gain will be set.
Set Left Amp.
14
13
‘1’ indicates left amplifier gain will be set.
Set Right Amp.
12
‘1’ indicates right amplifier gain will be set.
Index Offset (for Input Amplifiers on Sum Widgets and Selector Widgets).
11:8
5 bits index offset in connection list is used to select which input gain will be set on a Sum or a Selector
widget. The index is ignored if the node is not a Sum or a Selector widget, or the ‘Set Input Amp’ bit is not
set.
7
Mute.
0: Unmute
1: Mute (-∞gain)
6:0
Gain[6:0].
A 7-bit step value specifying the amplifier gain.
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8.13. Verb – Get Converter Format (Verb ID=Ah)
Table 45. Verb – Get Converter Format (Verb ID=Ah)
Get Command Format
Codec Response Format
Response [31:0]
Bit[15:0] are Converter Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Ah
0’s
Codec Response for NID=02h~06h, 10h, 25h (Output Converters: Front, Surr, Cen/LFE, Side-Surr, Fout DAC,
SPDIF-OUT, SPDIF-OUT2).
Codec Response for NID=08h~0Ah (Input Converters: LINE, MIX ADC, and SPDIF-IN)
Bit
31:16
15
Description
Reserved. Read as 0.
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
Sample Base Rate Multiple (MULT).
000b: ×1
011b: ×4
001b: ×2
100b~111b: Reserved
010b: ×3
10:8
Sample Base Rate Divisor (DIV).
000b: /1
011b: /4
110b: /7
001b: /2
100b: /5
111b: /8
010b: /3
101b: /6
7
Reserved. Read as 0.
Bits per Sample (BITS).
000b: 8 bits
6:4
001b: 16 bits
100b: 32 bits
010b: 20 bits
101b~111b: Reserved
011b: 24 bits
Number of Channels.
0: 1 channel
……
3:0
1: 2 channels
15: 16 channels
2: 3 channels
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8.14. Verb – Set Converter Format (Verb ID=2h)
Table 46. Verb – Set Converter Format (Verb ID=2h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for All Nodes
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=2h
Set Format [15:0]
‘Set’ Payload in Command Bit[15:0]
Bit
31:16
15
Description
Reserved. Read as 0.
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
Sample Base Rate Multiple (MULT).
000b: ×1
011b: ×4
001b: ×2
100b~111b: Reserved
010b: ×3
10:8
Sample Base Rate Divisor (DIV).
000b: /1
011b: /4
110b: /7
001b: /2
100b: /5
111b: /8
010b: /3
101b: /6
7
Reserved. Read as 0.
Bits per Sample (BITS).
000b: 8 bits
6:4
001b: 16 bits
100b: 32 bits
010b: 20 bits
101b~111b: Reserved
011b: 24 bits
Number of Channels.
0: 1 channel
……
3:0
1: 2 channels
15: 16 channels
2: 3 channels
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8.15. Verb – Get Power State (Verb ID=F05h)
Table 47. Verb – Get Power State (Verb ID=F05h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h
Verb ID=Ah
0’s
Power State [7:0]
Codec Response for NID=01h (Audio Function Group)
Codec Response for NID=02h~05h, 25h, 08h, 09h (Audio Input/Output Converter)
Codec Response for NID=11h, 12h, 14h~1Fh (Pin Widget)
Codec Response for NID=06h, 10h, 0Ah (Audio Input/Output Converter)
Bit
31:6
5:4
Description
Reserved. Read as 0’s.
PS-Act. Actual Power State [1:0].
00: Power state is D0
01: Power state is D1
11: Power state is D3
10: Power state is D2
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set.
3:2
1:0
Reserved. Read as 0’s.
PS-Set. Set Power State [1:0].
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
PS-Set controls the current power setting of the referenced node.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (Returns 00000000h).
8.16. Verb – Set Power State (Verb ID=705h)
Table 48. Verb – Set Power State (Verb ID=705h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=705h
Power State [7:0]
0’s for All Nodes
‘Power State’ in Command Bit[7:0]
Bit
7:6
5:4
Description
Reserved. Read as 0’s.
PS-Act. Actual Power State [1:0].
00: Power state is D0
01: Power state is D1
11: Power state is D3
10: Power state is D2
PS-Act indicates the actual power state of the referenced node.
3:2
1:0
Reserved. Read as 0’s.
PS-Set. Set Power State [1:0].
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
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8.17. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F06h
0’s
Stream & Channel [7:0]
Codec Response for NID=02h~05h,25h, 06h, 10h (Output Converters: Front, Surr, Cen/LFE, Side-Surr, Fout DAC,
SPDIF-OUT, SPDIF-OUT2)
Codec Response for NID=08h~0Ah (Input Converters: LINE ADC, MIX ADC, and SPDIF-IN)
Bit
31:8
7:4
Description
Reserved. Read as 0’s.
Stream[3:0].
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
3:0
Channel[3:0].
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its
left and right channel.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (Returns 00000000h).
8.18. Verb – Set Converter Stream, Channel (Verb ID=706h)
Table 50. Verb – Set Converter Stream, Channel (Verb ID=706h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=706h
Stream & Channel [7:0]
0’s for All Nodes
‘Stream and Channel’ in Command Bit[7:0]
Bit
31:8
7:4
Description
Reserved. Read as 0’s.
Set Stream[3:0].
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Set Channel[3:0].
1:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its
left and right channel.
Note: This verb assigns stream and channel for output converters (NID=02h~06h, 25h, 10h) and input converters
(NID=08h~0Ah). Other widgets will ignore this verb.
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8.19. Verb – Get Pin Widget Control (Verb ID=F07h)
Table 51. Verb – Get Pin Widget Control (Verb ID=F07h)
Get Command Format
Codec Response Format
Response [31:0]
Pin Control [7:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=F07h
0’s
Codec Response for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 11h, 1Fh, (Pin Complex: FRONT, SURR, CENLFE, SIDESURR,
MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, SPDIF-OUT, SPDIF-OUT2, and SPDIF-IN)
Bit
31:1
7
Description
Reserved. Read as 0’s.
H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O Unit).
0: Disabled
Out Enable (Output Buffet Enable, EN_OBUF for an I/O Unit).
0: Disabled 1: Enabled
In Enable (Input Buffer Enable, EN_IBUF for an I/O Unit).
1: Enabled
6
5
0: Disabled
1: Enabled
4:3
2:0
Reserved.
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled)
011b: Reserved
001b: 50% of LDO-OUT1
100b: 80% of LDO-OUT1
010b: Ground 0V
101b: 100% of LDO-OUT1
110b~111b: Reserved
Codec Response for Other NID
Bit
Description
Not Supported (Returns 00000000h).
31:0
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8.20. Verb – Set Pin Widget Control (Verb ID=707h)
Table 52. Verb – Set Pin Widget Control (Verb ID=707h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for All Nodes
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Verb ID=707h
Payload Bit [7:0]
Pin Control [7:0]
CAd=X
‘Pin Control’ in command [7:0] for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 11h, 1Fh (Pin Complex: FRONT, SURR, CENLFE,
SIDESURR, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, SPDIF-OUT, SPDIF-OUT2, and SPDIF-IN)
Bit
31:1
7
Description
Reserved. Read as 0’s.
H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O Unit).
0: Disabled
Out Enable (Output Buffet Enable, EN_OBUF for an I/O Unit).
0: Disabled 1: Enabled
In Enable (Input Buffer Enable, EN_IBUF for an I/O Unit).
1: Enabled
6
5
0: Disabled
1: Enabled
4:3
2:0
Reserved.
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled)
011b: Reserved
001b: 50% of LDO-OUT1
100b: 80% of LDO-OUT1
010b: Ground 0V
101b: 100% of LDO-OUT1
110b~111b: Reserved
8.21. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real-time event.
Table 53. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID= F08h
0’s
32-bit Response
Codec Response for NID=01h (GPIO in Audio Function Group), 14h~1Ch, 1Eh, 11h, 1Fh (Port A to H, CD-IN,
SPDIF-OUT, SPDIF-OUT2 and SPDIF-IN)
Bit
31:8
7
Description
Reserved. Read as 0’s.
Unsolicited Response is Enabled.
0: Disabled
1: Enabled
6:4
3:0
Reserved. Read as 0’s.
Assigned Tag for Unsolicited Response.
The tag[3:0] is assigned by software to determine which widget generates unsolicited responses.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (Returns 00000000h).
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8.22. Verb – Set Unsolicited Response Control (Verb ID=708h)
Enables a widget to generate an unsolicited response.
Table 54. Verb – Set Unsolicited Response Control (Verb ID=708h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=708h
EnableUnsol [7:0]
0’s for All Nodes
‘EnableUnsol’ in Command Bit[7:0] for NID=01h (GPIO in Audio Function Group), 14h~1Ch, 1Eh, 11h, 1Fh (Port A to
H, CD-IN, SPDIF-OUT, SPDIF-OUT2 and SPDIF-IN)
Bit
31:8
7
Description
Reserved. Read as 0’s.
Enable Unsolicited Response.
0: Disable
1: Enable
6:4
3:0
Reserved. Read as 0’s.
Tag for Unsolicited Response.
Tag[3:0] is defined by software to assign a 4-bit tag for nodes that are enabled to generate unsolicited
responses.
8.23. Verb – Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 55. Verb – Get Pin Sense (Verb ID=F09h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F09h
0’s
32-bit Response
Codec Response for NID = 14h~1Bh, 11h, 1Eh, 1Fh
Bit
Description
31
Presence Detect Status.
0: No device is attached to the pin
1: Device is attached to the pin
Measured Impedance.
30:0
The ALC888S-VD does not support hardware impedance detection. This field is read as 0s.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (Returns 00000000h).
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8.24. Verb – Execute Pin Sense (Verb ID=709h)
Table 56. Verb – Execute Pin Sense (Verb ID=709h)
Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= 709h
Right Channel[0]
0’s for All Nodes
‘Payload’ in Command Bit[7:0]
Bit
7:1
0
Description
Reserved. Read as 0’s.
Right (Ring) Channel Select.
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)
The ALC888S-VD does not support hardware impedance sensing and will ignore this control.
8.25. Verb – Get Volume Knob Widget (Verb ID=F0Fh)
Table 57. Verb – Get Volume Knob (Verb ID=F0Fh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=21h Verb ID= F0Fh
0’s
Bit[31:8]=0s, Bit[7:0] is Volume
Codec Response for NID = 21h (Volume Knob Widget)
Bit
31:8
7
Description
Reserved.
Direct.
0: The volume generated by external HW volume control will be sent by unsolicited response. Software is
responsible for programming the amplifier appropriately
1: The volume generated by external HW volume control will directly affect the volume of the amplifier.
Volume in Steps.
6:0
Note: The ALC888S-VD does not support Volume Knob Widget and will ignore this verb and respond with 0’s.
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8.26. Verb – Set Volume Knob Widget (Verb ID=70Fh)
Table 58. Verb – Set Volume Knob (Verb ID=70Fh)
Set Command Format
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=21h Verb ID= 70Fh Bit[7] is ‘Direct’ Control
‘Payload’ in Command Bit[7:0]
Bit
31:8
7
Description
Reserved.
Direct.
0: The volume generated by external HW volume control will be sent by unsolicited response. Software is
responsible for programming the amplifier appropriately
1: The volume generated by external HW volume control will directly affect the volume of the amplifier.
Reserved.
6:0
Note: The ALC888S-VD does not support Volume Knob Widget and will ignore this verb and respond with 0’s.
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Datasheet
8.27. Verb – Get Configuration Default (Verb ID=F1Ch)
Reads the 32-bit sticky register for each Pin Widget configured by software.
Table 59. Verb – Get Configuration Default (Verb ID=F1Ch)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F1Ch
0’s
32-bit Response
Codec Response for NID=14h~1Bh (Port-A~Port-H), 1Ch (CD-IN), 1Dh (BEEP-IN), 1Eh (SPDIF-OUT),
1Fh (SPDIF-IN), 11h (SPDIF-OUT2), and 12h (Digital MIC)
Bit
Description
31:0
32-Bit Configuration Information for Each Pin Widget.
Default value for each pin widget.
[31:30]: Port Connectivity (0h: Port; 2h: Header; 1h: Not Connected)
[29:24]: Location
[23:20]: Default Device
[19:16]: Connection Type
[15:12]: Color
[11:08]: Misc
[07:04]: Default Association
[03:00]: Sequence
NID 14h
NID 15h
NID 16h
NID 17h
NID 18h
NID 19h
01014030h
01011031h
01016032h
01012033h
01A19850h 02A19C80h
NID 1Ah
NID 1Bh
NID 1Ch
NID 1Dh
NID 1Eh
NID 1Fh
01813051h
02214C40h
9993105Fh
00000100h
01441070h
41C46060h
NID 11h
NID 12h
411110F0h
411111F0h
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).
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Table 60. Default Configuration in Chip (14h~1Ch)
NID=
Name
14h
FRONT
Jack
15h
16h
17h
SIDE
Jack
18h
MIC1
Jack
19h
MIC2
Jack
1Ah
LINE1
Jack
1Bh
LINE2
Jack
1Ch
CD-IN
Header
Inside
AUX
SURR CEN/LFE
Port
Jack
Rear
Jack
Rear
Location
Device
Con Type
Color
Rear
Rear
Rear
Front
Mic In
Rear
Front
Line Out Line Out Line Out Line Out
Mic In
Line In
HP Out
1/8" Jack 1/8" Jack 1/8" Jack 1/8" Jack 1/8" Jack 1/8" Jack 1/8" Jack 1/8" Jack
ATAPI
Black
Green
Black
Orange
Grey
Pink
Pink
Blue
Green
Misc
8Vrefo
8Vrefo
8Vrefo
8Vrefo
9Vrefo
9Vrefo
8Vrefo
9Vrefo
8Vrefo
8Retask 8Retask 8Retask 8Retask 8Retask 9Retask 8Retask 9Retask 8Retask
8Sensing 8Sensing 8Sensing 8Sensing 8Sensing 8Sensing 8Sensing 8Sensing 8Sensing
9JD
3h
9JD
3h
9JD
3h
9JD
3h
9JD
5h
9JD
8h
9JD
5h
9JD
4h
8JD
5h
Association
Sequence
0h
1h
2h
3h
0h
0h
1h
0h
Fh
Table 61. Default Configuration in Chip (1Dh~12h)
NID=
Name
1Dh
1Eh
SPDIF-OUT
Jack
1Fh
SPDIF-IN
NC
11h
SPDIF-OUT2
NC
12h
BEEP-IN
Internal
Unknown
Other
Digital MIC
NC
Port
Location
Device
Con Type
Color
Rear
Rear
Rear
Rear
SPDIF Out
RCA
SPDIF-In
RCA
Speaker
1/8" Jack
Black
Speaker
1/8" Jack
Black
Other
Other
Black
Orange
8Vrefo
8Retask
8Sensing
9JD
Misc
8Vrefo
8Retask
8Sensing
8JD
8Vrefo
8Retask
8Sensing
9JD
8Vrefo
8Retask
8Sensing
9JD
8Vrefo
8Retask
8Sensing
8JD
Association
Sequence
0h
7h
6h
Fh
Fh
0h
0h
0h
0h
0h
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Datasheet
8.28. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh, 11h, 12h,
1Eh, and 1Fh, e.g., placement and expected default device.
Table 62. Verb – Set Configuration Default Bytes 0, 1, 2, 3
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=71Ch,
Label [7:0]
0’s for All Nodes
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=14h~1Bh (Port-A~Port-H), 1Ch (CD-IN), 1Dh (BEEP-IN), 1Eh (SPDIF-OUT), 1Fh
(SPDIF-IN), 11h (SPDIF-OUT2), and 12h (Digital MIC). Other widgets will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
8.29. Verb – Get BEEP Generator (Verb ID=F0Ah)
Table 63. Verb – Get BEEP Generator (Verb ID= F0Ah)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID= F0Ah
0’s
Divider [7:0]
‘Response’ for NID=01h (Audio Function Group)
Bit
31:8
7:0
Description
Reserved.
Frequency Divider, F[7:0].
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in
F[7:0].
The lowest tone is 48kHz/(255×4)=47Hz.
The highest tone is 48kHz/(1×4)=12kHz.
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Codec Response for Other NID
Bit
Description
31:0
0’s.
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SPDIF Outputs
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Datasheet
8.30. Verb – Set BEEP Generator (Verb ID=70Ah)
Table 64. Verb – Set BEEP Generator (Verb ID= 70Ah)
Set Command Format
Codec Response Format
Response [31:0]
0’s for All Nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=70Ah
Divider [7:0]
‘Divider’ in Set Command
Bit
31:8
7:0
Description
Reserved.
Frequency Divider, F[7:0].
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in
F[7:0].
The lowest tone is 48kHz/(255×4)=47Hz.
The highest tone is 48kHz/(1×4)=12kHz.
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
8.31. Verb – Get GPIO Data (Verb ID=F15h)
Table 65. Verb – Get GPIO Data (Verb ID= F15h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=F15h
0’s
32-bit Response
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:2] Data. Not supported in the ALC888S-VD.
GPIO[1:0] Data.
2:0
The value written (output) or sensed (input) on the corresponding pin if it is enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s.
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Datasheet
8.32. Verb – Set GPIO Data (Verb ID=715h)
Table 66. Verb – Set GPIO Data (Verb ID= 715h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h Verb ID=715h
Data [7:0]
0’s for All Nodes
‘Data’ in Set command for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:2] Output Data. Not supported in the ALC888S-VD.
GPIO[1:0] Output Data.
2:0
The value written determines the value driven on a pin that is configured as an output pin.
Codec Response for All NID
Bit
Description
31:0
0’s.
8.33. Verb – Get GPIO Enable Mask (Verb ID=F16h)
Table 67. Verb – Get GPIO Enable Mask (Verb ID= F16h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h Verb ID=F16h
0’s
EnableMask [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:3
2:0
Description
Reserved.
GPIO[1:0] Enable Mask.
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
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8.34. Verb – Set GPIO Enable Mask (Verb ID=716h)
Table 68. Verb – Set GPIO Enable Mask (Verb ID=716h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for All Nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=716h
Enable Mask [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:2] Enable Mask. Not supported in the ALC888S-VD.
GPIO[1:0] Enable Mask.
2:0
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
8.35. Verb – Get GPIO Direction (Verb ID=F17h)
Table 69. Verb – Get GPIO Direction (Verb ID=F17h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h Verb ID=F17h
0’s
Direction [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:2] Direction Control. Not supported in the ALC888S-VD.
GPIO[1:0] Direction Control.
2:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
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Datasheet
8.36. Verb – Set GPIO Direction (Verb ID=717h)
Table 70. Verb – Set GPIO Direction (Verb ID=717h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for All Nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=717h
Direction [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:2] Direction Control. Not supported in the ALC888S-VD.
GPIO[1:0] Direction Control.
2:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.37. Verb – Get GPIO Unsolicited Response Enable Mask
(Verb ID=F19h)
Table 71. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=F19h
0’s
UnsolEnable [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC888S-VD.
GPIO[1:0] Unsolicited Enable Mask.
2:0
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
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Datasheet
8.38. Verb – Set GPIO Unsolicited Response Enable Mask
(Verb ID=719h)
Table 72. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for All Nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=719h
UnsolEnable [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:3
Description
Reserved.
GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC888S-VD.
GPIO[1:0] Unsolicited Enable Mask.
2:0
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Note 2: The unsolicited response of corresponding GPIO is enabled when it’s ‘Enable Mask’and Verb-‘Unsolicited
Response’for NID=01h are enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.39. Verb – Function Reset (Verb ID=7FFh)
Table 73. Verb – Function Reset (Verb ID=7FFh)
Command Format (NID=01h)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=7FFh
0’s
Codec Response
Bit
Description
Reserved. Read as 0’s.
31:0
Note: The Function Reset command causes all widgets in the ALC888S-VD to return to their power on default state.
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Datasheet
8.40. Verb – Get Digital Converter Control 1, 2, 3, 4
(Verb ID=F0Dh, F0Eh, F3Eh, F3Fh)
Table 74. Verb – Get Digital Converter Control 1, 2, 3, 4 (Verb ID=F0Dh, F0Eh, F3Eh, F3Fh)
Get Command Format
Codec Response Format
Bit [31:28]
CAd=X
Bit [27:20]
Node ID=Xh Verb ID=F0Dh/F0Eh/
F3Eh/F3Fh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Bit[31:16]=0’s,
Bit[15:0] are SIC Bit
0’s
NID=06h (SPDIF-OUT) Response to ‘Get verb’ – F0Dh/F0Eh/F3Eh/F3Fh
NID=10h (SPDIF-OUT2) Response to ‘Get verb’ – F0Dh/F0Eh/F3Eh/F3Fh
Bit
31:24
23
Description – SIC (SPDIF IEC Control) Bit[15:0]
Read as 0’s.
Keep Alive Enable.
0: Disable (SPDIF output is disabled in D2/D3 mode)
1: Enable (SPDIF output is enabled in D2/D3 mode)
Reserved. Read as 0’s.
22:20
19:16
IEC Coding Type.
Not supported in ALC888S-VD, read as 0’s.
Reserved. Read as 0’s.
15
14:8
7
CC[6:0] (Category Code).
LEVEL (Generation Level).
PRO (Professional or Consumer Format).
0: Consumer format
6
1: Professional format
5
4
3
/AUDIO (Non-Audio Data Type).
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright).
0: Asserted
1: Not asserted
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
VCFG for Validity Control (Control V Bit and Data in Sub-Frame).
V for Validity Control (Control V Bit and Data in Sub-Frame).
Digital Enable (DigEn).
2
1
0
0: OFF
1: ON
NID=0Ah (SPDIF-IN) Response to ‘Get verb’ - F0Dh/F0Eh
Bit
31:15
14:8
Description (part of SPDIF-IN Channel Status)
Reserved. Read as 0’s.
CC[6:0] (Category Code).
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NID=0Ah (SPDIF-IN) Response to ‘Get verb’ - F0Dh/F0Eh
Bit
7
Description (part of SPDIF-IN Channel Status)
LEVEL (Generation Level).
PRO (Professional or Consumer Format).
0: Consumer format
6
1: Professional format
5
/AUDIO (Non-Audio Data Type).
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright).
0: Asserted1: Not asserted
PRE (Pre-Emphasis).
4
3
0: None
1: Filter pre-emphasis is 50/15 microseconds
Reserved.
2
1
Invalid. V Bit in Sub-Frame of SPDIF-IN.
0: Data X and Y are valid, or SPDIF-IN is not locked
1: At least one of data X and Y is invalid
Digital Enable (DigEn).
0
0: OFF
1: ON
Codec Response for Other NID
Bit
Description
31:0
0’s.
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Datasheet
8.41. Verb – Set Digital Converter Control 1, 2, 3, 4
(Verb ID=70Dh, 70Eh, 73Eh, 73Fh)
Table 75. Verb – Set Digital Converter Control 1, 2, 3, 4 (Verb ID=70Dh, 70Eh, 73Eh, 73Fh)
Set Command Format (Verb ID=70Dh, Set Control 1)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=70Dh
SIC [7:0]
Set Command Format (Verb ID=70Eh, Set Control 2)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh
Verb ID=70Eh
SIC [15:8]
Set Command Format (Verb ID=73Eh, Set Control 3)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh
Verb ID=73Eh
SIC [23:16]
Set Command Format (Verb ID=73Fh, Set Control 4)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh
Verb ID=73Fh
SIC [31:24]
‘Payload’ in Set Control 1 for NID=06h and 10h (SPDIF-OUT and SPDIF-OUT2)
Bit
7
Description – SIC (SPDIF IEC Control) Bit[7:0]
LEVEL (Generation Level).
6
PRO (Professional or Consumer Format).
0: Consumer format
1: Professional format
5
4
3
/AUDIO (Non-Audio Data Type).
0: PCM data
COPY (Copyright).
0: Asserted
1: AC3 or other digital non-audio data
1: Not asserted
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
1
0
VCFG for Validity Control (Control V Bit and Data in Sub-Frame).
V for Validity Control (Control V Bit and Data in Sub-Frame).
Digital Enable (DigEn).
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=06h and 10h (SPDIF-OUT and SPDIF-OUT2)
Bit
7
Description – SIC (SPDIF IEC Control) Bit[7:0]
Reserved. Read as 0’s.
6:0
CC[6:0] (Category Code).
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‘Payload’ in Set Control 3 for NID=06h and 10h (SPDIF-OUT and SPDIF-OUT2)
Bit
Description – SIC (SPDIF IEC Control) Bit[23:16]
Keep Alive Enable.
7
0: Disable (SPDIF output would be disabled in D2/D3 mode)
1: Enable (SPDIF output would be enabled in D2/D3 mode)
Reserved.
6:0
‘Payload’ in Set Control 4 for NID=06h and 10h (SPDIF-OUT and SPDIF-OUT2)
Bit
Description – SIC (SPDIF IEC Control) Bit[31:24]
7:0
Reserved.
‘Payload’ in Set Control 1 for NID=0Ah (SPDIF-IN)
Bit
7:1
0
Description – SIC (SPDIF IEC Control) Bit[7:0]
Reserved.
Digital Enable (DigEn).
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=0Ah (SPDIF-IN)
Bit
Description – SIC (SPDIF IEC Control) Bit[7:0]
7:0
Reserved. Read as 0’s.
Note: Other widgets will ignore this verb.
8.42. Verb – Get Subsystem ID [31:0]
(Verb ID=F20h/F21h/F22h/F23h)
32-bit Read/Write register for Audio Function Group (NID=01h)
Table 76. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)
Get Command Format Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=01h
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd = X
Verb ID=F20h
0s
32-bit Response
Codec Response for NID=01h
Bit
31:16
15:8
7:0
Description
Subsystem ID[23:8] (Default=10ECh).
Subsystem ID[7:0] (Default=08h).
Assembly ID[7:0] (Default=88h).
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ALC888S-VD
Datasheet
8.43. Verb – Set Subsystem ID [31:0] (Verb ID=723h for [31:24],
722h for [23:16], 721h for [15:8], 720h for [7:0])
Table 77. Verb – Set Subsystem ID [31:0]
(Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0])
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd = X Node ID=01h
Verb ID=723h,
Label [7:0]
0s for All Nodes
722h, 721h, 720h
Codec Response for all NID
Bit
Description
31:0
0s.
8.44. Verb – Get EAPD Control (Verb ID=F0Ch for Get)
Table 78. Verb – Get EAPD Control (Verb ID=F0Ch)
Get Command Format (NID=14h and 15h)
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=14h/1Bh Verb ID=F0Ch
0s
Bit[1] is EAPD Control
Codec Response for NID=14h (FRONT, port-D) and 1Bh (LINE2, port-E)
Bit
31:3
2
Description
Reserved.
L-R Swap. The ALC888S-VD does not support swapping left and right channels. Read as 0.
1
EAPD Value.
0: EAPD pin state is low
1: EAPD pin state is high
0
Bridge Tied Load (BTL) Enable. The ALC888S-VD does not support BTL output. Read as 0.
Codec Response in for Other NID
Bit
Description
31:0
0’s.
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
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Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
8.45. Verb – Set EAPD Control (Verb ID=70Ch for Set)
Table 79. Verb – Set EAPD Control (Verb ID=70Ch for Set)
Set Command Format (NID=14h and 15h)
Codec Response Format
Response [31:0]
0s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=14h/1Bh Verb ID=70Ch Bit[1] is EAPD Control
Payload in Set Commend for NID=14h (FRONT, port-D) and 1Bh (LINE2, port-E)
Bit
7:3
2
Description
Reserved. Written Data is Ignored.
L-R Swap. The ALC888S-VD does not support swapping left and right channels, written data is ignored.
1
EAPD Value.
0: EAPD pin state is low
1: EAPD pin state is high
0
Bridge Tied Load (BTL) Enable. The ALC888S-VD does not support BTL output. Written data is ignored.
Note: Pin 47 is shared by the EPAD and SPDIF-IN functions. Pin 47 will act as EAPD and reflect the set EAPD state in
payload bit[1] when pin widget SPDIF-IN is not connected via the programming configuration register. Other widgets
will ignore this verb
Codec Response
Bit
Description
31:0
0’s.
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
70
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 80. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Typical
Maximum
Units
Power Supply
Digital Power for Core
Digital Power for HDA Link
Analog
DVDD
DVDD-IO*
LDO-IN**
LDO-OUT1
Ta
3.0
1.5
4.5
4.05
0
3.3
3.3
5.0
4.5
-
3.6
3.6
5.5
4.95
+70
+125
V
V
V
V
Ambient Operating Temperature
Storage Temperature
oC
oC
Ts
-
-
ESD (Electrostatic Discharge)
Susceptibility Voltage
4000
All Pins
*: The digital link power DVDD-IO must be lower than the digital core power DVDD.
**: The standard testing condition before shipping is AVDD = 5.0V unless specified. Customers designing with a different
AVDD should contact Realtek technical support representatives for special testing support.
9.1.2. Threshold Voltage
DVDD-IO= 1.5V±5%/3.3V±5%, DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load.
Table 81. Threshold Voltage
Parameter
Symbol
Vin
VIL
VIH
VOH
VOL
VIL
VIH
VOH
VOL
-
Minimum
Typical
Maximum
Units
V
Input Voltage Range
-0.30
-
-
-
-
-
-
-
DVDD+0.30
Low Level Input Voltage (HDA link)
High Level Input Voltage (HDA link)
High Level Output Voltage (HDA link)
Low Level Output Voltage (HDA link)
Low Level Input Voltage (SPDIF-IN, GPIOs)
High Level Input Voltage (SPDIF-IN, GPIOs)
High Level Output Voltage (SPDIF-OUT, GPIOs)
Low Level Output Voltage (SPDIF-OUT, GPIOs)
Input Leakage Current
-
0.4×DVDD-IO
V
0.6×DVDD-IO
-
V
0.9×DVDD-IO
-
V
-
0.1×DVDD-IO
V
-
0.44×DVDD (1.45)
V
0.56×DVDD (1.85)
-
V
0.9×DVDD
-
V
-
-10
-10
-
-
-
0.1×DVDD
V
10
10
-
µA
µA
mA
Ω
Output Leakage Current (Hi-Z)
-
-
Output Buffer Drive Current
-
5
Internal Pull Up Resistance
-
-
50k
-
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
71
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
9.1.3. Digital Filter Characteristics
Table 82. Digital Filter Characteristics
Filter
Description
Minimum
Typical
Maximum
Units
KHz
KHz
dB
ADC Filter
Passband (Upper Band < -0.030dB)
Passband (Upper Band < -1.0dB)
Passband Ripple
-
0.4350×Fs
-
-
0.4571×Fs
-
-
-
-
±0.030
Stopband
0.565×Fs
-
-
-
KHz
dB
Stopband Attenuation
Passband Frequency Response: -0.15dB
(Fs=192000)
80
-
-
ADC Highpass Filter
DAC Lowpass Filter
20
Hz
Passband Frequency Response: -0.03dB
Stopband
-
0.441×Fs
-
KHz
KHz
dB
0.559×Fs
-
-
1.5×Fs
Stopband Rejection
90
-
-
±0.030
-
Passband Ripple
-
dB
DAC Highpass Filter
Passband Frequency Response: -0.15dB
(Fs=192000)
-
20
Hz
Note: Fs=Sample rate.
9.1.4. SPDIF Input/Output Characteristics
DVDD=3.3V, Tambient=25°C, with 75Ω external load.
Table 83. SPDIF Input/Output Characteristics
Parameter
Symbol
VOH
VOL
VIH
Minimum
Typical
Maximum
Units
SPDIF-OUT High Level Output
SPDIF-OUT Low Level Output
SPDIF-IN High Level Input
SPDIF-IN Low Level Input
SPDIF-IN Bias Level
3.0
3.3
-
0.3
-
V
V
V
V
V
-
0
1.85
-
-
VIL
-
-
1.45
-
Vt
1.65
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
72
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
9.2. AC Characteristics
9.2.1. Link Reset and Initialization Timing
Table 84. Link Reset and Initialization Timing
Parameter
Symbol
TRST
Minimum
100.167
100
Typical
Maximum
Units
µs
RESET# Active Low Pulse Width
-
-
-
-
RESET# Inactive to BCLK Startup Delay for
PLL Ready Time
TPLL
µs
SDI Initialization Request
TFRAME
-
-
25
Frame Time
Initialization
Sequence
>= 4 BCLK
4 BCLK
4 BCLK
BCLK
Normal Frame
SYNC
SYNC
SDO
SDI
Initialization
Request
RESET#
T
RST
T
T
FRAME
PLL
Figure 15. Link Reset and Initialization Timing
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
73
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
9.2.2. Link Timing Parameters at the Codec
Table 85. Link Timing Parameters at the Codec
Parameter
Symbol
Minimum
23.9976
41.163
-
Typical
Maximum
24.0024
42.171
500
Units
MHz
ns
BCLK Frequency
BCLK Period
24.0
-
Tcycle
41.67
BCLK Jitter
Tjitter
Thigh
Tlow
150
ns
BCLK High Pulse Width
BCLK Low Pulse Width
17.5
-
-
-
24.16
24.16
-
ns
17.5
ns
SDO Setup Time at Both Rising
and Falling Edge of BCLK
Tsetup
5
ns
SDO Hold Time at Both Rising
and Falling Edge of BCLK
Thold
Ttco
5
3
0
-
-
-
-
11.0
7
ns
ns
ns
SDI Valid Time After Rising Edge
of BCLK (1:50pF External Load)
SDI Flight Time
Tflight
Figure 16. Link Signals Timing
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
74
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
9.2.3. SPDIF Output and Input Timing
Table 86. SPDIF Output and Input Timing
Parameter
Symbol
-
Minimum
Typical
3.072
Maximum
Units
MHz
ns
SPDIF-OUT Frequency
SPDIF-OUT Period1
-
-
Tcycle
Tjitter
THigh
TLow
Trise
-
325.6
-
SPDIF-OUT Jitter
-
-
4
ns
SPDIF-OUT High Level Width
SPDIF-OUT Low Level Width
SPDIF-OUT Rising Time
SPDIF-OUT Falling Time
SPDIF-IN Period2
156.2 (48%)
162.8 (50%)
162.8 (50%)
2.0
169.2 (52%)
ns (%)
ns (%)
ns
156.2 (48%)
169.2 (52%)
-
-
Tfall
-
2.0
-
ns
Tcycle
Tjitter
THigh
TLow
-
325.6
-
ns
SPDIF-IN Jitter
-
-
10
ns
SPDIF-IN High Level Width
SPDIF-IN Low Level Width
146.4 (45%)
146.4 (45%)
162.8 (50%)
162.8 (50%)
179 (55%)
179 (55%)
ns (%)
ns (%)
Note 1: Bit parameters for 48kHz sample rate of SPDIF-OUT.
Note 2: Bit parameters for 48kHz sample rate of SPDIF-IN.
T
cycle
T
T
low
high
V
OH
V
IH
V
t
V
IL
V
OL
T
T
rise
fall
Figure 17. Output and Input Timing
9.2.4. Test Mode
The ALC888S-VD does not support test mode or Automatic Test Equipment (ATE) mode.
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
75
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
9.3. Analog Performance
• Tambient=25oC, DVDD=3.3V±5%, AVDD=5.0V±5%
Standard Test Conditions
• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz
Table 87. Analog Performance
Parameter
Min
Typical
Max
Units
Full-Scale Input Voltage
Vrms
All Inputs (Gain=0dB) to ADC
-
1.5
-
Full-Scale Output Voltage (Gain=0dB)
DAC
Headphone Amplifier Output@32Ω Load
-
-
1.2
1.1
-
-
Vrms
Vrms
Dynamic Range with –60dB Signal (A-Weight)
ADC
DAC
-
92
-
90
95
93
-
97
-
dB FSA
dB FSA
dB FSA
Headphone Amplifier Output@32Ω Load
THD+N with –3dB Signal (No A-Weight)
ADC from Port-C and Port-F
ADC from Other Port Except Port-C and Port-F
DAC to All Port
-
-
-
-
-84
-85
-84
-75
-
-
-
-
dB FS
dB FS
dB FS
dB FS
Headphone Amplifier Output@32Ω Load
Magnitude Response (10KΩ Load)
0
0
0
0
0
0
-
-
-
-
-
-
-
21,792
43,584
87,168
19,200
38,400
76,800
Hz
Hz
Hz
Hz
Hz
Hz
dB
dB
dB
KΩ
All DAC @Fs=48KHz (FR=±0.05dB)
All DAC @Fs=96KHz (FR=±0.05dB)
All DAC @Fs=192KHz (FR=±0.05dB)
All ADC @Fs=48KHz (FR=±0.04dB)
All ADC @Fs=96KHz (FR=±0.04dB)
All ADC @Fs=192KHz (FR=±0.04dB)
Power Supply Rejection (Measured at 1kHz Point)
Amplifier Gain Step
-72
1.0
-80
64
-
-
-
-
-
Channel Separation (Crosstalk)
Input Impedance (Gain=0dB)
Output Impedance
-
-
Amplified Output
Non-Amplified Output
-
-
2
200
-
-
Ω
Ω
Digital Power Supply Current (Normal/DVD-Audio)
DVDD=3.3V
-
-
-
-
12/28
-
mA
µA
mA
µA
Digital Power Supply Current (D2)
DVDD=3.3V
-
1100
Analog Power Supply Current (Normal Operation)
AVDD=5.0V
48
-
-
Analog Power Supply Current (D2)
AVDD=5.0V
530
VREFOUTx Output Voltage
VREFOUTx Output Current
-
-
0.5×LDO-OUT1 0.8×LOD-OUT1
V
5
-
mA
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
76
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
10. Application Circuits
To get the best compatibility in hardware design and software driver, any modification should be
confirmed with Realtek. Realtek may update the latest application circuits onto our web site
(www.realtek.com) without modifying this datasheet.
10.1. Desktop System
This following pages show an example of a 7.1 channel output desktop system with three analog jacks on
the rear panel, and with two re-tasking analog jacks on the front panel.
Table 88. Desktop System
Analog Port
Pin
Location
Function Description
FRONT (Port-D)
SURR (Port-A)
CENTER/LFE (Port-G)
SIDE (Port-H)
35, 36
39, 41
43, 44
45, 46
21, 22
23, 24
14, 15
Rear Panel Front Channel Line Output and Amplified Output.
Rear Panel Surround Channel Line Output.
Rear Panel Center and Low Frequency (Sub-Woofer) Channel Line Output.
Rear Panel Side Surround Channel Line Output.
Rear Panel Analog Microphone Input.
MIC1 (Port-B)
LINE1 (Port-C)
LINE2 (Port-E)
Rear Panel Analog Line Input.
Front Panel Re-Tasking Jack Supports Headphone Out (Default), Microphone
Input, and Line Input.
MIC2 (Port-F)
16, 17
Front Panel Re-Tasking Jack Supports Microphone Input (Default), Line Input,
and Headphone Output.
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
77
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
MIC1-VREFO-R
LINE2-VREFO
MIC2-VREFO
FERB2
Standby +5V
+
D1
+10u
AZ2015-01L / AZ2015-01H
R3
R5
Sense B
5.1K, 1%
10K, 1%
SIDESURR-JD
CEN-JD
MIC1-VREFO-L
C6
LDO-OUT
FRONT-L
FRONT-R
C4
R9
10u/X5R
+
C5
20K, 1%
MIC2-JD
LINE2-JD
+
R11
0.1u
10u
39.2K 1%
DGND
AGND
U2
Tied at one point only under
the codec or near the codec
PIN37-VREFO
37
24
23
22
21
20
19
18
17
16
15
14
13
LINE1-R
LINE1-L
MIC1-R
PIN37-VREFO-R
LINE1-R
LINE1-L
MIC1-R
MIC1-L
CD-R
38
39
40
41
42
43
44
45
46
47
48
LDO-OUT
SURR-L
LDO-OUT2
SURR-OUT-L
JDREF
R14
20K, 1%
MIC1-L
R15 1k
CD-IN Header
C16
C17
C18
1u
1u
1u
J1
4
SURR-R
SURR-OUT-R
AVSS2
3
2
1
R16 1k
R17 1k
CD-GND
CD-L
ALC888S-VD
CEN
LFE
CEN
MIC2-R
LFE
MIC2-R
MIC2-L
LINE2-R
LINE2-L
Sense A
MIC2-L
SIDESURR-L
SIDESURR-R
SIDE-OUT-L
SIDE-OUT-R
EAPD/SPDIFI
SPDIFO1
LINE2-R
LINE2-L
R22
Sense A
5.1K,1%
10K,1%
20K,1%
FRONT-JD
LINE1-JD
MIC1-JD
R25
R26
R29
S/PDIF-IN
Split by DGND
39.2K,1%
SURR-JD
S/PDIF-OUT
+3.3VD
C28
1u
R34 47K
Ext. PCBEEP
C31 C29
0.1u 10u
+
C35
10u
C34
0.1u
R38
R39
22
4.7K
Azalia-RESET#
Azalia-SYNC
SPDIF-OUT2_HDMI
DMIC-CLK
R42
R48
x/0
0/x
+DVDD_Scalable
+3.3VD
R69 0/X
R47 0/X
R70 0/X
R52 0/X
Azalia-SDIN
Azalia-BCLK
GPIO0
GPIO1
R50 22
C37
10u
C40
0.1u
+
C39
22P
DMIC-DATA
Azalia-SDOUT
Figure 18. Filter Connection
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
78
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
AUDIO FRONT HEADER
MIC2-VREFO
D4
BAT54A/SOT
R20
R21
+3.3VD
4.7K
4.7K
R24
C20
C21
100u R25 75
100u R27 75
MIC2-L
MIC2-R
10K
CON10A
J1
1
3
5
7
9
2
4
6
8
10
PRESENCE#
GPI to South Bridge
C24
C27
100u R30 75
100u R32 75
LINE2-R
LINE2-L
Key
MIC2-JD
LINE2-JD
R38
R37
R41 R42 R43 R44
22K 22K 22K 22K
4.7K
4.7K
D5
BAT54A/SOT
LINE2-VREFO
HD Audio Front Panel I/O Module
PORT-E (LINE2) and PORT-F (MIC2) are front panel I/O
J2
FIO-PORT-F-L
1
3
5
7
9
2
4
6
8
10
FIO-PORT-F-R
FIO-PORT-E-R
FIO-SENSE
FIO-PRESENCE#
PORT-F-SENSE-RETURN
KEY
FIO-PORT-E-L
PORT-E-SENSE-RETURN
JACK 7
FIO-SENSE
PORT-E-SENSE-RETURN
CON10A
4
3
5
FIO-PORT-E-R
FIO-PORT-E-L
L18
L19
FERB
FERB
2
1
C54
C55
FIO-PORT-E (Port-E)
100P
100P
JACK 8
4
3
5
FIO-SENSE
PORT-F-SENSE-RETURN
FIO-PORT-F-R
FIO-PORT-F-L
L20
L21
FERB
FERB
2
1
C57
C58
100P
FIO-PORT-F (Port-F)
100P
Figure 19. Front Panel Header and Front Panel Module Connection
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
79
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
ANALOG I/O CONNECTOR
R70
R71
2.2K
2.2K
MIC1-VREFO-L
MIC1-VREFO-R
JACK 9
JACK 10
MIC1-JD
FERB
CEN-JD
4
3
5
4
3
5
C66 4.7u/X5R/0805/10V R72 75
C68 4.7u/X5R/0805/10V R74 75
L22
L24
C67
C69
10u R73 75
10u R75 75
L23
L25
FERB
FERB
MIC1-R
MIC1-L
LFE
FERB
CEN
2
1
2
1
C70 C71
100P 100P
R76 R77
22K 22K
C72 C73
100P 100P
MIC-IN (Port-B)
JACK 11
CENTER/LFE (Port-G)
JACK 12
LINE1-JD
FERB
SURR-JD
FERB
4
3
5
4
3
5
C74 4.7u/X5R/0805/10V R78 75
C76 4.7u/X5R/0805/10V R80 75
L26
L28
C75
C77
10u R79 75
10u R81 75
L27
L29
LINE1-R
LINE1-L
SURR-R
SURR-L
FERB
FERB
2
1
2
1
C78 C79
100P 100P
R82 R83
22K 22K
C80 C81
100P 100P
LINE-IN (Port-C)
SURROUND (Port-A)
JACK 13
JACK 14
FRONT-JD
FERB
SIDESURR-JD
FERB
4
3
5
4
3
5
C82
C84
100u
100u
R84 75
R86 75
L30
L32
C83
C85
10u R85 75
10u R87 75
L31
L33
FRONT-R
FRONT-L
SIDESURR-R
SIDESURR-L
FERB
FERB
2
1
2
1
C86 C87
100P 100P
R88 R89
C88 C89
100P 100P
R90 R91
FRONT-OUT (Port-D)
SIDESURR (Port-H)
22K
22K
22K
22K
Figure 20. Jack Connection at Rear Panel
S/PDIF module option 1: Optical
S/PDIF option 2: RCA only
S/PDIF option 3: Optical
&
RCA
U7
4
TOTX178
5
U8
4
TORX178S
U9
4
TOTX178
S/PDIF-OUT
C90
Transmitter
S/PDIF-OUT
1
R92 100
Receiver
Transmitter
5
5
J8
0.01u
C91
R93
220
RCA
100P
R94 10
S/PDIF-OUT
C92
0.1u
L34
47uH
C93
0.1u
C94
0.1u
+5VD
+5VD
+5VD
U10 TORX178S
S/PDIF-IN
S/PDIF-IN
R
S/PDIF-OUT
Receiver
C95
S/PDIF-IN
1
470p R95 10
C97
4
5
C96
S/PDIF-IN
S/PDIF-OUT
S
470p R96 10
1
R97 100
C98
100P
R98
75
J5A2
RCA
J9
RCA
J10
RCA
0.01u
C100
100P
R99
75
C101
100P
R100
220
C99
S/PDIF-IN
470p
R101 10
L35
47uH
C102
0.1u
+5VD
Figure 21. SPDIF Input/Output Connection
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
80
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
11. Application Supplements
11.1. Standby Mode
In standby mode the ALC888S-VD turns on DC bias on all analog input and output ports
(NID=14h~1Bh). This is a special application to avoid ‘Pop’ noise while the system is in power on and
power off transition stages.
Table 89 shows the DC bias state when Standby mode is enabled.
Table 89. Standby Mode
+3.3V on DVDD (Pin-1)
No (<2.0V)
+5VA on AVDD
Operation Mode
Shut Down
Standby Mode
Normal
No
Yes
No
No (<2.0V)
Yes (>2.0V)
Yes (>2.0V)
Yes
Normal
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
81
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
11.2. Digital Microphone Implementation
This section describes the ALC888S-VD digital microphone implementation. There is one Clock output
pin and 1 Data input pin in the ALC888S-VD. The ALC888S-VD provides the clock signal to the digital
microphone. When the digital microphone receives the external sound input, it converts the analog signals
to digital in a 1-bit format. The 1-bit data is delivered to the codec though the data input pin. The Digital
Filter in the audio codec converts the 1-bit data stream into Pulse Code Modulation (PCM) data. The
PCM data is sent to the HDA controller through the HDA link.
Figure 22. Digital Microphone Implementation
The ALC888S-VD supports a two-wire interface for the digital microphone and operates in
single-channel (mono type) or stereo-channel mode. One pin is clock output to the digital microphone,
and the other is a serial pin. The default clock output is 2.048MHz.
The ALC888S-VD uses one data pin to support stereo inputs from various digital microphones and
microphone module. Popular digital microphones provided from Fortemedia, Akustica, Knowles, and
Hosiden are supported. Please contact Realtek and your digital microphone vendor to get the best
compatibility between the ALC888S-VD and various digital microphones.
Figure 23. Stereo Digital Microphone Connection
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
82
Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
12. Mechanical Dimensions
L
L1
SYMBOL
MILLIMETER
INCH
TYP MAX
MIN TYP MAX MIN
TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING,
FOOTPRINT 2.0mm
A
A1
A2
c
-
-
-
1.60
0.15
-
-
-
0.063
0.006
0.05
0.002
1.35 1.40 1.45
0.053 0.055 0.057
LEADFRAME MATERIAL
0.09
-
0.20
0.004
-
0.008
APPROVE
CHECK
DOC. NO.
VERSION 02
D
9.00 BSC
7.00 BSC
5.50
0.354 BSC
0.276 BSC
0.217
D1
D2
E
DWG NO. PKGC-065
DATE
9.00 BSC
7.00BSC
5.50
0.354 BSC
0.276 BSC
0.217
REALTEK SEMICONDUCTOR CORP.
E1
E2
b
0.17 0.20
0.50 BSC
3.5o
0.45 0.60
1.00
0.27 0.007 0.008
0.0196 BSC
3.5o
0.011
7o
e
TH
L
0o
7o
0o
0.75 0.018 0.0236 0.030
0.0393
L1
-
-
-
-
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
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Track ID: JATR-2265-11 Rev. 1.2
ALC888S-VD
Datasheet
13. Ordering Information
Table 90. Ordering Information
Part Number
Description
Status
ALC888S-VD2-GR LQFP-48 with ‘Green’ Package
Production
Note: See page 7 for ‘Green’package and version identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com
7.1+2 Channel HD Audio Codec with Two Independent
SPDIF Outputs
84
Track ID: JATR-2265-11 Rev. 1.2
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