RTL8101L-GR [REALTEK]
Micro Peripheral IC;
| 型号： | RTL8101L-GR |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | Micro Peripheral IC LTE |
| 文件： | 总96页 (文件大小：928K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RTL8101L
RTL8101L-LF
RTL8101L-GR
SINGLE-CHIP FAST ETHERNET CONTROLLER AND
MC’97 CONTROLLER WITH POWER MANAGEMENT
DATASHEET
Rev. 1.5
20 April 2006
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-557-6047
www.realtek.com.tw
RTL8101L
Datasheet
COPYRIGHT
©2006 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document provides detailed user guidelines to achieve the best performance when implementing a
2-layer board PC design with the RTL8101L Single-Chip Fast Ethernet Controller and MC’97 Controller
with Power Management control.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
Release Date
Summary
1.5
2006/04/20
First official release.
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Datasheet
Table of Contents
1. GENERAL DESCRIPTION................................................................................................................................................1
2. FEATURES...........................................................................................................................................................................2
2.1.
2.2.
ETHERNET CONTROLLER FEATURES ...............................................................................................................................2
MC’97 CONTROLLER FEATURES.....................................................................................................................................3
3. SYSTEM APPLICATIONS ................................................................................................................................................3
4. BLOCK DIAGRAM.............................................................................................................................................................4
5. PIN ASSIGNMENTS...........................................................................................................................................................5
5.1.
6. PIN DESCRIPTIONS ..........................................................................................................................................................6
6.1. POWER MANAGEMENT/ISOLATION INTERFACE...............................................................................................................6
PACKAGE IDENTIFICATION..............................................................................................................................................5
6.2. PCI INTERFACE ...............................................................................................................................................................7
6.3. EEPROM INTERFACE .....................................................................................................................................................8
6.4. POWER PINS ....................................................................................................................................................................9
6.5. LED INTERFACE..............................................................................................................................................................9
6.6.
6.7. AC-LINK PINS...............................................................................................................................................................10
6.8. TEST AND OTHER PINS ..................................................................................................................................................10
ATTACHMENT UNIT INTERFACE......................................................................................................................................9
7. ETHERNET CONTROLLER REGISTER DESCRIPTIONS ......................................................................................11
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
RECEIVE STATUS REGISTER IN RX PACKET HEADER....................................................................................................14
TRANSMIT STATUS REGISTER (TSD0-3)(OFFSET 0010H-001FH, R/W)........................................................................14
ERSR: EARLY RX STATUS REGISTER (OFFSET 0036H, R)............................................................................................16
COMMAND REGISTER (OFFSET 0037H, R/W)................................................................................................................17
INTERRUPT MASK REGISTER (OFFSET 003CH-003DH, R/W)........................................................................................18
INTERRUPT STATUS REGISTER (OFFSET 003EH-003FH, R/W) ......................................................................................19
TRANSMIT CONFIGURATION REGISTER (OFFSET 0040H-0043H, R/W)..........................................................................20
RECEIVE CONFIGURATION REGISTER (OFFSET 0044H-0047H, R/W)............................................................................22
9346CR: 93C46 COMMAND REGISTER (OFFSET 0050H, R/W).....................................................................................25
CONFIG 0: CONFIGURATION REGISTER 0 (OFFSET 0051H, R/W)............................................................................26
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7.11.
7.12.
7.13.
7.14.
7.15.
7.16.
7.17.
7.18.
7.19.
7.20.
7.21.
7.22.
7.23.
7.24.
7.25.
7.26.
7.27.
7.28.
CONFIG 1: CONFIGURATION REGISTER 1 (OFFSET 0052H, R/W)............................................................................27
MEDIA STATUS REGISTER (OFFSET 0058H, R/W) .....................................................................................................28
CONFIG 3: CONFIGURATION REGISTER3 (OFFSET 0059H, R/W).............................................................................29
CONFIG 4: CONFIGURATION REGISTER4 (OFFSET 005AH, R/W)............................................................................30
MULTIPLE INTERRUPT SELECT REGISTER (OFFSET 005CH-005DH, R/W)................................................................31
PCI REVISION ID (OFFSET 005EH, R) .......................................................................................................................31
TRANSMIT STATUS OF ALL DESCRIPTORS (TSAD) REGISTER (OFFSET 0060H-0061H, R/W)...................................32
BASIC MODE CONTROL REGISTER (OFFSET 0062H-0063H, R/W).............................................................................33
BASIC MODE STATUS REGISTER (OFFSET 0064H-0065H, R).....................................................................................34
AUTO-NEGOTIATION ADVERTISEMENT REGISTER (OFFSET 0066H-0067H, R/W) ....................................................35
AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (OFFSET 0068H-0069H, R) ..............................................36
AUTO-NEGOTIATION EXPANSION REGISTER (OFFSET 006AH-006BH, R) ................................................................37
DISCONNECT COUNTER (OFFSET 006CH-006DH, R).................................................................................................37
FALSE CARRIER SENSE COUNTER (OFFSET 006EH-006FH, R) ..................................................................................37
NWAY TEST REGISTER (OFFSET 0070H-0071H, R/W)..............................................................................................38
RX_ER COUNTER (OFFSET 0072H-0073H, R) ..........................................................................................................38
CS CONFIGURATION REGISTER (OFFSET 0074H-0075H, R/W)..................................................................................38
CONFIG5: CONFIGURATION REGISTER 5 (OFFSET 00D8H, R/W)...............................................................................39
8. MC’97CONTROLLERREGISTERANDDESCRIPTORDESCRIPTIONS.................................................................................40
8.1.
STARTING DESCRIPTOR INDEX FOR LINE-OUT (OFFSET 0000H, R/W).........................................................................40
CURRENT DESCRIPTOR INDEX FOR LINE-OUT (OFFSET 0001H, RO) ...........................................................................40
LAST DESCRIPTOR INDEX FOR LINE-OUT (OFFSET 0002H, R/W) ................................................................................41
LINE-OUT DMA STATUS REGISTER (OFFSET 0003H, RO)...........................................................................................41
LINE-OUT DMA CONTROL REGISTER (OFFSET 0004H-0005H, R/W)..........................................................................41
RESIDUAL SAMPLES COUNT IN CURRENT LINE-OUT DESCRIPTOR REGISTER (OFFSET 0006H - 0007H, R/W).............42
LINE-OUT DESCRIPTOR BASE ADDRESS REGISTER (OFFSET 000CH – 000FH, R/W)...................................................42
STARTING DESCRIPTOR INDEX FOR LINE-IN (OFFSET 0010H, R/W) ............................................................................42
CURRENT DESCRIPTOR INDEX FOR LINE-IN (OFFSET 0011H, RO) ...............................................................................42
LAST DESCRIPTOR INDEX FOR LINE-IN (OFFSET 0012H, R/W) ................................................................................43
LINE-IN DMA STATUS REGISTER (OFFSET 0013H, RO) ..........................................................................................43
LINE-IN DMA CONTROL REGISTER (OFFSET 0014H-0015H, R/W)..........................................................................43
RESIDUAL SAMPLES COUNT IN CURRENT LINE-IN DESCRIPTOR REGISTER (OFFSET 0016H - 0017H, R/W).............44
LINE-IN DESCRIPTOR BASE ADDRESS REGISTER (OFFSET 001CH – 001FH, R/W)....................................................44
MC’97-LINK CONTROL REGISTER (OFFSET 0020H-0021H, R/W).............................................................................44
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
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8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.23.
8.24.
8.25.
8.26.
MC’97-LINK STATUS AND INDEX REGISTER (OFFSET 0022H-0023H, R/W).............................................................45
AC-LINK DATA PORT (OFFSET 0024H - 0025H, R/W) ..............................................................................................46
GPIO CONTROL TO MC’97 (OFFSET 0026H - 0027H, R/W)......................................................................................47
REAL TIME GPIO INPUT DATA FROM MC’97 (OFFSET 0028H - 0029H, RO) ...........................................................47
INTERRUPT STATUS REGISTER (OFFSET 002AH-002BH, R/W) .................................................................................47
PCI GPIO SETUP REGISTER (OFFSET 002CH-002DH, R/W) .....................................................................................49
PCI GPIO STATUS REGISTER (OFFSET 002EH-002FH, R/W)....................................................................................50
EEPROM (93C46) COMMAND REGISTER (OFFSET 0030H, R/W) .............................................................................51
CONTEXT FOR LINE-OUT DESCRIPTOR (OFFSET 0000H-00FFH)...............................................................................52
CONTEXT FOR LINE-IN DESCRIPTOR (OFFSET 0000H-00FFH) ..................................................................................52
DESCRIPTOR DEFINITION ..........................................................................................................................................53
9. EEPROM (93C46) CONTENTS.......................................................................................................................................54
9.1.
9.2.
EEPROM RELATED ETHERNET MAC REGISTERS ........................................................................................................56
EEPROM RELATED POWER MANAGEMENT REGISTERS...............................................................................................56
10.
PCI CONFIGURATION SPACE REGISTERS..........................................................................................................57
10.1.
10.2.
10.3.
10.4.
10.5.
PCI CONFIGURATION SPACE REGISTERS...................................................................................................................57
PCI CONFIGURATION SPACE FUNCTIONS ..................................................................................................................59
PCI CONFIGURATION SPACE STATUS........................................................................................................................60
DEFAULT VALUES AFTER POWER-ON (RSTB ASSERTED) ........................................................................................65
PCI POWER MANAGEMENT FUNCTIONS....................................................................................................................66
10.5.1. Power Down Mode...............................................................................................................................................66
10.6.
11.
11.1.
VPD (VITAL PRODUCT DATA)..................................................................................................................................70
FUNCTIONAL DESCRIPTION...................................................................................................................................71
TRANSMIT OPERATION..............................................................................................................................................71
RECEIVE OPERATION.................................................................................................................................................71
WANDER COMPENSATION.........................................................................................................................................71
SIGNAL DETECT ........................................................................................................................................................71
LINE QUALITY MONITOR ..........................................................................................................................................72
CLOCK RECOVERY MODULE .....................................................................................................................................72
LOOPBACK OPERATION.............................................................................................................................................72
TX ENCAPSULATION..................................................................................................................................................72
COLLISION.................................................................................................................................................................72
11.2.
11.3.
11.4.
11.5.
11.6.
11.7.
11.8.
11.9.
11.10. RX DECAPSULATION .................................................................................................................................................73
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11.11. FLOW CONTROL ........................................................................................................................................................73
11.11.1.
11.11.2.
Control Frame Transmission............................................................................................................................73
Control Frame Reception.................................................................................................................................73
11.12. LED FUNCTIONS .......................................................................................................................................................74
11.12.1.
11.12.2.
11.12.3.
11.12.4.
10/100Mbps Link Monitor................................................................................................................................74
LED_RX............................................................................................................................................................74
LED_TX............................................................................................................................................................75
LED_TX+LED_RX...........................................................................................................................................75
12.
13.
APPLICATION DIAGRAM .........................................................................................................................................76
CHARACTERISTICS ...................................................................................................................................................77
13.1.
13.2.
THERMAL CHARACTERISTICS....................................................................................................................................77
DC CHARACTERISTICS ..............................................................................................................................................77
13.2.1. Supply Voltage (Vcc = 3.0V min. to 3.6V max.)...................................................................................................77
13.3.
AC CHARACTERISTICS ..............................................................................................................................................78
13.3.1. PCI Bus Operation Timing...................................................................................................................................78
14.
15.
MECHANICAL DIMENSIONS ...................................................................................................................................85
ORDERING INFORMATION .....................................................................................................................................86
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List of Tables
TABLE 1. POWER MANAGEMENT/ISOLATION INTERFACE ..............................................................................................................6
TABLE 2. PCI INTERFACE ..............................................................................................................................................................7
TABLE 3. EEPROM INTERFACE ....................................................................................................................................................8
TABLE 4. POWER PINS ...................................................................................................................................................................9
TABLE 5. LED INTERFACE.............................................................................................................................................................9
TABLE 6. ATTACHMENT UNIT INTERFACE.....................................................................................................................................9
TABLE 7. AC-LINK PINS..............................................................................................................................................................10
TABLE 8. TEST AND OTHER PINS.................................................................................................................................................10
TABLE 9. REGISTER DESCRIPTIONS .............................................................................................................................................11
TABLE 10. RECEIVE STATUS REGISTER IN RX PACKET HEADER ..................................................................................................14
TABLE 11. TRANSMIT STATUS REGISTER......................................................................................................................................14
TABLE 12. ERSR: EARLY RX STATUS REGISTER .........................................................................................................................16
TABLE 13. COMMAND REGISTER ..................................................................................................................................................17
TABLE 14. INTERRUPT MASK REGISTER .......................................................................................................................................18
TABLE 15. INTERRUPT STATUS REGISTER.....................................................................................................................................19
TABLE 16. TRANSMIT CONFIGURATION REGISTER........................................................................................................................20
TABLE 17. RECEIVE CONFIGURATION REGISTER...........................................................................................................................22
TABLE 18. 9346CR: 93C46 COMMAND REGISTER........................................................................................................................25
TABLE 19. CONFIG 0: CONFIGURATION REGISTER 0...................................................................................................................26
TABLE 20. CONFIG 1: CONFIGURATION REGISTER 1...................................................................................................................27
TABLE 21. MEDIA STATUS REGISTER............................................................................................................................................28
TABLE 22. CONFIG 3: CONFIGURATION REGISTER3....................................................................................................................29
TABLE 23. CONFIG 4: CONFIGURATION REGISTER4....................................................................................................................30
TABLE 24. MULTIPLE INTERRUPT SELECT REGISTER ....................................................................................................................31
TABLE 25. PCI REVISION ID.........................................................................................................................................................31
TABLE 26. TRANSMIT STATUS OF ALL DESCRIPTORS (TSAD) REGISTER .....................................................................................32
TABLE 27. BASIC MODE CONTROL REGISTER...............................................................................................................................33
TABLE 28. BASIC MODE STATUS REGISTER..................................................................................................................................34
TABLE 29. AUTO-NEGOTIATION ADVERTISEMENT REGISTER.......................................................................................................35
TABLE 30. AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER ............................................................................................36
TABLE 31. AUTO-NEGOTIATION EXPANSION REGISTER................................................................................................................37
TABLE 32. DISCONNECT COUNTER ...............................................................................................................................................37
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TABLE 33. FALSE CARRIER SENSE COUNTER................................................................................................................................37
TABLE 34. NWAY TEST REGISTER................................................................................................................................................38
TABLE 35. RX_ER COUNTER........................................................................................................................................................38
TABLE 36. CS CONFIGURATION REGISTER....................................................................................................................................38
TABLE 37. CONFIG5. CONFIGURATION REGISTER 5 ......................................................................................................................39
TABLE 38. MC’97 REGISTERS.......................................................................................................................................................40
TABLE 39. STARTING DESCRIPTOR INDEX FOR LINE-OUT ...........................................................................................................40
TABLE 40. CURRENT DESCRIPTOR INDEX FOR LINE-OUT ............................................................................................................40
TABLE 41. LAST DESCRIPTOR INDEX FOR LINE-OUT ...................................................................................................................41
TABLE 42. LINE-OUT DMA STATUS REGISTER ...........................................................................................................................41
TABLE 43. LINE-OUT DMA CONTROL REGISTER ........................................................................................................................41
TABLE 44. RESIDUAL SAMPLES COUNT IN CURRENT LINE-OUT DESCRIPTOR REGISTER.............................................................42
TABLE 45. LINE-OUT DESCRIPTOR BASE ADDRESS REGISTER ....................................................................................................42
TABLE 46. STARTING DESCRIPTOR INDEX FOR LINE-IN...............................................................................................................42
TABLE 47. CURRENT DESCRIPTOR INDEX FOR LINE-IN................................................................................................................42
TABLE 48. LAST DESCRIPTOR INDEX FOR LINE-IN.......................................................................................................................43
TABLE 49. LINE-IN DMA STATUS REGISTER...............................................................................................................................43
TABLE 50. LINE-IN DMA CONTROL REGISTER............................................................................................................................43
TABLE 51. RESIDUAL SAMPLES COUNT IN CURRENT LINE-IN DESCRIPTOR REGISTER ................................................................44
TABLE 52. LINE-IN DESCRIPTOR BASE ADDRESS REGISTER .........................................................................................................44
TABLE 53. MC’97-LINK CONTROL REGISTER...............................................................................................................................44
TABLE 54. MC’97-LINK STATUS AND INDEX REGISTER ...............................................................................................................45
TABLE 55. AC-LINK DATA PORT..................................................................................................................................................46
TABLE 56. GPIO CONTROL TO MC’97..........................................................................................................................................47
TABLE 57. REAL TIME GPIO INPUT DATA FROM MC’97 .............................................................................................................47
TABLE 58. INTERRUPT STATUS REGISTER.....................................................................................................................................47
TABLE 59. PCI GPIO SETUP REGISTER.........................................................................................................................................49
TABLE 60. PCI GPIO STATUS REGISTER ......................................................................................................................................50
TABLE 61. EEPROM (93C46) COMMAND REGISTER....................................................................................................................51
TABLE 62. CONTEXT FOR LINE-OUT DESCRIPTOR........................................................................................................................52
TABLE 63. CONTEXT FOR LINE-IN DESCRIPTOR ...........................................................................................................................52
TABLE 64. EEPROM (93C46) CONTENTS ....................................................................................................................................54
TABLE 65. EEPROM RELATED ETHERNET MAC REGISTERS.......................................................................................................56
TABLE 66. EEPROM RELATED POWER MANAGEMENT REGISTERS .............................................................................................56
TABLE 67. PCI CONFIGURATION SPACE FUNCTIONS.....................................................................................................................59
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TABLE 68. PCI CONFIGURATION SPACE STATUS ..........................................................................................................................60
TABLE 69. INPUT OUTPUT ADDRESS REGISTER.............................................................................................................................62
TABLE 70. BASE MEMORY ADDRESS FOR MEMORY ACCESSES ....................................................................................................62
TABLE 71. BASE MEMORY ADDRESS FOR MEMORY ACCESSES ....................................................................................................63
TABLE 72. DEFAULT VALUES AFTER POWER-ON (RSTB ASSERTED)...........................................................................................65
TABLE 73. THERMAL CHARACTERISTICS ......................................................................................................................................77
TABLE 74. SUPPLY VOLTAGE (3.0V MIN. TO 3.6V MAX.)..............................................................................................................77
TABLE 75. ORDERING INFORMATION ............................................................................................................................................86
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List of Figures
FIGURE 1. BLOCK DIAGRAM..........................................................................................................................................................4
FIGURE 2. PIN ASSIGNMENTS ........................................................................................................................................................5
FIGURE 3. LED_RX ....................................................................................................................................................................74
FIGURE 4. LED_TX.....................................................................................................................................................................75
FIGURE 5. LED_TX+LED_RX ...................................................................................................................................................75
FIGURE 6. APPLICATION DIAGRAM..............................................................................................................................................76
FIGURE 7. TARGET READ.............................................................................................................................................................78
FIGURE 8. TARGET WRITE ...........................................................................................................................................................79
FIGURE 9. CONFIGURATION READ ...............................................................................................................................................79
FIGURE 10. CONFIGURATION WRITE .............................................................................................................................................80
FIGURE 11. BUS ARBITRATION......................................................................................................................................................80
FIGURE 12. MEMORY READ ..........................................................................................................................................................81
FIGURE 13. MEMORY WRITE.........................................................................................................................................................81
FIGURE 14. TARGET INITIATED TERMINATION - RETRY ................................................................................................................82
FIGURE 15. TARGET INITIATED TERMINATION - DISCONNECT ......................................................................................................82
FIGURE 16. TARGET INITIATED TERMINATION - ABORT................................................................................................................83
FIGURE 17. MASTER INITIATED TERMINATION – ABORT ..............................................................................................................83
FIGURE 18. PARITY OPERATION - ONE EXAMPLE..........................................................................................................................84
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1. General Description
The Realtek RTL8101L is a highly integrated and cost-effective single-chip Fast Ethernet controller that
provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u
100Base-TX specifications and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced
Configuration Power management Interface (ACPI), PCI power management for modern operating
systems that are capable of Operating System Directed Power Management (OSPM) to achieve the most
efficient power management possible. The RTL8101L no longer supports CardBus mode (the RTL8139C
does).
In addition to the ACPI feature, the RTL8101L supports remote wake-up (including AMD Magic Packet,
LinkChg, and Microsoft® wake-up frame) in both ACPI and APM environments. The RTL8101L is
capable of performing an internal reset through the application of auxiliary power. When auxiliary power is
applied and the main power remains off, the RTL8101L is ready and waiting for a Magic Packet or Link
Change to wake the system up. Also, the LWAKE pin provides 4 different output signals including active
high, active low, positive pulse, and negative pulse. The versatility of the RTL8101L LWAKE pin provides
motherboards with Wake-On-LAN (WOL) functionality.
The RTL8101L also supports Analog Auto-Power-down, that is, the analog part of the RTL8101L can be
shut down temporarily according to user requirements or when the RTL8101L is in a power down state with
the wakeup function disabled. In addition, when the analog part is shut down and the IsolateB pin is low
(i.e. the main power is off), then both the analog and digital parts stop functioning and the power
consumption of the RTL8101L is negligible. The RTL8101L also supports an auxiliary power auto-detect
function, and will auto-configure related bits of their own PCI power management registers in PCI
configuration space.
PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies
hardware (i.e., the OEM brand name of the RTL8101L LAN card). The information may consist of part
number, serial number, and other detailed information.
To provide cost down support, the RTL8101L is capable of using a 25MHz crystal or OSC as its internal
clock source.
The RTL8101L keeps network maintenance costs low and eliminates usage barriers. It is the easiest way to
upgrade a network from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps
bandwidth possible at no additional cost. To improve compatibility with other brands’ products, the
RTL8101L is also capable of receiving packets with InterFrameGap no less than 40 Bit-Time. The
RTL8101L is highly integrated and requires no ‘glue’ logic or external memory.
The RTL8101L includes a PCI and Expansion Memory Share Interface (Realtek patent) for a boot ROM
and can be used in diskless workstations, providing maximum network security and ease of management.
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2. Features
2.1. Ethernet Controller Features
100 pin LQFP
Supports auxiliary power-on internal
Integrated Fast Ethernet MAC, Physical
chip, and transceiver in one chip
10Mbps and 100Mbps operation
Supports 10Mbps and 100Mbps N-way
Auto-negotiation
reset, for remote wake-up when main
power remains off
Supports auxiliary power auto-detect, and
sets the related capability of power
management registers in PCI
configuration space
PCI local bus single-chip Fast Ethernet
controller
Includes a programmable PCI burst size
and early Tx/Rx threshold
Complies with PCI Revision 2.2
Supports PCI clock 16.75MHz-40MHz
Supports PCI target fast back-to-back
transaction
Supports a 32-bit general-purpose timer
with the external PCI clock as clock
source to generate a timer-interrupt
Contains two large (2Kbyte) independent
receive and transmit FIFOs
Provides PCI bus master data transfers
and PCI memory space or I/O space
mapped data transfers of RTL8101L's
operational registers
Advanced power saving mode when
LAN function or wakeup function is not
used
Supports PCI VPD (Vital Product Data)
Supports ACPI, PCI power management
Supports 25MHz crystal or 25MHz OSC
as the internal clock source. The
frequency deviation of either crystal or
OSC must be within 50 PPM.
Uses 93C46 (64*16-bit EEPROM) to
store resource configuration, ID
parameter, and VPD data
Supports LED pins for various network
activity indications
Complies with to PC99/PC2001 standard
Supports Wake-On-LAN function and
remote wake-up (Magic Packet, LinkChg
and Microsoft® wake-up frame)
Supports 4 Wake-On-LAN (WOL)
signals (active high, active low, positive
pulse, and negative pulse)
Supports loopback capability
Half/Full duplex capability
Supports Full Duplex Flow Control
(IEEE 802.3x)
3.3V power supply, 3.3V and 5V I/O
tolerance
Interface for 128K byte (max) Boot ROM
for both EEPROM and Flash Memory
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2.2. MC’97 Controller Features
MC’97 compatible digital controller chip
PCI local bus single-chip Fast Ethernet
controller
Supports 16-bit modem line (LINE1)
Full-duplex operation for simultaneous
LINE1 transactions
32-bit PCI bus master and PCI v 2.2
compliant
Low latency GPIO updated
8 double-WORD (16 samples) FIFO
depth for each bus master of
LINE1-OUT/IN
PCI Bus Power Management Interface
Specification v 1.1 compliant
High performance bus master DMA for
data transfer
3.3V power supply, 3.3V and 5V I/O
tolerance
AC’97 v 2.2 compliant
3. System Applications
Ethernet Network Interface Controller
Lan On Motherboard
Embedded System
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4. Block Diagram
MAC
EEPROM
Interface
LED Driver
Power Control Logic
Early Interrupt
Threshold
Register
Interrupt
Control
Logic
Early Interrupt
Control Logic
PCI
Interface
Transmit/
Receive
Logic
FIFO
Control
Logic
FIFO
MII
Interface
Interface
PHY
100M
5B 4B
Decoder
Data
Alignment
RXD
RXC 25M
Descrambler
10/100
half/full
Switch
Logic
MII
Interface
TXD
TXC 25M
4B 5B
Encoder
Scrambler
10/100M Auto-negotiation
Control Logic
Link Pulse
10M
TXC10
TXD10
Manchester Coded
Waveform
10M Output Waveform
Shaping
RXC10
RXD10
Data Recovery
Receive Low Pass Filter
Transceiver
TD+
TXC 25M
TXD
3 Level
Driver
TXO+
TXO -
Parrallel
to Serial
Variable Current
Baseline
Wander
Correction
Peak
Detect
RXIN+
RXIN-
MLT-3
to NRZI
3 Level
Comparator
Adaptive
Equalizer
ck
Data
RXC 25M
RXD
Serial to
Parrallel
Master
PPL
Slave
PLL
Control
Voltage
25M
Figure 1. Block Diagram
Single-Chip Fast Ethernet Controller and MC’97
Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
5. Pin Assignments
Figure 2. Pin Assignments
5.1. Package Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2. Lead (Pb)-Free package is
indicated by an ‘L’. The version is indicated by the letter shown in the location marked ‘V’.
Single-Chip Fast Ethernet Controller and MC’97
Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
6. Pin Descriptions
The following signal type codes are used in the tables:
I: Input.
O: Output.
T/S: Tri-State bi-directional input/output pin.
S/T/S: Sustained Tri-State.
O/D: Open Drain.
Note that some pins have multiple functions. See Figure 2, on page 5, for a graphical representation.
6.1. Power Management/Isolation Interface
Table 1. Power Management/Isolation Interface
Symbol
PMEB
Type
O/D
Pin No
57
Description
Power Management Event.
(PME#)
Open drain, active low. Used by the RTL8101L to request a change in
its current power management state and/or to indicate that a power
management event has occurred.
I
74
64
ISOLATEB
(ISOLATE#)
Isolate Pin: Active low.
Isolates the RTL8101L from the PCI bus. The RTL8101L does not
drive its PCI outputs (excluding PME#) and does not sample its PCI
input (including RST# and PCICLK) as long as the Isolate pin is
asserted.
O
LWAKE
LAN WAKE-UP Signal.
Signals to the motherboard that it should execute the wake-up process.
The motherboard must support Wake-On-LAN (WOL). There are 4
output choices, active high, active low, positive pulse, and negative
pulse, that may be asserted from the LWAKE pin. See the LWACT bit
in Table 20. CONFIG 1: Configuration Register 1, page 27, for the
setting of this output signal. The default output is an active high
signal.
When a PME event is received, LWAKE and PMEB assert at the same
time if LWPME (bit4, CONFIG4) is set to 0. If LWPME is set to 1,
LWAKE asserts only when PMEB asserts and ISOLATEB is low.
This pin is a 3.3V signaling output pin.
Single-Chip Fast Ethernet Controller and MC’97
Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
6.2. PCI Interface
Table 2. PCI Interface
Symbol
Type
Pin No
Description
T/S
85-87, 89, 91-93, 96,
8-15, 28-30, 32-36, 39-43,
45-47
AD31-0
PCI address and data multiplexed pins. AD31-24 are shared with
BootROM data pins, while AD16-0 are shared with BootROM
address pins.
T/S
I
84, 17, 27, 38
97
C/BE3-0
CLK
PCI bus command and byte enables multiplexed pins.
Clock: This PCI Bus clock provides timing for all transactions and bus
phases, and is input to PCI devices. The rising edge defines the start of
each phase. The clock frequency ranges from 0 to 33MHz.
S/T/S
S/T/S
21
18
DEVSELB
FRAMEB
Device select: As a bus master, the RTL8101L samples this signal to
insure that a PCI target recognizes the destination address for the data
transfer. As a target, the RTL8101L asserts this signal low when it
recognizes its target address after FRAMEB is asserted.
Cycle frame: As a bus master, this pin indicates the beginning and
duration of an access. FRAMEB is asserted low to indicate the start of
a bus transaction. While FRAMEB is asserted, data transfer continues.
When FRAMEB is deasserted, the transaction is in the final data
phase.
As a target, the device monitors this signal before decoding the
address to check if the current transaction is addressed to it.
I
82
GNTB
Grant: This signal is asserted low to indicate to the RTL8101L that the
central arbiter has granted ownership of the bus to the RTL8101L.
This input is used when the RTL8101L is acting as a bus master.
T/S
I
83
98
80
REQB
IDSEL
INTAB
Request: The RTL8101L will assert this signal low to request the
ownership of the bus from the central arbiter.
Initialization device select: This pin allows the RTL8101L to identify
when configuration read/write transactions are intended for it.
O/D
INTAB: Used to request an interrupt. It is asserted low when an
interrupt condition occurs, as defined by the Interrupt Status, Interrupt
Mask and Interrupt Enable registers.
S/T/S
19
IRDYB
Initiator ready: This indicates the initiating agent’s ability to complete
the current data phase of the transaction.
As a bus master, this signal will be asserted low when the RTL8101L is
ready to complete the current data phase transaction. This signal is used
in conjunction with the TRDYB signal. Data transaction takes place at
the rising edge of CLK when both IRDYB and TRDYB are asserted
low. As a target, this signal indicates that the master has put data on the
bus.
S/T/S
20
TRDYB
Target ready: This indicates the target agent’s ability to complete the
current phase of the transaction.
As a bus master, this signal indicates that the target is ready for the
data during write operations and with the data during read operations.
As a target, this signal will be asserted low when the (slave) device is
ready to complete the current data phase transaction. This signal is
used in conjunction with the IRDYB signal. Data transaction takes
place at the rising edge of CLK when both IRDYB and TRDYB are
asserted low.
Single-Chip Fast Ethernet Controller and MC’97
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Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
Symbol
Type
Pin No
Description
T/S
24
PAR
Parity: This signal indicates even parity across AD31-0 and C/BE3-0
including the PAR pin. As a master, PAR is asserted during address
and write data phases. As a target, PAR is asserted during read data
phases.
S/T/S
25
PERRB
Parity Error: When the RTL8101L is the bus master and a parity error
is detected, the RTL8101L asserts both SERR bit in ISR and
Configuration Space command bit 8 (SERRB enable). Next, it
completes the current data burst transaction, then stops operation and
resets itself. After the host clears the system error, the RTL8101L
continues its operation.
When the RTL8101L is the bus target and a parity error is detected, the
RTL8101L asserts this PERRB pin low.
O/D
26
SERRB
System Error: If an address parity error is detected and Configuration
Space Status register bit 15 (detected parity error) is enabled,
RTL8101L asserts both SERRB pin low and bit 14 of Status register in
Configuration Space.
S/T/S
I
23
81
STOPB
RSTB
Stop: Indicates the current target is requesting the master to stop the
current transaction.
Reset: When RSTB is asserted low, the RTL8101L performs an
internal system hardware reset. RSTB must be held for a minimum of
120 ns.
6.3. EEPROM Interface
Table 3. EEPROM Interface
Symbol
Type
Pin No
Description
I/O
53
AUX/EEDI
1. Aux. Power Detect: This pin is used to notify the RTL8101L of the
existence of Aux. power during initial power-on or a PCI reset.
This pin should be pulled high to the Aux. power via a resistor to
detect the Aux. power. Doing so, will enable wakeup support from
ACPI D3 cold or APM power-down. If this pin is not pulled high, the
RTL8101L assumes that no Aux. power exists.
O
O, I
O
54
52
55
EESK
EEDO
EECS
The MA2-0 pins are switched to EESK, EEDI, EEDO in 93C46
programming or auto-load mode.
The MA2-0 pins are switched to EESK, EEDI, EEDO in 93C46
programming or auto-load mode.
EEPROM chip select.
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Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
6.4. Power Pins
Table 4. Power Pins
Description
Symbol
VDD
Type
Pin No
6, 22, 37, 49, 90, 95
59, 70, 75
P
P
P
P
P
p
+3.3V (Digital)
+3.3V (Analog)
+2.5V (Digital)
+2.5V (Analog)
Digital Ground
Analog Ground
AVDD
VDD25
AVDD25
DGND
AGND
48, 94
58
2, 16, 31, 44, 88
62, 66, 73
6.5. LED Interface
Table 5. LED Interface
Symbol
Type
Pin No
Description
LED0, 1, 2
O
78, 77, 76
LED Pins
LEDS1-0
00
01
TX/RX
10
TX
11
TX
TX/RX
LINK100
LINK10
LED0
LED1
LED2
LINK10/100 LINK10/100
FULL RX
LINK100
LINK10
During power down mode, the LEDs are OFF.
If LED1 is pulled low by a 10K resistor, the RT8101L runs in
modem-only mode and a 93C46 is not necessary.
6.6. Attachment Unit Interface
Table 6. Attachment Unit Interface
Symbol
TXD+
TXD-
RXIN+
RXIN-
X1
Type
O
Pin No
72
71
Description
10/100Base-T Transmit (TX) data.
O
I
I
68
67
10/100Base-T Receive (RX) data.
I
61
60
25MHz Crystal/OSC Input.
Crystal Feedback Output.
O
X2
This output is used in a crystal connection only. It must be left open when
X1 is driven with an external 25MHz oscillator.
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Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
6.7. AC-Link Pins
Table 7. AC-Link Pins
Symbol
Type
Pin No
Description
O
1
AC_RSTB
AC_SYNC
AC_DOUT
AC_DIN
AC_BCK
INTBB
MC’97 Reset: Hardware reset to Codec.
MC’97 SYNC: 48Khz fixed rate sample sync to Codec.
MC’97 Serial Data Out: Serial data output to Codec.
MC’97 Serial Data In: Serial data input from Codec.
O
O
3
4
I
5
I
7
MC’97 Bit Clock: 12.288Mhz serial data clock generated by Codec.
INTBB is used for function 1 device (Modem) to request an interrupt.
O/D
I/O
I/O
79
100
99
GPIO0
General Purpose I/O pins: Both can be programmed as input or output
by bit0-1 of PCI GPIO Setup Register.
GPIO1
6.8. Test and Other Pins
Table 8. Test and Other Pins
Symbol
RTT3
Type
TEST
Pin No
63
Description
Chip test pin.
I/O
I/O
65
50
RTSET
This pin must be pulled low by a resistor.
CLKRUNB
Clock run: This signal is used by the RTL8101L to request starting (or
speeding up) the clock, CLK. CLKRUNB also indicates the clock
status. For the RTL8101L, CLKRUNB is an open drain output as well
as an input. The RTL8101L requests the central resource to start,
speed up, or maintain the interface clock by the assertion of
CLKRUNB. For the host system, it is an S/T/S signal. The host
system (central resource) is responsible for maintaining CLKRUNB
asserted, and for driving it high to the negated (deasserted) state.
O
-
51
ROMCS/OEB
NC
ROM Chip select and Output Enable: This is the chip select signal and
output enable of the Boot PROM.
56, 69
Reserved.
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RTL8101L
Datasheet
7. Ethernet Controller Register Descriptions
The RTL8101L provides the following set of operational registers mapped into PCI memory space or I/O
space.
Table 9. Register Descriptions
Offset
R/W
Tag
Description
R/W
IDR0
0000h
ID Register 0.
ID registers 0-5 are only permitted to read/write via 4-byte access.
Read access can be byte, word, or double word access. The initial
value is auto-loaded from the EEPROM EthernetID field.
R/W
R/W
R/W
R/W
R/W
-
IDR1
IDR2
IDR3
IDR4
IDR5
-
0001h
ID Register 1.
0002h
ID Register 2.
0003h
ID Register 3.
0004h
ID Register 4.
0005h
ID Register 5.
0006h-0007h
0008h
Reserved.
R/W
MAR0
Multicast Address Register 0.
The MAR register 0-7 are only permitted to read/write via 4-byte
access. Read access can be byte, word, or double-word access. The
driver is responsible for initializing these registers.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
TSD0
0009h
Multicast Address Register 1.
Multicast Address Register 2.
Multicast Address Register 3.
Multicast Address Register 4.
Multicast Address Register 5.
Multicast Address Register 6.
Multicast Address Register 7.
Transmit Status of Descriptor 0.
Transmit Status of Descriptor 1.
Transmit Status of Descriptor 2.
Transmit Status of Descriptor 3.
Transmit Start Address of Descriptor 0.
Transmit Start Address of Descriptor 1.
Transmit Start Address of Descriptor 2.
Transmit Start Address of Descriptor 3.
Receive (Rx) Buffer Start Address.
Early Receive (Rx) Byte Count Register.
Early Rx Status Register.
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h-0013h
0014h-0017h
0018h-001Bh
001Ch-001Fh
0020h-0023h
0024h-0027h
0028h-002Bh
002Ch-002Fh
0030h-0033h
0034h-0035h
0036h
TSD1
TSD2
TSD3
TSAD0
TSAD1
TSAD2
TSAD3
RBSTART
ERBCR
ERSR
R
R/W
R/W
R
CR
0037h
Command Register.
CAPR
CBR
0038h-0039h
003Ah-003Bh
Current Address of Packet Read.
Current Buffer Address.
The initial value is 0000h. It reflects total received byte-count in the
Rx buffer.
R/W
IMR
003Ch-003Dh
Interrupt Mask Register.
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Offset
R/W
R/W
R/W
R/W
R/W
Tag
ISR
Description
003Eh-003Fh
0040h-0043h
0044h-0047h
0048h-004Bh
Interrupt Status Register.
Transmit (Tx) Configuration Register.
Receive (Rx) Configuration Register.
Timer CounT Register.
TCR
RCR
TCTR
This register contains a 32-bit general-purpose timer. Writing any
value to this register will reset the original timer and start a count
from zero.
R/W
MPC
004Ch-004Fh
Missed Packet Counter.
Indicates the number of packets discarded due to Rx FIFO overflow.
It is a 24-bit counter. After s/w reset, MPC is cleared. Only the lower
3 bytes are valid.
When any value is written, MPC will be reset also.
93C46 Command Register.
Configuration Register 0.
Configuration Register 1.
Reserved.
R/W
R/W
R/W
-
9346CR
CONFIG0
CONFIG1
-
0050h
0051h
0052h
0053H
R /W
TimerInt
0054h-0057h
Timer Interrupt Register.
Once having written a non-zero value to this register, the Timeout bit
of the ISR register will be set whenever the TCTR reaches that value.
The Timeout bit will never be set whilst the TimerInt register is zero.
R/W
R/W
R/W
-
MSR
CONFIG3
CONFIG4
-
0058h
Media Status Register.
0059h
Configuration register 3.
Configuration register 4.
Reserved.
005Ah
005Bh
R/W
R
MULINT
RERID
-
005Ch-005Dh
005Eh
Multiple Interrupt Select.
PCI Revision ID = 10h.
Reserved.
-
005Fh
R
TSAD
0060h-0061h
0062h-0063h
0064h-0065h
0066h-0067h
0068h-0069h
006Ah-006Bh
006Ch-006Dh
006Eh-006Fh
0070h-0071h
0072h-0073h
0074h-0075h
0076-0077h
0078h-007Bh
007Ch-007Fh
0080h
Transmit Status of All Descriptors.
Basic Mode Control Register.
Basic Mode Status Register.
Auto-Negotiation Advertisement Register.
Auto-Negotiation Link Partner Register.
Auto-Negotiation Expansion Register.
Disconnect Counter.
R/W
R
BMCR
BMSR
ANAR
ANLPAR
ANER
DIS
R/W
R
R
R
R
FCSC
False Carrier Sense Counter.
N-way Test Register.
R/W
R
NWAYTR
REC
RX_ER Counter.
R/W
-
CSCR
CS Configuration Register.
Reserved.
-
R/W
R/W
R/W
-
PHY1_PARM
TW_PARM
PHY2_PARM
-
PHY parameter 1.
Twister parameter.
PHY parameter 2.
0081-0083h
0084h
Reserved.
R/W
CRC0
Power Management CRC register0 for wakeup frame 0.
Single-Chip Fast Ethernet Controller and MC’97
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Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
Offset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
Tag
CRC1
Description
0085h
Power Management CRC register1 for wakeup frame 1.
Power Management CRC register2 for wakeup frame 2.
Power Management CRC register3 for wakeup frame 3.
Power Management CRC register4 for wakeup frame 4.
Power Management CRC register5 for wakeup frame 5.
Power Management CRC register6 for wakeup frame 6.
Power Management CRC register7 for wakeup frame 7.
Power Management wakeup frame0 (64bit).
CRC2
0086h
CRC3
0087h
CRC4
0088h
CRC5
0089h
CRC6
008Ah
CRC7
008Bh
Wakeup0
Wakeup1
Wakeup2
Wakeup3
Wakeup4
Wakeup5
Wakeup6
Wakeup7
LSBCRC0
LSBCRC1
LSBCRC2
LSBCRC3
LSBCRC4
LSBCRC5
LSBCRC6
LSBCRC7
-
008Ch–0093h
0094h–009Bh
009Ch–00A3h
00A4h–00ABh
00ACh–00B3h
00B4h–00BBh
00BCh–00C3h
00C4h–00CBh
00CCh
Power Management wakeup frame1 (64bit).
Power Management wakeup frame2 (64bit).
Power Management wakeup frame3 (64bit).
Power Management wakeup frame4 (64bit).
Power Management wakeup frame5 (64bit).
Power Management wakeup frame6 (64bit).
Power Management wakeup frame7 (64bit).
LSB of the mask byte of wakeup frame0 within offset 12 to 75.
LSB of the mask byte of wakeup frame1 within offset 12 to 75.
LSB of the mask byte of wakeup frame2 within offset 12 to 75.
LSB of the mask byte of wakeup frame3 within offset 12 to 75.
LSB of the mask byte of wakeup frame4 within offset 12 to 75.
LSB of the mask byte of wakeup frame5 within offset 12 to 75.
LSB of the mask byte of wakeup frame6 within offset 12 to 75.
LSB of the mask byte of wakeup frame7 within offset 12 to 75.
Reserved.
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h-00D7h
00D8h
R/W
-
Config5
-
Configuration register 5.
00D9h-00FFh
Reserved.
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Datasheet
7.1. Receive Status Register in RX Packet Header
Table 10. Receive Status Register in RX Packet Header
Bit
R/W
Symbol
Description
R
MAR
15
Multicast Address Received.
This bit set to 1 indicates that a multicast packet has been received.
Physical Address Matched.
This bit set to 1 indicates that the destination address of this packet
matches the value written in ID registers.
R
R
PAM
BAR
14
13
Broadcast Address Received.
This bit set to 1 indicates that a broadcast packet is received. BAR, MAR
bit will not be set simultaneously.
-
-
12-6
5
Reserved.
R
ISE
Invalid Symbol Error (100Base-TX only).
This bit set to 1 indicates that an invalid symbol was encountered during
the reception of this packet.
R
R
RUNT
LONG
4
3
Runt Packet Received.
This bit set to 1 indicates that the received packet length is smaller than
64 bytes ( i.e. media header + data + CRC < 64 bytes )
Long Packet.
This bit set to 1 indicates that the size of the received packet exceeds
4k bytes.
R
R
CRC
FAE
2
1
Cyclic Redundancy Check (CRC) Error.
When set, indicates that a CRC error occurred on the received packet.
Frame Alignment Error.
When set, indicates that a frame alignment error occurred on this
received packet.
R
ROK
0
Receive OK.
When set, indicates that a good packet was received.
7.2. Transmit Status Register
(TSD0-3)(Offset 0010h-001Fh, R/W)
The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8101L
when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written. It is not affected
when software writes to these bits. These registers are only permitted to be written via double-word access.
After a software reset, all bits except the OWN bit are reset to 0.
Table 11. Transmit Status Register
Bit
R/W
Symbol
Description
31
R
CRS
Carrier Sense Lost.
This bit is set to 1 when the carrier is lost during transmission of a
packet.
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Bit
R/W
Symbol
Description
30
R
TABT
Transmit Abort.
This bit is set to 1 if the transmission of a packet was aborted. This bit
is read only, writing to this bit is not affected.
29
28
R
R
OWC
CDH
Out of Window Collision.
This bit is set to 1 if the RTL8101L encountered an ‘out of window’
collision during the transmission of a packet.
CD HeartBeat.
The NIC watches for a collision signal (i.e., CD Heartbeat signal)
during the first 6.4µs of the InterFrame Gap following a transmission.
This bit is set if the transceiver fails to send this signal.
This bit is cleared in 100Mbps mode.
Number of Collision Count.
27-24
R
NCC3-0
Indicates the number of collisions encountered during the
transmission of a packet.
23-22
21-16
-
-
Reserved.
R/W
ERTXTH5-0
Early Tx Threshold.
Specifies the threshold level in the Tx FIFO to begin the transmission.
When the byte count of the data in the Tx FIFO reaches this level, (or
the FIFO contains at least one complete packet) the RTL8101L will
transmit this packet.
000000 = 8 bytes
These fields count from 000001 to 111111 in units of 32 bytes.
This threshold must be prevented from exceeding 2k bytes.
Transmit OK.
Set to 1 indicates that the transmission of a packet was completed
successfully and no transmit underrun has occurred.
15
14
R
R
TOK
TUN
Transmit FIFO Underrun.
Set to 1 if the Tx FIFO was exhausted during the transmission of a
packet. The RTL8101L can re-transfer data if the Tx FIFO underruns.
That is, when TSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or
ISR<TER>=1).
13
R/W
R/W
OWN
SIZE
OWN.
The RTL8101L sets this bit to 1 when the Tx DMA operation of this
descriptor has completed. The driver must set this bit to 0 when the
Transmit Byte Count (bits 0-12) is written. The default value is 1.
12-0
Descriptor Size.
The total size in bytes of the data in this descriptor. If the packet length
is more than 1792 bytes (0700h), the Tx queue will be invalid, i.e. the
next descriptor will be written only after the OWN bit of that long
packet’s descriptor has been set.
Single-Chip Fast Ethernet Controller and MC’97
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Track ID: JATR-1076-21 Rev. 1.5
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Datasheet
7.3. ERSR: Early RX Status Register (Offset 0036h, R)
Table 12. ERSR: Early RX Status Register
Bit
7-4
3
R/W
-
Symbol
-
Description
Reserved.
R
ERGood
Early Rx Good packet.
This bit is set whenever a packet is completely received and the packet
is good. Writing a 1 to this bit will clear it.
2
1
R
R
ERBad
Early Rx Bad packet.
This bit is set whenever a packet is completely received and the packet
is bad. Writing a 1 to this bit will clear it.
EROVW
Early Rx OverWrite.
This bit is set when the RTL8101L’s local address pointer is equal to
CAPR. In Early Mode, this is different from buffer overflow. It
happens when the RTL8101L detects an Rx error and wants to fill
another packet data from the beginning address of that error packet.
Writing a 1 to this bit will clear it.
0
R
EROK
Early Rx OK.
The power-on value is 0. It is set when the Rx byte count of the
arriving packet exceeds the Rx threshold. After the whole packet is
received, the RTL8101L will set ROK or RER in ISR and clear this bit
simultaneously. Setting this bit will invoke an ROK interrupt.
Single-Chip Fast Ethernet Controller and MC’97
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Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
7.4. Command Register (Offset 0037h, R/W)
This register is used for issuing commands to the RTL8101L. These commands are issued by setting the
corresponding bits for the function. A global software reset along with individual reset and enable/disable for
transmitter and receiver are provided here.
Table 13. Command Register
Bit
7-5
4
R/W
-
Symbol
Description
Reserved.
Reset.
-
R/W
RST
Setting to 1 forces the RTL8101L to a software reset state which
disables the transmitter and receiver, reinitializes the FIFOs, resets the
system buffer pointer to the initial value (Tx buffer is at TSAD0, Rx
buffer is empty). The values of IDR0-5 and MAR0-7 and PCI
configuration space will have no changes. This bit is 1 during the reset
operation, and is cleared to 0 by the RTL8101L when the reset
operation is complete.
3
2
R/W
R/W
RE
TE
Receiver Enable.
When set to 1, makes the idle receive state machine active. This bit
will read back as a 1 whenever the receive state machine is active.
After initial power-up, software must ensure that the receiver has
completely reset before setting this bit. This bit will be reset after PCI
reset deassertion.
Transmitter Enable.
When set to 1, and the transmit state machine is idle, the transmit state
machine will become active. This bit will read back as a 1 whenever
the transmit state machine is active. After initial power-up, software
must ensure that the transmitter has completely reset before setting
this bit. This bit will be reset after PCI reset deassertion.
1
0
-
-
Reserved.
R
BUFE
Buffer Empty.
RX Buffer Empty. There are no packets stored in the RX buffer ring.
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Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
7.5. Interrupt Mask Register (Offset 003Ch-003Dh, R/W)
This register masks the interrupts that can be generated from the Interrupt Status Register. A hardware reset
will clear all mask bits. Setting a mask bit allows the corresponding bit in the Interrupt Status Register to
cause an interrupt. The Interrupt Status Register bits are always set to 1 if the condition is present,
regardless of the state of the corresponding mask bit.
Table 14. Interrupt Mask Register
Bit
R/W
Symbol
Description
15
R/W
SERR
System Error Interrupt.
1: Enable
0: Disable
14
13
R/W
R/W
TimeOut
LenChg
Time Out Interrupt.
1: Enable
0: Disable
Cable Length Change Interrupt.
1: Enable
0: Disable
12-7
6
-
-
Reserved.
R/W
FOVW
Rx FIFO Overflow Interrupt.
1: Enable
0: Disable
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
PUN/LinkChg
RXOVW
TER
Packet Underrun/Link Change Interrupt.
1: Enable
0: Disable
Rx Buffer Overflow Interrupt.
1: Enable
0: Disable
Transmit Error Interrupt.
1: Enable
0: Disable
TOK
Transmit OK Interrupt.
1: Enable
0: Disable
RER
Receive Error Interrupt.
1: Enable
0: Disable
ROK
Receive OK Interrupt.
1: Enable
0: Disable
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RTL8101L
Datasheet
7.6. Interrupt Status Register (Offset 003Eh-003Fh, R/W)
This register indicates the source of an interrupt when the INTA pin goes active. Enabling the
corresponding bits in the Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt.
When an interrupt is active, one or more bits in this register are set to 1. The interrupt Status Register
reflects all current pending interrupts, regardless of the state of the corresponding mask bit in the IMR.
Writing a 1 to any bit will reset that bit, but writing a 0 has no effect.
Table 15. Interrupt Status Register
Bit
R/W
Symbol
Description
15
R/W
SERR
System Error.
Set to 1 when the RTL8101L signals a system error on the PCI bus.
Time Out.
Set to 1 when the TCTR register reaches the value of the TimerInt
register.
14
13
R/W
R/W
TimeOut
LenChg
Cable Length Change.
Cable length is changed after Receiver is enabled.
Reserved.
12 - 7
6
-
-
R/W
FOVW
Rx FIFO Overflow.
Set when an overflow occurs on the Rx status FIFO.
Packet Underrun/Link Change.
Set to 1 when CAPR is written but Rx buffer is empty, or when link
status is changed.
5
4
3
R/W
R/W
R/W
PUN/LinkChg
RXOVW
TER
Rx Buffer Overflow.
Set when receive (Rx) buffer ring storage resources have been
exhausted.
Transmit (Tx) Error.
Indicates that a packet transmission was aborted, due to excessive
collisions, according to the TXRR’s setting.
2
1
R/W
R/W
TOK
RER
Transmit (Tx) OK.
Indicates that a packet transmission has completed successfully.
Receive (Rx) Error.
Indicates that a packet has either a CRC error or Frame Alignment
Error (FAE). Collided frames will not be recognized as CRC errors if
the length of the frame is shorter than 16 bytes.
0
R/W
ROK
Receive (Rx) OK.
In normal mode, indicates the successful completion of a packet
reception. In early mode, indicates that the Rx byte count of the
arriving packet exceeds the early Rx threshold.
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Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
7.7. Transmit Configuration Register (Offset 0040h-0043h, R/W)
This register defines the Transmit Configuration for the RTL8101L. It controls such functions as
Loopback, programmable InterFrame Gap, Fill and Drain Thresholds, and maximum DMA burst size.
Table 16. Transmit Configuration Register
Bit
31
R/W
-
Symbol
Description
-
Reserved.
30~26
R
HWVERID_A
Hardware Version ID A.
Bit30 Bit29 Bit28 Bit27 Bit26 Bit23 Bit22
RTL8139
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
RTL8139A
RTL8139A-G
RTL8139B
RTL8130
RTL8139C
RTL8100
RTL8100B
RTL8100C
RTL8139D
RTL8139C+
RTL8101L
Reserved
1
1
1
1
1
1
0
0
1
1
1
1
0
1
Other combinations.
25, 24
R/W
IFG1, 0
InterFrame Gap time.
This field allows the user to adjust the InterFrame Gap time below the
standard: 9.6µs for 10Mbps, 960ns for 100Mbps. The time can be
programmed from 9.6µs to 8.4µs (10Mbps) and 960ns to 840ns
(100Mbps). Note that any value other than (1, 1) will violate the IEEE
802.3 standard.
The formula for the InterFrame Gap is:
10Mbps: 8.4µs + 0.4(IFG(1:0)) µs
100Mbps: 840ns + 40(IFG(1:0)) ns
Hardware Version ID B.
Reserved.
23, 22
21~19
18, 17
R
-
HWVERID_B
-
R/W
LBK1, LBK0
Loopback test.
There will be no packets on the TX+/- lines under the Loopback test
condition. The loopback function must be independent of the link
state.
00: Normal operation
01: Reserved
10: Reserved
11: Loopback mode
Append CRC.
16
R/W
CRC
Setting to 1 means that there is no CRC appended at the end of a
packet. Setting to 0 means that there is a CRC appended at the end of a
packet.
15~11
-
-
Reserved.
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RTL8101L
Datasheet
Bit
R/W
Symbol
Description
10~8
R/W
MXDMA2, 1, 0
Max DMA Burst Size per Tx DMA Burst.
This field sets the maximum size of transmit DMA data bursts
according to the following table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = 2048 bytes
Tx Retry Count.
7-4
R/W
TXRR
These are used to specify additional transmission retries in multiple of
16 (IEEE 802.3 CSMA/CD retry count). If the TXRR is set to 0, the
transmitter will re-transmit 16 times before aborting due to excessive
collisions. If the TXRR is set to a value greater than 0, the transmitter
will re-transmit a number of times equals to the following formula
before aborting:
Total retries = 16 + (TXRR * 16)
The TER bit in the ISR register or transmit descriptor will be set when
the transmission fails and reaches to this specified retry count.
3-1
0
-
-
Reserved.
W
CLRABT
Clear Abort.
Setting this bit to 1 causes the RTL8101L to retransmit the packet at
the last transmitted descriptor when this transmission was aborted.
Setting this bit is only permitted in the transmit abort state.
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Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
7.8. Receive Configuration Register
(Offset 0044h-0047h, R/W)
This register is used to set the receive configuration for the RTL8101L. Receive properties such as
accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here.
Table 17. Receive Configuration Register
Bit
31-28
R/W
-
Symbol
Description
-
Reserved.
27-24
R/W
ERTH3, 2, 1, 0
Early Rx threshold bits.
These bits are used to select the Rx threshold multiplier of a whole
packet that has been transferred to the system buffer in early mode
whilst the frame protocol is under the RTL8101L’s definition.
0000 = No early Rx threshold
0010 = 2/16
0001 = 1/16
0011 = 3/16
0101 = 5/16
0111 = 7/16
1001 = 9/16
1011 = 11/16
1101 = 13/16
1111 = 15/16
0100 = 4/16
0110 = 6/16
1000 = 8/16
1010 = 10/16
1100 = 12/16
1110 = 14/16
23-18
17
-
-
Reserved.
R/W
MulERINT
Multiple Early Interrupt select.
When this bit is set, any received packet invokes early interrupt
according to MULINT<MISR[11:0]> setting in early mode. When
this bit is reset, the packets of familiar protocols (IPX, IP, NDIS, etc)
invoke early interrupt according to RCR<ERTH[3:0]> setting in early
mode. The packets of unfamiliar protocols will invoke early interrupt
according to the setting of MULINT<MISR[11:0]>.
16
R/W
RER8
Receive Error 8 bytes.
1: The RTL8101L accepts error packets with a length of 8~64 bytes.
0: The RTL8101L accepts error packets with a length larger than
64 bytes. The power-on default is zero.
If AER or AR is set, the RER (Receive Error) will be set when the
RTL8101L receives an error packet with a length larger than 8 bytes.
RER8 is irrelevant in this situation.
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RTL8101L
Datasheet
Bit
R/W
Symbol
Description
15~13
R/W
RXFTH2, 1, 0
Rx FIFO Threshold.
Specifies the Rx FIFO Threshold level. When the number of received
data bytes from a packet that is being received into the RTL8101L’s Rx
FIFO has reached this level (or the FIFO contains a complete packet),
the receive PCI bus master function will begin to transfer the data from
the FIFO to the host memory. This field sets the threshold level
according to the following table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = No Rx threshold. The RTL8101L begins the transfer of data
after receiving a whole packet in the FIFO.
12, 11
R/W
R/W
RBLEN1, 0
Rx Buffer Length.
This field indicates the size of the Rx ring buffer:
00 = 8k + 16 bytes
01 = 16k + 16 bytes
10 = 32K + 16 bytes
11 = 64K + 16 bytes
10~8
MXDMA2, 1, 0
Max DMA Burst Size per Rx DMA Burst.
This field sets the maximum size of the receive DMA data bursts:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = Unlimited
7
R/W
WRAP
Wraps packet data into the beginning of the Rx buffer.
0: The RTL8101L will transfer the rest of the packet data into the beginning
of the Rx buffer if this packet has not been completely moved into the Rx
buffer and the transfer has arrived at the end of the Rx buffer.
1: The RTL8101L will keep moving the rest of the packet data into the
memory immediately after the end of the Rx buffer, if this packet has not
been completely moved into the Rx buffer and the transfer has arrived at
the end of the Rx buffer. The software driver must reserve at least 1.5
Kbytes buffer to accept the remainder of the packet. We assume that the
remainder of the packet is X bytes. The next packet will be moved into
the memory from the X byte offset at the top of the Rx buffer.
This bit is invalid when the Rx buffer is set to 64 Kbytes.
Reserved.
6
-
-
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RTL8101L
Datasheet
Bit
R/W
Symbol
Description
5
R/W
AER
Accept Error Packet.
1: Packets with CRC errors, alignment errors, and/or collided fragments
will be accepted.
0: Packets with the above errors will be rejected.
Accept Runt.
4
R/W
AR
This bit allows the receiver to accept packets that are smaller than
64 bytes. The packet must be at least 8 bytes long to be accepted as a
runt.
1: Accept
0: Reject
3
2
1
0
R/W
R/W
R/W
R/W
AB
AM
Accept Broadcast packets.
1: Accept
0: Reject
Accept Multicast packets.
1: Accept
0: Reject
APM
AAP
Accept Physical Match packets.
1: Accept
0: Reject
Accept All Packets.
Set to 1 to accept all packets with a physical destination address.
1: Accept
0: Reject
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RTL8101L
Datasheet
7.9. 9346CR: 93C46 Command Register
(Offset 0050h, R/W)
This register is used for issuing commands to the RTL8101L. These commands are issued by setting the
corresponding bits for the function. A warm software reset along with individual reset and enable/disable for
transmitter and receiver are also provided.
Table 18. 9346CR: 93C46 Command Register
Bit
R/W
Symbol
Description
7-6
R/W
EEM1-0
Operating Mode: These 2 bits set the RTL8101L operating mode.
EEM1 EEM0 Operating Mode
0
0
Normal: RTL8101L network/host
communication mode.
0
1
Auto-load: Entering this mode will force the
RTL8101L to load the contents of the 93C46 as
if an RSTB signal had been asserted. This
auto-load operation will take about 2ms. After
it is completed, the RTL8101L goes back to
normal mode automatically
(EEM1 = 0 EEM0 = 0) and all other registers
are reset to default values.
1
1
0
1
93C46 Programming: In this mode both
network and host bus master operations are
disabled. The 93C46 can be directly accessed
via bit3-0 which now reflects the states of
EECS, EESK, EEDI, & EEDO pins
respectively.
Config Register Write Enable: Before writing
to CONFIG0, 1, 3, 4 registers, and bit 13, 12,
and 8 of BMCR (offset 62h-63h), the
RTL8101L must be placed in this mode. This
will protect the RTL8101L’s configuration
from accidental change.
4-5
3
-
-
Reserved.
R/W
R/W
R/W
R
EECS
EESK
EEDI
EEDO
These bits reflect the state of EECS, EESK, EEDI, and EEDO pins in
auto-load or 93C46 programming mode.
2
1
0
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RTL8101L
Datasheet
7.10. CONFIG 0: Configuration Register 0
(Offset 0051h, R/W)
Table 19. CONFIG 0: Configuration Register 0
Bit
R/W
Symbol
Description
7
R
SCR
Scrambler Mode.
Always 0.
6
R
R
R
R
PCS
T10
PCS Mode.
Always 0.
5
10Mbps Mode.
Always 0.
4-3
2-0
PL1, PL0
BS2, BS1, BS0
10Mbps Medium Type.
Always (PL1, PL0) = (1, 0).
Select Boot ROM size (Auto-loaded from EEPROM).
BS2
BS1
BS0
Description
No Boot ROM
8K Boot ROM
16K Boot ROM
32K Boot ROM
64K Boot ROM
128K Boot ROM
unused
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
unused
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7.11. CONFIG 1: Configuration Register 1
(Offset 0052h, R/W)
Table 20. CONFIG 1: Configuration Register 1
Bit
R/W
Symbol
Description
7-6
R/W
LEDS1-0
Refer to section 6.5 LED Interface, page 9, for a detailed LED pin description.
The initial value of these bits comes from the 93C46.
5
R/W
DVRLOAD
Driver Load.
Software may use this bit to make sure that the driver has been loaded.
1: Driver loaded
0: Driver not loaded
When the command register bits IOEN, MEMEN, and BMEN of the PCI
configuration space are written, the RTL8101L will clear this bit automatically.
4
R/W
LWACT
LWAKE active mode: The LWACT bit and LWPTN bit in CONFIG4 register
are used to program the LWAKE pin’s output signal. Depending on the
combination of these two bits, there may be 4 choices of LWAKE signal,
i.e., active high, active low, positive (high) pulse, and negative (low) pulse. The
output pulse width is about 150ms.
The default value of each of these two bits is 0, i.e., the default output signal of
the LWAKE pin is an active high signal.
LWAKE Output
LWPTN
LWACT
0
1
0
1
Active high*
Active low
Positive pulse
Negative pulse
* Default value.
3
2
1
0
R
MEMMAP
IOMAP
VPD
Memory Mapping.
Operational registers are mapped into PCI memory space.
I/O Mapping.
Operational registers are mapped into PCI I/O space.
Set to enable Vital Product Data.
VPD data is stored in the 93C46 from within offset 40h-7Fh.
Power Management Enable.
R
R/W
R/W
PMEn
Writable only when the 93C46CR register EEM1:0 = [1:1].
Let A denote the New_Cap bit (bit 4 of the Status Register) in the PCI
Configuration space offset 06H.
Let B denote the Cap_Ptr register in the PCI Configuration space offset 34H.
Let C denote the Cap_ID (power management) register in the PCI
Configuration space offset 50H.
Let D denote the power management registers in the PCI Configuration space
offset from 52H to 57H.
Let E denote the Next_Ptr (power management) register in the PCI
Configuration space offset 51H.
PMEn Description
1: A=1, B=50h, C=01h, D valid, E=0
0: A=B=C=E=0, D not valid
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RTL8101L
Datasheet
7.12. Media Status Register (Offset 0058h, R/W)
This register allows configuration of device and PHY options, and provides PHY status information.
Table 21. Media Status Register
Bit
7
R/W
R/W
Symbol
TXFCE/
Description
Tx Flow Control Enable.
LdTXFCE
Flow control is valid in full-duplex mode only. This register’s default
value comes from the 93C46.
RTL8101L
Remote
TXFCE/LdTXFCE
ANE = 1
NWAY FLY
mode
R/O
ANE = 1
ANE = 1
NWAY mode
only
R/W
No NWAY
-
R/W
R/W
ANE = 0 &
full-duplex mode
ANE = 0 &
-
Invalid
half-duplex mode
NWAY FLY mode: NWay with flow control capability.
NWAY mode only: NWay without flow control capability.
RX Flow control Enable.
6
R/W
RXFCE
Flow control is enabled in full-duplex mode only. The default value
comes from the 93C46.
5
4
-
-
Reserved.
R
Aux_Status
Aux. Power present Status.
1: Aux. Power is present
0: Aux. Power is absent
The value of this bit is fixed after each PCI reset.
3
2
R
R
SPEED_10
LINKB
Speed. Set when current media is 10Mbps. Reset when current media
is 100Mbps.
Inverse of Link status.
0: Link OK
1: Link Fail.
1
0
R
R
TXPF
RXPF
Transmit Pause Flag.
Set when the RTL8101L sends a pause packet. Reset when the
RTL8101L sends a timer done packet.
Receive Pause Flag.
Set when the RTL8101L is in backoff state because a pause packet was
received.
Reset when the pause state is cleared.
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7.13. CONFIG 3: Configuration Register3
(Offset 0059h, R/W)
Table 22. CONFIG 3: Configuration Register3
Bit
R/W
Symbol
Description
7
R
GNTSel
Grant Select.
Sets the Frame’s asserted time after the Grant signal has been asserted.
Frame and Grant are PCI signals.
1: Delay one clock from GNT assertion
0: No delay
6
R/W
PARM_En
Parameter Enable (Used in 100Mbps mode only).
0: The 9346CR register EEM1:0 = [1:1] will enable the PHY1_PARM,
PHY2_PARM, and TW_PARM registers to be written via software.
1: Allows parameters to be auto-loaded from the 93C46, and disables
writing to PHY1_PARM, PHY2_PARM and TW_PARM registers via
software. PHY1_PARM and PHY2_PARM can be auto-loaded from
the EEPROM in this mode. The parameter auto-load process is
executed each time the Link is OK in 100Mbps mode.
5
R/W
Magic
Magic Packet.
This bit is valid when the PWEn bit of the CONFIG1 register is set.
The RTL8101L will assert the PMEB signal to wakeup the operating
system when a Magic Packet is received.
Once the RTL8101L has been enabled for Magic Packet wakeup, it
scans all incoming packets addressed to the node for a specific data
sequence that indicates to the controller that this is a Magic Packet. A
Magic Packet must also meet the basic requirements of:
Destination address + Source address + data + CRC.
The destination address may be the node ID of the receiving station or
a multicast address, which includes the broadcast address.
The specific sequence consists of 16 duplications of a 6-byte ID
register, with no breaks nor interrupts. This sequence can be located
anywhere within the packet, but must be preceded by a
synchronization stream, 6 bytes of FFh. The device will also accept a
multicast address, as long as the 16 duplications of the IEEE MAC
address match the address of the ID register.
If the Node ID is 11h 22h 33h 44h 55h 66h, then the magic packet’s
format is similar to the following:
Destination address + source address + MISC + FF FF FF FF FF FF +
MISC + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 +
11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33
44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66
+ 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33
44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + MISC + CRC
4
3
R/W
LinkUp
Link Up.
This bit is valid when the PWEn bit of CONFIG1 register is set. The
RTL8101L, when in an adequate power state, will assert the PMEB
signal to wakeup the operating system when the cable connection is
re-established.
-
-
Reserved.
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Datasheet
Bit
R/W
Symbol
Description
2
R
CLKRUN_En
CLKRUN Enable.
1: Enable CLKRUN
0: Disable CLKRUN
Reserved.
1
0
-
-
R
FBtBEn
Fast-Back-to-Back Enable.
Set to 1 to enable Fast-Back-to-Back.
7.14. CONFIG 4: Configuration Register4
(Offset 005Ah, R/W)
Table 23. CONFIG 4: Configuration Register4
Bit
R/W
Symbol
Description
7
R/W
RxFIFOAutoClr
Receive FIFO buffer Auto-Clear.
When set to 1, the RTL8101L will clear the Rx FIFO buffer
automatically.
6
5
R/W
R/W
AnaOff
Analog Power Off.
This bit cannot be auto-loaded from EEPROM (93C46).
1: Turns off the analog power of the RTL8101L internally
0: Normal working state. This is also the power-on default value
Long Wake-up Frame.
LongWF
The initial value comes from EEPROM auto-load.
0: The RTL8101L supports up to 8 wake-up frames, each with masked
bytes selected from offset 12 to 75
1: The RTL8101L supports up to 5 wake-up frames, each with a 16-bit
CRC algorithm for MS Wakeup Frame support. The low byte of the
16-bit CRC should be placed in the corresponding CRC register, and
the high byte of the 16-bit CRC should be placed in the corresponding
LSB CRC register.
Wake-up frames 0 and 1 are the same as above, except that the masked
bytes start from offset 0 to 63. Wake-up frames 2 and 3 are merged into
one long wake-up frame with masked bytes selected from offset 0 to
127. Wake-up frames 4, 5, 6, and 7 are merged into another 2 long
wake-up frames. Refer to 10.5 PCI Power Management Functions,
page 66, for a detailed description.
4
R/W
LWPME
LWAKE vs. PMEB.
1: LWAKE can only be asserted when PMEB is asserted and
ISOLATEB is low
0: LWAKE and PMEB are asserted at the same time
3
2
-
-
Reserved.
R/W
LWPTN
LWAKE Pattern.
See the LWACT bit in Table 20. CONFIG 1: Configuration Register 1,
page 27.
1
-
-
Reserved.
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Bit
R/W
Symbol
Description
0
R/W
PBWakeup
Pre-Boot Wakeup.
The initial value comes from EEPROM auto-load.
1: Pre-Boot Wakeup disabled (suitable for CardBus and MiniPCI
applications)
0: Pre-Boot Wakeup enabled
7.15. Multiple Interrupt Select Register
(Offset 005Ch-005Dh, R/W)
Note: The following is true when MulERINT=0 (bit17, RCR). When MulERINT=1, any received packet
invokes an early interrupt according to the MISR[11:0] setting in Early Mode.
If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to the RTL8101L,
RCR<ERTH[3:0]> will not be used to transfer data in early mode. This register will be written to the
received data length in order to make an early Rx interrupt for the unfamiliar protocol.
Table 24. Multiple Interrupt Select Register
Bit
15-12
11-0
R/W
-
Symbol
-
Description
Reserved.
R/W
MISR11-0
Multiple Interrupt Select Register.
Indicates that the RTL8101L made an Rx interrupt after transferring
byte data into the system memory. If the value of these bits is zero,
there will be no early interrupt when the RTL8101L prepares to
execute the first PCI transaction of the received data. Bit1, 0 must be
zero.
The ERTH3-0 bits should not be set to 0 when the multiple interrupt
select register is used.
7.16. PCI Revision ID (Offset 005Eh, R)
Table 25. PCI Revision ID
Bit
R/W
Symbol
Description
7-0
R
Revision ID
The value in PCI Configuration Space offset 08h is 10h.
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7.17. Transmit Status of All Descriptors (TSAD) Register
(Offset 0060h-0061h, R/W)
Table 26. Transmit Status of All Descriptors (TSAD) Register
Bit
15
14
13
12
11
10
9
R/W
R
Symbol
TOK3
Description
TOK bit of Descriptor 3.
TOK bit of Descriptor 2.
TOK bit of Descriptor 1.
TOK bit of Descriptor 0.
TUN bit of Descriptor 3.
TUN bit of Descriptor 2.
TUN bit of Descriptor 1.
TUN bit of Descriptor 0.
TABT bit of Descriptor 3.
TABT bit of Descriptor 2.
TABT bit of Descriptor 1.
TABT bit of Descriptor 0.
OWN bit of Descriptor 3.
OWN bit of Descriptor 2.
OWN bit of Descriptor 1.
OWN bit of Descriptor 0.
R
TOK2
R
TOK1
R
TOK0
R
TUN3
TUN2
TUN1
TUN0
TABT3
TABT2
TABT1
TABT0
OWN3
OWN2
OWN1
OWN0
R
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
R
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7.18. Basic Mode Control Register (Offset 0062h-0063h, R/W)
Table 27. Basic Mode Control Register
Bit
Name
Description/Usage
Default/Attribute
15
Reset
This bit sets the status and control registers of the PHY (register
0062-0074H) to the default state. This bit is self-clearing.
0, RW
1: Software reset
0: Normal operation
14
13
-
Reserved.
-
Spd_Set
This bit sets the network speed.
1: 100Mbps
0, RW
0: 10Mbps. This bit’s initial value comes from the 93C46
This bit enables/disables the NWay auto-negotiation function.
1: Enable auto-negotiation, bit13 will be ignored.
0: Disables auto-negotiation, bit13 and bit8 will determine the
link speed and the data transfer mode, respectively. This bit’s
initial value comes from the 93C46.
12
Auto Negotiation
Enable
0, RW
(ANE)
11-10
9
-
Reserved.
-
Restart Auto
Negotiation
This bit allows the NWay auto-negotiation function to be reset.
1: Re-start auto-negotiation
0: Normal operation
0, RW
8
Duplex Mode
This bit sets the duplex mode.
1: Full-duplex
0, RW
0: Normal operation. This bit’s initial value comes from the
93C46.
7-0
-
Reserved.
-
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7.19. Basic Mode Status Register (Offset 0064h-0065h, R)
Table 28. Basic Mode Status Register
Bit
Name
Description/Usage
Default/Attribute
15
100Base-T4
0, RO
1: Enable 100Base-T4 support
0: Disable 100Base-T4 support
14
13
12
11
100Base_TX_ FD
100BASE_TX_HD
10Base_T_FD
10_Base_T_HD
-
1, RO
1, RO
1, RO
1, RO
1: Enable 100Base-TX full-duplex support
0: Disable 100Base-TX full-duplex support
1: Enable 100Base-TX half-duplex support
0: Disable 100Base-TX half-duplex support
1: Enable 10Base-T full-duplex support
0: Disable 10Base-T full-duplex support
1: Enable 10Base-T half-duplex support
0: Disable 10Base-T half-duplex support
Reserved.
10-6
5
-
Auto Negotiation
Complete
0, RO
1: Auto-negotiation process completed
0: Auto-negotiation process not completed
1: Remote fault condition detected (cleared on read)
0: No remote fault condition detected.
1: Link has not experienced fail state
0: Link experienced fail state
4
3
2
1
0
Remote Fault
Auto Negotiation
Link Status
0, RO
1, RD
0, RO
0, RO
1, RO
1: Valid link established
0: No valid link established
Jabber Detect
1: Jabber condition detected
0: No jabber condition detected
Extended Capability
1: Extended register capability
0: Basic register capability only
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7.20. Auto-Negotiation Advertisement Register
(Offset 0066h-0067h, R/W)
This register contains the advertised abilities of this device, as are transmitted to its link partner during
auto-negotiation.
Table 29. Auto-Negotiation Advertisement Register
Bit
Name
Description/Usage
Default/Attribute
15
NP
0, RO
Next Page bit.
1: Transmitting the protocol specific data page
0: Transmitting the primary capabilities data page
1: Acknowledge reception of link partner capability data word
Remote Fault.
14
13
ACK
RF
0, RO
0, RW
1: Advertise remote fault detection capability
0: Do not advertise remote fault detection capability
Reserved.
12-11
10
-
-
Pause
The default value comes
from EEPROM, RO
1: Flow control supported by local node
0: Flow control not supported by local mode
1: 100Base-T4 supported by local node
0: 100Base-T4 not supported by local node
1: 100Base-TX full-duplex supported by local node
0: 100Base-TX full-duplex not supported by local node
1: 100Base-TX supported by local node
0: 100Base-TX not supported by local node
1: 10Base-T full-duplex supported by local node
0: 10Base-T full-duplex not supported by local node
1: 10Base-T supported by local node
0: 10Base-T not supported by local node
9
8
T4
TXFD
TX
0, RO
1, RW
7
1, RW
6
10FD
10
1, RW
5
1, RW
4-0
Selector
<00001>, RW
Binary encoded selector supported by this node. Currently only
CSMA/CD <00001> is specified. No other protocols are
supported.
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7.21. Auto-Negotiation Link Partner Ability Register
(Offset 0068h-0069h, R)
This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. If
Next Pages are supported, the content changes after a successful auto-negotiation.
Table 30. Auto-Negotiation Link Partner Ability Register
Bit
Name
Description/Usage
Default/Attribute
15
NP
0, RO
Next Page bit.
1: Transmitting the protocol specific data page
0: Transmitting the primary capability data page
14
ACK
0, RO
1: Link partner acknowledges reception of local node’s capability
data word
13
12-11
10
RF
-
0, RO
-
1: Link partner is indicating a remote fault
Reserved.
Pause
0, RO
1: Flow control supported by link partner
0: Flow control is not supported by link partner
1: 100Base-T4 supported by link partner
0: 100Base-T4 not supported by link partner
1: 100Base-TX full duplex is supported by link partner
0: 100Base-TX full duplex not supported by link partner
1: 100Base-TX supported by link partner
0: 100Base-TX not supported by link partner
1: 10Base-T full duplex supported by link partner
0: 10Base-T full duplex not supported by link partner
1: 10Base-T is supported by link partner
0: 10Base-T not supported by link partner
9
8
T4
TXFD
TX
0, RO
0, RO
7
0, RO
6
10FD
10
0, RO
5
0, RO
4-0
Selector
<00000>, RO
Link Partner's binary encoded node selector. Currently only
CSMA/CD <00001> is specified.
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7.22. Auto-Negotiation Expansion Register
(Offset 006Ah-006Bh, R)
This register contains additional NWay auto-negotiation status information.
Table 31. Auto-Negotiation Expansion Register
Bit
15-5
4
Name
-
Description/Usage
Default/Attribute
-
Reserved. These bits are always set to 0.
Multiple Link Fault.
MLF
0, RO
1: Fault occurred
0: No fault occurred
3
LP_NP_ABLE
0, RO
Status indicating whether the link partner supports Next Page
negotiation.
1: Supported
0: Not supported
2
1
NP_ABLE
PAGE_RX
0, RO
0, RO
This bit indicates whether the local node is able to send additional
Next Pages.
This bit is set when a new Link Code Word Page has been
received. The bit is automatically cleared when the auto
negotiation link partner’s ability register (register 5) is read.
0
LP_NW_ABLE
0, RO
1: Link partner supports NWay auto negotiation.
7.23. Disconnect Counter (Offset 006Ch-006Dh, R)
Table 32. Disconnect Counter
Bit
Name
Description/Usage
Default/Attribute
15-0
DCNT
This 16-bit counter increments by 1 for every disconnect event. It
rolls over when full. It is cleared to zero by a read command.
h'[0000], R
7.24. False Carrier Sense Counter (Offset 006Eh-006Fh, R)
This counter provides information required to implement the ‘FalseCarriers’ attribute within the MAU
managed object class, Clause 30 of the IEEE 802.3u specification.
Table 33. False Carrier Sense Counter
Bit
Name
Description/Usage
Default/Attribute
15-0
FCSCNT
h'[0000], R
This 16-bit counter increments by 1 for each false carrier event. It
is cleared to zero by a read command.
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7.25. NWay Test Register (Offset 0070h-0071h, R/W)
Table 34. NWay Test Register
Bit
15-8
7
Name
-
Description/Usage
Default/Attribute
-
Reserved.
NWLPBK
-
0, RW
-
1: Set NWay to loopback mode
Reserved.
6-4
3
ENNWLE
FLAGABD
FLAGPDF
FLAGLSC
0, RW
0, RO
0, RO
0, RO
1: LED0 Pin indicates linkpulse
1: Auto negotiation experienced ability detect state
1: Auto negotiation experienced parallel detection fault state
1: Auto negotiation experienced link status check state
2
1
0
7.26. RX_ER Counter (Offset 0072h-0073h, R)
Table 35. RX_ER Counter
Bit
Name
Description/Usage
Default/Attribute
15-0
RXERCNT
h'[0000],
R
This 16-bit counter increments by 1 for each valid packet
received. It is cleared to zero by a read command.
7.27. CS Configuration Register (Offset 0074h-0075h, R/W)
Table 36. CS Configuration Register
Bit
15
Name
Testfun
-
Description/Usage
Default/Attribute
0, WO
1: Auto negotiation to speed up internal timer
Reserved.
14-10
9
-
LD
1, RW
Active low TPI link disable signal. When low, TPI still transmits
link pulses and TPI maintains a good link state.
8
HEARTBEAT
1, RW
The HEARTBEAT function is only valid in 10Mbps mode.
1: HEARTBEAT enable
0: HEARTBEAT disable
7
6
JBEN
1, RW
1, RW
1: Enable jabber function
0: Disable jabber function
F_LINK_100
Used to login a forced good link at 100Mbps for diagnostics
purposes.
1: Disable
0: Enable
5
4
3
F_Connect
-
0, RW
-
Assertion of this bit forces the disconnect function to be bypassed.
Reserved.
Con_status
0, RO
This bit indicates the status of the connection.
1: Valid connected link detected
0: Disconnected link detected
2
Con_status_En
0, RW
Assertion of this bit configures the LED1 pin to indicate
connection status.
1
0
-
-
Reserved.
PASS_SCR
0, RW
Bypass Scramble.
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7.28. Config5: Configuration Register 5 (Offset 00D8h, R/W)
This register, unlike other Config registers, is not protected by the 93C46 Command register. There is no
need to enable the Config register write prior to writing to Config5.
Table 37. Config5. Configuration Register 5
Bit
7
R/W
-
Symbol
Description
-
Reserved.
6
R/W
BWF
Broadcast Wakeup Frame.
1: Enable Broadcast Wakeup Frame with Destination ID field mask
bytes of FF FF FF FF FF FF
0: Default value. Disable Broadcast Wakeup Frame with Destination
ID field mask bytes of FF FF FF FF FF FF
5
4
R/W
R/W
MWF
UWF
Multicast Wakeup Frame.
1: Enable Multicast Wakeup Frame with mask bytes of only the
Destination ID field, which is a multicast address
0: Default value. Disable Multicast Wakeup Frame with mask bytes
of only the Destination ID field, which is a multicast address
Unicast Wakeup Frame.
1: Enable Unicast Wakeup Frame with mask bytes of only the
Destination ID field, which is its own physical address
0: Default value. Disable Unicast Wakeup Frame with mask bytes of
only the Destination ID field, which is its own physical address
3
2
R/W
R/W
FIFOAddrPtr
LDPS
FIFO Address Pointer (Realtek internal use only).
The power-on default value of this bit is 0.
Link Down Power Saving mode.
1: Disable
0: Enable. When the cable is disconnected (Link Down), the analog
part will power itself down (PHY Tx part and part of the Twister)
automatically except for the PHY Rx part and the part of the twister
that monitors the SD signal in case the cable is reconnected and the
Link should be established again
1
0
R/W
R/W
LANWake
PME_STS
LANWake signal enable/disable.
1: Enable LANWake signal
0: Disable LANWake signal
PME_Status bit.
Always sticky/can be reset by PCI RST# and software.
1: The PME_Status bit may be reset by PCI reset or by software
0: The PME_Status bit may only be reset by software
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8. MC’97 Controller Register and Descriptor Descriptions
Table 38. MC’97 Registers
Description
Offset
R/W
0000h
R/W
Starting Descriptor Index for LINE1-Out
Current Descriptor Index for LINE1-Out
Last Descriptor Index for LINE1-Out
LINE1-Out DMA Status Register
LINE1-Out DMA Control Register
Residual Samples Count in Current LINE1-Out Descriptor Register
Reserved
0001h
R
0002h
R/W
R
0003h
0004h-0005h
0006h-0007h
0008h-000Bh
000Ch-000Fh
0010h
R/W
R
-
R/W
R/W
R
LINE1-Out Descriptor Base Address Register
Starting Descriptor Index for LINE1-In
Current Descriptor Index for LINE1-In
Last Descriptor Index for LINE1-In
LINE1-In DMA Status Register
0011h
0012h
R/W
R
0013h
0014h-0015h
0016h-0017h
0018h-001Bh
001Ch-001Fh
0020h-0021h
0022h-0023h
0024h-0025h
0026h-0027h
0028h-0029h
002Ah-002Bh
002Ch-002Dh
002Eh-002Fh
R/W
R
LINE1-In DMA Control Register
Residual Samples Count in Current LINE1-In Descriptor Register
Reserved
-
R/W
R/W
R/W
R/W
R/W
R
LINE1-In Descriptor Base Address Register
AC-LINK Control register
AC-LINK Status and Index register
AC-LINK Data Port
MC97 GPIO Control Register
MC97 GPIO Status Register
R/W
R/W
R/W
Interrupt Status Register
PCI GPIO Setup Register (PCIGPIO)
PCI GPIO Status Register (PCIGPIOSR)
8.1. Starting Descriptor Index for LINE-Out (Offset 0000h, R/W)
Table 39. Starting Descriptor Index for LINE-Out
Bit
R/W
Symbol
Description
7-5
-
-
Reserved
4-0
R/W
LO_SDILO
Assign the first descriptor to be run when LINE1-Out bus master
starts.
8.2. Current Descriptor Index for LINE-Out (Offset 0001h, RO)
Table 40. Current Descriptor Index for LINE-Out
Bit
R/W
Symbol
Description
7-5
-
-
Reserved
4-0
R
LO_CDILO
Indicates the current descriptor is running.
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8.3. Last Descriptor Index for LINE-Out (Offset 0002h, R/W)
Table 41. Last Descriptor Index for LINE-Out
Bit
R/W
Symbol
Description
7-5
-
-
Reserved
4-0
R
LO_LDILO
Assign the last descriptor to be run. After the last transaction has been
completed for this last descriptor, the LINE-Out bus master should stop.
8.4. LINE-Out DMA Status Register (Offset 0003h, RO)
Table 42. LINE-Out DMA Status Register
Bit
R/W
Symbol
Description
7-2
-
-
Reserved
1
0
R
R
LO_Curr_Last
LO_LH
Current descriptor is the last descriptor. This bit will be auto-cleared
The LINE-Out bus master is not active or the last descriptor has finished
transaction. This bit will be auto cleared by H/W when bus master is active.
8.5. LINE-Out DMA Control Register
(Offset 0004h-0005h, R/W)
Table 43. LINE-Out DMA Control Register
Symbol Description
Bit
15-12
11-8
R/W
-
-
Reserved
R/W
LO_DMA_TH
LINE-OUT DMA Threshold Control.
0, 1: When the FIFO is empty, DMA will be triggered.
2, 3: When the sample number in FIFO < 2, DMA will be triggered.
…
E, F: When the sample number in FIFO < 14, DMA will be triggered.
Once LINE1-Out DMA is triggered, DMA will continuously read from
system memory until the samples number in the FIFO is equal to the
threshold.
7
R/W
LO_RS_DMA
Set to clear all registers (offset at 0000h ~ 0007h) related to DMA, and
output FIFO should be flushed. This bit is auto cleared and should be set
only when DMA is halted
6-5
4
-
-
Reserved
R/W
FIFOUNIE
FIFO Under-Run Interrupt Enable.
1: Enable interrupt caused by FIFO under-run
0: Disable interrupt caused by FIFO under-run even the ‘FIFO_un’ is set
Current Descriptor Interrupt Enable:
1: Enable interrupt caused by current descriptor has finished its transaction
0: Disable interrupt caused by current descriptor even the ‘Curr_End’ is set
Last Descriptor Interrupt Enable.
3
2
R/W
R/W
LO_CDIE
LO_LDIE
1: Enable interrupt caused by the last descriptor has finished its transaction
0: Disable interrupt caused by the last descriptor even the ‘Last_End’ is set
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Bit
R/W
Symbol
Description
1
R/W
LO_PDMA
Pause LINE-Out DMA.
1: The LINE1-Out DMA is paused. FIFO request to PCI bus is frozen,
residual data in FIFO send to AC-LINK is also froze, whether controller
should continuously send the latest data before FIFO froze depends on
the BU setting for descriptor
0: Resume DMA
0
R/W
LO_Start
LINE-Out DMA Start/Stop.
1: Start bus master transaction, and the first descriptor assigned in
‘Starting Descriptor Index’
0: Stop bus master transaction
8.6. Residual Samples Count in Current LINE-Out Descriptor
Register (Offset 0006h - 0007h, R/W)
Table 44. Residual Samples Count in Current LINE-Out Descriptor Register
Bit
R/W
Symbol
Description
15-0
R
LO_RSS
The residual samples number should be read in system memory for
current descriptor. (sample: a 16-bit word)
8.7. LINE-Out Descriptor Base Address Register (Offset 000Ch –
000Fh, R/W)
Table 45. LINE-Out Descriptor Base Address Register
Bit
R/W
Symbol
Description
31-2
R/W
LO_DBA
LINE-Out Descriptor Base Address [31:2]
LINE-Out Descriptor Base Address [1:0]. Hardwired to 0.
1-0
R
8.8. Starting Descriptor Index for LINE-In (Offset 0010h, R/W)
Table 46. Starting Descriptor Index for LINE-In
Bit
R/W
Symbol
Description
7-5
-
-
Reserved
4-0
R/W
LI_SDILI
Assign the first descriptor to be run when LINE-In bus master starts.
8.9. Current Descriptor Index for LINE-In (Offset 0011h, RO)
Table 47. Current Descriptor Index for LINE-In
Bit
R/W
Symbol
Description
7-5
-
-
Reserved
4-0
R
LI_CDILI
Indicates the current descriptor been running.
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8.10. Last Descriptor Index for LINE-In (Offset 0012h, R/W)
Table 48. Last Descriptor Index for LINE-In
Bit
R/W
Symbol
Description
7-5
-
-
Reserved
4-0
R
LI_LDILI
Assign the last descriptor to be run. After the last transaction has been
completed for this last descriptor, LINE-In bus master should stop.
8.11. LINE-In DMA Status Register (Offset 0013h, RO)
Table 49. LINE-In DMA Status Register
Bit
R/W
Symbol
Description
7-2
-
-
Reserved
1
0
R
R
LI_Curr_Last
LI_LH
Current descriptor is the last descriptor. This bit will be auto-cleared
The LINE-In bus master is not active or the last descriptor has finished
transaction. This bit will be auto-cleared by H/W when the bus master is
active.
8.12. LINE-In DMA Control Register (Offset 0014h-0015h, R/W)
Table 50. LINE-In DMA Control Register
Bit
R/W
Symbol
Description
15-12
-
-
Reserved
11-8
R/W
LI_DMA_TH
LINE-In DMA Threshold Control:
0, 1: When the FIFO is empty, DMA will be triggered.
2, 3: When the sample number in FIFO >= 2, DMA will be triggered.
…
E, F: When the sample number in FIFO >=14, DMA will be triggered.
Once the LINE-In DMA is triggered, DMA will continuously read from
System memory until the samples number in FIFO is equal to threshold.
7
R/W
LI_RS_DMA
Set to clear all registers (offset at 0010h ~ 0017h) related to DMA, and
output FIFO should be flushed. This bit is auto-cleared and should be set
only when DMA is halted.
6-5
4
-
-
Reserved
R/W
FIFOOVIE
FIFO Over-Run Interrupt Enable.
1: Enable interrupt caused by FIFO over-run
0: Disable interrupt caused by FIFO over-run even the ‘FIFO_ov’ is set
Current Descriptor Interrupt Enable.
1: Enable interrupt caused by current descriptor has finished its transaction
0: Disable interrupt caused by current descriptor even the ‘Curr_End’ is set
Last Descriptor Interrupt Enable.
3
2
R/W
R/W
LI_CDIE
LI_LDIE
1: Enable interrupt caused by the last descriptor has finished its transaction
0: Disable interrupt caused by the last descriptor even the ‘Last_End’ is set
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RTL8101L
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Bit
R/W
Symbol
Description
1
R/W
LI_PDMA
Pause LINE-In DMA.
1: The LINE1-In DMA is paused. FIFO send to PCI bus is frozen, data in
FIFO received from AC-LINK is flushed. Whether the controller should
continuously send the latest data before the FIFO froze depends on the
BU setting for the descriptor.
0: Resume DMA
0
R/W
LI_Start
LINE-In DMA Start/Stop.
1: Start bus master transaction. This is the first descriptor assigned in the
‘Starting Descriptor Index’
0: Stop bus master transaction
8.13. Residual Samples Count in Current LINE-In Descriptor
Register (Offset 0016h - 0017h, R/W)
Table 51. Residual Samples Count in Current LINE-In Descriptor Register
Bit
R/W
Symbol
Description
15-0
R
LI_RSS
The residual samples number should be read in system memory for the
current descriptor (sample: a 16-bit word).
8.14. Line-In Descriptor Base Address Register
(Offset 001Ch – 001Fh, R/W)
Table 52. Line-In Descriptor Base Address Register
Bit
R/W
Symbol
Description
31-2
R/W
LI_DBA
LINE-In Descriptor Base Address [31:2].
LINE-In Descriptor Base Address [1:0]. Hardwired to 0.
1-0
R
The LINE-In Descriptor Base Address (LI_DBA) points to the starting address of continuous 64 double-WORD descriptor’s
DMA context stored in main memory.
8.15. MC’97-Link Control Register (Offset 0020h-0021h, R/W)
Table 53. MC’97-Link Control Register
Bit
15-8
7
R/W
-
Symbol
-
Description
Reserved
R/W
MCSDLB
1: MC97_SDATAIN source comes from MC97_SDATAOUT
0: Normal (MC97_SDATAIN source comes from MC’97)
Reserved
6
5
-
-
R/W
ACLINK_WPE
AC-LINK Wake-up PME# Enable.
1: Enable a PME# when MC’97 issues a wake-up event on MC-LINK
0: Disable
If it is disabled, AC-LINK wake-up event doesn’t set PME_Status
(PCR4C.15), but AC-LINK wake-up event (ACLINK_WES) is still
indicated in INTSR.4.
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Bit
R/W
Symbol
Description
4
R/W
ACLINK_WIE
AC-LINK Wake-up Interrupt Enable.
1: Enable an interrupt when MC’97 issues a wake-up event on AC-LINK
0: Disable
When disabled, an AC-LINK wake-up event does not trigger an
interrupt, but an AC-LINK wake-up event (ACLINK_WES) is still
indicated in INTSR.4
3
2
R/W
R/W
ACLINK_OFF
AC-LINK Shut Off
1: Drive all AC-LINK outputs low if AC97_BITCLK is stopped, also
disable Line-In buffer. It’s software’s responsibility to set this bit after
power-down MC’97 command to enable AC-LINK wake-up event
function. It means that wake-up functions defined in bit[5:4] and
ACLINK_WES (INTSR.4) will be effective when this bit is set
0: Normal operation
ACLINK_WRST
MC’97 Warm Reset.
1: Writing a ‘1’ to drive AC97_SYNC high at least 1.2us
Writing a ‘1’ to this bit only effective while AC97_BITCLK is
stopped. If software wants to issue a warm reset while AC97_BITCLK
is running, the write is ignored and this bit is unchanged
0: No effect (normal)
This bit is auto cleared by hardware after warm reset had been issued.
MC’97 Cold Reset.
1: Writing a ‘1’ to drive AC97_RESET# low for at least 1.2µs
0: No effect (normal, AC97_RESET# kept as high)
This bit is auto set by hardware after cold reset had been issued.
GPI Interrupt Enable.
1
0
R/W
R/W
ACLINK_CRST
GPIE
1: The change on GPI Interrupt Status (AC-LINK status bit-0 of
slot-12) will cause an interrupt on the PCI interface
0: Interrupt is not generated even if GPI Interrupt Status is set
Note 1: AC-LINK wake-up event: AC97_SDATAIN is resumed high when AC-LINK signals are shut off.
Note 2: Bit 5 and bit 3 are sticky bits preserved by consuming power from Vaux.
8.16. MC’97-Link Status and Index Register
(Offset 0022h-0023h, R/W)
Table 54. MC’97-Link Status and Index Register
Bit
R/W
Symbol
Description
15
R
ACLINK_BZ
AC-LINK busy.
1: AC-LINK is busy with an MC’97 register read/write transaction
0: No access is in progress
It is set when controller is doing an AC-LINK read/write transaction, it is auto
cleared by hardware after the transaction has been finished or AC-LINK Read
Time-Out is set. Software should check this bit before doing an AC-LINK
Read/Write command. Any written data into bit[7:0] before this bit is cleared
by HW will be ignored.
14
R
MC_RDY
1: MC’97 is in ready state. This bit indicates the state of bit-15 in slot-0 of
AC97_SDATAIN
0: MC’97 is not ready
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Bit
R/W
Symbol
Description
13
R
ACLINK_RTO
AC-LINK Read Time-Out.
1: Set when the MC’97 does not respond to a read command within 4 AC-LINK
frames.· This bit is auto-cleared by hardware when the controller receives data
from the MC’97 within 4 frames of the read command being issued.
0: MC’97 read completed
Note: Also cleared each time the Command Bit (ACLINK_CB) is written.
12
R
ACLINK_RD
AC-LINK Read Data is Available.
1: The read data is available
0: The read data is not available
This bit is set after data has been got from AC-LINK, and is cleared each time
the Command Bit (ACLINK_CB) is written.
This bit is also set when AC-LINK Read Time-Out is set. Software should
ignore the read back data in this case.
11-10
9
-
-
Reserved
R
GPIO_BZ¸
GPIO output data status.
1: Previous data has not been sent yet
0: Previous data sent
This bit is set by hardware after software writes data into GPIOCR and the
transaction on the SDATA-OUT slot-12 has not completed. It is auto-cleared
by hardware after the transaction on SDATA-OUT slot-12 has completed.
8
R
GPIO_INT
GPIO Interrupt.
1: GPIO interrupt
0: No GPIO interrupt
This bit reflects the state of bit 0 in Slot 12 of SDATA-IN.
Bit 8 reflects the real time GPIO interrupt status on SDATA-IN from MC’97. It
is latched from SDATA-IN input slot 12 bit 0 when data is valid.
7
R/W
R/W
ACLINK_CB
ACLINK_CIP
AC-LINK Command Bit.
1: Read mixer command
0: Write mixer command
6-0
AC-LINK Mixer Command Index Port
Note: AC-LINK wake-up event. AC97_SDATAIN is resumed high when AC-LINK signals are shut off.
8.17. AC-Link Data Port (Offset 0024h - 0025h, R/W)
Table 55. AC-Link Data Port
Bit
R/W
Symbol
Description
15-0
R/W
ACLINK_DP
Write: 16 bits of mixer data written to the MC’97.
Read: 16 bits of mixer read from the MC’97.
Note: The written data should be sent to MC’97 when writing to ACLINK_CB.
The read data is effective if ACLINK_RD=1 (AC-LINK data is available). It is mapped into a different data port. Any read
from this port will always get mixer data from the MC’97.
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8.18. GPIO Control to MC’97 (Offset 0026h - 0027h, R/W)
Table 56. GPIO Control to MC’97
Bit
R/W
Symbol
Description
15-0
R/W
GPIOOD
MC’97’s GPIO output data.
Note: Bit [15:0] controls the GPIO [15:0] output of MC97. Bit 15~0 are sent on SDATA-OUT slot-12 bit 19 to bit 4.
Software should check ACSIR.9 (GPIO_Busy) before writing data. If GPIO_Busy is set by hardware and bit[15:0] are
changed, any pending data will be overwritten.
8.19. Real Time GPIO Input Data From MC’97
(Offset 0028h - 0029h, RO)
Table 57. Real Time GPIO Input Data From MC’97
Bit
R/W
Symbol
Description
15-0
R
GPIOID
MC’97’s GPIO input data.
Note 1: These bits reflect the real time GPIO input status on SDATA-IN from MC97. Bits 15~0 are latched from SDATA-IN
input slot 12 bit 19~4 when data is valid.
Note 2: These bits are real-time updated according to SDATA-IN slot-12 in every frame.
8.20. Interrupt Status Register (Offset 002Ah-002Bh, R/W)
Table 58. Interrupt Status Register
Bit
R/W
Symbol
Description
15
R/W
SERR_IE
SERR# Interrupt Enable.
1: Enable interrupt when RTL8101L signals SERR# on PCI bus
0: Disable
14
R/W
SERR_IS
SERR# Interrupt Status.
1: SERR# interrupt, RTL8101L signals SERR# on PCI bus
0: No SERR# interrupt
This controller will generate an SERR# interrupt when (SERR_IE=1)
& (SERR# Status=1, Status[14] in configuration space).
Write a ‘1’ to clear this bit and its interrupt.
Reserved
13-10
9
-
-
R/W
PCIGPIO1_IS·
PCIGPIO1 Interrupt Status.
1: PCIGPIO1 interrupt
0: No PCIGPIO1 interrupt
Note: Only when PCIGPIOx pin is used as input. Write 1 to clear this
status bit and its interrupt.
8
R/W
PCIGPIO0_IS
PCIGPIO0 Interrupt Status.
1: PCIGPIO0 interrupt
0: No PCIGPIO0 interrupt
Write 1 to clear this status bit and its interrupt.
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Bit
R/W
Symbol
Description
7
R/W
FIFO_ov
LINE-In’s FIFO Over-run.
1: FIFO error indicates a FIFO over-run. This will cause an interrupt if
the enable bit in the Control Register is set. This bit and its interrupt
should be cleared by writing a ‘1’. Data received after overrun occurs
will not enter into FIFO.
6
5
4
R/W
R/W
R/W
LI_Curr_End
LI_Last_End
Completion of current LINE-In’s descriptor.
1: The current descriptor has sent the last sample to system memory.
This will cause an interrupt if the enable bit in Control Register is set.
This bit and its interrupt should be cleared by writing a ‘1’
Completion of the last LINE-In’s descriptor.
1: The last descriptor has sent the last sample to system memory. This
will cause an interrupt if the enable bit in Control Register is set. This
bit and its interrupt should be cleared by writing a ‘1’
ACLINK_WES
AC-LINK Wake-up Event Status.
1: AC-LINK wake-up event occurred
0: No wake-up event
This bit is set if ACLINK wake-up event is detected. This controller
will generate an interrupt when (ACLINK_WES=1) &
(ACLINK_WIE=1). Write a ‘1’ to clear this bit and its interrupt.
This bit will not be set when ACLINK Shut-Off (ACCR.3) is 0. Once
it is set by an ACLINK wake-up event, it can only be cleared after
ACLINK Shut-Off is cleared.
Note: Bit 4 is a sticky bit, preserved by consuming power from Vaux.
3
2
R/W
R/W
FIFO_un
LINE1-Out FIFO Under-run.
1: FIFO error indicates a FIFO under-run. This will cause an interrupt
if the enable bit in LINE1-Out’s Control Register is set. This bit and its
interrupt should be cleared by writing a ‘1’
LO_Curr_End
Completion of current Line1-Out’s descriptor.
1: The current LINE1-Out’s descriptor has got the last sample from
system memory. This will cause an interrupt if the enable bit in Control
Register is set. This bit and its interrupt should be cleared by writing a
‘1’
1
0
R/W
R/W
LO_Last_End
GPIS
Completion of the last LINE1-Out’s descriptor.
1: The last descriptor has got the last sample from system memory.
This will cause an interrupt if the enable bit in Control Register is set.
This bit and its interrupt should be cleared by writing a ‘1’.
MC’97 GPIO Interrupt Status.
1: MC’97 GPIO interrupt. The GPIO_INT (ACSIR.8) has been set
0: No MC’97 GPIO interrupt
This bit is set if GPIO_INT (ACSIR.8) has been set. This controller
will generate an interrupt when (GPIS=1) & (GPIE=1).
Writing a ‘1’ will clear this bit and it’s interrupt.
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8.21. PCI GPIO Setup Register (Offset 002Ch-002Dh, R/W)
Table 59. PCI GPIO Setup Register
Bit
R/W
Symbol
Description
15-10
-
-
Reserved
9
R/W
PCIGPIO1_PEE
PCIGPIO1 PME# Event Enable (when PCIGPIO1 is used as input).
1: Enable
0: Disable
A low to high transaction on PCIGPIO1 will trigger the PCI PME# in
D3 state.
PCIGPIO[9:8] and PCIGPIO[1:0] are sticky bits and can be powered
by Vaux.
8
R/W
PCIGPIO0_PEE
PCIGPIO0 PME# Event Enable (when PCIGPIO0 is used as input).
1: Enable
0: Disable
A low to high transaction on PCIGPIO0 will trigger the PCI PME# in
D3 state.
PCIGPIO[9:8] and PCIGPIO[1:0] are sticky bits and can be powered
by Vaux.
7-6
5
-
-
Reserved
R/W
PCIGPIO1_IE
PCIGPIO1 interrupt Enable (when PCIGPIO1 is used as input).
1: Enable
0: Disable
A low to high transaction PCIGPIO1 will trigger the PCI interrupt.
PCIGPIO0 interrupt Enable (when PCIGPIO0 is used as input).
1: Enable
4
R/W
PCIGPIO0_IE
0: Disable
A low to high transaction PCIGPIO0 will trigger the PCI interrupt.
Reserved
3-2
1
-
-
R/W
PCIGPIO1_PC
PCIGPIO1 Primitive Control.
1: Set PCIGPIO1 as output pin
0: Set PCIGPIO1 as input pin
PCIGPIO0 Primitive Control.
1: Set PCIGPIO0 as output pin
0: Set PCIGPIO0 as input pin
0
R/W
PCIGPIO0_PC
Note: The PME# only be asserted when RTL8101L is in D3 state.
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8.22. PCI GPIO Status Register (Offset 002Eh-002Fh, R/W)
Table 60. PCI GPIO Status Register
Bit
R/W
Symbol
Description
15-10
-
-
Reserved
9
R/W
PCIGPIO1_PMES
PCIGPIO1 PME# Event Status.
1: PCIGPIO1 PME# event has occurred in D3 state.
0: No PCIGPIO1 PME# event has occurred in D3 state.
Write a 1 to clear this status bit.
8
R/W
PCIGPIO0_PMES
PCIGPIO0 PME# Event Status.
1: PCIGPIO0 PME# event has occurred in D3 state.
0: No PCIGPIO0 PME# event has occurred in D3 state.
Write a 1 to clear this status bit.
7-2
1
-
-
Reserved
R/W
PCIGPIO1_IOS
PCIGPIO1 Input/Output Status.
1: PCIGPIO1 is driven high by external device (input).
/ Drive PCIGPIO1 high (output).
0: PCIGPIO1 is driven low by external device (input).
/ Drive PCIGPIO1 low (output).
Note: When this pin is used as input, PCIGPIO[9:8] and
PCIGPIO[1:0] are sticky bits and can be powered by Vaux.
0
R/W
PCIGPIO0_IOS
PCIGPIO0 Input/Output Status.
1: PCIGPIO0 is driven high by external device (input).
/ Drive PCIGPIO0 high (output).
0: PCIGPIO0 is driven low by external device (input).
/ Drive PCIGPIO0 low (output).
Note: When this pin is used as input, PCIGPIO[9:8] and
PCIGPIO[1:0] are sticky bits and can be powered by Vaux.
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8.23. EEPROM (93C46) Command Register (Offset 0030h, R/W)
Table 61. EEPROM (93C46) Command Register
Bit
R/W
Symbol
Description
7-6
R/W
EEM1-0
Operating Mode: These 2 bits select the RTL8101L operating mode.
EEM1 EEM0 Operating Mode
0
0
Normal (RTL8101L network/host
communication mode)
0
1
Auto-load: Entering this mode will make the
RTL8101L load the contents of 93C46 like
when the RSTB signal is asserted. This
auto-load operation will take about 2 ms.
After it is completed, the RTL8101L goes
back to the normal mode automatically
(EEM1 = EEM0 = 0) and all the other
registers are reset to default values.
1
1
0
1
93C46 programming: In this mode, both
network and host bus master operations are
disabled. The 93C46 can be directly accessed
via bit3-0 which now reflect the states of
EECS, EESK, EEDI, & EEDO pins
respectively.
Config register write enable: Before writing
to CONFIG0, 1, 3, 4 registers, and bit13, 12,
8 of BMCR(offset 62h-63h), the RTL8101L
must be placed in this mode. This will
prevent RTL8101L's configurations from
accidental change.
4-5
3
-
-
Reserved
R/W
R/W
R/W
R
EECS
EESK
EEDI
EEDO
These bits reflect the state of EECS, EESK, EEDI, and EEDO pins in
auto-load or 93C46 programming mode.
2
1
0
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8.24. Context For Line-Out Descriptor (Offset 0000h-00FFh)
Table 62. Context For Line-Out Descriptor
Description
Memory Address
LO_DBA+0000h~0003h
DMAAddress for Line-Out Descriptor 00h
Buffer Size for Line-Out Descriptor 00h
DMAAddress for Line-Out Descriptor 01h
Buffer Size for Line-Out Descriptor 01h
LO_DBA+0004h~0007h
LO_DBA+0008h~000Bh
LO_DBA+000Ch~000Fh
:
:
:
:
LO_DBA+00F0h~00F3h
LO_DBA+00F4h~00F7h
LO_DBA+00F8h~00FBh
LO_DBA+00FCh~00FFh
DMAAddress for Line-Out Descriptor 1Eh
Buffer Size for Line-Out Descriptor 1Eh
DMAAddress for Line-Out Descriptor 1Fh
Buffer Size for Line-Out Descriptor 1Fh
8.25. Context For Line-In Descriptor (Offset 0000h-00FFh)
Table 63. Context For Line-In Descriptor
Memory Address
Description
LI_DBA+0000h~0003h
DMAAddress for Line-In Descriptor 00h
Buffer Size for Line-In Descriptor 00h
DMAAddress for Line-In Descriptor 01h
Buffer Size for Line-In Descriptor 01h
:
LI_DBA+0004h~0007h
LI_DBA+0008h~000Bh
LI_DBA+000Ch~000Fh
:
:
:
LI_DBA+00F0h~00F3h
LI_DBA+00F4h~00F7h
LI_DBA+00F8h~00FBh
LI_DBA+00FCh~00FFh
DMAAddress for Line-In Descriptor 1Eh
Buffer Size for Line-In Descriptor 1Eh
DMAAddress for Line-In Descriptor 1Fh
Buffer Size for Line-In Descriptor 1Fh
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8.26. Descriptor Definition
DMA Address for Line1-Out/In Descriptor X
LxDBA+00H~03H:
31
2
1
0
0
0
DMA Start Address [31:2]
Buffer Size for Line1-Out/In Descriptor X
LxDBA+04H~07H:
31
I
30
29
15
14
1
0
0
BU
Reserved
Buffer Length
DMA Start Address [31:0]:
This is the physical start address for the descriptor’s DMA operation.
I:
When set to a 1 by S/W, the controller should issue an interrupt upon completion of this buffer.
BU:
If set to a 0, the controller should continuously send the last valid data when FIFO is under-run (keep the
last data, and validate the tag bit for Slot-5 on AC_DOUT).
If set to a 1, the controller continuously sends the last invalid data when FIFO is empty or under-run (keep
the last data, but invalidate the tag bit for Slot-5 on AC_DOUT).
Note: The BU bit is only effective for LINE1-Out master.
Buffer Length [14:0]:
The size of the data buffer is measured in 16-bit samples. The maximum number of samples is 32767. A
value of 0 means there is no sample transferred into this buffer. To achieve an efficient PCI transaction, the
buffer length must be an even number.
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9. EEPROM (93C46) Contents
The 93C46 is a 1K-bit EEPROM. Although it is actually addressed by words, its contents are listed below
by bytes for convenience. After the valid duration of the RSTB pin or auto-load command in the 9346CR,
the RTL8101L performs a series of EEPROM read operations from the 93C46 addresses 00H to 31H.
We recommend you obtain Realtek approval before changing the default settings of the EEPROM.
Table 64. EEPROM (93C46) Contents
Bytes
00h
Contents
29h
Description
These 2 bytes contain the ID code word for the RTL8101L. The RTL8101L will load
the contents of EEPROM into the corresponding location if the ID word (8129h) is
correct. Otherwise, the RTL8101L will not proceed with the EEPROM auto-load
process.
01h
81h
02h-05h
-
Reserved. The RTL8101L no longer supports auto-load of Vender ID and Device ID.
The default values of VID and DID are hex 10EC and 8139, respectively.
06h-07h
08h-09h
0Ah
SVID
SMID
PCI Subsystem Vendor ID, PCI configuration space offset 2Ch-2Dh.
PCI Subsystem ID, PCI configuration space offset 2Eh-2Fh.
PCI Minimum Grant Timer, PCI configuration space offset 3Eh.
PCI Maximum Latency Timer, PCI configuration space offset 3Fh.
MNGNT
MXLAT
MSRBMCR
0Bh
0Ch
Bits 7-6 map to bits 7-6 of the Media Status register (MSR); Bits 5, 4, 0 map to bits 13,
12, 8 of the Basic Mode Control register (BMCR); Bits 3-2 are reserved. If the network
speed is set to Auto-Detect mode (i.e. NWay mode), then Bit 1=0 means the local
RTL8101L supports flow control (IEEE 802.3x). In this case, Bit 10=1 in the
Auto-negotiation Advertisement Register (offset 66h-67h), and Bit 1=1 means the
local RTL8101L does not support flow control. In this case, Bit 10=0 in
Auto-negotiation Advertisement. This is because there are NWay switch hubs which
keep sending flow control pause packets for no reason, if the link partner supports
NWay flow control.
0Dh
CONFIG3
RTL8101L Configuration register 3, operational register offset 59H.
0Eh-13h
Ethernet ID
Ethernet ID. After an auto-load command or hardware reset, the RTL8101L loads the
Ethernet ID to IDR0-IDR5 of RTL8101L's I/O registers.
14h
15h
CONFIG0
CONFIG1
PMC
RTL8101L Configuration register 0, operational registers offset 51h.
RTL8101L Configuration register 1, operational registers offset 52h.
Reserved. Do not change this field without Realtek approval.
Power Management Capabilities. PCI configuration space address 52h and 53h.
Reserved. Do not change this field without Realtek approval.
Power Management Control/Status. PCI configuration space address 55h.
Reserved. Do not change this field without Realtek approval.
RTL8101L Configuration register 4, operational registers offset 5Ah.
Reserved. Do not change this field without Realtek approval.
16h-17h
18h
19h
PMCSR
CONFIG4
1Ah-1Dh
PHY1_PARM_U
PHY Parameter 1-U for RTL8101L. Operational registers of the RTL8101L are from
78h to 7Bh.
1Eh
PHY2_PARM_U
Reserved. Do not change this field without Realtek approval.
PHY Parameter 2-U for RTL8101L. Operational register of the RTL8101L is 80h.
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Bytes
Contents
Description
1Fh
CONFIG_5
Do not change this field without Realtek approval.
Bit7-6: Reserved.
Bit5-4: Multi-function Select:
00b: Ethernet Controller Only
01b: MC’97 Controller Only
10b: Ethernet+MC’97 Controllers
11b:After ver F Ethernet+Auto-detect MC’97 Controllers
If the RTL8101L detects the MC’97, the RTL8101L is set to
Multi-function. Otherwise it set to Ethernet only. The MC’97 is only
detected during power on or reset.
Note: For versions A to E, 11b=Ethernet+MC’97 Controllers
Bit3: Reserved.
Bit2: Link Down Power Saving mode:
Set to 1: Disable.
Set to 0: Enable. When the cable is disconnected (Link Down), the analog part will
power itself down (PHY Tx part and part of twister) automatically, except PHY Rx
part and part of twister to monitor SD signal in case the cable is re-connected and
the Link needs to be established again.
Bit1: LANWake signal Enable/Disable
Set to 1: Enable LANWake signal.
Set to 0: Disable LANWake signal.
Bit0: PME_Status bit properties
Set to 1: The PME_Status bit can be reset by PCI reset or by software if
D3cold_support_PME is 0. If D3cold_support_PME=1, the PME_Status bit is a
sticky bit.
Set to 0: The PME_Status bit is always a sticky bit and can only be reset by
software.
20h-21h
22h-23h
24h-25h
26h-27h
28h-2Bh
MC97_VID
MC97_DID
MC97_SVID
MC97_SDID
Vendor ID of the MC’97 Controller.
Device ID of the MC’97 Controller.
Sub-Vendor ID of the MC’97 Controller.
Sub-Device ID of the MC’97 Controller.
PHY1_PARM_T Reserved. Do not change this field without Realtek approval.
PHY Parameter 1-T for the RTL8101L. Operational registers of the RTL8101L are
from 78h to 7Bh.
2Ch
PHY2_PARM_T Reserved. Do not change this field without Realtek approval.
2Dh-31h
32h-33h
-
Reserved.
CheckSum
Reserved. Do not change this field without Realtek approval.
Checksum of the EEPROM content.
34h-3Eh
3Fh
-
Reserved. Do not change this field without Realtek approval.
Reserved. Do not change this field without Realtek approval.
PXE ROM code parameter.
PXE_Para
40h-7Fh
VPD_Data
VPD data field. Offset 40h is the start address of the VPD data.
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RTL8101L
Datasheet
9.1. EEPROM Related Ethernet MAC Registers
Table 65. EEPROM Related Ethernet MAC Registers
Offset
Name
Type
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00h-05h IDR0 – IDR5 R/W*
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BS2
-
-
BS1
-
-
BS0
-
51h
52h
58h
63H
59h
5Ah
CONFIG0
R
*
-
W
R
CONFIG1
LEDS1
LEDS1
LEDS0
LEDS0
DVRLOAD LWACT MEMMAP IOMAP
VPD
VPD
PMEN
PMEN
*
DVRLOAD LWACT
-
-
W
R
TxFCE
TxFCE
RxFCE
RxFCE
-
-
-
-
-
-
-
-
-
-
-
-
*
W
R
MSRBMCR
-
-
-
-
Spd_Set
Spd_Set
ANE
ANE
-
-
-
-
-
-
FUDUP
FUDUP
*
W
R
CONFIG3
CONFIG4
GNTDel PARM_EN
Magic
Magic
LinkUp
LinkUp
-
-
-
-
-
-
FBtBEn
-
*
-
PARM_EN
AnaOff
W
*
RxFIFO
AutoClr
LongWF
LWPME
-
LWPTN
LDPS
-
-
R/W
78h-7Bh PHY1_PARM R/W**
7Ch-7Fh TW1_PARM R/W**
TW2_PARM
32-bit Read Write
32-bit Read Write
32-bit Read Write
8-bit Read Write
80h
PHY2_PARM R/W**
D8h
CONFIG5
*
-
-
-
-
-
LAN
Wake
PME_ST
S
R/W
*'
*
Registers marked with type = 'W can be written only if bits EEM1=EEM0=1.
**'
** Registers marked with type = 'W can be written only if bits EEM1=EEM0=1 and CONFIG3<PARM_EN> = 0.
9.2. EEPROM Related Power Management Registers
Table 66. EEPROM Related Power Management Registers
Configuration Name Type
Space Offset
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
52h
53h
55h
PMC
R
R
Aux_I_b1
Aux_I_b0
DSI
Reserved PMECLK
Version
PME_D3cold PME_D3hot PME_D2 PME_D1 PME_D0
D2
D1
Aux_I_b2
PME_En
PME_En
PMCSR
R
PME_Status
PME_Status
-
-
-
-
-
-
-
-
-
-
-
-
W
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RTL8101L
Datasheet
10. PCI Configuration Space Registers
10.1. PCI Configuration Space Registers
No.
00h
01h
02h
03h
04h
Name
Type
R
Bit7
Bit6
Bit5
Bit4
Bit3
1
Bit2
1
Bit1
Bit0
VID
1
1
1
0
0
0
0
0
0
0
1
1
R
0
0
0
1
0
0
DID
R
0
0
1
1
1
0
R
1
0
0
0
0
0
Command
R
0
PERRSP
0
0
-
BMEN
MEMEN
MEMEN
IOEN
IOEN
W
R
-
PERRSP
-
-
-
BMEN
05h
0
0
0
0
0
-
FBTBEN SERREN
W
R
-
-
-
-
-
-
-
SERREN
06h
07h
Status
FBBC
0
0
NewCap
-
0
0
0
R
DPERR
SSERR
RMABT
RTABT
STABT
DST1
DST0
DPD
W
R
DPERR
SSERR
RMABT
RTABT
STABT
-
-
DPD
08h Revision ID
0
0
0
0
0
0
0
0
09h
0Ah
0Bh
0Ch
0Dh
PIFR
SCR
BCR
CLS
LTR
R
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
1
R
0
0
0
0
0
0
0
0
R
LTR7
LTR6
LTR5
LTR4
LTR3
LTP2
LTR1
LTR0
LTR0
0
W
R
LTR7
LTR6
LTR5
LTR4
LTR3
LTP2
LTR1
0Eh
0Fh
10h
HTR
BIST
IOAR
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
IOIN
-
W
R/W
R/W
R/W
R
-
-
-
-
-
-
-
11h
12h
13h
14h
IOAR15
IOAR23
IOAR31
0
IOAR14
IOAR22
IOAR30
0
IOAR13
IOAR21
IOAR29
0
IOAR12
IOAR20
IOAR28
0
IOAR11
IOAR19
IOAR27
0
IOAR10
IOAR18
IOAR26
0
IOAR9
IOAR17
IOAR25
0
IOAR8
IOAR16
IOAR24
MEMIN
-
MEMAR
W
R/W
R/W
R/W
-
-
-
-
-
-
-
15h
16h
17h
MEM15
MEM23
MEM31
MEM14
MEM22
MEM30
MEM13
MEM21
MEM29
MEM12
MEM20
MEM28
MEM11
MEM19
MEM27
MEM10
MEM18
MEM26
MEM9
MEM17
MEM25
MEM8
MEM16
MEM24
18h-2
Bh
RESERVED
2Ch
2Dh
2Eh
2Fh
30h
SVID
SMID
BMAR
R
R
SVID7
SVID15
SMID7
SMID15
0
SVID6
SVID14
SMID6
SMID14
0
SVID5
SVID13
SMID5
SMID13
0
SVID4
SVID12
SMID4
SMID12
0
SVID3
SVID11
SMID3
SMID11
0
SVID2
SVID1
SVID0
SVID8
SMID0
SMID8
BROMEN
BROMEN
0
SVID10
SVID9
R
SMID2
SMID1
R
SMID10
SMID9
R
0
-
0
-
W
R
-
-
-
-
-
31h
BMAR15
BMAR15
BMAR23
BMAR31
BMAR14
BMAR14
BMAR22
BMAR30
BMAR13 BMAR12 BMAR11
BMAR13 BMAR12 BMAR11
0
-
0
-
W
R/W
R/W
-
32h
33h
BMAR21 BMAR20 BMAR19 BMAR18 BMAR17 BMAR16
BMAR29 BMAR28 BMAR27 BMAR26 BMAR25 BMAR24
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RTL8101L
Datasheet
No.
Name
Type
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
34h
Cap_Ptr
R
0
1
0
1
0
0
0
0
35h-3
Bh
RESERVED
3Ch
3Dh
3Eh
3Fh
ILR
IPR
R/W
R
IRL7
ILR6
ILR5
ILR4
ILR3
ILR2
ILR1
ILR0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
MNGNT
MXLAT
R
R
40h–
4Fh
RESERVED
50h
51h
52h
53h
54h
PMID
NextPtr
PMC
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
R
Aux_I_b1
Aux_I_b0
DSI
Reserved PMECLK
Version
D1
R
PME_D3cold PME_D3hot PME_D2 PME_D1 PME_D0
D2
0
-
Aux_I_b2
PMCSR
R
0
0
-
0
-
0
-
0
-
Power State
Power State
PME_En
W
R
-
55h
PME_Status
PME_Status
-
-
-
-
-
-
-
W
-
-
-
-
-
PME_En
56h–
5Fh
RESERVED
60h
61h
62h
VPDID
NextPtr
R
R
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
Flag VPD
Address
R/W VPDADDR VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD
7
6
R5
R4
R3
R2
R1
R0
63h
R/W
Flag
VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD
14
R13
R12
R11
R10
R9
R8
64h
65h
66h
67h
VPD Data
R/W
R/W
R/W
R/W
Data7
Data15
Data23
Data31
Data6
Data14
Data22
Data30
Data5
Data4
Data3
Data2
Data1
Data9
Data17
Data25
Data0
Data8
Data16
Data24
Data13
Data21
Data29
Data12
Data20
Data28
Data11
Data19
Data27
Data10
Data18
Data26
68h-F
Fh
RESERVED
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RTL8101L
Datasheet
10.2. PCI Configuration Space Functions
The PCI configuration space is intended for configuration, initialization, and catastrophic error handling
functions. The functions of the RTL8101L’s configuration space are described below.
VID: Vendor ID. This field defaults to a value of 10ECh (Realtek Semiconductor’s PCI Vendor ID).
DID: Device ID. This field defaults to a value of 8139h.
Command: The command register is a 16-bit register used to provide coarse control over a device’s ability
to generate and respond to PCI cycles.
Table 67. PCI Configuration Space Functions
Bit
Symbol
Description
15-10
-
Reserved
9
FBTBEN
Fast Back-To-Back Enable: Config3<FBtBEn>=0:Read as 0. Write operation has no effect. The
RTL8101L will not generate Fast Back-to-back cycles. When Config3<FbtBEn>=1, this read/write
bit controls whether or not a master can do fast back-to-back transactions to different devices.
Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1 means
the master is allowed to generate fast back-to-back transaction to different agents. A value of 0
means fast back-to-back transactions are only allowed to the same agent. This bit’s state after RST#
is 0.
8
7
6
SERREN
ADSTEP
PERRSP
System Error Enable: When set to 1, the RTL8101L asserts the SERRB pin when it detects a parity
error on the address phase (AD<31:0> and CBEB<3:0> ).
Address/Data Stepping: Read as 0, write operation has no effect. The RTL8101L never performs
address/data stepping.
Parity Error Response: When set to 1, the RTL8101L will assert the PERRB pin on the detection of
a data parity error when acting as the target, and will sample the PERRB pin as the master. When set
to 0, any detected parity error is ignored and the RTL8101L continues normal operation.
Parity checking is disabled after hardware reset (RSTB).
5
4
3
VGASNOOP
MWIEN
VGA palette SNOOP: Read as 0, write operation has no effect.
Memory Write and Invalidate cycle Enable: Read as 0, write operation has no effect.
SCYCEN
Special Cycle Enable: Read as 0, write operation has no effect. The RTL8101L ignores all special
cycle operations.
2
BMEN
Bus Master Enable: When set to 1, the RTL8101L is capable of acting as a bus master. When set to
0, it is prohibited from acting as a PCI bus master.
For normal operation this bit must be set by the system BIOS.
1
0
MEMEN
IOEN
Memory Space Access: When set to 1, the RTL8101L responds to memory space accesses. When
set to 0, the RTL8101L ignores memory space accesses.
I/O Space Access: When set to 1, the RTL8101L responds to IO space access. When set to 0, the
RTL8101L ignores I/O space accesses.
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Datasheet
10.3. PCI Configuration Space Status
Status: The status register is a 16-bit register used to record status information of PCI bus related events.
Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set.
Table 68. PCI Configuration Space Status
Bit
Symbol Description
15
DPERR
Detected Parity Error.
When set indicates that the RTL8101L detected a parity error, even if parity error handling is disabled
in the command register PERRSP bit.
14
13
SSERR
Signaled System Error.
When set indicates that the RTL8101L asserted the system error pin, SERRB.
Writing a 1 clears this bit to 0.
RMABT
Received Master Abort.
When set indicates that the RTL8101L terminated a master transaction with master abort.
Writing a 1 clears this bit to 0.
12
11
RTABT
STABT
DST1-0
DPD
Received Target Abort.
When set indicates that the RTL8101L master transaction was terminated due to a target abort. Writing
a 1 clears this bit to 0.
Signaled Target Abort.
Set to 1 whenever the RTL8101L terminates a transaction with target abort. Writing a 1 clears this bit
to 0.
10-9
8
Device Select Timing.
These bits encode the timing of DEVSELB. They are set to 01b (medium), indicating the RTL8101L
will assert DEVSELB two clocks after FRAMEB is asserted.
Data Parity error Detected.
This bit sets when the following conditions are met:
•
The RTL8101L asserts parity error (PERRB pin) or it senses the assertion of the PERRB pin by
another device.
•
•
The RTL8101L operates as a bus master for the operation that caused the error.
The Command register PERRSP bit is set.
Writing a 1 clears this bit to 0.
7
6
FBBC
UDF
Fast Back-To-Back Capable.
Config3<FbtBEn>=0, Read as 0. Write operation has no effect.
Config3<FbtBEn>=1, Read as 1.
User Definable Features.
Read as 0. Write operation has no effect.
The RTL8101L does not support UDF.
66MHz Capable.
Read as 0. Write operation has no effect.
The RTL8101L has no 66MHz capability.
New Capability.
5
66MHz
NewCap
-
4
Config3<PMEn>=0, Read as 0. Write operation has no effect.
Config3<PMEn>=1, Read as 1.
0-3
Reserved.
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RTL8101L
Datasheet
RID: Revision ID Register
The Revision ID register is an 8-bit register that specifies the RTL8101L controller revision number.
PIFR: Programming Interface Register
The programming interface register is an 8-bit register that identifies the programming interface of the
RTL8101L controller.
PIFR = 00h (the PCI specification does not define any specific value for network devices).
SCR: Sub-Class Register
The Sub-class register is an 8-bit register that identifies the function of the RTL8101L.
SCR = 00h indicates that the RTL8101L is an Ethernet controller.
BCR: Base-Class Register
The Base-Class Register is an 8-bit register that broadly classifies the function of the RTL8101L.
BCR = 02h indicates that the RTL8101L is a network controller.
CLS: Cache Line Size
Reads will return a 0, writes are ignored.
LTR: Latency Timer Register
Specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8101L.
When the RTL8101L asserts FRAMEB, its latency timer starts to count. If the RTL8101L deasserts FRAMEB
prior to count expiration, the contents of the latency timer are ignored. Otherwise, after the count expires, the
RTL8101L initiates transaction termination as soon as its GNTB is deasserted. Software is able to read or write,
and the default value is 00H.
HTR: Header Type Register
Reads will return a 0, writes are ignored.
BIST: Built-In Self Test
Reads will return a 0, writes are ignored.
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Datasheet
IOAR: Input Output Address Register
This register specifies the base IO address that is required to build an address map during configuration. It
also specifies the number of bytes required as well as an indication that it can be mapped into IO space.
Table 69. Input Output Address Register
Bit
Symbol
Description
31-8
IOAR31-8
Base IO Address.
This is set by software to the base IO address for the operational register map.
IO Size.
7-2
IOSIZE
Read back as 0. This allows the PCI bridge to determine that the RTL8101L requires 256 bytes of IO
space.
1
0
-
Reserved.
IOIN
IO Space Indicator.
Read only. Set to 1 by the RTL8101L to indicate that it is capable of being mapped into IO space.
MEMAR: Memory Address Register
This register specifies the base memory address for memory accesses to the RTL8101L operational
registers. This register must be initialized prior to accessing any of the RTL8101L’s registers with memory
access.
Table 70. Base Memory Address for Memory Accesses
Bit
Symbol Description
31-8
MEM31-8
MEMSIZE
MEMPF
Base Memory Address.
This is set by software to the base address for the operational register map.
Memory Size.
These bits return 0, which indicates that the RTL8101L requires 256 bytes of Memory Space.
Memory Pre-Fetchable.
7-4
3
Read only. Set to 0 by the RTL8101L.
Memory Location Select.
2-1
MEMLOC
Read only. Set to 0 by the RTL8101L.
This indicates that the base register is 32-bits wide and can be placed anywhere in the 32-bit memory
space.
0
MEMIN
Memory Space Indicator.
Read only. Set to 0 by the RTL8101L to indicate that it is capable of being mapped into memory
space.
SVID: Subsystem Vendor ID
This field will be set to a value corresponding to the PCI Subsystem Vendor ID in the external EEPROM. If
there is no EEPROM, this field will default to a value of 10ECh (Realtek Semiconductor’s PCI Subsystem
Vendor ID).
SMID: Subsystem ID
This field will be set to a value corresponding to the PCI Subsystem ID in the external EEPROM. If there is
no EEPROM, this field will default to a value of 8139h.
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RTL8101L
Datasheet
BMAR: Base Memory Address Register
This register specifies the base memory address for memory accesses to the RTL8101L’s operational
registers. This register must be initialized prior to accessing any RTL8101L register with memory access.
Table 71. Base Memory Address for Memory Accesses
Bit
Symbol
Description
31-18
BMAR31-18
Boot ROM Base Address
17-11
ROMSIZE
These bits indicate how many Boot ROM spaces are to be supported.
The Relationship between Config 0 <BS2:0> and BMAR17-11 is the following:
BS2 BS1 BS0 Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No Boot ROM, BROMEN=0 (R)
8K Boot ROM, BROMEN (R/W), BMAR12-11 = 0 (R), BMAR17-13 (R/W)
16K Boot ROM, BROMEN (R/W), BMAR13-11 = 0 (R), BMAR17-14 (R/W)
32K Boot ROM, BROMEN (R/W), BMAR14-11 = 0 (R), BMAR17-15 (R/W)
64K Boot ROM, BROMEN (R/W), BMAR15-11 = 0 (R), BMAR17-16 (R/W)
128K Boot ROM, BROMEN(R/W), BMAR16-11=0 (R), BMAR17 (R/W)
unused
unused
10-1
0
-
Reserved (read back 0)
BROMEN
Boot ROM Enable: This is used by the PCI BIOS to enable accesses to Boot ROM.
ILR: Interrupt Line Register
The Interrupt Line Register is an 8-bit read-only register used to indicate the routing of the interrupt. It is
written by the POST software to set an interrupt line for the RTL8101L.
IPR: Interrupt Pin Register (Read Only IPR = 01H)
The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the RTL8101L. The
RTL8101L uses an INTA interrupt pin.
MNGNT: Minimum Grant Timer (Read Only)
Specifies the minimum burst period the RTL8101L needs at a 33MHz clock rate, in units of 1/4
microseconds. This field will be set to a value from the external EEPROM. If there is no EEPROM, this
field will default to a value of 20h.
MXLAT: Maximum Latency Timer (Read Only)
Indicates how long the RTL8101L is allowed access to the PCI bus, in units of 1/4 microseconds. This field
will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value
of 20h.
Cap_ID: Capability ID: Read only
Read as 01h (PCI bus power management capability ID)
Next_Item_Ptr: Next Item Pointer: Read only
Read as 00h (Last capability list)
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Datasheet
Power Management Capabilities:
Bit
Type
Function
15
R
Read as 1 (PME# can be asserted from D3cold
)
14
13
12
11
10
9
R
R
R
R
R
R
R
R
R
R
R
Read as 1 (PME# can be asserted from D3hot)
Read as 0 (PME# can not be asserted from D2)
Read as 0 (PME# can not be asserted from D1)
Read as 0 (PME# can not be asserted from D0)
Read as 0 (Not support D2 state)
Read as 0 (Not support D1 state)
8:6
5
Read as 010 (consume maximum 100mA from Vaux
)
Read as 1 (Device Specific Initialization (DSI) required)
Read as 0
4
3
Read as 0 (PCI clock is not required for PME# operation)
Read as 010b
2:0
(PCI Power Management Interface Specification Revision 1.1)
Once Vaux is not supplied, bit[15] reads as 0 to indicate PME# is not supported in D3(cold), and bit[8:6] reads as 000b.
PMCSR:
Bit
Type
Function
15
R/W
PME_Status.
0: Normal
1: PME# asserted
Data_Scale.
Read as 00b
Data_Select.
Read as 0000b
PME_En.
14:13
12:9
8
R
R
R/W
0: Disable
1: Enable
7:2
1:0
R
Read as 0
R/W
PowerState.
00: D0
01: Reserved
10: Reserved
11: D3hot
Writing ‘1’ to bit 15 will clear it and cause the function to stop asserting PME#. Write a ‘0’ has no effect. Note that bit 15 is
independent of bit 8.
Writing ‘01’ and ‘10’ to bit 1,0 has no effect on the RTL8101L. The RTL8101L terminates the cycle normally and discards the
data (bit 1, 0 only).
Bit 15 and bit 8 are sticky. The System OS should clear them after booting. These 2 bits consume power from Vaux. Bits except bit
15/8 consume power from normal power source.
Because PCI 2.3 supports auxiliary power Vaux, the chip designer must pay attention to the interface of PME# related circuit and
non-PME# related circuit.
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10.4. Default Values After Power-on (RSTB Asserted)
Table 72. Default Values After Power-on (RSTB Asserted)
No.
00h
01h
02h
03h
04h
Name
VID
Type
R
Bit7
1
Bit6
1
Bit5
1
Bit4
0
Bit3
1
Bit2
Bit1
Bit0
0
1
0
0
0
0
0
0
0
0
0
R
0
0
0
1
0
0
DID
R
0
0
1
1
1
1
R
1
0
0
0
0
1
Command
R
0
0
0
0
0
0
W
R
-
PERRSP
-
-
-
BMEN MEMEN
IOEN
05h
0
0
0
0
0
0
0
0
W
R
-
-
-
-
-
-
0
-
SERREN
06h
07h
Status
0
0
0
NewCap
0
0
0
R
0
0
0
0
0
0
1
0
W
R
DPERR
SSERR
RMABT
RTABT
STABT
-
-
DPD
08h
09h
0Ah
0Bh
0Ch
0Dh
Revision ID
PIFR
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
SCR
R
0
0
0
0
0
0
0
0
BCR
R
0
0
0
0
0
0
1
0
CLS
R
0
0
0
0
0
0
0
0
LTR
R
0
0
0
0
0
0
0
0
W
R
LTR7
LTR6
LTR5
LTR4
LTR3
LTP2
0
LTR1
LTR0
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
|
HTR
BIST
IOAR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
R
0
R
0
R/W
R/W
R/W
R
0
0
0
MEMAR
0
R/W
R/W
R/W
0
0
0
RESERVED(ALL 0)
2Bh
2Ch
2Dh
2Eh
2Fh
30h
SVID
SMID
BMAR
R
R
1
0
0
1
0
-
1
0
0
0
0
-
1
0
1
0
0
-
0
1
1
0
0
-
1
0
1
0
0
-
1
0
0
0
0
-
0
0
0
0
0
-
0
1
R
1
R
1
R
BROMEN
W
R
BROMEN
31h
BMAR15 BMAR14 BMAR13 BMAR12 BMAR11
BMAR15 BMAR14 BMAR13 BMAR12 BMAR11
0
-
0
-
0
-
W
R/W
R/W
R
32h
33h
34h
BMAR23 BMAR22 BMAR21 BMAR20 BMAR19 BMAR18 BMAR17 BMAR16
BMAR31 BMAR30 BMAR29 BMAR28 BMAR27 BMAR26 BMAR25 BMAR24
Cap-Ptr
Ptr7
Ptr6
Ptr5
Ptr4
Ptr3
Ptr2
Ptr1
Ptr0
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No.
35h
|
Name
Type
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RESERVED(ALL 0)
3Bh
3Ch
3Dh
3Eh
3Fh
40h
|
ILR
IPR
R/W
R
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
MNGNT
MXLAT
R
0
R
0
RESERVED(ALL 0)
-
FFh
10.5. PCI Power Management Functions
The RTL8101L complies with ACPI (Rev 1.1), PCI Power Management (Rev 1.1), and the Device Class
Power Management Reference Specification (V1.0a), such as to support an Operating System-Directed
Power Management (OSPM) environment. To support this, the RTL8101L provides the following
capabilities:
• The RTL8101L can monitor the network for a Wakeup Frame (AMD Magic Packet, LinkChg,
Microsoft® wake-up frame), and notify the system via PME# should such a packet or event arrive.
Then the system can be restored to a working state to process incoming jobs.
• The RTL8101L can be isolated from the PCI bus automatically via the auxiliary power circuit when the
PCI bus is in B3 state, i.e. the power on the PCI bus is removed. The RTL8101L can be disabled when
needed by pulling the isolate pin low to 0V.
10.5.1. Power Down Mode
When the RTL8101L is in power down mode (D1 ~ D3):
• The Rx state machine is stopped and the RTL8101L monitors the network for wakeup events. The
RTL8101L will not reflect the status of any incoming packets in the ISR register and will not receive
any packets into the Rx FIFO.
• The FIFO status and the packets that are already in the Rx FIFO before entering power down mode are
held by the RTL8101L during power down mode.
• Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held.
• After restoration to a D0 state, PCI bus master mode transfers data to the Tx FIFO that was not moved
into the Tx FIFO before the last break. Apacket that was not transmitted completely before power down
mode is transmitted again.
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D3cold_support_PME bit (bit15, PMC register) & Aux_I_b2:0 (bit8:6, PMC register) in PCI
configuration space
• If 9346 D3cold_support_PME bit (bit15, PMC) = 1, the above 4 bits depend on the existence of
Aux power.
• If 9346 D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0’s.
Examples:
9346 D3c_support_PME = 1
• If Aux. power exists, then PMC in PCI config space is the same as 9346 PMC,
i.e. if 9346 PMC = C2 F7, then PCI PMC = C2 F7.
• Aux. power is absent, then PMC in PCI config space is the same as 9346 PMC except the above
4 bits are all 0’s. I.e. if 9346 PMC = C2 F7, then PCI PMC = 02 76.
Note: In this case, if wakeup support is desired when the main power is off, it is suggested that the
EEPROM PMC be set to: C2 F7 (Realtek default value). It is not recommended to set the D0_support_PME
bit to 1.
9346 D3c_support_PME = 0,
• If Aux. power exists, then PMC in PCI config space is the same as 9346 PMC,
i.e. if 9346 PMC = C2 77, then PCI PMC = C2 77.
• If Aux. power is absent, then PMC in PCI config space is the same as 9346 PMC except the above
4 bits are all 0’s, i.e. if 9346 PMC = C2 77, then PCI PMC = 02 76.
Note: In this case, if wakeup support is not desired when main power is off, it is suggested that the 9346
PMC be set to 02 76. It is not recommended to set the D0_support_PME bit to 1.
Link Wakeup
Link Wakeup occurs when the following conditions are met:
• The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8101L is
in isolation state, or the PME# can be asserted in the current power state.
• The Link status is re-established.
Magic Packet Wakeup
A Magic Packet Wakeup occurs when the following conditions are met:
• The destination address of the received Magic Packet matches.
• The received Magic Packet does not contain a CRC error.
• The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8101L is in
isolation state, or the PME# can be asserted in the current power state.
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• The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in
any part of a valid (Fast) Ethernet packet.
A Wakeup Frame event occurs only when the following conditions are met:
• The destination address of the received Wakeup Frame matches.
• The received Wakeup Frame does not contain a CRC error.
• The PMEn bit (CONFIG1#0) is set to 1.
• The 8-bit CRC* (or 16-bit CRC**) of the received Wakeup Frame matches with the 8-bit CRC (or
16-bit CRC) of the sample Wakeup Frame pattern received from the local machine’s OS.
• The last masked byte*** of the received Wakeup Frame matches with the last masked byte*** of the
sample Wakeup Frame pattern provided by the local machine’s OS (In Long Wakeup Frame mode, the
last masked byte field is replaced with the high byte of the 16-bit CRC).
*8-bit CRC:
8-bit CRC logic is used to generate an 8-bit CRC from the masked bytes of the received Wakeup Frame
packet within offset 12 to 75. Software should calculate the 8-bit Power Management CRC for each specific
sample wakeup frame and store the calculated CRC in the corresponding CRC register for the RTL8101L
to check whether there is a Wakeup Frame coming in.
**16-bit CRC: (Long Wakeup Frame mode, the mask bytes cover from offset 0 to 127)
Long Wakeup Frame: The RTL8101L also supports 3 long Wakeup Frames. If the range of mask bytes of
the sample Wakeup Frame, passed down by the OS to the driver, exceeds the range from offset 12 to 75, the
related registers of wakeup frame 2 and 3 can be merged to support one long wakeup frame by setting the
LongWF (bit0, CONFIG4). Thus, the range of effective mask bytes extends from offset 0 to 127. The low
byte and high byte of the calculated 16-bit CRC should be put into register CRC2 and LSBCRC2
respectively. The mask bytes (16 bytes) should be stored in register Wakeup2 and Wakeup3. The CRC3
and LSBCRC3 have no meaning in this case and should be reset to 0. Long Wakeup Frame pairs are frames
4 and 5, and frames 6 and 7. The CRC5, CRC7, LSBCRC5, and LSBCRC7 have no meaning in this case
and should be set to 0 if the RTL8101L is to support long Wakeup Frames. The RTL8101L supports
2 normal wakeup frames and 3 long wakeup frames.
***Last Masked Byte:
The last byte of the masked bytes of the received Wakeup Frame packet within offset 12 to 75 (in 8-bit CRC
mode) should match the last byte of the masked bytes of the sample Wakeup Frame provided by the local
machine’s OS.
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PME# Signal
The PME# signal is asserted only when the following conditions are met:
• The PMEn bit (bit0, CONFIG1) is set to 1.
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8101L may assert PME# in current power state, or when the RTL8101L is in isolation state.
Refer to 10.1 PCI Configuration Space , page 57, PME_Support (bit15-11) of the PMC register.
• A Magic Packet, LinkChg, or Wakeup Frame event has occurred.
Writing a 1 to the PME_Status (bit15) of PMCSR register in the PCI Configuration Space will clear this bit
and cause the RTL8101L to stop asserting a PME# (if enabled).
When the RTL8101L is in power down mode, e.g. D1-D3, the IO, and MEM are all disabled. After RST# is
asserted, the power state must be changed to D0 if the original power state was D3cold. There is no hardware
enforced delays in the RTL8101L’s power state. When in ACPI mode, the RTL8101L does not support
PME from D0 owing to the PMC register setting (this setting comes from EEPROM).
LWAKE Signal
The RTL8101L also supports the LAN WAKE-UP function. The LWAKE pin is used to notify the
motherboard to execute the wake-up process whenever the RTL8101L receives a wakeup event, such as a
Magic Packet.
The LWAKE signal is asserted according to the following setting:
• LWPME bit (bit4, CONFIG4)
0: LWAKE is asserted whenever a wakeup event occurs
1: LWAKE can only be asserted when PMEB is asserted and ISOLATEB is low
• Bit1 of DELAY byte (offset 1Fh, EEPROM)
0: LWAKE signal is disabled
1: LWAKE signal is enabled
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10.6. VPD (Vital Product Data)
Bit 31 of the VPD is used to issue VPD read/write commands and is also a flag used to indicate whether the
transfer of data between the VPD data register and the 93C46 has completed or not.
Write VPD register (write data to the 93C46)
• Write the flag bit to 1 at the same time the VPD address is written. When the flag bit is set to 0 by the
RTL8101L, the VPD data (all 4 bytes) has been transferred from the VPD data register to the 93C46.
Read VPD register (read data from the 93C46)
• Write the flag bit to a zero at the same time the VPD address is written. When the flag bit is set to one by
the RTL8101L, the VPD data (all 4 bytes) has been transferred from the 93C46 to the VPD data register.
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11. Functional Description
11.1. Transmit Operation
The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main
memory. When the entire packet has been transferred to the Tx buffer, the RTL8101L is instructed to move
the data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. When the transmit FIFO
contains a complete packet or is filled to the programmed threshold level, the RTL8101L begins packet
transmission.
11.2. Receive Operation
The incoming packet is placed in the RTL8101L’s Rx FIFO. Concurrently, the RTL8101L performs
address filtering of multicast packets according to the hash algorithms. When the amount of data in the Rx
FIFO reaches the level defined in the Receive Configuration Register, the RTL8101L requests the PCI bus
to begin transferring the data to the Rx buffer in PCI bus master mode.
11.3. Wander Compensation
The RTL8101L is ANSI TP-PMD compliant and supports Input Wander and Base Line Wander (BLW)
compensation in 100Base-TX mode. The RTL8101L does not require external attenuation circuitry at its
receive inputs, RD+/-. It accepts TP-PMD compliant waveforms directly, requiring only 100Ω termination
and a 1:1 transformer.
BLW is the change in the average DC content, over time, of an AC coupled digital transmission over a
given transmission medium and is a result of the interaction between the low frequency components of a
transmitted bit stream and the frequency response of the AC coupling component(s) within the transmission
system. If the low-frequency content of the digital bit stream goes below the low-frequency pole of the AC
coupling transformers, then the droop characteristics of the transformers will dominate, resulting in
potentially serious BLW. If BLW is not compensated, packet loss can occur.
11.4. Signal Detect
The RTL8101L supports signal detect in 100Base-TX mode. The reception of normal 10Base-T link pulses
and fast link pulses (defined by IEEE 802.3u Auto-negotiation) by the 100Base-TX receiver do not cause
the RTL8101L to assert signal detect.
The signal detect function of the RTL8101L is incorporated to meet the specifications mandated by the
ANSI FDDI TP-PMD standard as well as the IEEE 802.3 100Base-TX standard for both voltage thresholds
and timing parameters.
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11.5. Line Quality Monitor
The line quality monitor function is available in 100Base-TX mode. It is possible to determine the amount
of Equalization being used by accessing certain test registers with the DSP engine. This provides a crude
indication of connected cable length. This function allows for a quick and simple verification of the line
quality in that any significant deviation from an expected register value (based on a known cable length)
would indicate that the signal quality has deviated from the expected nominal case.
11.6. Clock Recovery Module
The Clock Recovery Module (CRM) is supported in 100Base-TX mode. The CRM accepts 125Mbps
MLT-3 data from the equalizer. The DPLL locks onto the 125Mbps data stream and extracts a 125MHz
recovered clock. The extracted and synchronized clock and data are used as required by the synchronous
receive operations.
11.7. Loopback Operation
Loopback mode is normally used to verify that the logic operations up to the Ethernet cable function
correctly. In loopback mode for 100Mbps, the RTL8101L takes frames from the transmit descriptor and
transmits them up to internal Twister logic.
11.8. Tx Encapsulation
While operating in 100Base-TX mode, the RTL8101L encapsulates the frames that it transmits according
to the 4B/5B code-groups table. The changes to the original packet data are listed below:
The first byte of the preamble in the MAC frame is replaced with the JK symbol pair.
After the CRC, the TR symbol pair is inserted.
11.9. Collision
If the RTL8101L is not in full-duplex mode, a collision event occurs when the receive input is not idle while
the RTL8101L transmits. If the collision was detected during the preamble transmission, a jam pattern is
transmitted after completing the preamble (including the JK symbol pair).
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11.10. Rx Decapsulation
The RTL8101L continuously monitors the network when reception is enabled. When activity is recognized
it starts to process the incoming data.
After detecting receive activity on the line, the RTL8101L starts to process the preamble bytes based on the
mode of operation.
While operating in 100Base-TX mode, the RTL8101L expects the frame to start with the symbol pair JK in
the first byte of the 8-byte preamble.
The RTL8101L checks the CRC bytes and checks whether the packet data ends with the TR symbol pair. If
not, the RTL8101L reports an RSR CRC error.
The RTL8101L reports an RSR CRC error in 100Base-TX mode if an invalid symbol (4B/5B Table) is
received in the middle of the frame. The RSR<ISR> bit also sets.
11.11. Flow Control
The RTL8101L supports IEEE 802.3X flow control for improved performance in full-duplex mode. It
detects PAUSE packets to achieve flow control tasks.
11.11.1. Control Frame Transmission
When the RTL8101L detects that it’s free receive buffer is less than 3K bytes, it sends a PAUSE packet
with pause_time (=FFFFh) to inform the source station to stop transmission for the specified period of time.
After the driver has processed the packets in the receive buffer and updated the boundary pointer, the
RTL8101L sends another PAUSE packet with pause_time (=0000h) to wake up the source station to restart
transmission.
11.11.2. Control Frame Reception
The RTL8101L enters a backoff state for a specified period of time when it receives a valid PAUSE packet
with pause_time (=n). If the PAUSE packet is received while the RTL8101L is transmitting, the RTL8101L
starts to back off after the current transmission completes. The RTL8101L is free to transmit the next packet
when it receives a valid PAUSE packet with pause_time (=0000h) or the backoff timer (=n*512 bit time)
elapses.
Note: The PAUSE operation cannot be used to inhibit transmission of MAC Control frames (e.g. PAUSE
packet). NWay flow control capability can be disabled. Refer to section 9 EEPROM (93C46) Contents,
page 54.
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11.12. LED Functions
11.12.1. 10/100Mbps Link Monitor
The Link Monitor senses whether a station is connected and monitors link integrity.
Note: In 10/100Mbps mode, LED function is the same as that of the RTL8139C(L).
11.12.2. LED_RX
Power On
LED = High
No
Receiving Packet?
Yes
LED = High for (100 ±10) ms
LED = Low for (12 ±2) ms
Figure 3. LED_RX
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11.12.3. LED_TX
Power On
LED = High
No
Transmitting Packet?
Yes
LED = High for (100 ±10) ms
LED = Low for (12 ±2) ms
Figure 4. LED_TX
11.12.4. LED_TX+LED_RX
Power On
LED = High
No
Tx or Rx Packet?
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
Figure 5. LED_TX+LED_RX
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12. Application Diagram
Figure 6. Application Diagram
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13. Characteristics
13.1. Thermal Characteristics
Table 73. Thermal Characteristics
Parameter
Minimum
Maximum
+125
Units
-55
°C
°C
Storage temperature.
Operating temperature.
0
70
13.2. DC Characteristics
13.2.1. Supply Voltage (Vcc = 3.0V min. to 3.6V max.)
Table 74. Supply Voltage (3.0V min. to 3.6V max.)
Symbol
Parameter
Conditions
Minimum Maximum
Units
V
I
0.9 * Vcc
Vcc
V
Minimum High Level Output Voltage.
OH
OH= -8mA
V
I
0.1 * Vcc
Vcc+0.5
0.3 * Vcc
1.0
V
V
Maximum Low Level Output Voltage.
Minimum High Level Input Voltage.
Maximum Low Level Input Voltage.
Input Current.
OL
OL= 8mA
V
0.5 * Vcc
-0.5
IH
V
V
IL
I
V
V
-1.0
µA
IN
IN= CC or
GND
I
V
V
-10
10
80
µA
Tri-State Output Leakage Current.
Average Operating Supply Current.
OZ
OUT= CC or
GND
I
I
0mA,
mA
CC
OUT=
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13.3. AC Characteristics
13.3.1. PCI Bus Operation Timing
Target Read
Figure 7. Target Read
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Target Write
Figure 8. Target Write
Configuration Read
Figure 9. Configuration Read
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Configuration Write
Figure 10. Configuration Write
Bus Arbitration
Figure 11. Bus Arbitration
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Memory Read
Figure 12. Memory Read
Memory Write
Figure 13. Memory Write
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Target Initiated Termination - Retry
Figure 14. Target Initiated Termination - Retry
Target Initiated Termination - Disconnect
Figure 15. Target Initiated Termination - Disconnect
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Target Initiated Termination - Abort
Figure 16. Target Initiated Termination - Abort
Master Initiated Termination – Abort
Figure 17. Master Initiated Termination – Abort
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Parity Operation - One Example
Figure 18. Parity Operation - One Example
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14. Mechanical Dimensions
Note:
1.To be determined at seating plane -c-
2.Dimensions D1 and E1 do not include mold protrusion.
D1 and E1 are maximum plastic body size dimensions
Symbol Dimension in
inch
Dimension in
mm
Min Nom Max Min Nom Max
0.067 1.70
0.000 0.004 0.008 0.00 0.1 0.20
0.051 0.055 0.059 1.30 1.40 1.50
0.006 0.009 0.011 0.15 0.22 0.29
0.006 0.008 0.010 0.15 0.20 0.25
including mold mismatch.
A
A1
A2
B
b1
C
-
-
-
-
3.Dimension b does not include dambar protrusion.
Dambar can not be located on the lower radius of the foot.
4.Exact shape of each corner is optional.
5.These dimensions apply to the flat section of the lead
between 0.10 mm and 0.25 mm from the lead tip.
6. A1 is defined as the distance from the seating plane
to the lowest point of the package body.
0.004
0.004
-
-
0.008 0.09
0.006 0.09
-
-
0.20
0.16
c1
D
D1
E
0.630 BSC
0.551 BSC
0.630 BSC
0.551 BSC
0.020 BSC
16.00 BSC
14.00 BSC
16.00 BSC
14.00 BSC
0.50 BSC
7.Controlling dimension: millimeter.
8. Reference document: JEDEC MS-026 , BED.
TITLE: 100LD LQFP ( 14x14x1.4mm)
PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm
LEADFRAME MATERIAL:
E1
L
L1
0.016 0.024 0.031 0.40 0.60 0.80
0.039 REF 1.00 REF
APPROVE
DOC. NO.
VERSION
PAGE
1
OF
θ
θ
°
°
°
°
-
°
°
°
°
9
-
0
0
3.5
-
9
0
0
3.5
-
CHECK
DWG NO. LQ100 - P1
DATE
1
θ
θ
°
°
12 TYP
12 TYP
2
REALTEK SEMICONDUCTOR CORP.
°
°
12 TYP
12 TYP
3
Single-Chip Fast Ethernet Controller and MC’97
Controller w/Power Management
85
Track ID: JATR-1076-21 Rev. 1.5
RTL8101L
Datasheet
15. Ordering Information
Table 75. Ordering Information
Part No.
Package
Status
MP
RTL8101L
100-pin LQFP
RTL8101L-LF
RTL8101L-GR
RTL8101L with Lead (Pb)-Free package
RTL8101L with Green package
MP
MP
Note: See page 5 for package identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-557-6047
www.realtek.com.tw
Single-Chip Fast Ethernet Controller and MC’97
Controller w/Power Management
86
Track ID: JATR-1076-21 Rev. 1.5
相关型号：
RTL8101LLQFP
REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC97 CONTROLLER WITH POWER MANAGEMENT
ETC
RTL8101LQFP
REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC97 CONTROLLER WITH POWER MANAGEMENT
ETC
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