RTL8201E-VB-GR [REALTEK]
Ethernet Transceiver, CMOS, PQCC32, GREEN, MO-220, QFN-32;型号: | RTL8201E-VB-GR |
厂家: | Realtek Semiconductor Corp. |
描述: | Ethernet Transceiver, CMOS, PQCC32, GREEN, MO-220, QFN-32 以太网:16GBASE-T 电信 电信集成电路 |
文件: | 总44页 (文件大小:796K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
RTL8201E-GR
RTL8201EL-GR
RTL8201E-VB-GR
RTL8201EL-VB-GR
SINGLE-CHIP/PORT 10/100 FAST
ETHERNET PHYCEIVER WITH AUTO MDIX
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.3
16 December 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8201E(L)
Datasheet
COPYRIGHT
©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
Release Date
2008/06/18
2008/08/08
Summary
1.0
First release.
1.1
Revised Table 19, page 15.
Added section 8.5 LED and PHY Address Configuration, page 21.
Revised section 8.11 3.3V Power Supply and Voltage Conversion Circuit, page 25.
Added section 9.1.3 Power On Sequence, page 26.
Added section 9.1.4 PHY Reset Sequence, page 27.
Revised Table 32, page 28.
1.2
1.3
2008/11/14
2008/12/16
Removed RMII function.
Removed INTB function.
Added RTL8201E(L)-VB-GR version and features (RMII and INTB).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
ii
Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
Table of Contents
1.
2.
3.
4.
5.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
APPLICATIONS................................................................................................................................................................2
BLOCK DIAGRAM...........................................................................................................................................................3
PIN ASSIGNMENTS .........................................................................................................................................................4
5.1.
RTL8201EL LQFP-48 PIN ASSIGNMENTS...................................................................................................................4
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................4
RTL8201E QFN-32 PIN ASSIGNMENTS.......................................................................................................................5
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................5
5.2.
5.3.
5.4.
6.
PIN DESCRIPTIONS.........................................................................................................................................................6
6.1.
MII INTERFACE............................................................................................................................................................6
RMII INTERFACE (RTL8201E(L)-VB ONLY)..............................................................................................................8
SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY ...................................................................................................8
CLOCK INTERFACE.......................................................................................................................................................8
10MBPS/100MBPS NETWORK INTERFACE ...................................................................................................................9
DEVICE CONFIGURATION INTERFACE ..........................................................................................................................9
LED INTERFACE/PHY ADDRESS CONFIGURATION ....................................................................................................10
POWER AND GROUND PINS ........................................................................................................................................10
RESET AND OTHER PINS.............................................................................................................................................10
NC (NOT CONNECTED) PINS......................................................................................................................................10
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
7.
REGISTER DESCRIPTIONS.........................................................................................................................................11
7.1.
REGISTER 0 BASIC MODE CONTROL REGISTER..........................................................................................................11
REGISTER 1 BASIC MODE STATUS REGISTER.............................................................................................................12
REGISTER 2 PHY IDENTIFIER REGISTER 1..................................................................................................................12
REGISTER 3 PHY IDENTIFIER REGISTER 2..................................................................................................................13
REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ...................................................................13
REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)....................................................14
REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ............................................................................15
REGISTER 16 NWAY SETUP REGISTER (NSR)............................................................................................................15
REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR).................................................15
REGISTER 18 RX_ER COUNTER (REC) .....................................................................................................................16
REGISTER 19 SNR DISPLAY REGISTER ......................................................................................................................16
REGISTER 25 TEST REGISTER.....................................................................................................................................16
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
8.
FUNCTIONAL DESCRIPTION.....................................................................................................................................17
8.1.
MII AND MANAGEMENT INTERFACE..........................................................................................................................18
8.1.1. Data Transition ....................................................................................................................................................18
8.1.2. Serial Management...............................................................................................................................................19
8.1.3. Interrupt (RTL8201EL-VB Only)..........................................................................................................................20
8.2.
AUTO-NEGOTIATION AND PARALLEL DETECTION .....................................................................................................20
8.2.1. Setting the Medium Type and Interface Mode to MAC.........................................................................................20
8.3.
FLOW CONTROL SUPPORT..........................................................................................................................................20
HARDWARE CONFIGURATION AND AUTO-NEGOTIATION...........................................................................................21
LED AND PHY ADDRESS CONFIGURATION ...............................................................................................................21
SERIAL NETWORK INTERFACE ...................................................................................................................................22
POWER DOWN, LINK DOWN, AND POWER SAVING MODES........................................................................................22
MEDIA INTERFACE.....................................................................................................................................................23
8.4.
8.5.
8.6.
8.7.
8.8.
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with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
8.8.1. 100Base-TX Transmit and Receive Operation .....................................................................................................23
8.8.2. 100Base-FX Fiber Transmit and Receive Operation ...........................................................................................23
8.8.3. 10Base-T Transmit and Receive Operation..........................................................................................................24
8.9.
REPEATER MODE OPERATION....................................................................................................................................24
RESET AND TRANSMIT BIAS.......................................................................................................................................24
3.3V POWER SUPPLY AND VOLTAGE CONVERSION CIRCUIT......................................................................................25
FAR END FAULT INDICATION.....................................................................................................................................25
8.10.
8.11.
8.12.
9.
CHARACTERISTICS......................................................................................................................................................26
9.1.
DC CHARACTERISTICS...............................................................................................................................................26
9.1.1. Absolute Maximum Ratings..................................................................................................................................26
9.1.2. Operating Conditions...........................................................................................................................................26
9.1.3. Power On Sequence..............................................................................................................................................26
9.1.4. PHY Reset Sequence.............................................................................................................................................27
9.1.5. Power Dissipation ................................................................................................................................................27
9.1.6. Input Voltage: Vcc................................................................................................................................................28
9.2.
AC CHARACTERISTICS...............................................................................................................................................28
9.2.1. MII Transmission Cycle Timing ...........................................................................................................................28
9.2.2. MII Reception Cycle Timing.................................................................................................................................30
9.2.3. RMII Transmission Cycle Timing (RTL8201E(L)-VB Only) ................................................................................31
9.2.4. RMII Reception Cycle Timing (RTL8201E(L)-VB Only)......................................................................................31
9.2.5. SNI Transmission Cycle Timing ...........................................................................................................................32
9.2.6. SNI Reception Cycle Timing.................................................................................................................................33
9.2.7. MDC/MDIO Timing .............................................................................................................................................34
9.2.8. Transmission without Collision............................................................................................................................34
9.2.9. Reception without Error.......................................................................................................................................35
9.3.
9.4.
CRYSTAL CHARACTERISTICS .....................................................................................................................................35
TRANSFORMER CHARACTERISTICS ............................................................................................................................35
10.
MECHANICAL DIMENSIONS.................................................................................................................................36
10.1.
10.2.
RTL8201E 32-PIN QFN ............................................................................................................................................36
RTL8201EL 48-PIN LQFP ........................................................................................................................................37
11.
ORDERING INFORMATION...................................................................................................................................38
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
List of Tables
TABLE 1. MII INTERFACE ..............................................................................................................................................................6
TABLE 2. RMII INTERFACE (RTL8201E(L)-VB ONLY)................................................................................................................8
TABLE 3. SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY......................................................................................................8
TABLE 4. CLOCK INTERFACE.........................................................................................................................................................8
TABLE 5. 10MBPS/100MBPS NETWORK INTERFACE......................................................................................................................9
TABLE 6. DEVICE CONFIGURATION INTERFACE.............................................................................................................................9
TABLE 7. LED INTERFACE/PHY ADDRESS CONFIGURATION ......................................................................................................10
TABLE 8. POWER AND GROUND PINS ..........................................................................................................................................10
TABLE 9. RESET AND OTHER PINS...............................................................................................................................................10
TABLE 10. NC (NOT CONNECTED) PINS........................................................................................................................................10
TABLE 11. REGISTER 0 BASIC MODE CONTROL REGISTER............................................................................................................11
TABLE 12. REGISTER 1 BASIC MODE STATUS REGISTER...............................................................................................................12
TABLE 13. REGISTER 2 PHY IDENTIFIER REGISTER 1 ...................................................................................................................12
TABLE 14. REGISTER 3 PHY IDENTIFIER REGISTER 2 ...................................................................................................................13
TABLE 15. REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR).....................................................................13
TABLE 16. REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................14
TABLE 17. REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ..............................................................................15
TABLE 18. REGISTER 16 NWAY SETUP REGISTER (NSR) .............................................................................................................15
TABLE 19. REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR)...................................................15
TABLE 20. REGISTER 18 RX_ER COUNTER (REC).......................................................................................................................16
TABLE 21. REGISTER 19 SNR DISPLAY REGISTER ........................................................................................................................16
TABLE 22. REGISTER 25 TEST REGISTER.......................................................................................................................................16
TABLE 23. SERIAL MANAGEMENT ................................................................................................................................................19
TABLE 24. SETTING THE MEDIUM TYPE AND INTERFACE MODE TO MAC....................................................................................20
TABLE 25. AUTO-NEGOTIATION MODE PIN SETTINGS ..................................................................................................................21
TABLE 26. POWER SAVING MODE PIN SETTINGS ..........................................................................................................................22
TABLE 27. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................26
TABLE 28. OPERATING CONDITIONS .............................................................................................................................................26
TABLE 29. POWER ON SEQUENCE .................................................................................................................................................26
TABLE 30. PHY RESET SEQUENCE OPERATING CONDITIONS........................................................................................................27
TABLE 31. POWER DISSIPATION....................................................................................................................................................27
TABLE 32. INPUT VOLTAGE: VCC .................................................................................................................................................28
TABLE 33. MII TRANSMISSION CYCLE TIMING .............................................................................................................................28
TABLE 34. MII RECEPTION CYCLE TIMING ...................................................................................................................................30
TABLE 35. RMII TRANSMISSION CYCLE TIMING (RTL8201E(L)-VB ONLY)...............................................................................31
TABLE 36. RMII RECEPTION CYCLE TIMING (RTL8201E(L)-VB ONLY).....................................................................................31
TABLE 37. SNI TRANSMISSION CYCLE TIMING.............................................................................................................................32
TABLE 38. SNI RECEPTION CYCLE TIMING...................................................................................................................................33
TABLE 39. MDC/MDIO TIMING...................................................................................................................................................34
TABLE 40. CRYSTAL CHARACTERISTICS .......................................................................................................................................35
TABLE 41. TRANSFORMER CHARACTERISTICS ..............................................................................................................................35
TABLE 42. ORDERING INFORMATION ............................................................................................................................................38
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM..........................................................................................................................................................3
FIGURE 2. RTL8201EL LQFP-48 PIN ASSIGNMENTS....................................................................................................................4
FIGURE 3. RTL8201E QFN-32 PIN ASSIGNMENT..........................................................................................................................5
FIGURE 4. READ CYCLE...............................................................................................................................................................19
FIGURE 5. WRITE CYCLE .............................................................................................................................................................19
FIGURE 6. LED AND PHY ADDRESS CONFIGURATION ................................................................................................................21
FIGURE 7. POWER ON SEQUENCE ................................................................................................................................................26
FIGURE 8. PHY RESET SEQUENCE...............................................................................................................................................27
FIGURE 9. MII TRANSMISSION CYCLE TIMING-1.........................................................................................................................29
FIGURE 10. MII TRANSMISSION CYCLE TIMING-2.........................................................................................................................29
FIGURE 11. MII RECEPTION CYCLE TIMING-1 ..............................................................................................................................30
FIGURE 12. MII RECEPTION CYCLE TIMING-2 ..............................................................................................................................30
FIGURE 13. RMII TRANSMISSION CYCLE TIMING .........................................................................................................................31
FIGURE 14. RMII RECEPTION CYCLE TIMING ...............................................................................................................................31
FIGURE 15. SNI TRANSMISSION CYCLE TIMING-1 ........................................................................................................................32
FIGURE 16. SNI TRANSMISSION CYCLE TIMING-2 ........................................................................................................................32
FIGURE 17. SNI RECEPTION CYCLE TIMING-1 ..............................................................................................................................33
FIGURE 18. SNI RECEPTION CYCLE TIMING-2 ..............................................................................................................................33
FIGURE 19. MDC/MDIO TIMING..................................................................................................................................................34
FIGURE 20. MAC TO PHY TRANSMISSION WITHOUT COLLISION .................................................................................................34
FIGURE 21. PHY TO MAC RECEPTION WITHOUT ERROR .............................................................................................................35
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
1. General Description
The RTL8201E(L) is a single-chip/single-port Fast Ethernet PHYceiver that supports:
• MII (Media Independent Interface)
• RMII (Reduced Media Independent Interface; RTL8201E(L)-VB only)
• SNI (Serial Network Interface)
It implements all 10/100M Ethernet Physical-layer functions including the Physical Coding Sublayer
(PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-
PMD), with an auto MDIX function, 10Base-Tx Encoder/Decoder, and Twisted-Pair Media Access Unit
(TPMAU).
A PECL (Pseudo Emitter Coupled Logic) interface is supported to connect with an external 100Base-FX
fiber optical transceiver. The chip utilizes an advanced CMOS process to meet low voltage and low
power requirements. With on-chip DSP (Digital Signal Processing) technology, the chip provides
excellent performance under all operating conditions.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
1
Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
2. Features
Supports MII and 7-wire SNI (Serial
Supports repeater mode
Network Interface)
Supports Interrupt function (RTL8201EL-
Supports RMII mode (RTL8201E(L)-VB
VB only)
only)
Adaptive Equalization
10/100Mbps operation
Network status LEDs
Full/half duplex operation
Twisted pair or fiber mode output
Auto-Negotiation
Flow control support
25MHz crystal/oscillator as clock source
IEEE 802.3/802.3u compliant
Supports power down mode
Low power supply, 1.2V, and 3.3V; 1.2V is
Supports operation under Link Down Power
generated by an internal regulator
Saving mode
0.11µm CMOS process
Supports Base Line Wander (BLW)
48-pin LQFP package (RTL8201EL)
32-pin QFN package (RTL8201E)
compensation
Supports auto MDIX
3. Applications
Network Interface Adapter
MAU (Media Access Unit)
CNR (Communication and Network Riser)
ACR (Advanced Communication Riser)
Ethernet hub
Ethernet switch
In addition, it can be used in any embedded system with an Ethernet MAC that needs a UTP physical
connection or Fiber PECL interface to an external 100Base-FX optical transceiver module.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
4. Block Diagram
100 M
Data
Alignment
RXD
5B
4B
Descrambler
Decoder
RXC 25M
MII
Interface
10/100
RMII
Half/Full
Interface
Switch
Logic
TXD
4B
5B
Scrambler
SNI
25M
Encoder
TXC
Interface
10/100M Auto-negotiation
Control Logic
Link Pulse
10M
TXC10
TXD10
Manchester Coded
Waveform
10M Output Waveform
Shaping
RXC10
RXD10
Data Recovery
Receive Low Pass Filter
TD+
25M
TXC
TXO+
Parrallel
to Serial
3 Level
Driver
TXO-
TXD
Variable
Current
Baseline
Wander
Correction
Peak
Detect
RXIN+
RXIN-
3 Level
MLT-3
to NRZI
Adaptive
Equalizer
Comparator
25M
RXC
ck
Master
PPL
Serial to
Parrallel
Slave
PLL
RXD
data
Control
Voltage
25M
Figure 1. Block Diagram
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
5. Pin Assignments
5.1. RTL8201EL LQFP-48 Pin Assignments
Figure 2. RTL8201EL LQFP-48 Pin Assignments
5.2. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2. The version is shown in the
location marked ‘V’.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
5.3. RTL8201E QFN-32 Pin Assignments
Figure 3. RTL8201E QFN-32 Pin Assignment
5.4. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3. The version is shown in the
location marked ‘V’.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
6. Pin Descriptions
I: Input
LI: Latched Input during Power up or Reset
O: Output
IO: Bi-directional input and output
P: Power
HZ: High impedance during power on reset
PD: Internal Pull down during power on reset
PU: Internal Pull up during power on reset
6.1. MII Interface
Table 1. MII Interface
Pin No. Pin No. Description
(48-Pin) (32-Pin)
Name
Type
TXC
O/HZ
22
15
Transmit Clock.
This pin provides a continuous clock as a timing reference for
TXD[3:0] and TXEN.
TXEN
I/PD
I/PD
27
20
Transmit Enable.
The input signal indicates the presence of valid nibble data on
TXD[3:0]. An internal weakly pulled low resistor prevents the bus
floating.
TXD[0:3]
RXC
23, 24,
25, 26
16, 17, Transmit Data.
18, 19 The MAC will source TXD[0:3] synchronous with TXC when TXEN is
asserted. An internal weakly pulled low resistor prevents the bus
floating.
O/HZ
19
38
13
27
Receive Clock.
This pin provides a continuous clock reference for RXDV and
RXD[0:3] signals. RXC is 25MHz in 100Mbps mode and 2.5MHz in
10Mbps mode.
COL/SNI
LI/O/PD
Collision Detect.
COL is asserted high when a collision is detected on the media.
This pin’s status is latched at power on reset to determine at which
interface mode to operate:
0: MII/RMII mode
1: SNI mode
This pin can be directly connected to GND or VCC.
Note: Only the RTL8201E(L)-VB supports RMII mode.
CRS/RPTR/
CRS_DV
LI/O/PD
36
26
Carrier Sense.
This pin’s signal is asserted high if the media is not in Idle state.
At power on reset, this pin set high to put the RTL8201E(L) into
repeater mode.
This pin can be directly connected to GND or VCC.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
Name
Type
Pin No. Pin No. Description
(48-Pin) (32-Pin)
RXDV
LI/O/PD
13
8
Receive Data Valid.
This pin’s signal is asserted high when received data is present on the
RXD[3:0] lines. The signal is de-asserted at the end of the packet. The
signal is valid on the rising edge of the RXC.
This pin should be pulled low when operating in MII mode.
0: MII mode
1: RMII mode
An internal weakly pulled low resistor sets this to the default of MII
mode. It is possible to use an external 4.7KΩ pulled high resistor to
enable RMII mode.
After power on, the pin operates as the Receive Data Valid pin.
Note: Only the RTL8201E(L)-VB supports RMII mode.
RXD[0:3]
O/PD
14, 16, 9, 10, 11, Receive Data.
17, 18
12
These are the four parallel receive data lines aligned on the nibble
boundaries driven synchronously to the RXC for reception by the
external physical unit (PHY).
RXER/FXEN LI/O/PD
39
28
Receive Error.
If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or
invalid symbol, this pin will go high.
Fiber/UTP Enable.
This pin’s status is latched at power on reset to determine the media
mode to operate in.
1: Fiber mode
0: UTP mode
An internal weakly pulled low resistor sets this to the default of UTP
mode. It is possible to use an external 4.7KΩ pulled high resistor to
enable fiber mode. After power on, the pin operates as the Receive
Error pin.
MDC
I/PU
30
31
22
23
Management Data Clock.
This pin provides a clock synchronous to MDIO, which may be
asynchronous to the transmit TXC and receive RXC clocks. The clock
rate can be up to 2.5MHz. Use an internal weakly pulled high resistor to
prevent the bus floating.
MDIO
IO/PU
Management Data Input/Output.
This pin provides the bi-directional signal used to transfer management
information.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
6.2. RMII Interface (RTL8201E(L)-VB Only)
Table 2. RMII Interface (RTL8201E(L)-VB Only)
Name
Type
IO
Pin No. Pin No. Description
(48-Pin) (32-Pin)
TXC
22
15
Synchronous 50MHz Clock Reference for Receive, Transmit, and
Control Interface. The direction is decided by Register 25.
CRS/RPTR/
CRS_DV
O
36
26
Carrier Sense/Receive Data Valid.
CRS_DV shall be asserted by the PHY when the receive medium is
non-idle.
RXD[0:1]
TXEN
O
I
14, 16
27
9, 10
20
Receive Data.
Transmit Enable.
TXD[0:1]
RXER/FXEN
I
23, 24
39
16, 17 Transmit Data.
28 Receive Error.
O
6.3. SNI (Serial Network Interface) 10Mbps Only
Table 3. SNI (Serial Network Interface) 10Mbps Only
Name
Type
Pin No.
(48-Pin)
Pin No. Description
(32-Pin)
COL/SNI
RXD0
O/PD
O/PD
38
14
36
27
9
Collision Detect.
Received Serial Data.
Carrier Sense.
CRS/RPTR/ O/PD
CRS_DV
26
RXC
O/HZ
I/PD
19
23
22
27
13
16
15
20
Receive Clock. Resolved from received data.
Transmit Serial Data.
TXD0
TXC
O/HZ
I/PD
Transmit Clock. Generated by PHY.
TXEN
Transmit Enable. For MAC to indicate transmit operation.
6.4. Clock Interface
Table 4. Clock Interface
Name
Type
Pin No.
(48-Pin)
Pin No. Description
(32-Pin)
CKXTAL2
O
43
32
25MHz Crystal Output.
This pin provides the 25MHz crystal output. It must be left open
when an external 25MHz oscillator drives X1.
CKXTAL1
I
42
31
25MHz Crystal Input.
This pin provides the 25MHz crystal input. If a 25MHz oscillator is
used, connect CKXTAL1 to the oscillator’s output (see 9.3 Crystal
Characteristics, page 35, for clock source specifications).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
6.5. 10Mbps/100Mbps Network Interface
Table 5. 10Mbps/100Mbps Network Interface
Name
Type
Pin No.
(48-Pin)
Pin No. Description
(32-Pin)
MDI+[0]
MDI-[0]
O
1
2
3
4
Transmit Output.
Differential transmit output pair shared by 100Base-TX, 100Base-
FX, and 10Base-T modes. When configured as 100Base-TX, output
is an MLT-3 encoded waveform. When configured as 100Base-FX,
the output is pseudo-ECL level.
RSET
I
I
46
1
Transmit Bias Resistor Connection.
This pin should be pulled to GND by a 2.49KΩ (1%) resistor to
define driving current for the transmit DAC. The resistance value
may be changed, depending on experimental results of the
RTL8201E(L).
MDI+[1]
MDI-[1]
4
5
5
6
Receive Input.
Differential receive input pair shared by 100Base-TX, 100Base-FX,
and 10Base-T modes.
6.6. Device Configuration Interface
Table 6. Device Configuration Interface
Type Pin No. Pin No. Description
(48-Pin) (32-Pin)
Name
RXDV
LI/O
/PD
13
8
RMII/MII Interface
This pin’s status is latched at power on reset to determine at which
interface mode to operate:
0: MII mode
1: RMII mode
An internal weakly pulled low resistor sets this to the default MII
mode. It is possible to use an external 4.7KΩ pulled high resistor to
enable RMII mode.
Note: Only the RTL8201E(L)-VB supports RMII mode.
LED0/PHYAD[0]
LED1/PHYAD[1]
LI/O
/HZ
34
35
24
25
PHY Address. Sets the PHY address for the device.
CRS/RPTR/
CRS_DV
LI/O
/PD
36
26
Repeater Mode.
Set high to put the RTL8201E(L) into repeater mode. This pin can be
directly connected to GND or VCC.
COL/SNI
LI/O
/PD
38
27
MII/RMII/SNI Interface.
This pin is latched to input at a power on or reset condition. Pull high
to set the RTL8201E(L) into SNI mode operation. Set low for
MII/RMII mode. This pin can be directly connected to GND or VCC.
Note: Only the RTL8201E(L)-VB supports RMII mode.
RXER/FXEN
LI/O
/PD
39
28
Fiber/UTP Interface.
This pin’s status is latched at power on reset to determine the media
mode to operate in.
1: Fiber mode
0: UTP mode
An internal weakly pulled low resistor sets this to the default of UTP
mode. It is possible to use an external 4.7KΩ pulled high resistor to
enable fiber mode.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
6.7. LED Interface/PHY Address Configuration
Table 7. LED Interface/PHY Address Configuration
Name
Type
Pin No. Pin No. Description
(48-Pin) (32-Pin)
LED0/PHYAD[0]
LED1/PHYAD[1]
LI/O/HZ
LI/O/HZ
34
35
24
25
Link Indicator.
Receive/Transmit LED.
6.8. Power and Ground Pins
Table 8. Power and Ground Pins
Name
Type
Pin No.
(48-Pin)
Pin No. Description
(32-Pin)
AVDD33
DVDD33
P
P
6, 41
7, 30
3.3V Analog Power Input.
3.3V power supply for analog circuit; should be well decoupled.
15, 21, 37
14
3.3V Digital Power Input.
3.3V power supply for digital circuit.
DVDD12
GND
P
P
28
-
-
1.2V Digital Power.
7, 20, 33, 47
Ground. Should be connected to a larger GND plane.
6.9. Reset and Other Pins
Table 9. Reset and Other Pins
Name
Type
Pin No.
(48-Pin)
Pin No. Description
(32-Pin)
PHYRSTB
I/HZ
29
21
RESETB.
Set low to reset the chip. For a complete reset, this pin must be
asserted low for at least 10ms.
PWOUT12D
PWOUT12A
O
O
40
48
29
2
Power Output.
Be sure to connect a 0.1µF ceramic capacitor for decoupling
purposes.
The connection method is outlined in 8.11 3.3V Power Supply
and Voltage Conversion Circuit, page 25.
INTB
32
-
Interrupt.
Set low if link status change, duplex change and auto negotiation
fail, Active Low.
Note: Only the RTL8201EL-VB supports Interrupt pin.
6.10. NC (Not Connected) Pins
Table 10. NC (Not Connected) Pins
Name
Type
Pin No.
(48-Pin)
Pin No. Description
(32-Pin)
NC
-
3, 8, 9, 10, 11, 12, 32, 44, 45
-
Not Connected.
(Pin 32 is NC in RTL8201EL-GR Only)
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
7. Register Descriptions
This section describes the functions and usage of the registers available in the RTL8201E(L).
In this section the following abbreviations are used:
RO: Read Only
RW: Read/Write
7.1. Register 0 Basic Mode Control Register
Table 11. Register 0 Basic Mode Control Register
Address Name
Description
Mode Default
0:15
0:14
0:13
Reset
This bit sets the status and control registers of the PHY in the default
state. This bit is self-clearing.
RW
RW
RW
0
0
0
1: Software reset
0: Normal operation
Loopback
Spd_Set
This bit enables loopback of transmit data nibbles TXD3:0 to the
receive data path.
1: Enable loopback
0: Normal operation
This Bit Sets the Network Speed.
1: 100Mbps
0: 10Mbps
After completing auto negotiation, this bit will reflect the Speed status.
1: 100Base-T
0: 10Base-T
When 100Base-FX mode is enabled, this bit=1 and is read only.
0:12
0:11
Auto
Negotiation
Enable
This Bit Enables/Disables the NWay Auto-Negotiation Function.
1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored
0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the link
speed and the data transfer mode, respectively
RW
RW
1
0
When 100Base-FX mode is enabled, this bit=0 and is read only.
Power Down
This bit turns down the power of the PHY chip, including the internal
crystal oscillator circuit.
The MDC, MDIO is still alive for accessing the MAC.
1: Power down
Reserved.
0: Normal operation
0:10
0:9
Reserved
-
-
Restart Auto
Negotiation
This bit allows the NWay auto-negotiation function to be reset.
1: Re-start auto-negotiation
RW
0
0: Normal operation
0:8
Duplex Mode
This bit sets the duplex mode if auto-negotiation is disabled (bit
0:12=0).
RW
0
-
1: Full duplex
0: Half duplex
After completing auto-negotiation, this bit will reflect the duplex status.
1: Full duplex
Reserved.
0: Half duplex
0:7~0
Reserved
-
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with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
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Datasheet
7.2. Register 1 Basic Mode Status Register
Table 12. Register 1 Basic Mode Status Register
Address Name
Description
Mode Default
1:15
1:14
1:13
1:12
1:11
100Base-T4
1: Enable 100Base-T4 support
RO
RO
RO
RO
RO
0
1
1
1
1
0: Suppress 100Base-T4 support
1: Enable 100Base-TX full duplex support
0: Suppress 100Base-TX full duplex support
1: Enable 100Base-TX half duplex support
0: Suppress 100Base-TX half duplex support
1: Enable 10Base-T full duplex support
0: Suppress 10Base-T full duplex support
1: Enable 10Base-T half duplex support
0: Suppress 10Base-T half duplex support
Reserved.
100Base_TX_ FD
100Base_TX_HD
10Base_T_FD
10_Base_T_HD
1:10~7 Reserved
-
-
1:6
MF Preamble Suppression
The RTL8201E(L) will accept management frames with
preamble suppressed.
RO
1
A minimum of 32 preamble bits are required for the first
SMI read/write transaction after reset. One idle bit is
required between any two management transactions as per
IEEE 802.3u specifications.
1:5
1:4
Auto Negotiation Complete 1: Auto-negotiation process completed
RO
RO
0
0
0: Auto-negotiation process not completed
Remote Fault
1: Remote fault condition detected (cleared on read)
0: No remote fault condition detected
When in 100Base-FX mode, this bit means an in-band
signal Far-End-Fault has been detected (see 8.12 Far End
Fault Indication, page 25).
1:3
1:2
Reserved
Reserved.
-
-
Link Status
1: Valid link established
0: No valid link established
Reserved.
RO
0
1:1~0
Reserved
-
-
7.3. Register 2 PHY Identifier Register 1
Table 13. Register 2 PHY Identifier Register 1
Address Name
Description
Mode Default
RO 001Ch
2:15~0 OUI_MSB
Organizationally Unique Identifier Bit 3:18
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
7.4. Register 3 PHY Identifier Register 2
Table 14. Register 3 PHY Identifier Register 2
Address Name
Description
Mode
RO
Default
110010
000001
0101
3:15~10 OUI_LSB
Organizationally Unique Identifier Bit 19:24
Model Number
3:9~4
3:3~0
Model Number
RO
Revision Number Revision Number
RO
7.5. Register 4 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner
during auto-negotiation.
Table 15. Register 4 Auto-Negotiation Advertisement Register (ANAR)
Address Name
Description
Mode
Default
4:15
NP
Next Page Bit.
RO
0
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
1: Acknowledge reception of link partner capability data word
0: Do not acknowledge reception
4:14
4:13
ACK
RF
RO
0
0
1: Advertise remote fault detection capability
0: Do not advertise remote fault detection capability
Reserved.
RW
4:12~11 Reserved
-
-
4:10
RXFC
1: RX flow control is supported by local node
0: RX flow control not supported by local node
1: 100Base-T4 is supported by local node
0: 100Base-T4 not supported by local node
1: 100Base-TX full duplex is supported by local node
0: 100Base-TX full duplex not supported by local node
1: 100Base-TX is supported by local node
0: 100Base-TX not supported by local node
1: 10Base-T full duplex supported by local node
0: 10Base-T full duplex not supported by local node
1: 10Base-T is supported by local node
0: 10Base-T not supported by local node
RW
0
4:9
T4
RO
RW
RW
RW
RW
RW
0
4:8
TXFD
TX
1
4:7
1
4:6
10FD
10
1
1
4:5
4:4~0
Selector
Binary Encoded Selector Supported by This Node.
Currently only CSMA/CD 00001 is specified. No other protocols
are supported.
00001
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7.6. Register 5 Auto-Negotiation Link Partner Ability Register
(ANLPAR)
This register contains the advertised abilities of the Link Partner as received during auto-negotiation. The
content changes after a successful auto-negotiation if Next-pages are supported.
Table 16. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR)
Address Name
Description
Mode
Default
5:15
5:14
5:13
NP
Next Page Bit.
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
RO
0
ACK
RF
1: Link partner acknowledges reception of local node’s
capability data word
0: No acknowledgement
RO
RO
0
0
1: Link partner is indicating a remote fault
0: Link partner is not indicating a remote fault
Reserved.
5:12
5:11
Reserved
TXFC
-
-
1: TX flow control is supported by Link partner
0: TX flow control not supported by Link partner
1: RX flow control is supported by Link partner
0: RX flow control not supported by Link partner
1: 100Base-T4 is supported by link partner
RO
0
5:10
5:9
5:8
5:7
RXFC
T4
RO
RO
RO
RO
0
0
0
0
0: 100Base-T4 not supported by link partner
TXFD
100Base-TX
1: 100Base-TX full duplex is supported by link partner
0: 100Base-TX full duplex not supported by link partner
1: 100Base-TX is supported by link partner
0: 100Base-TX not supported by link partner
This bit will also be set if the link in 100Base is established by
parallel detection.
5:6
5:5
10FD
1: 10Base-T full duplex is supported by link partner
0: 10Base-T full duplex not supported by link partner
RO
RO
0
0
10Base-T
1: 10Base-T is supported by link partner
0: 10Base-T not supported by link partner
This bit will also be set if the link in 10Base-T is established by
parallel detection.
5:4~0
Selector
Link Partner’s Binary Encoded Node Selector.
Currently only CSMA/CD 00001 is specified.
RO
00000
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7.7. Register 6 Auto-Negotiation Expansion Register (ANER)
This register contains additional status for NWay auto-negotiation.
Table 17. Register 6 Auto-Negotiation Expansion Register (ANER)
Description
Address Name
Mode Default
6:15~5 Reserved
Reserved.
-
-
6:4
6:3
6:2
6:1
MLF
Indicates whether a Multiple Link Fault Has Occurred.
RO
0
1: Fault occurred
LP_NP_ABLE Indicates whether the Link Partner Supports Next Page Negotiation.
1: Supported 0: Not supported
0: No fault occurred
RO
RO
RO
0
0
0
NP_ABLE
This bit indicates whether the local node is able to send additional Next
Pages. Internal use only.
PAGE_RX
This Bit is Set when a New Link Code Word Page Has Been Received.
It is automatically cleared when the auto-negotiation link partner’s
ability register (register 5) is read by management.
6:0
LP_NW_ABLE 1: Link partner supports NWay auto-negotiation.
RO
0
7.8. Register 16 NWay Setup Register (NSR)
Table 18. Register 16 NWay Setup Register (NSR)
Address Name
Description
Mode Default
16:15~11 Reserved
Realtek Test Mode Internal Use.
-
-
Do not change this field without Realtek’s approval.
16:10
16:9
Testfun
1: Auto-negotiation speeds up internal timer
1: Set NWay to loopback mode
RW
RW
-
0
0
-
NWLPBK
16:8~3 Reserved
Reserved.
16:2
16:1
16:0
FLAGABD
FLAGPDF
FLAGLSC
1: Auto-negotiation experienced ability detect state
1: Auto-negotiation experienced parallel detection fault state
1: Auto-negotiation experienced link status check state
RO
RO
RO
0
0
0
7.9. Register 17 Loopback, Bypass, Receiver Error Mask
Register (LBREMR)
Table 19. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR)
Address Name
Description
Mode Default
17:15
17:14
17:13
17:12
17:11
17:10
17:9
RPTR
Set to 1 to put the RTL8201E(L) into repeater mode.
Assertion of this bit allows bypassing of the 4B/5B & 5B/4B encoder.
Assertion of this bit allows bypassing of the Scrambler/Descrambler.
Set to 1 to enable Link Down Power Saving mode.
Set to 1 to power down the analog function of transmitter and receiver.
Sets the inverse function of the Receive/Transmit LED.
Set to 1 to enable DSP loopback.
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
1
0
1
BP_4B5B
BP_SCR
LDPS
AnalogOFF
BMODE_EN
LB
17:8
F_Link_10
Used to logic force a good link in 10Mbps for diagnostic purposes.
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Address Name
Description
Mode Default
17:7
17:6
17:5
17:4
F_Link_100
Used to logic force a good link in 100Mbps for diagnostic purposes.
Set to 1 to enable jabber function in 10Base-T.
Assertion of this bit causes a code error detection to be reported.
RW
RW
RW
RW
1
1
0
0
JBEN
CODE_err
PME_err
Assertion of this bit causes a pre-mature end error detection to be
reported.
17:3
17:2
LINK_err
PKT_err
Assertion of this bit causes a link error detection to be reported.
RW
RW
0
0
Assertion of this bit causes a ‘detection of packet errors due to 722 ms
time-out’ to be reported.
17:1
17:0
FXMODE
SNIMODE
This bit indicates whether Fiber Mode is enabled.
This bit indicates whether SNI Mode is enabled.
RW
RW
0
0
7.10. Register 18 RX_ER Counter (REC)
Table 20. Register 18 RX_ER Counter (REC)
Address Name
Description
Mode
Default
18:15~0 RXERCNT
This 16-bit counter increments by 1 for each invalid packet received.
The value is valid while the link is established.
RO
0000
7.11. Register 19 SNR Display Register
Table 21. Register 19 SNR Display Register
Address
Name
Description
Mode
Default
19:15~4 Reserved
Realtek Test Mode Internal Use.
-
-
Do not change this field without Realtek’s approval.
19:3~0
SNR_0
These 4-Bits Show the Signal to Noise Ratio Value.
RW
0000
7.12. Register 25 Test Register
Table 22. Register 25 Test Register
Address Name
Description
Mode
RW
Default
25:15~12 Test
Reserved for Internal Testing.
-
This Bit Decides the Type of TXC in RMII mode
RW
1
25:11
25:10
RMII_CLKIN
0: Output
1: Input
RMII Mode
This Bit Sets the RMII Mode.
RW
0
1: RMII mode
Reserved.
0: MII mode
25:9
Reserved
-
-
25:7~8
PHYAD[1:0]
Reflects the PHY address defined by external PHY address
configuration pins.
RO
00001
25:6~2
25:1
Test
Reserved for Internal Testing.
RO
RO
-
LINK10
1: 10Base-T link established
0
0: No 10Base-T link established
25:0
LINK100
1: 100Base-FX or 100Base-TX link established
0: No 100Base link established
RO
0
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Track ID: JATR-1076-21 Rev. 1.3
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8. Functional Description
The RTL8201E(L) PHYceiver is a physical layer device that integrates 10Base-T and
100Base-TX/100Base-FX functions, and some extra power management features. This device supports
the following functions:
• MII interface with MDC/MDIO SMI management interface to communicate with the MAC
• IEEE 802.3u clause 28 Auto-Negotiation ability
• Flow control ability support to cooperate with MAC
• Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO
• Flexible LED configuration
• 7-wire SNI (Serial Network Interface) support (only in 10Mbps mode)
• Power Down mode support
• 4B/5B transform
• Scrambling/De-scrambling
• NRZ to NRZI, NRZI to MLT-3
• Manchester Encode and Decode for 10Base-T operation
• Clock and Data recovery
• Adaptive Equalization
• Far End Fault Indication (FEFI) in fiber mode
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
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8.1. MII and Management Interface
8.1.1. Data Transition
To set the RTL8201E(L) for MII mode operation, pull the COL/SNI pin low.
The MII (Media Independent Interface) is an 18-signal interface (as described in IEEE 802.3u) supplying
a standard interface between the PHY and MAC layer. This interface operates at two frequencies –
25MHz and 2.5MHz – to support 100Mbps/10Mbps bandwidth for both transmit and receive functions.
Transmission
The MAC asserts the TXEN signal. It then changes byte data into 4-bit nibbles and passes them to the
PHY via TXD[3:0]. The PHY will sample TXD[3:0] synchronously with TXC – the transmit clock signal
supplied by PHY – during the interval TXEN is asserted.
Reception
The PHY asserts the RXEN signal. It passes the received nibble data RXD[3:0] clocked by RXC. CRS
and COL signals are used for collision detection and handling.
In 100Base-TX mode, when the decoded signal in 5B is not IDLE, the CRS signal will assert. When 5B is
recognized as IDLE it will be de-asserted. In 10Base-T mode, CRS will assert when the 10M preamble
has been confirmed and will be de-asserted when the IDLE pattern has been confirmed.
The RXDV signal will be asserted when decoded 5B are /J/K/ and will be de-asserted if the 5B are /T/R/
or IDLE in 100Mbps mode. In 10Mbps mode, the RXDV signal is the same as the CRS signal.
The RXER (Receive Error) signal will be asserted if any 5B decode errors occur, e.g., an invalid J/K,
invalid T/R, or invalid symbol. This pin will go high for one or more clock periods to indicate to the
reconciliation sublayer that an error was detected somewhere in the frame.
Note: The RTL8201E(L) does not use a TXER signal. This does not affect the transmit function.
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Track ID: JATR-1076-21 Rev. 1.3
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8.1.2. Serial Management
The MAC layer device can use the MDC/MDIO management interface to control a maximum of 4
RTL8201E(L) devices, configured with different PHY addresses (00b to 11b).
During a hardware reset, the logic levels of pins 34/24 and 35/25 are latched into the RTL8201E(L) to be
set as the PHY address for management communication via the serial interface. The read and write frame
structure for the management interface is illustrated in Figure 4 and Figure 5.
MDC
Z
0
1
1
0
A4 A3 A2
A1 A0 R4 R3 R2 R1 R0
REGAD[4:0]
0
D14
D15 D13 D12
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA
32 1s
MDIO
Preamble
ST
OP
PHYAD[4:0]
TA
Idle
MDIO is sourced by PHY. Clock data from PHY on rising edge of MDC
MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC
Figure 4. Read Cycle
MDC
0
1
0
1
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
PHYAD[4:0] REGAD[4:0]
1
0
D14
D11
D8 D7 D6 D5
DATA
MDIO
D15
D13 D12
D10 D9
D4 D3 D2 D1 D0
32 1s
OP
Preamble
ST
TA
Idle
MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC
Figure 5. Write Cycle
Table 23. Serial Management
Name
Description
Preamble
32 Contiguous Logical 1’s Sent by the MAC on MDIO Along With 32 Corresponding Cycles on MDC.
This provides synchronization for the PHY.
ST
Start of Frame.
Indicated by a 01 pattern.
OP
Operation Code.
Read: 10
Write: 01
PHYAD
REGAD
TA
PHY Address.
Up to 4 PHYs can be connected to one MAC. This 2-bit field selects which PHY the frame is directed to.
Register Address.
This is a 5-bit field that sets which of the 32 registers of the PHY this operation refers to.
Turnaround.
This is a 2-bit-time spacing between the register address and the data field of a frame to avoid contention
during a read transaction. For a read transaction, both the STA and the PHY remain in a high-impedance
state for the first bit time of the turnaround. The PHY drives a zero bit during the second bit time of the
turnaround of a read transaction.
DATA
IDLE
Data.
These are the 16 bits of data.
Idle Condition.
Not truly part of the management frame. This is a high impedance state. Electrically, the PHY’s pull-up
resistor will pull the MDIO line to a logical ‘1’.
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Datasheet
8.1.3. Interrupt (RTL8201EL-VB Only)
Whenever there is a status change on the media that the RTL8201EL-VB detected, the RTL8201EL-VB
will drive the interrupt pin (INTB) low to issue an interrupt event. The MAC senses the status change and
accesses the registers through the MDC/MDIO interface in response.
Once these status registers have been read by MAC through the MDC/MDIO, the INTB is de-asserted.
The RTL8201EL-VB interrupt function removes the need for continuous polling through the
MDC/MDIO management interface.
8.2. Auto-Negotiation and Parallel Detection
The RTL8201E(L) supports IEEE 802.3u clause 28 Auto-negotiation for operation with other transceivers
supporting auto-negotiation. The RTL8201E(L) can auto-detect the link partner’s abilities and determine
the highest speed/duplex configuration possible between the two devices. If the link partner does not
support auto-negotiation, then the RTL8201E(L) will enable half duplex mode and enter parallel
detection mode. The RTL8201E(L) will default to transmitting FLP (Fast Link Pulse) and wait for the
link partner to respond. If the RTL8201E(L) receives a FLP, then the auto-negotiation process will go on.
If it receives NLP (Normal Link Pulse), then the RTL8201E(L) will change to 10Mbps and half duplex
mode. If it receives a 100Mbps IDLE pattern, it will change to 100Mbps and half duplex mode.
8.2.1. Setting the Medium Type and Interface Mode to MAC
Table 24. Setting the Medium Type and Interface Mode to MAC
FXEN
COL/SNI
RXDV
Operation Mode
H
H
H
L
L
L
L
L
H
L
L
H
L
H
X
L
Fiber Mode and MII Mode.
Fiber Mode and RMII Mode.
Fiber Mode and SNI Mode.
UTP Mode and MII Mode.
UTP Mode and RMII Mode.
UTP Mode and SNI Mode.
H
X
8.3. Flow Control Support
The RTL8201E(L) supports flow control indications. The MAC can program the MII register to indicate
to the PHY that flow control is supported. When the MAC supports the Flow Control mechanism, setting
bit 10 of the ANAR register using the MDC/MDIO SNI interface, then the RTL8201E(L) will add the
ability to its NWay ability. If the Link partner also supports Flow Control, then the RTL8201E(L) can
recognize the Link partner’s NWay ability by examining bit 10 of ANLPAR (register 5).
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8.4. Hardware Configuration and Auto-Negotiation
This section describes methods to configure the RTL8201E(L) and set the auto-negotiation mode. Table
25 shows the various pins and their settings.
Table 25. Auto-Negotiation Mode Pin Settings
Pin Name
Description
CRS/RPTR/
CRS_DV
Pull high to set the RTL8201E(L) into Repeater Mode.
This pin is pulled low by default (see 8.9 Repeater Mode Operation, page 24).
COL/SNI
Pull low to set the RTL8201E(L) into MII/RMII Mode operation, which is the Default Mode for the
RTL8201E(L). This pin pulled high will set the RTL8201E(L) into SNI mode operation. When set to SNI
mode, the RTL8201E(L) will operate at 10Mbps (see section 8.6 Serial Network Interface, page 22).
8.5. LED and PHY Address Configuration
In order to reduce the pin count on the RTL8201E(L), the LED pins are duplexed with the PHY address
pins. The external combinations required for strapping and LED usage must be considered in order to
avoid contention. Specifically, when the LED outputs are used to drive LEDs directly, the active state of
each output driver is dependent on the logic level sampled by the corresponding PHYAD input upon
power-up/reset. For example, as Figure 6 (left-side) shows, if a given PHYAD input is resistively pulled
high, then the corresponding output will be configured as an active low driver. On the right side, we can
see that if a given PHYAD input is resistively pulled low then the corresponding output will be
configured as an active high driver. The PHY address configuration pins should not be connected to GND
or VCC directly, but must be pulled high or low through a resistor (e.g., 4.7KΩ). If no LED indications
are needed, the components of the LED path (LED+510Ω) can be removed.
PHY Address[:]=Logical 1
LED Indication=Active low
PHY Address[:]=Logical 0
LED Indication=Active High
Figure 6. LED and PHY Address Configuration
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Track ID: JATR-1076-21 Rev. 1.3
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Datasheet
8.6. Serial Network Interface
The RTL8201E(L) also supports the traditional 7-wire serial interface to operate with legacy MACs or
embedded systems. To setup for this mode of operation, pull the COL/SNI pin high. In this mode, the
RTL8201E(L) will set the default operation to 10Mbps and half-duplex mode. This interface consists of a
10Mbps transmit and receive clock generated by PHY, 10Mbps transmit and receive serial data, transmit
enable, collision detect, and carry sense signals.
8.7. Power Down, Link Down, and Power Saving Modes
Three types of Power Saving mode operation are supported. This section describes how to implement
each mode through software.
Table 26. Power Saving Mode Pin Settings
Mode
Description
Analog Off
Setting bit 11 of register 17 to 1 will put the RTL8201E(L) into analog off state. In analog off state, the
RTL8201E(L) will power down all analog functions such as transmit, receive, PLL, etc. However, the
internal 25MHz crystal oscillator will not be powered down. Digital functions in this mode are still
available which allows reacquisition of analog functions
LDPS
PWD
Setting bit 12 of register 17 to 1 will put the RTL8201E(L) into LDPS (Link Down Power Saving) mode.
In LDPS mode, the RTL8201E(L) will detect the link status to decide whether or not to turn off the
transmit function. If the link is off, FLP or 100Mbps IDLE/10Mbps NLP will not be transmitted.
However, some signals similar to NLP will be transmitted. Once the receiver detects leveled signals, it
will stop the signal and transmit FLP or 100Mbps IDLE/10Mbps NLP again. This can cut power used by
60%~80% when the link is down.
Setting bit 11 of register 0 to 1 puts the RTL8201E(L) into power down mode. This is the maximum
power saving mode while the RTL8201E(L) is still alive. In PWD mode, the RTL8201E(L) will turn off
all analog/digital functions except the MDC/MDIO management interface. Therefore, if the
RTL8201E(L) is put into PWD mode and the MAC wants to recall the PHY, it must create the
MDC/MDIO timing by itself (this is done by software).
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8.8. Media Interface
8.8.1. 100Base-TX Transmit and Receive Operation
100Base-TX Transmit
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 25MHz (TXC) is transformed into 5B symbol code
(4B/5B encoding). Scrambling, serializing, and conversion to 125MHz, and NRZ to NRZI then takes
place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver.
The transmitter will first assert TXEN. Before transmitting the data pattern, it will send a /J/K/ symbol
(Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame
delimiter. For better EMI performance, the seed of the scrambler is based on the PHY address. In a
hub/switch environment, each RTL8201E(L) will have different scrambler seeds and so spread the output
of the MLT-3 signals.
100Base-TX Receive
The received signal is compensated by the adaptive equalizer to make up for signal loss due to cable
attenuation and Inter Symbol Interference (ISI). Baseline Wander Correction monitors the process and
dynamically applies corrections to the process of signal equalization. The Phase Locked Loop (PLL) then
recovers the timing information from the signals and from the receive clock. With this, the received signal
is sampled to form NRZI (Non-Return-to-Zero Inverted) data. The next steps are the NRZI to NRZ (Non-
Return-to-Zero) process, unscrambling of the data, serial to parallel and 5B to 4B conversion, and passing
of the 4B nibble to the MII interface.
8.8.2. 100Base-FX Fiber Transmit and Receive Operation
The RTL8201E(L) can be configured to 100Base-FX mode via hardware configuration. The hardware
100Base-FX setting takes priority over NWay settings. A scrambler is not required in 100Base-FX.
100Base-FX Transmit
Di-bits of TXD are processed as 100Base-TX except without a scrambler before the NRZI stage. Instead
of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL
signals, which enter the fiber transceiver in differential-pair form.
100Base-FX Receive
The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the
clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX.
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8.8.3. 10Base-T Transmit and Receive Operation
10Base-T Transmit
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 2.5MHz (TXC) is first fed to a parallel-to-serial
converter, then the 10Mbps NRZ signal is sent to a Manchester encoder. The Manchester encoder
converts the 10Mbps NRZ data into a Manchester Encoded data stream for the TP transmitter and adds a
Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Finally, the encoded data
stream is shaped by a band-limited filter embedded in the RTL8201E(L) and then transmitted.
10Base-T Receive
In 10Base-T receive mode, the Manchester decoder in the RTL8201E(L) converts the Manchester
encoded data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then the serial
NRZ data stream is converted to a parallel 4-bit nibble signal (RXD[0:3]).
8.9. Repeater Mode Operation
Setting bit 15 of register 17 to 1, or pulling the RPTR pin high, sets the RTL8201E(L) into repeater mode.
In repeater mode, the RTL8201E(L) will assert CRS high only when receiving a packet. In NIC mode, the
RTL8201E(L) will assert CRS high both when transmitting and receiving packets. If using the
RTL8201E(L) in a NIC or switch application, set to the default mode. NIC/Switch mode is the default
setting and has the RPTR pin pulled low, or bit 15 of register 17 is set to 0.
8.10. Reset and Transmit Bias
The RTL8201E(L) can be reset by pulling the PHYRSTB pin low for about 10ms, then pulling the pin
high. It can also be reset by setting bit 15 of register 0 to 1, and then setting it back to 0. Reset will clear
the registers and re-initialize them. The media interface will disconnect and restart the auto-
negotiation/parallel detection process.
The RSET pin must be pulled low by a 2.49KΩ resister with 1% accuracy to establish an accurate
transmit bias. This will affect the signal quality of the transmit waveform. Keep its circuitry away from
other clock traces and transmit/receive paths to avoid signal interference.
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Datasheet
8.11. 3.3V Power Supply and Voltage Conversion Circuit
The RTL8201E(L) is fabricated in a 0.11µm process. The core circuit needs to be powered by 1.2V,
however, the digital IO and DAC circuits need a 3.3V power supply. Regulators are embedded in the
RTL8201E(L) to convert 3.3V to 1.2V. An external 1.2V power supply is not suggested, as the internal
regulators cannot be disabled, and two 1.2V power sources may conflict. As with many commercial
voltage conversion devices, the 1.2V output pin (PWFBOUT) of this circuit requires the use of an output
capacitor (0.1µF ceramic capacitor is recommended) as part of the device frequency compensation.
The analog and digital ground planes should be as large and intact as possible. If the ground plane is large
enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the
total ground plane is not sufficiently large, partition of the ground plane is not a good idea. In this case,
all the ground pins can be connected together to a larger single and intact ground plane.
8.12. Far End Fault Indication
The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled,
and indicates when a FEFI has been detected. FEFI is an alternative in-band signaling method which is
composed of 84 consecutive ‘1’s followed by one ‘0’. When the RTL8201E(L) detects this pattern three
times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem. On
the other hand, if an incoming signal fails to cause a ‘Link OK’, the RTL8201E(L) will start sending this
pattern, which in turn causes the remote side to detect a Far End Fault. This means that the receive path
has a problem from the point of view of the RTL8201E(L). The FEFI mechanism is used only in
100Base-FX mode.
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Datasheet
9. Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 27. Absolute Maximum Ratings
Item
Minimum
2.97V
Typical
3.3V
-
Maximum
3.63V
Supply Voltage
Storage Temperature
-55°C
125°C
9.1.2. Operating Conditions
Table 28. Operating Conditions
Item
Vcc 3.3V 3.3V Supply Voltage
TA Ambient Operating Temperature
Condition
Minimum
2.97V
Typical
3.3V
-
Maximum
3.63V
0°C
70°C
9.1.3. Power On Sequence
Figure 7. Power On Sequence
Table 29. Power On Sequence
Minimum
Symbol
Rt1
Description
Maximum
50ms
3.3V Rise Time
1.2V Delay Time
1ms
Rt2
300µs
1ms
The RTL8201E(L) needs 250ms power on time. After 250ms it can access the PHY register from
MDC/MDIO.
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9.1.4. PHY Reset Sequence
Figure 8. PHY Reset Sequence
Table 30. PHY Reset Sequence Operating Conditions
Symbol
Rt1
Description
Minimum
Maximum
10ms
3.3V Rise Time (PHYRST)
1.2V Delay Time
1ms
Rt2
300µs
1ms
9.1.5. Power Dissipation
Test Condition: The data was measured from an RTL8201EL Demo Board. The total current
consumption is defined as the system current consumption, including AVDD3.3, DVDD3.3, AVDD1.2,
and DVDD1.2V power consumption, as well as regulator loss.
Table 31. Power Dissipation
Symbol
PLDPS
PAnaOff
PPWD
Condition
Total Current Consumption
Link Down Power Saving Mode
Analog Off Mode
Power Down Mode
100Base Full Duplex
10Base-T Full Duplex
10Base-T Transmit
10Base-T Receive
10Base-T Idle
27mA
20mA
15mA
62mA
67mA
66mA
29mA
27mA
P100F
P10F
P10TX
P10RX
P10IDLE
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Datasheet
9.1.6. Input Voltage: Vcc
Table 32. Input Voltage: Vcc
Symbol Condition
Minimum
Maximum
Vcc +0.5V
0.7V
TTL VIH Input High Voltage
TTL VIL Input Low Voltage
TTL VOH Output High Voltage
TTL VOL Output Low Voltage
-
-
0.5*Vcc
-0.5V
IOH=-8mA
IOL=8mA
0.65*Vcc
-
Vcc
0.7V
TTL IOZ
IIN
Tri-State Leakage
Input Current
Vout=Vcc or GND
Vin=Vcc or GND
-110µA
-1µA
10µA
10µA
IPL
Input Current with Internal weakly pulled low resistor Vin=Vcc or GND
-1µA
100µA
10µA
IPH
Input Current with Internal weakly pulled high
resistor
Vin=Vcc or GND
-110µA
PECL VIH PECL Input High Voltage
PECL VIL PECL Input Low Voltage
PECL VOH PECL Output High Voltage
PECL VOL PECL Output Low Voltage
-
-
-
-
Vdd -1.16V Vdd -0.88V
Vdd -1.81V Vdd -1.47V
Vdd -1.02V
-
-
Vdd -1.62V
9.2. AC Characteristics
9.2.1. MII Transmission Cycle Timing
Table 33. MII Transmission Cycle Timing
Symbol Description
Minimum Typical Maximum Unit
T1
T2
t3
TXCLK High Pulse Width
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
14
140
14
140
-
20
26
260
26
260
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
TXCLK Low Pulse Width
TXCLK Period
20
200
40
-
400
-
t4
TXEN, TXD[0:3]
Setup to TXCLK Rising Edge
10
5
-
-
-
-
t5
TXEN, TXD[0:3]
Hold After TXCLK Rising Edge
0
-
25
-
0
-
t6
TXEN Sampled to CRS High
TXEN Sampled to CRS Low
Transmit Latency
-
-
40
400
160
2000
140
2000
170
-
-
-
-
t7
-
-
-
t8
60
-
70
-
t9
Sampled TXEN Inactive to End of Frame
-
100
-
-
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Figure 9 and Figure 10 and show an example of a packet transfer from MAC to PHY on the MII interface.
t
3
VI H(min)
VI L(max)
TXCLK
t
t
2
1
t
t
5
4
VIH(min)
VI L(max)
TXD[0:3]
TXEN
Figure 9. MII Transmission Cycle Timing-1
TXCLK
TXEN
TXD[0:3]
t
t
7
6
CRS
t
t
8
9
TPTX+-
Figure 10. MII Transmission Cycle Timing-2
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9.2.2. MII Reception Cycle Timing
Table 34. MII Reception Cycle Timing
Symbol Description
Minimum Typical Maximum Unit
t1
t2
t3
t4
t5
t6
t7
t8
t9
RXCLK High Pulse Width
RXCLK Low Pulse Width
RXCLK Period
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
14
140
14
140
-
20
26
260
26
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
20
200
260
-
40
-
400
-
RXER, RXDV, RXD[0:3]
Setup to RXCLK Rising Edge
10
10
10
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RXER, RXDV, RXD[0:3]
Hold After RXCLK Rising Edge
-
-
Receive Frame to CRS High
130
2000
240
1000
150
3200
120
1000
-
End of Receive Frame to CRS Low
Receive Frame to Sampled Edge of RXDV
-
-
-
-
End of Receive Frame to Sampled Edge of RXDV 100Mbps
10Mbps
-
-
Figure 11 and Figure 12 show an example of a packet transfer from PHY to MAC on the MII interface.
t
3
V
V
RXCLK
I H(min)
I L(max)
t
t
2
t
t
5
4
1
RXD[0:3]
RXDV
V
V
I H(min)
I L(max)
RXER
Figure 11. MII Reception Cycle Timing-1
RXCLK
t9
t8
RXDV
RXD[0:3]
t6
t7
CRS
TPRX+-
Figure 12. MII Reception Cycle Timing-2
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9.2.3. RMII Transmission Cycle Timing (RTL8201E(L)-VB Only)
Table 35. RMII Transmission Cycle Timing (RTL8201E(L)-VB Only)
Symbol
Description
Minimum Typical Maximum Unit
REF_CLK Frequency
REF_CLK Duty Cycle
T_ipsu_txd_rmii
T_iphd_txd_rmii
Frequency of Reference Clock
Duty Cycle of Reference Clock
TXD/TXEN Setup Time to REFCLK
TXD/TXEN Hold Time from REFCLK
-
35
4
50
-
-
65
-
MHz
%
-
ns
2
-
-
ns
T_ipsu_txd_rmii
T_iphd_txd_rmii
REFCLK
TXD
Valid Data
Figure 13. RMII Transmission Cycle Timing
9.2.4. RMII Reception Cycle Timing (RTL8201E(L)-VB Only)
Table 36. RMII Reception Cycle Timing (RTL8201E(L)-VB Only)
Symbol
Description
Minimum Typical Maximum Unit
T_ipsu_rxd_rmii
T_iphd_rxd_rmii
RXD/CRS_DV Setup Time to REFCLK
RXD/CRS_DV Hold Time from REFCLK
4
2
-
-
-
-
ns
ns
T_ipsu_rxd_rmii
T_iphd_rxd_rmii
REFCLK
RXD
Valid Data
Figure 14. RMII Reception Cycle Timing
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9.2.5. SNI Transmission Cycle Timing
Table 37. SNI Transmission Cycle Timing
Symbol Description
Minimum
Maximum
Unit
ns
t1
t2
t3
t4
t5
t8
TXCLK High Pulse Width
36
36
80
20
10
-
-
-
TXCLK Low Pulse Width
ns
TXCLK Period
120
-
ns
TXEN, TXD0 Setup to TXCLK Rising Edge
TXEN, TXD0 Hold after TXCLK Rising Edge
Transmit Latency
ns
-
ns
50
ns
Figure 15 and Figure 16 show an example of a packet transfer from MAC to PHY on the SNI interface.
Note: SNI mode only runs at 10Mbps.
Figure 15. SNI Transmission Cycle Timing-1
TXCLK
TXEN
TXD0
t
8
TPTX+-
Figure 16. SNI Transmission Cycle Timing-2
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9.2.6. SNI Reception Cycle Timing
Table 38. SNI Reception Cycle Timing
Symbol Description
Minimum
Typical
Maximum
Unit
ns
t1
t2
t3
t4
t5
t6
t7
t8
RXCLK High Pulse Width
36
36
80
40
40
-
-
-
-
RXCLK Low Pulse Width
-
ns
RXCLK Period
-
120
-
ns
RXD0 Setup to RXCLK Rising Edge
RXD0 Hold after RXCLK Rising Edge
Receive Frame to CRS High
End of Receive Frame to CRS Low
Decoder Acquisition Time
-
ns
-
-
-
ns
50
160
1800
ns
-
-
ns
-
600
ns
Figure 17 and Figure 18 show an example of a packet transfer from PHY to MAC on the SNI interface.
Note: SNI mode only runs at 10Mbps.
Figure 17. SNI Reception Cycle Timing-1
Figure 18. SNI Reception Cycle Timing-2
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9.2.7. MDC/MDIO Timing
Table 39. MDC/MDIO Timing
Symbol Description
Minimum
160
Maximum
Unit
ns
t1
t2
t3
t4
t5
t6
MDC High Pulse Width
MDC Low Pulse Width
MDC Period
-
160
-
ns
400
-
-
ns
MDIO Setup to MDC Rising Edge
10
10
0
ns
MDIO Hold Time from MDC Rising Edge
MDIO Valid from MDC Rising Edge
-
ns
300
ns
t
3
V
IH(min)
IL (max)
MDC
V
t
t
t
t
5
4
1
2
MDIO
Sourced by
STA
V
IH(min)
V
IL (max)
t
6
MDIO
V
Sourced by
IH(min)
V
RTL8201EL
I L(max)
Figure 19. MDC/MDIO Timing
9.2.8. Transmission without Collision
Figure 20 shows an example of a packet transfer from MAC to PHY.
Figure 20. MAC to PHY Transmission Without Collision
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9.2.9. Reception without Error
Figure 21 shows an example of a packet transfer from PHY to MAC.
Figure 21. PHY to MAC Reception Without Error
9.3. Crystal Characteristics
Table 40. Crystal Characteristics
Parameter
Range
Nominal Frequency
Oscillation Mode
25.000MHz
Base wave
±50ppm
Frequency Tolerance at 25°C
Frequency Tolerance at -20~70°C
Operating Temperature Range
Equivalent Series Resistance
Drive Level
±30ppm
-10°C ~ +70°C
30ohm Max.
0.1mV
Load Capacitance
20pF
Shunt Capacitance
7pF Max.
Insulation Resistance
Test Impedance Meter
Aging Rate Per Year
Mega ohm Min./DC 100V
Saunders 250A
±0.0003%
9.4. Transformer Characteristics
Table 41. Transformer Characteristics
Parameter
Turn Ratio
Transmit End
1:1 CT
Receive End
1:1 CT
Inductance (min.)
350µH @ 8mA
350µH @ 8mA
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10. Mechanical Dimensions
10.1. RTL8201E (32-Pin QFN)
Symbol
Dimension in mm
Dimension in inch
Nom
Min
0.75
0.00
Nom
0.85
Max
1.00
0.05
Min
0.030
0.000
Max
0.039
0.002
A
A1
A3
b
0.034
0.02
0.001
0.20 REF
0.25
0.008 REF
0.010
0.18
-
0.30
0.6
0.007
-
0.012
0.024
c
-
-
D/E
D2/E2
e
5.00 BSC
3.35
0.197 BSC
0.132
3.10
3.60
0.122
0.012
0.142
0.020
0.50 BSC
0.40
0.020 BSC
0.016
L
0.30
0.50
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENTL: JEDEC MO-220.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
36
Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
10.2. RTL8201EL (48-Pin LQFP)
Symbol
Dimension in mm
Nom
Dimension in inch
Min
-
Max
1.60
0.15
1.45
0.27
Min
-
Nom
Max
0.063
0.006
0.057
0.011
A
A1
A2
b
-
-
0.05
1.35
0.17
-
0.002
0.053
0.007
-
1.40
0.055
0.22
0.009
D/E
D1/E1
e
9.00 BSC
7.00 BSC
0.50 BSC
0.60
0.354 BSC
0.276 BSC
0.020 BSC
0.024
L
0.45
0.75
0.018
0.030
L1
1.00 REF
0.039 REF
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENTL: JEDEC MS-026.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
37
Track ID: JATR-1076-21 Rev. 1.3
RTL8201E(L)
Datasheet
11. Ordering Information
Table 42. Ordering Information
Part Number
RTL8201E-GR
Package
Status
32-Pin QFN with Green Package
Production
Production
Sampling
Sampling
RTL8201EL-GR
RTL8201E-VB-GR
RTL8201EL-VB-GR
48-Pin LQFP with Green Package
RTL8201E-GR Version B (adds RMII and INTB support)
RTL8201EL-GR Version B (adds RMII and INTB support)
Note: See page 4 and 5 for package identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan.
Tel: 886-3-578-0211 Fax: 886-3-577-6047
www.realtek.com
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
38
Track ID: JATR-1076-21 Rev. 1.3
相关型号:
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