2SK3919-ZK-AZ
更新时间:2024-09-18 14:22:56
品牌:RENESAS
描述:64000mA, 25V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-252AB, TO-252, MP-3Z, 3 PIN
2SK3919-ZK-AZ 概述
64000mA, 25V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-252AB, TO-252, MP-3Z, 3 PIN 小信号场效应晶体管
2SK3919-ZK-AZ 规格参数
是否无铅: | 不含铅 | 是否Rohs认证: | 符合 |
生命周期: | Obsolete | 零件包装代码: | TO-252AB |
包装说明: | SMALL OUTLINE, R-PSSO-G2 | 针数: | 4 |
Reach Compliance Code: | compliant | ECCN代码: | EAR99 |
HTS代码: | 8541.29.00.95 | 风险等级: | 5.33 |
外壳连接: | DRAIN | 配置: | SINGLE WITH BUILT-IN DIODE |
最小漏源击穿电压: | 25 V | 最大漏极电流 (Abs) (ID): | 64 A |
最大漏极电流 (ID): | 64 A | 最大漏源导通电阻: | 0.0056 Ω |
FET 技术: | METAL-OXIDE SEMICONDUCTOR | JEDEC-95代码: | TO-252AB |
JESD-30 代码: | R-PSSO-G2 | 元件数量: | 1 |
端子数量: | 2 | 工作模式: | ENHANCEMENT MODE |
最高工作温度: | 150 °C | 封装主体材料: | PLASTIC/EPOXY |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE |
峰值回流温度(摄氏度): | 260 | 极性/信道类型: | N-CHANNEL |
最大功率耗散 (Abs): | 36 W | 认证状态: | Not Qualified |
子类别: | FET General Purpose Power | 表面贴装: | YES |
端子形式: | GULL WING | 端子位置: | SINGLE |
处于峰值回流温度下的最长时间: | NOT SPECIFIED | 晶体管应用: | SWITCHING |
晶体管元件材料: | SILICON | Base Number Matches: | 1 |
2SK3919-ZK-AZ 数据手册
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PDF下载DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SK3919
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
ORDERING INFORMATION
The 2SK3919 is N-channel MOS FET device that
features a low on-state resistance and excellent switching
characteristics, and designed for low voltage high current
applications such as DC/DC converter with synchronous
rectifier.
PART NUMBER
2SK3919
PACKAGE
TO-251 (MP-3)
TO-252 (MP-3ZK)
2SK3919-ZK
(TO-251)
FEATURES
• Low on-state resistance
RDS(on)1 = 5.6 mΩ MAX. (VGS = 10 V, ID = 32 A)
• Low Ciss: Ciss = 2050 pF TYP.
• 5 V drive available
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
(TO-252)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
25
±20
V
V
±64
A
±256
36
A
Total Power Dissipation (TC = 25°C)
Total Power Dissipation
W
W
°C
°C
A
PT2
1.0
Channel Temperature
Tch
150
Storage Temperature
Tstg
−55 to +150
27
Single Avalanche Current Note2
Single Avalanche Energy Note2
IAS
EAS
73
mJ
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Starting Tch = 25°C, VDD = 12.5 V, RG = 25 Ω, VGS = 20 → 0 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D17078EJ2V0DS00 (2nd edition)
Date Published September 2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2004
2SK3919
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
µA
nA
V
IDSS
VDS = 25 V, VGS = 0 V
10
±100
3.0
IGSS
VGS = ±20 V, VDS = 0 V
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 16 A
VGS = 10 V, ID = 32 A
VGS = 5.0 V, ID = 16 A
Gate Cut-off Voltage
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
Ciss
2.0
9.7
2.5
19
Note
Forward Transfer Admittance
S
Note
Drain to Source On-state Resistance
4.5
6.8
2050
460
330
16
5.6
mΩ
mΩ
pF
pF
pF
ns
13.7
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
VDS = 10 V
VGS = 0 V
f = 1 MHz
Coss
Crss
td(on)
tr
VDD = 12.5 V, ID = 32 A
VGS = 10 V
19
ns
RG = 10 Ω
Turn-off Delay Time
Fall Time
td(off)
tf
53
ns
22
ns
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
QG
VDD = 20 V
VGS = 10 V
ID = 64 A
42
nC
nC
nC
V
QGS
QGD
VF(S-D)
trr
8
15
Note
Body Diode Forward Voltage
IF = 64 A, VGS = 0 V
IF = 64 A, VGS = 0 V
di/dt = 100 A/µs
0.97
23
Reverse Recovery Time
Reverse Recovery Charge
Note Pulsed
ns
Qrr
11
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
D.U.T.
V
GS
R
L
R
G
= 25 Ω
90%
V
GS
Wave Form
VGS
10%
0
R
G
PG.
GS = 20 → 0 V
PG.
50 Ω
V
DD
V
DD
V
VDS
90%
90%
V
DS
V
0
GS
BVDSS
10% 10%
V
DS
Wave Form
0
I
AS
V
DS
τ
I
D
td(on)
tr
td(off)
tf
VDD
ton
toff
τ = 1 µs
Duty Cycle ≤ 1%
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
= 2 mA
I
G
R
L
PG.
50 Ω
V
DD
2
Data Sheet D17078EJ2V0DS
2SK3919
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
120
100
80
60
40
20
0
40
35
30
25
20
15
10
5
0
0
25
50
75 100 125 150 175
0
25
50
75 100 125 150 175
TC - Case Temperature - °C
TC - Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
1000
100
10
I
D(pulse)
PW = 100 µs
I
D(DC)
R
DS(on) Limited
(at VGS = 10 V)
Power Dissipation Limited
1 ms
10 ms
1
T
C
= 25°C
Single pulse
0.1
0.1
1
10
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
100
10
R
th(ch-A) = 125°C/W
Rth(ch-C) = 3.47°C/W
1
0.1
0.01
Single pulse
100 1000
100 µ
1 m
10 m
100 m
1
10
PW - Pulse Width - s
3
Data Sheet D17078EJ2V0DS
2SK3919
DRAIN CURRENT vs.
FORWARD TRANSFER CHARACTERISTICS
DRAIN TO SOURCE VOLTAGE
300
250
200
150
100
50
1000
100
10
T
ch = −55°C
25°C
V
GS = 10 V
75°C
125°C
150°C
1
5.0 V
0.1
0.01
V
DS = 10 V
Pulsed
Pulsed
0
0
0.5
1
1.5
2
2.5
0
1
2
3
4
5
6
VDS - Drain to Source Voltage - V
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
4
3
2
1
0
100
10
1
T
ch = −55°C
25°C
V
DS = 10 V
I = 1 mA
D
75°C
125°C
150°C
V
DS = 10 V
Pulsed
0.1
0.1
1
10
100
-100
-50
0
50
100
150
200
ID - Drain Current - A
Tch - Channel Temperature - °C
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
15
15
Pulsed
Pulsed
10
10
VGS = 5.0 V
I = 32 A
D
5
0
5
0
10 V
1
10
100
1000
0
5
10
15
20
ID - Drain Current - A
VGS - Gate to Source Voltage - V
4
Data Sheet D17078EJ2V0DS
2SK3919
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
10000
10
8
C
iss
6
4
2
0
V
GS = 10 V
1000
100
C
oss
V
GS = 0 V
I = 32 A
D
C
rss
f = 1 MHz
Pulsed
0.01
0.1
1
10
100
-100
-50
0
50
100
150
200
VDS - Drain to Source Voltage - V
Tch - Channel Temperature - °C
SWITCHING CHARACTERISTICS
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
1000
100
10
30
25
20
15
10
5
12
10
8
I = 64 A, 42 A (at VDD = 5 V)
D
V
DD = 20 V
12.5 V
5 V
t
d(off)
t
f
6
t
t
d(on)
r
V
GS
4
V
V
DD = 12.5 V
2
GS = 10 V
V
DS
R = 10 Ω
G
1
0
0
0.1
1
10
100
0
20
40
ID - Drain Current - A
QG - Gate Charge - nC
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
1000
100
10
1000
100
10
di/dt = 100 A/µs
V
GS = 10 V
V
GS = 0 V
0 V
1
0.1
0.01
Pulsed
1.5
1
0
0.5
1
1
10
IF - Diode Forward Current - A
100
VF(S-D) - Source to Drain Voltage - V
5
Data Sheet D17078EJ2V0DS
2SK3919
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
SINGLE AVALANCHE ENERGY
DERATING FACTOR
100
10
1
120
100
80
60
40
20
0
V
DD = 12.5 V
= 25 Ω
GS = 20 → 0 V
AS ≤ 27 A
R
G
V
I
I
AS = 27 A
E
AS = 73 mJ
V
DD = 12.5 V
= 25 Ω
GS = 20 → 0 V
Starting Tch = 25°C
R
G
V
25
50
75
100
125
150
0.01
0.1
1
10
Starting Tch - Starting Channel Temperature - °C
L - Inductive Load - mH
6
Data Sheet D17078EJ2V0DS
2SK3919
PACKAGE DRAWINGS (Unit: mm)
1) TO-251 (MP-3)
2) TO-252 (MP-3ZK)
6.6 0.2
Mold Area
2.3 0.1
5.3 TYP.
4.3 MIN.
0.5 0.1
2.3 0.1
6.5 0.2
5.1 TYP.
4.3 MIN.
4
0.5 0.1
No Plating
4
1
2
3
No Plating
1
2
3
1.14 MAX.
No Plating
0.75 0.12
1.14 MAX.
0 to 0.25
0.5 0.1
2.3 2.3
0.5 0.1
0.76 0.1
2.3 TYP.
1.0
2.3 TYP.
1. Gate
2. Drain
3. Source
4. Fin (Drain)
1. Gate
2. Drain
3. Source
4. Fin (Drain)
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Source
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop generation of static electricity as much as
possible, and quickly dissipate it once, when it has occurred.
7
Data Sheet D17078EJ2V0DS
2SK3919
•
The information in this document is current as of September, 2004. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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defined above).
M8E 02. 11-1
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