5962R9675501V9X [RENESAS]
PARALLEL, WORD INPUT LOADING, 12-BIT DAC, UUC24;
| 型号： | 5962R9675501V9X |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | PARALLEL, WORD INPUT LOADING, 12-BIT DAC, UUC24 输入元件 |
| 文件： | 总7页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-565ARH
TM
Data Sheet
November 2000
File Number 3278.4
Radiation Hardened High Speed,
Features
Monolithic Digital-to-Analog Converter
• Electrically Screened to SMD # 5962-96755
• QML Qualified per MIL-PRF-38535 Requirements
• Total Dose . . . . . . . . . . . . . . . . . . . . . 100 krad (Si) (Max)
• DAC and Reference on a Single Chip
The HS-565ARH is a fast, radiation hardened 12-bit current
output, digital-to-analog converter. The monolithic chip
includes a precision voltage reference, thin-film R-2R ladder,
reference control amplifier and twelve high-speed bipolar
current switches.
• Pin Compatible with AD-565A and HI-565A
• Very High Speed: Settles to 0.50 LSB in 500ns Max
• Monotonicity Guaranteed Over Temperature
• 0.50 LSB Max Nonlinearity Guaranteed Over Temperature
• Low Gain Drift
The Intersil Corporation Dielectric Isolation process provides
latch-up free operation while minimizing stray capacitance
and leakage currents, to produce an excellent combination
of speed and accuracy. Also, ground currents are minimized
to produce a low and constant current through the ground
terminal, which reduces error due to code-dependent ground
currents.
o
(Max., DAC Plus Reference) . . . . . . . . . . . . . . .50ppm/ C
• ±0.75 LSB Accuracy Guaranteed Over Temperature
(±0.125 LSB Typical at 25 C)
HS-565ARH die are laser trimmed for a maximum integral
nonlinearity error of ±0.25 LSB at 25 C. In addition, the low
o
o
noise buried zener reference is trimmed both for absolute
value and minimum temperature coefficient.
Applications
• High Speed A/D Converters
• Precision Instrumentation
• Signal Reconstruction
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96755. A “hot-link” is provided
on our homepage for downloading.
Functional Diagram
BIP.
REF OUT VCC
www.intersil.com/spacedefense/space.htm
OFF.
11
4
3
20V
SPAN
8
+
5K
5K
10V
10
9
Ordering Information
10V
SPAN
-
9.95K
IO
IREF
DAC
0.5mA
INTERNAL
MKT. NUMBER
TEMP. RANGE
19.95K
6
5
o
REF
IN
OUT
ORDERING NUMBER
5962R9675501V9A
5962R9675501VJC
5962R9675501VXC
( C)
+
-
3.5K
3K
2.5K
(4X IREF
X CODE)
HS0-565ARH-Q
HS1-565ARH-Q
HS9-565ARH-Q
25
REF
GND
-55 to 125
-55 to 125
-55 to 125
7
12
24 . . . 13
MSB LSB
-VEE PWR
GND
HS9-565ARH/PROTO HS9-565ARH/PROTO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1
HS-565ARH
Pinouts
HS1-565ARH
MIL-STD-1835 CDIP2-T24
(SBDIP)
TOP VIEW
NC
NC
1
2
24 BIT 1 IN (MSB)
23 BIT 2 IN
22
VCC
3
BIT 3 IN
REF OUT
REF GND
REF IN
21 BIT 4 IN
20 BIT 5 IN
19 BIT 6 IN
18 BIT 7 IN
17 BIT 8 IN
16 BIT 9 IN
15 BIT 10 IN
14 BIT 11 IN
13 BIT 12 IN (LSB)
4
5
6
-VEE
7
BIPOLAR RIN
IDAC OUT
10V SPAN
8
9
10
20V SPAN 11
PWR GND 12
H59-565ARH
MIL-STD-1835 CDFP4-F24
(CERAMIC FLATPACK)
TOP VIEW
BIT 1 IN
(MSB)
1
24
23
22
21
20
19
18
17
16
15
14
13
NC
NC
2
BIT 2 IN
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
BIT 7 IN
BIT 8 IN
BIT 9 IN
BIT 10 IN
BIT 11 IN
3
VCC
4
REF OUT
REF GND
REF IN
5
6
7
-VEE
8
BIPOLAR RIN
IDAC OUT
10V SPAN
20V SPAN
PWR GND
9
10
11
12
BIT 12 IN
(LSB)
2
HS-565ARH
Definitions of Specifications
Burn-In Bias Circuit
Digital Inputs
1
2
24
23
22
21
20
19
18
17
16
15
14
13
NC
BIT 1
BIT 2
BIT 3
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
The HS-565ARH accepts digital input codes in binary format
and may be user connected for any one of three binary
codes. Straight binary, Two’s Complement (see note below),
or Offset Binary, (See Operating Instructions).
NC
+15V
3
VCC
C1
D1
4
REF OUT BIT 4
REF GND BIT 5
5
DIGITAL
INPUT
ANALOG OUTPUT
6
REF IN
-VEE
BIT 6
BIT 7
BIT 8
BIT 9
-15V
D2
(NOTE)
TWO’S
7
STRAIGHT
BINARY
OFFSET
C2
C3
8
BIP OFF
OUT
MSB...LSB
000 ... 000
100 ... 000
111 ... 111
011 ... 111
BINARY
-FS (Full Scale)
Zero
COMPLEMENT
9
Zero
Zero
+10V
D3
10
11
12
10V SPAN BIT 10
20V SPAN BIT 11
PWR GND BIT 12
0.50 FS
-FS
+FS - 1LSB
+FS - 1LSB
Zero - 1LSB
+FS - 1LSB
F11
0.50 FS - 1LSB Zero - 1LSB
NOTE: Invert MSB with external inverter to obtain Two’s
Complement Coding
NOTES:
D1 = D2 = D3 = IN4002 or Equivalent
Accuracy
F0 to F11:
VIH = 5.0V ±0.5V
VIL = 0.0V ±0.5V
Nonlinearity - Nonlinearity of a D/A converter is an
important measure of its accuracy. It describes the deviation
from an ideal straight line transfer curve drawn between zero
(all bits OFF) and full scale (all bits ON).
F0 = 100kHz ±10% (50% Duty Cycle)
F1 = F0/2
F2 = F0/4
F3 = F0/8
F4 = F0/16
F5 = F0/32
F6 = F0/64
F7 = F0/128
F8 = F0/256
F9 = F0/512
F10 = F0/1024
F11 = F0/2048
Differential Nonlinearity - For a D/A converter, it is the
difference between the actual output voltage change and the
ideal (1 LSB) voltage change for a one bit change in code. A
Differential Nonlinearity of ±1 LSB or less guarantees
monotonicity; i.e., the output always increases and never
decreases for an increasing input.
Radiation Bias Circuit
1
24
23
22
21
20
19
18
17
16
15
14
13
NC
BIT 1
BIT 2
BIT 3
2
NC
Settling Time
+15V
3
VCC
Settling time is the time required for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition,
settling to within 0.50 LSB of final value.
4
5
REF OUT
REF GND
REF IN
-VEE
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
+5V
6
-15V
7
Drift
8
BIP OFF
OUT
Gain Drift - The change in full scale analog output over the
9
specified temperature range expressed in parts per million of
+10V
o
o
full scale range per C (ppm of FSR/ C). Gain error is
10
11
12
10V SPAN BIT 10
20V SPAN BIT 11
PWR GND BIT 12
o
measured with respect to 25 C at high (TH) and low (TL)
temperatures. Gain drift is calculated for both high (TH -
o
o
25 C) and low ranges (25 C - TL) by dividing the gain error by
the respective change in temperature. The specification is the
larger of the two representing worst case drift.
NOTE: Power Supply Levels are 0.5V
Offset Drift - The change in analog output with all bits OFF
over the specified temperature range expressed in parts per
o
o
million of full scale range per C (ppm of FSR/ C). Offset
o
error is measured with respect to 25 C at high (TH) and low
(TL) temperatures. Offset drift is calculated for both high (TH
o
o
- 25 C) and low (25 C - TL) ranges by dividing the offset
error by the respective change in temperature. The
3
HS-565ARH
specification given is the larger of the two, representing
worst case drift.
+15V
100kΩ
100Ω
R1
50kΩ
Power Supply Sensitivity
R2
100Ω
-15V
Power Supply Sensitivity is a measure of the change in gain
and offset of the D/A converter resulting from a change in -
15V or +15V supplies. It is specified under DC conditions
and expressed as parts per million of full scale range per
percent of change in power supply (ppm of FSR/%).
VCC
REF OUT
BIP.
4
3
8
OFF.
11
20V SPAN
HS-565ARH
+
-
5K
5K
10V
10
VO
10V SPAN
IREF
9.95K
Compliance
DAC
19.95
DAC
OUT
0.5mA
K
6
5
C
-
Compliance Voltage is the maximum output voltage range
that can be tolerated and still maintain its specified accuracy.
Compliance Limit implies functional operation only and
makes no claims to accuracy.
IO
REF
IN
+
-
9
3.5K
3K
(4 x IREF
x CODE)
+
2.5K
REF
GND
R (SEE
TABLE 7)
CODE
INPUT
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half scale or the major
carry code transition from 011 . . . 1 to 100 . . . 0 or vice
versa. For example, if turn ON is greater than turn OFF for
011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0
exists, such that, the output momentarily glitches toward
zero output. Matched switching times and fast switching will
reduce glitches considerably.
7
. . . . .
13
24
MSB
-VEE
LSB
PWR
GND
FIGURE 1. UNIPOLAR VOLTAGE OUTPUT
No Trim Operation
The HS-565ARH will perform as specified without calibration
adjustments. To operate without calibration, substitute 50Ω
resistors for the 100Ω trimming potentiometers: In Figure 1
replace R2 with 50Ω; also remove the network on pin 8 and
connect 50Ω to ground. For bipolar operation in Figure 2,
replace R3 and R4 with 50Ω resistors.
Applying the HS-565ARH
OP AMP Selection
With these changes, performance is guaranteed as shown
under Specifications, “External Adjustments”. Typical
unipolar zero will be ±0.50 LSB plus the op amp offset.
The HS-565ARH’s current output may be converted to
voltage using the standard connections shown in Figures 1
and 2. The choice of operational amplifier should be
reviewed for each application, since a significant trade-off
may be made between speed and accuracy. Remember
settling time for the DAC-amplifier combination is
The feedback capacitor C must be selected to minimize
settling time.
R4
100Ω
2 2
) + (t )
R3
100Ω
(t
VCC
REF OUT
D
A
BIP.
OFF.
4
3
8
11
10
where t , t are settling times for the DAC and amplifier.
D
A
20V SPAN
10V SPAN
HS-565ARH
+
-
5K
5K
10V
VO
IREF
9.95K
DAC
DAC
OUT
0.5mA
19.95K
6
5
C
-
IO
REF
IN
+
-
9
3.5K
3K
(4 x IREF
x CODE)
+
2.5K
REF
GND
R (SEE
TABLE 7)
CODE
INPUT
7
. . . . .
13
24
MSB
-VEE
LSB
PWR
GND
FIGURE 2. BIPOLAR VOLTAGE OUTPUT
4
HS-565ARH
The usual specification is based on a 10V step, produced by
Calibration
simultaneously switching all bits from off-to-on (tON) or on-
to-off (tOFF). The slower of the two cases is specified, as
measured from 50% of the digital input transition to the final
entry within a window of 0.50 LSB about the settled value.
Four measurements characterize a given type of DAC:
Calibration provides the maximum accuracy from a
converter by adjusting its gain and offset errors to zero, For
the HS-565ARH, these adjustments are similar whether the
current output is used, or whether an external op amp is
added to convert this current to a voltage. Refer to Table 7
for the voltage output case, along with Figure 1 or 2.
(a) tON, to final value +0.50 LSB
(b) tON, to final value -0.50 LSB
(c) tOFF, to final value +0.50 LSB
(d) OFF, to final value -0.50 LSB
Calibration is a two step process for each of the five output
ranges shown in Table 7. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which
translates the output characteristic, i.e. affects each code by
the same amount.
(Cases (b) and (c) may be eliminated unless the overshoot
exceeds 0.50 LSB). For example, refer to Figures 3A and 3B
for the measurement of case (d).
Next adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about the negative FS value.
For the bipolar ranges, this approach leaves an error at the
zero code, whose maximum values is the same as for
integral nonlinearity error. In general, only two values of
output may be calibrated exactly; all others must tolerate
some error. Choosing the extreme end points (plus and
minus full scale) minimizes this distributed error for all other
codes.
Procedure
As shown in Figure 3B, settling time equals tX plus the
comparator delay (tD = 15ns). To measure tX,
• Adjust the delay on generator number 2 for a tX of
several microseconds. This assures that the DAC
output has settled to its final wave.
• Switch on the LSB (+5V)
Settling Time
• Adjust the VLSB supply for 50% triggering at
COMPARATOR OUT. This is indicated by traces of
equal brightness on the oscilloscope display as shown
in Figure 3B. Note DVM reading.
This is a challenging measurement, in which the result
depends on the method chosen, the precision and quality of
test equipment and the operating configuration of the DAC
(test conditions). As a result, the different techniques in use
by converter manufacturers can lead to consistently different
results. An engineer should understand the advantage and
limitations of a given test methods before using the specified
settling time as a basis for design.
• Switch to LSB to Pulse (P)
• Readjust the VLSB supply for 50% triggering as before,
and note DVM reading. One LSB equals one tenth the
difference in the DVM readings noted above.
• Adjust the VLSB supply to reduce the DVM reading by
5 LSBs (DVM reads 10X, so this sets the comparator to
sense the final settled value minus 0.50 LSB).
Comparator output disappears.
The approach used for several years at Intersil calls for a
strobed comparator to sense final perturbations of the DAC
output waveform. This gives the LSB a reasonable
magnitude (814mV for the HS-565ARH, which provides the
comparator with enough overdrive to establish an accurate
±0.50 LSB window about the final settled value. Also, the
required test conditions simulate the DACs environment for a
common application - use in a successive approximation
A/D converter. Considerable experience has shown this to
be a reliable and repeatable way to measure settling time.
• Reduce generator number 2 delay until comparator
output reappears, and adjust for “equal brightness”.
• Measure tX from scope as shown in Figure 3B. Settling
time equals tX + tD, i.e. tX + 15ns.
TABLE 1. OPERATING MODES AND CALIBRATION
CIRCUIT CONNECTIONS
CALIBRATION
OUTPUT
RANGE
PIN 10
TO
PIN 11
TO
RESISTOR
(R)
APPLY
INPUT CODE
MODE
ADJUST
TO SET VO
Unipolar (See Figure 1)
0 to +10V
VO
Pin 10
1.43K
All 0’s
All 1’s
R1
R2
0V
+9.99756V
0 to +5V
VO
Pin 9
1.1K
All 0’s
All 1’s
R1
R2
0V
+4.99878V
5
HS-565ARH
TABLE 1. OPERATING MODES AND CALIBRATION
CIRCUIT CONNECTIONS
CALIBRATION
ADJUST
OUTPUT
RANGE
PIN 10
TO
PIN 11
TO
RESISTOR
(R)
APPLY
INPUT CODE
MODE
TO SET VO
Bipolar (See Figure 2)
±10V
NC
VO
VO
VO
1.69K
1.43K
1.1K
All 0’s
All 1’s
R3
R4
-10V
+9.99512V
±5V
Pin 10
Pin 9
All 0’s
All 1’s
R3
R4
-5V
+4.99756V
±2.5V
All 0’s
All 1’s
R3
R4
-2.5V
+2.49878V
SYNC
IN
PULSE
GENERATOR
NO. 1
PULSE
GENERATOR
NO. 2
OUT
OUT
TRIG
OUT
C
20V ± 20%
BIAS
A
HS-565ARH
TURN ON
8
24
TURN OFF
11
23
.
.
.
5K
5K
+3V
.
9.95K
10
9
.
50%
A
NC
.
DIGITAL
INPUT
0V
.
.
-0.50LSB
STROBE IN
D
.
.
B
+
DAC
OUTPUT
0V
.
~100
kHz
COMPARATOR
OUT
.
B
.
-
14
-400mV
(TURN OFF)
2.5K
SETTLING TIME
tD = COMPARATOR DELAY
P
5
13
2mA
5V
tX
COMP.
STROBE
2V
C
12
LSB
90
10
200K
50%
0.8V
“EQUAL BRIGHTNESS”
VLSB
SUPPLY
DVM
0.1µF
COMP.
OUT
4V
D
0V
FIGURE 3A. .
FIGURE 3B.
Other Considerations
from the internal ground node, regardless of input code. Part of the
DC current is supplied by the zener voltage reference, and the
remainder is sourced from the positive supply via a current mirror
which is laser trimmed for zero current through the external terminal
(pin 5).
Grounds
The HS-565ARH has two ground terminals, pin 5 (REF GND)
and pin 12 (PWR GND). These should not be tied together
near the package unless that point is also the system signal
ground to which all returns are connected. (If such a point
exists, then separate paths are required to pins 5 and 12).
Layout
Connections to pin 9 (IOUT) on the HS-565ARH are most
critical for high speed performance. Output capacitance of the
DAC is only 20pF, so a small change of additional capacitance
may alter the op amp’s stability and affect settling time.
Connections to pin 9 should be short and few. Component
leads should be short on the side connecting to pin 9 (as for
feedback capacitor C). See the Settling Time section.
The current through pin 5 is near zero DC (Note); but pin 12
carries up to 1.75mA of code - dependent current from bits
1, 2, and 3. The general rule is to connect pin 5 directly to
the system “quiet” point, usually called signal or analog
ground. Connect pin 12 to the local digital or power ground.
Then, of course, a single path must connect the
analog/signal and digital/power grounds.
Bypass Capacitors
NOTE: Current cancellation is a two step process within the HS-
565ARH in which code dependent variations are eliminated, the
resulting DC current is supplied internally. First an auxiliary 9-bit R-
2R ladder is driven by the complement of the DACs input code.
Together, the main and auxiliary ladders draw a continuous 2.25mA
Power supply bypass capacitors on the op amp will serve the
HS-565ARH also. If no op amp is used, a 0.01µF ceramic
capacitor from each supply terminal to pin 12 is sufficient,
since supply current variations are small.
6
HS-565ARH
Die Characteristics
DIE DIMENSIONS:
Backside Finish:
179 mils x 107 mils x 19 mils
Silicon
INTERFACE MATERIALS:
ASSEMBLY RELATED INFORMATION
Substrate Potential:
Glassivation:
Type: AlCu
Tie Substrate to VREF GND
Thickness: 8kÅ ±1kÅ
Top Metallization:
Type: Al/Copper
Thickness: 16kÅ ±2kÅ
Substrate:
ADDITIONAL INFORMATION:
Worst Case Current Density:
5
2
2.0 x 10 A/cm
Transistor Count:
200
Bipolar DI,
Metallization Mask Layout
HS-565ARH
(MSB)
BIT 1
VCC NC NC
A
BIT 2
3
3
1
VREF OUT
BIT 3
VREF
GND
BIT 4
BIT 5
VREF IN
-VS
BIT 6
BIPOLAR
12
BIT 7
BIT 8
IDAC
OUT
BIT 9
10V
SPAN
BIT 10
20V
SPAN
POWER
GND
BIT 12
(LSB)
BIT 11
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
7
相关型号：
5962R9675501VJC
PARALLEL, WORD INPUT LOADING, 0.35us SETTLING TIME, 12-BIT DAC, CDIP24, SIDE BRAZED, DIP-24
RENESAS
5962R9675701V9X
Magnitude Comparator, 4000/14000/40000 Series, 4-Bit, True Output, CMOS, DIE-16
WEDC
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