7540_技术文档

7540 Group

REJ03B0011-0400

Rev.4.00

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Jun 21, 2004

DESCRIPTION

The 7540 Group is the 8-bit microcomputer based on the 740 fam-

APPLICATION

Office automation equipment, factory automation equipment,

ily core technology.

The 7540 Group has a serial I/O, 8-bit timers, a 16-bit timer, and

an A/D converter, and is useful for control of home electric appli-

ances and office automation equipment.

home electric appliances, consumer electronics, car, etc.

Notes 1: Serial I/O2 can be used in the following cases;

(1) Serial I/O1 is not used,

(2) Serial I/O1 is used as UART and BRG output divided by 16 is

selected as the synchronized clock.

2: In this version, the operating temperature range and total time

are limited as follows;

55 °C to 85 °C: within total 6000 hours,

85 °C to 125 °C: within total 1000 hours.

FEATURES

• Basic machine-language instructions ...................................... 71

• The minimum instruction execution time ......................... 0.34µs

(at 6 MHz oscillation frequency, double-speed mode for the

shortest instruction)

• Memory size ROM............................................ 8 K to 32 K bytes

RAM ............................................. 384 to 768 bytes

• Programmable I/O ports ....................... 29 (25 in 32-pin version)

• Interrupts ................................................. 15 sources, 15 vectors

................................. (14 sources, 14 vectors for 32-pin version)

• Timers ............................................................................. 8-b✕it 4

...................................................................................... 16-b✕it 1

• Serial I/O1 ................... 8-bit✕ 1 (UART or Clock-synchronized)

• Serial I/O2 (Note 1) ..................... 8-bit ✕ 1 (Clock-synchronized)

• A/D converter ............................................... 10-bit✕ 8 channels

.................................................... (6 channels for 32-pin version)

• Clock generating circuit............................................. Built-in type

(low-power dissipation by an on-chip oscillator enabled)

(connect to external ceramic resonator or quartz-crystal oscilla-

tor permitting RC oscillation)

• Watchdog timer ............................................................ 16-bi✕t 1

• Power source voltage

X

IN oscillation frequency at ceramic oscillation, in double-speed mode

At 6 MHz .................................................................... 4.5 to 5.5 V

XIN oscillation frequency at ceramic oscillation, in high-speed mode

At 8 MHz .................................................................... 4.0 to 5.5 V

At 4 MHz .................................................................... 2.4 to 5.5 V

At 2 MHz .................................................................... 2.2 to 5.5 V

XIN oscillation frequency at RC oscillation in high-speed mode or

middle-speed mode

At 4 MHz .................................................................... 4.0 to 5.5 V

At 2 MHz .................................................................... 2.4 to 5.5 V

At 1 MHz .................................................................... 2.2 to 5.5 V

• Power dissipation

Mask ROM version ....................................... 22.5 mW (standard)

One Time PROM version ................................ 30 mW (standard)

• Operating temperature range................................... –20 to 85 °C

(–40 to 85 °C for extended operating temperature version)

(–40 to 125 °C for extended operating temperature 125 °C ver-

sion (Note 2))

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REJ03B0011-0400Z

7540 Group

PIN CONFIGURATION (TOP VIEW)

P0

7

1

16

15

14

13

12

11

10

9

25

26

27

28

29

30

31

32

P3

4

3

2

1

0

(LED

4

3

2

1

0

)

M37540Mx-XXXGP

M37540MxT-XXXGP

M37540MxV-XXXGP

M37540ExGP

M37540E8T-XXXGP

M37540E8V-XXXGP

P1

0

/R

X

D

1

/TX

P1

2

/SCLK1/SCLK2

/SRDY1/SDATA2

P1

3

P1

4

/CNTR

P2 AN

0

V

X

SS

0

/

0

OUT

IN

1

Package type: 32P6U-A

Fig. 1 Pin configuration (32P6U-A type)

1

2

3

4

P1

2

/SCLK1/SCLK2

36

P1

1

/T

X

D

1

P1

3

/SRDY1/SDATA2

35

34

P10

/R

X

1

P1

4

/CNTR

0

P0

7

6

5

4

P2

0

1

2

3

/AN

0

1

2

3

33

32

5

6

31

30

29

28

7

P0

3

/TXOUT

8

P0

2

/TZOUT

P2

4

5

6

/AN

4

5

6

9

P0

1

/TYOUT

10

11

12

27

26

P00

/CNTR

1

7

P3

7

6

5

4

3

/INT

0

25

24

23

VREF

(LED

6

5

4

3

)/INT

1

13

14

15

16

17

18

)

RESET

CNVSS

22

21

20

Vcc

X

IN

OUT

SS

2

1

0

2

1

0

X

19

V

Package type: 36P2R-A

Fig. 2 Pin configuration (36P2R-A type)

Rev.4.00 Jun 21, 2004 page 2 of 82

REJ03B0011-0400Z

7540 Group

P1

2

/SCLK1/SCLK2

32

P11

/TXD

1

P13

/SRDY1/SDATA2

31

30

P1

0

/R

XD1

2

3

4

P14/CNTR0

P0

7

29

28

P2

0

1

2

/AN

0

1

2

6

5

P2

5

4

6

7

8

27

26

25

P0

3

/TXOUT

3

4

3

4

2

/TZOUT

24

23

9

1/TYOUT

P2

5

/AN5

VREF

10

P00

/CNTR

1

P3

7

/INT

0

11

12

22

21

RESET

CNVSS

P3

4

(LED

4

)

13

20

19

V

X

CC

IN

OUT

P3

3

2

(LED

3

2

)

14

15

P3

1

0

(LED

1

0

)

X

18

17

16

P3

V

SS

Package type: 32P4B

Fig. 3 Pin configuration (32P4B-A type)

P14/CNTR0

NC

1

42

41

40

39

38

37

P13/SRDY1/SDATA2

P12/SCLK1/SCLK2

P11/TXD1

P1⁰/RXD1

P07

2

3

NC

P20/AN0

P2¹/AN1

NC

4

5

6

P06

36

35

7

P05

P2²/AN2

P23/AN3

8

P04

34

33

32

31

9

P03/TXOUT

P02/TZOUT

P01/TYOUT

P00/CNTR1

NC

P24/AN4

P25/AN5

P26/AN6

10

11

12

13

14

15

16

17

18

19

20

21

P27/AN7

NC

30

29

P37/INT0

NC

V^REF

28

27

26

25

24

23

P3⁶(LED6)/INT1

P35(LED5)

P3⁴(LED4)

P3³(LED3)

P3²(LED2)

P31(LED1)

P30(LED0)

RESET

CNVSS

Vcc

XIN

XOUT

22

VSS

Outline 42S1M

Fig. 4 Pin configuration (42S1M type)

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7540 Group

FUNCTIONAL BLOCK

K e y - o n w a k e u p

Fig. 5 Functional block diagram (32P6U package)

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7540 Group

K e y - o n w a k e u p

Fig. 6 Functional block diagram (36P2R package)

Rev.4.00 Jun 21, 2004 page 5 of 82

REJ03B0011-0400Z

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K e y - o n w a k e u p

Fig. 7 Functional block diagram (32P4B package)

Rev.4.00 Jun 21, 2004 page 6 of 82

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7540 Group

PIN DESCRIPTION

Table 1 Pin description

Name

Function

Function expect a port function

Vcc, Vss

Power source

(Note 1)

•Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss.

VREF

Analog reference •Reference voltage input pin for A/D converter

voltage

CNVss

RESET

XIN

CNVss

•Chip operating mode control pin, which is always connected to Vss.

Reset input

Clock input

•Reset input pin for active “L”

•Input and output pins for main clock generating circuit

•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.

•For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor.

•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

• When the on-chip oscillator is selected as the main clock, connect XIN pin to VSS and leave XOUT open.

XOUT

Clock output

I/O port P0

•8-bit I/O port.

• Key-input (key-on wake up

interrupt input) pins

P00/CNTR1

P01/TYOUT

P02/TZOUT

P03/TXOUT

P04–P07

•I/O direction register allows each pin to be individually pro-

grammed as either input or output.

• Timer Y, timer Z, timer X and

timer A function pin

•CMOS compatible input level

•CMOS 3-state output structure

•Whether a built-in pull-up resistor is to be used or not can be de-

termined by program.

P10/RxD1

P11/TxD1

• Serial I/O1 function pin

•5-bit I/O port

I/O port P1

•I/O direction register allows each pin to be individually pro-

grammed as either input or output.

P12/SCLK1/SCLK2

• Serial I/O1 function pin

• Serial I/O2 function pin

P1

3/SRDY1/SDATA2

•CMOS compatible input level

P14/CNTR0

• Timer X function pin

•CMOS 3-state output structure

•CMOS/TTL level can be switched for P10, P12 and P13

•8-bit I/O port having almost the same function as P0

•CMOS compatible input level

P20/AN0–P27/AN7

I/O port P2

(Note 2)

• Input pins for A/D converter

•CMOS 3-state output structure

P30–P35

I/O port P3

(Note 3)

•8-bit I/O port

•I/O direction register allows each pin to be individually programmed as either input or output.

•CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37).

•CMOS 3-state output structure

•P30 to P36 can output a large current for driving LED.

• Interrupt input pins

P36/INT1

P37/INT0

•Whether a built-in pull-up resistor is to be used or not can be de-

termined by program.

Notes 1: VCC = 2.4 to 5.5 V for the extended operating temperature version and the extended operating temperature 125 °C version.

2: P26/AN6 and P27/AN7 do not exist for the 32-pin version, so that Port P2 is a 6-bit I/O port.

3: P35 and P36/INT1 do not exist for the 32-pin version, so that Port P3 is a 6-bit I/O port.

Rev.4.00 Jun 21, 2004 page 7 of 82

REJ03B0011-0400Z

7540 Group

GROUP EXPANSION

Renesas plans to expand the 7540 group as follow:

Memory size

ROM/PROM size ................................................. 8 K to 32 K bytes

RAM size .............................................................. 384 to 768 bytes

Memory type

Support for Mask ROM version, One Time PROM version, and

Emulator MCU .

Package

32P4B .................................................. 32-pin plastic molded SDIP

32P6U-A ...................... 0.8 mm-pitch 32-pin plastic molded LQFP

36P2R-A ...................... 0.8 mm-pitch 36-pin plastic molded SSOP

42S1M.................................... 42-pin shrink ceramic PIGGY BACK

ROM size

(bytes)

M37540E8V

M37540E8T

32K

M37540E8

M37540M4V

M37540M4T

M37540M4

16K

M37540E2

M37540M2V

8K

M37540M2T

M37540M2

RAM size

(bytes)

384

512

768

0

Fig. 8 Memory expansion plan

Rev.4.00 Jun 21, 2004 page 8 of 82

REJ03B0011-0400Z

7540 Group

Currently supported products are listed below.

Table 2 List of supported products

(P) ROM size (bytes) RAM size

Part Number

Package

Remarks

ROM size for User ()

(bytes)

384

32P4B

Mask ROM version

M37540M2-XXXSP

M37540M2-XXXFP

M37540M2T-XXXFP

M37540M2V-XXXFP

M37540M2-XXXGP

M37540M2T-XXXGP

M37540M2V-XXXGP

M37540M4-XXXSP

M37540M4-XXXFP

M37540M4T-XXXFP

M37540M4V-XXXFP

M37540M4-XXXGP

M37540M4T-XXXGP

M37540M4V-XXXGP

M37540E2SP

8192

36P2R-A

(8062)

Mask ROM version (extended operating temperature version)

Mask ROM version (extended operating temperature 125 °C version)

Mask ROM version

32P6U-A

Mask ROM version (extended operating temperature version)

Mask ROM version (extended operating temperature 125 °C version)

Mask ROM version

32P4B

16384

512

36P2R-A

Mask ROM version

(16254)

Mask ROM version (extended operating temperature version)

Mask ROM version (extended operating temperature 125 °C version)

Mask ROM version

32P6U-A

Mask ROM version (extended operating temperature version)

Mask ROM version (extended operating temperature 125 °C version)

One Time PROM version (blank)

32P4B

36P2R-A

32P6U-A

32P4B

8192

384

768

One Time PROM version (blank)

M37540E2FP

(8062)

One Time PROM version (blank)

M37540E2GP

One Time PROM version (blank)

M37540E8SP

32768

36P2R-A

One Time PROM version (blank)

M37540E8FP

(32638)

One Time PROM version

M37540E8T-XXXFP

(shipped after programming, extended operating temperature version)

One Time PROM version (shipped after programming, extended

operating temperature 125 °C version)

M37540E8V-XXXFP

32P6U-A

42S1M

One Time PROM version (blank)

M37540E8GP

One Time PROM version

M37540E8T-XXXGP

(shipped after programming, extended operating temperature version)

One Time PROM version (shipped after programming, extended

operating temperature 125 °C version)

M37540E8V-XXXGP

M37540RSS

Emulator MCU

768

Rev.4.00 Jun 21, 2004 page 9 of 82

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7540 Group

FUNCTIONAL DESCRIPTION

Stack pointer (S)

The stack pointer is an 8-bit register used during subroutine calls

and interrupts. The stack is used to store the current address data

and processor status when branching to subroutines or interrupt

routines.

Central Processing Unit (CPU)

The MCU uses the standard 740 family instruction set. Refer to

the table of 740 family addressing modes and machine-language

instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL

for details on each instruction set.

The lower eight bits of the stack address are determined by the

contents of the stack pointer. The upper eight bits of the stack ad-

dress are determined by the Stack Page Selection Bit. If the Stack

Page Selection Bit is “0”, then the RAM in the zero page is used

as the stack area. If the Stack Page Selection Bit is “1”, then RAM

in page 1 is used as the stack area.

Machine-resident 740 family instructions are as follows:

1. The FST and SLW instructions cannot be used.

2. The MUL and DIV instructions can be used.

3. The WIT instruction can be used.

4. The STP instruction can be used. (This instruction cannot be

used while an on-chip oscillator is operating.)

The Stack Page Selection Bit is located in the SFR area in the

zero page. Note that the initial value of the Stack Page Selection

Bit varies with each microcomputer type. Also some microcom-

puter types have no Stack Page Selection Bit and the upper eight

bits of the stack address are fixed. The operations of pushing reg-

ister contents onto the stack and popping them from the stack are

shown in Fig. 10.

Accumulator (A)

The accumulator is an 8-bit register. Data operations such as data

transfer, etc., are executed mainly through the accumulator.

Index register X (X), Index register Y (Y)

Both index register X and index register Y are 8-bit registers. In

the index addressing modes, the value of the OPERAND is added

to the contents of register X or register Y and specifies the real

address.

Program counter (PC)

The program counter is a 16-bit counter consisting of two 8-bit

registers PCH and PCL. It is used to indicate the address of the

next instruction to be executed.

When the T flag in the processor status register is set to “1”, the

value contained in index register X becomes the address for the

second OPERAND.

b7

b0

A

X

Accumulator

Index Register X

Y

Index Register Y

S

Stack Pointer

b15

PC

H

PC

L

Program Counter

Processor Status Register (PS)

N V T B D I Z C

Carry Flag

Zero Flag

Interrupt Disable Flag

Decimal Mode Flag

Break Flag

Index X Mode Flag

Overflow Flag

Negative Flag

Fig. 9 740 Family CPU register structure

Rev.4.00 Jun 21, 2004 page 10 of 82

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On-going Routine

Execute JSR

Interrupt request

(Note)

M (S) (PCH)

(S) (S – 1)

M (S) (PCL)

(S) (S – 1)

M (S) (PS)

(S) (S – 1)

Store Return Address

on Stack

M (S) (PCH)

(S) (S – 1)

M (S) (PCL)

(S) (S – 1)

Subroutine

Store Return Address

on Stack

Store Contents of Processor

Status Register on Stack

Interrupt

Service Routine

I Flag “0” to “1”

Execute RTS

(S) (S + 1)

Fetch the Jump Vector

Execute RTI

(S) (S + 1)

Restore Return

Address

Restore Contents of

Processor Status Register

(PCL) M (S)

(S) (S + 1)

(PCH) M (S)

(PS)

M (S)

(S) (S + 1)

(PCL) M (S)

(S) (S + 1)

Restore Return

Address

(PCH) M (S)

Note : The condition to enable the interrupt

Interrupt enable bit is “1”

Interrupt disable flag is “0”

Fig. 10 Register push and pop at interrupt generation and subroutine call

Table 3 Push and pop instructions of accumulator or processor status register

Push instruction to stack

Pop instruction from stack

Accumulator

PHA

PHP

PLA

PLP

Processor status register

Rev.4.00 Jun 21, 2004 page 11 of 82

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7540 Group

Processor status register (PS)

(5) Break flag (B)

The processor status register is an 8-bit register consisting of

flags which indicate the status of the processor after an arithmetic

operation. Branch operations can be performed by testing the

Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)

flag. In decimal mode, the Z, V, N flags are not valid.

The B flag is used to indicate that the current interrupt was gener-

ated by the BRK instruction. The BRK flag in the processor status

register is always “0”. When the BRK instruction is used to gener-

ate an interrupt, the processor status register is pushed onto the

stack with the break flag set to “1”. The saved processor status is

the only place where the break flag is ever set.

After reset, the Interrupt disable (I) flag is set to “1”, but all other

flags are undefined. Since the Index X mode (T) and Decimal

mode (D) flags directly affect arithmetic operations, they should

be initialized in the beginning of a program.

(6) Index X mode flag (T)

When the T flag is “0”, arithmetic operations are performed be-

tween accumulator and memory, e.g. the results of an operation

between two memory locations is stored in the accumulator. When

the T flag is “1”, direct arithmetic operations and direct data trans-

fers are enabled between memory locations, i.e. between memory

and memory, memory and I/O, and I/O and I/O. In this case, the

result of an arithmetic operation performed on data in memory lo-

cation 1 and memory location 2 is stored in memory location 1.

The address of memory location 1 is specified by index register X,

and the address of memory location 2 is specified by normal ad-

dressing modes.

(1) Carry flag (C)

The C flag contains a carry or borrow generated by the arithmetic

logic unit (ALU) immediately after an arithmetic operation. It can

also be changed by a shift or rotate instruction.

(2) Zero flag (Z)

The Z flag is set if the result of an immediate arithmetic operation

or a data transfer is “0”, and cleared if the result is anything other

than “0”.

(7) Overflow flag (V)

(3) Interrupt disable flag (I)

The V flag is used during the addition or subtraction of one byte

of signed data. It is set if the result exceeds +127 to -128. When

the BIT instruction is executed, bit 6 of the memory location oper-

ated on by the BIT instruction is stored in the overflow flag.

The I flag disables all interrupts except for the interrupt generated

by the BRK instruction. Interrupts are disabled when the I flag is

“1”.

When an interrupt occurs, this flag is automatically set to “1” to

prevent other interrupts from interfering until the current interrupt

is serviced.

(8) Negative flag (N)

The N flag is set if the result of an arithmetic operation or data

transfer is negative. When the BIT instruction is executed, bit 7 of

the memory location operated on by the BIT instruction is stored in

the negative flag.

(4) Decimal mode flag (D)

The D flag determines whether additions and subtractions are ex-

ecuted in binary or decimal. Binary arithmetic is executed when

this flag is “0”; decimal arithmetic is executed when it is “1”.

Decimal correction is automatic in decimal mode. Only the ADC

and SBC instructions can be used for decimal arithmetic.

Table 4 Set and clear instructions of each bit of processor status register

C flag

SEC

CLC

Z flag

I flag

SEI

D flag

SED

CLD

B flag

T flag

SET

CLT

V flag

–

N flag

Set instruction

–

Clear instruction

CLI

CLV

Rev.4.00 Jun 21, 2004 page 12 of 82

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7540 Group

[CPU mode register] CPUM

The CPU mode register contains the stack page selection bit.

This register is allocated at address 003B16.

b7

b0

CPU mode register

(CPUM: address 003B16, initial value: 8016

)

Switching method of CPU mode register

Processor mode bits (Note 1)

b1 b0

Switch the CPU mode register (CPUM) at the head of program af-

ter releasing Reset in the following method.

0

1

0

1

0

1

Single-chip mode

Not available

Stack page selection bit

0

1

: 0 page

: 1 page

On-chip oscillator oscillation control bit

0

1

: On-chip oscillator oscillation enabled

: On-chip oscillator oscillation stop

XIN oscillation control bit

0

1

: Ceramic or RC oscillation enabled

: Ceramic or RC oscillation stop

Oscillation mode selection bit (Note 1)

0

1

: Ceramic oscillation

: RC oscillation

Clock division ratio selection bits

b7 b6

0

1

0

1

0

1

:

f(φ) = f(XIN)/2 (High-speed mode)

f(φ) = f(XIN)/8 (Middle-speed mode)

applied from on-cihp oscillator

f(φ) = f(XIN) (Double-speed mode)(Note 2)

Note 1: The bit can be rewritten only once after releasing reset. After rewriting

it is disable to write any data to the bit. However, by reset the bit is

initialized and can be rewritten, again.

(It is not disable to write any data to the bit for emulator MCU

“M37540RSS”.)

2: These bits are used only when a ceramic oscillation is selected.

Do not use these when an RC oscillation is selected.

Fig. 11 Structure of CPU mode register

Start with an on-chip oscillator

After releasing reset

An initial value is set as a ceramic

oscillation mode. When it is switched to an

RC oscillation, its oscillation starts.

Switch the oscillation mode

selection bit (bit 5 of CPUM)

When using a ceramic oscillation, wait until

establlishment of oscillation from oscillation starts.

When using an RC oscillation, wait time is not required

basically (time to execute the instruction to switch from

an on-chip oscillator meets the requirement).

Wait by on-chip oscillator operation

until establishment of oscillator clock

Select 1/1, 1/2, 1/8 or on-chip oscillator.

Switch the clock division ratio

selection bits (bits 6 and 7 of CPUM)

Main routine

Fig. 12 Switching method of CPU mode register

Rev.4.00 Jun 21, 2004 page 13 of 82

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7540 Group

Memory

Zero page

Special function register (SFR) area

The SFR area in the zero page contains control registers such as

I/O ports and timers.

The 256 bytes from addresses 000016 to 00FF16 are called the

zero page area. The internal RAM and the special function regis-

ters (SFR) are allocated to this area.

The zero page addressing mode can be used to specify memory

and register addresses in the zero page area. Access to this area

with only 2 bytes is possible in the zero page addressing mode.

RAM

RAM is used for data storage and for a stack area of subroutine

calls and interrupts.

Special page

ROM

The 256 bytes from addresses FF0016 to FFFF16 are called the

special page area. The special page addressing mode can be

used to specify memory addresses in the special page area. Ac-

cess to this area with only 2 bytes is possible in the special page

addressing mode.

The first 128 bytes and the last 2 bytes of ROM are reserved for

device testing and the rest is a user area for storing programs.

Interrupt vector area

The interrupt vector area contains reset and interrupt vectors.

000016

SFR area

Zero page

004016

010016

RAM

RAM area

address

XXXX16

RAM capacity

(bytes)

XXXX¹⁶

384

512

768

01BF16

023F16

033F16

Reserved area

044016

Not used

YYYY16

Reserved ROM area

(128 bytes)

ZZZZ16

FF0016

ROM

ROM area

ROM capacity

(bytes)

address

YYYY16

address

ZZZZ16

Special page

FFDC16

8192

16384

32768

E00016

C00016

800016

E08016

C08016

808016

Interrupt vector area

FFFE16

Reserved ROM area

FFFF16

Fig. 13 Memory map diagram

Rev.4.00 Jun 21, 2004 page 14 of 82

REJ03B0011-0400Z

7540 Group

Timer Y, Z mode register (TYZM)

Port P0 (P0)

000016

002016

002116

002216

Port P0 direction register (P0D)

Port P1 (P1)

000116

000216

Prescaler Y (PREY)

Timer Y secondary (TYS)

Port P1 direction register (P1D)

Timer Y primary (TYP)

000316

000416

000516

002316

002416

002516

Timer Y, Z waveform output control register (PUM)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Prescaler Z (PREZ)

Timer Z secondary (TZS)

Timer Z primary (TZP)

Prescaler 1 (PRE1)

000616

000716

000816

000916

002616

002716

002816

002916

Port P3 direction register (P3D)

Timer 1 (T1)

One-shot start register (ONS)

Timer X mode register (TXM)

000A16

000B16

000C16

000D16

002A16

002B16

002C16

002D16

Prescaler X (PREX)

Timer X (TX)

Timer count source set register (TCSS)

000E16

000F16

001016

001116

002E16

002F16

003016

003116

Serial I/O2 control register (SIO2CON)

Serial I/O2 register (SIO2)

001216

001316

001416

001516

003216

003316

003416

003516

A/D control register (ADCON)

A/D conversion register (low-order) (ADL)

A/D conversion register (high-order) (ADH)

Pull-up control register (PULL)

001616

001716

001816

001916

003616

003716

003816

003916

Port P1P3 control register (P1P3C)

Transmit/Receive buffer register (TB/RB)

Serial I/O1 status register (SIO1STS)

Serial I/O1 control register (SIO1CON)

MISRG

Watchdog timer control register (WDTCON)

Interrupt edge selection register (INTEDGE)

001A16

001B16

001C16

003A16

003B16

003C16

UART control register (UARTCON)

Baud rate generator (BRG)

CPU mode register (CPUM)

Interrupt request register 1 (IREQ1)

Interrupt request register 2 (IREQ2)

Interrupt control register 1 (ICON1)

Timer A mode register (TAM)

001D16

003D16

003E16

003F16

001E16 Timer A (low-order) (TAL)

001F16

Interrupt control register 2 (ICON2)

Timer A (high-order) (TAH)

Note : Do not access to the SFR area including nothing.

Fig. 14 Memory map of special function register (SFR)

Rev.4.00 Jun 21, 2004 page 15 of 82

REJ03B0011-0400Z

7540 Group

I/O Ports

[Pull-up control register] PULL

[Direction registers] PiD

By setting the pull-up control register (address 001616), ports P0

and P3 can exert pull-up control by program. However, pins set to

output are disconnected from this control and cannot exert pull-up

control.

The I/O ports have direction registers which determine the input/

output direction of each pin. Each bit in a direction register corre-

sponds to one pin, and each pin can be set to be input or output.

When “1” is set to the bit corresponding to a pin, this pin becomes

an output port. When “0” is set to the bit, the pin becomes an in-

put port.

Note: P26/AN6, P27/AN7, P35 and P36 do not exist for the 32-pin

version.

When data is read from a pin set to output, not the value of the pin

itself but the value of port latch is read. Pins set to input are float-

ing, and permit reading pin values.

Accordingly, the following settings are required;

. Set direction registers of ports P26 and P27 to output.

. Set direction registers of ports P35 and P36 to output.

If a pin set to input is written to, only the port latch is written to and

the pin remains floating.

[Port P1P3 control register] P1P3C

By setting the port P1P3 control register (address 001716), a

CMOS input level or a TTL input level can be selected for ports

P10, P12, P13, P36, and P37 by program.

b7

b0

Pull-up control register

(PULL: address 001616, initial value: 0016

)

P0

0

pull-up control bit

P0

P3

1

2

4

0

4

5

7

, P03 pull-up control bit

– P0

7

pull-up control bit

– P3

3

pull-up control bit

, P3 pull-up control bit

pull-up control bit

0 : Pull-up Off

1 : Pull-up On

6

Note : Pins set to output ports are disconnected from pull-up control.

Fig. 15 Structure of pull-up control register

b7

b0

Port P1P3 control register

(P1P3C: address 0017 16, initial value: 0016

)

P3

P1

7

6

0

/INT0 input level selection bit

0 : CMOS level

1 : TTL level

/INT1 input level selection bit

0 : CMOS level

1 : TTL level

,P12,P13 input level selection bit

0 : CMOS level

1 : TTL level

Not used

6/INT1 input level selection bit

Note: Keep setting the P3

to “0” (initial value) for 32-pin version.

Fig. 16 Structure of port P1P3 control register

Rev.4.00 Jun 21, 2004 page 16 of 82

REJ03B0011-0400Z

7540 Group

Table 5 I/O port function table

Name

Input/output

I/O format

Non-port function

Key input interrupt

Timer X function output

Timer Y function output

Timer Z function output

Timer A function input

Related SFRs

Diagram No.

P00/CNTR1

P01/TYOUT

P02/TZOUT

P03/TXOUT

P04–P07

I/O port P0 I/O individual •CMOS compatible

Pull-up control register

Timer Y mode register

Timer Z mode register

Timer X mode register

Timer Y,Z waveform

output control register

Timer A mode register

(1)

(2)

(3)

(4)

bits

input level

•CMOS 3-state output

(Note 1)

P10/RxD1

P11/TxD1

I/O port P1

Serial I/O1 function

input/output

Serial I/O1 control register

(5)

(6)

P12/SCLK1/SCLK2

P13/SRDY1/SDATA2

Serial I/O2 function

input/output

Serial I/O1 control register

Serial I/O2 control register

(7)

(8)

P14/CNTR0

Timer X function input/output Timer X mode register

(9)

P20/AN0–

P27/AN7

I/O port P2

(Note 2)

A/D conversion input

A/D control register

(10)

P30–P35

I/O port P3

(Note 3)

(11)

(12)

P36/INT1

P37/INT0

External interrupt input

Interrupt edge selection

register

Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level.

2: P26/AN6 and P27/AN7 do not exist for the 32-pin version.

3: P35 and P36/INT1 do not exist for the 32-pin version.

Rev.4.00 Jun 21, 2004 page 17 of 82

REJ03B0011-0400Z

7540 Group

(1)Port P00

(2)Ports P01, P02

Pull-up control

Direction

Pull-up control

Direction

register

Port latch

Data bus

Port latch

Data bus

**

Programmable waveform generation mode

Timer output

CNTR1 interrupt input

To key input interrupt

generating circuit

P0

0 key-on wakeup

To key input interrupt

generating circuit

selection bit

(3)Port P03

(4)Ports P04–P07

Pull-up control

Direction

register

Direction

register

Data bus

Port latch

Data bus

Port latch

Timer output

P03/TXOUT

output valid

To key input interrupt

generating circuit

To key input interrupt

generating circuit

(5)Port P10

(6)Port P11

Serial I/O1 enable bit

Receive enable bit

P11/TxD1 P-channel output disable bit

Serial I/O1 enable bit

Transmit enable bit

Direction

register

Direction

register

Data bus

Port latch

P1

0

, P12

, P13

input level

selection bit

Data bus

Port latch

Serial I/O1 input

*

(7)Port P12

Serial I/O1 output

S

CLK2 pin

selection bit

Serial I/O1 synchronous

clock selection bit

Serial I/O1 enable bit

Serial I/O1 mode selection bit

Serial I/O1 enable bit

Direction

register

Data bus

Port latch

P1

0

, P12, P13

input level

selection bit

Serial I/O1, serial I/O2 clock output

Serial I/O1, serial I/O2 clock input

*

P1

0

, P1

2

, P1

3

, P3

6

, and P3

7

input level are switched to the CMOS/TTL level by the port P1P3 control register.

*

When the TTL level is selected, there is no hysteresis characteristics.

P02/TZOUT;

**_{Programmable waveform generation mode}

Programmable one-shot generation mode

Programmable wait one-shot generation mode

Fig. 17 Block diagram of ports (1)

Rev.4.00 Jun 21, 2004 page 18 of 82

REJ03B0011-0400Z

7540 Group

(8) Port P1

3

(9) Port P1

4

SDATA2 output in operation signal

S

DATA2 pin selection bit

Direction

register

Serial I/O mode selection bit

Serial I/O1 enable bit

SRDY1 output enable bit

Direction

register

Port

latch

Data bus

Port latch

Pulse output mode

Timer output

P10, P12, P13

input level

CNTR0 interrupt input

selection bit

Serial I/O1 ready output

Serial I/O2 output

Serial I/O2 input

*

(11) Ports P30–P35

(10) Ports P20–P27

Direction

Pull-up control

register

Direction

register

Data bus

Port latch

Data bus

Port

latch

A/D converter input

Analog input pin

selection bit

(12) Ports P36, P37

Pull-up control

Direction

register

Data bus

Port

latch

P3 input level

selection bit

INT interrupt input

*

P1

0

, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.

*

When the TTL level is selected, there is no hysteresis characteristics.

Fig. 18 Block diagram of ports (2)

Rev.4.00 Jun 21, 2004 page 19 of 82

REJ03B0011-0400Z

7540 Group

Interrupts

✕✕Notes on use

Interrupts occur by 15 different sources : 5 external sources, 9 in-

When setting the followings, the interrupt request bit may be set to

“1”.

ternal sources and 1 software source.

•When setting external interrupt active edge

Related register: Interrupt edge selection register (address

003A16)

Interrupt control

All interrupts except the BRK instruction interrupt have an interrupt

request bit and an interrupt enable bit, and they are controlled by

the interrupt disable flag. When the interrupt enable bit and the in-

terrupt request bit are set to “1” and the interrupt disable flag is set

to “0”, an interrupt is accepted.

Timer X mode register (address 2B16)

Timer A mode register (address 1D16)

When not requiring the interrupt occurrence synchronized with

these setting, take the following sequence.

The interrupt request bit can be cleared by program but not be set.

The interrupt enable bit can be set and cleared by program.

The reset and BRK instruction interrupt can never be disabled with

any flag or bit. All interrupts except these are disabled when the

interrupt disable flag is set.

✕ Set the corresponding interrupt enable bit to “0” (disabled).

✕ Set the interrupt edge select bit (active edge switch bit) to “1”.

✕ Set the corresponding interrupt request bit to “0” after 1 or

more instructions have been executed.

When several interrupts occur at the same time, the interrupts are

received according to priority.

✕ Set the corresponding interrupt enable bit to “1” (enabled).

Interrupt operation

Upon acceptance of an interrupt the following operations are auto-

matically performed:

1. The processing being executed is stopped.

2. The contents of the program counter and processor status reg-

ister are automatically pushed onto the stack.

3. The interrupt disable flag is set and the corresponding interrupt

request bit is cleared.

4. Concurrently with the push operation, the interrupt destination

address is read from the vector table into the program counter.

Table 6 Interrupt vector address and priority

Vector addresses (Note 1)

Interrupt source Priority

Interrupt request generating conditions

At reset input

Remarks

High-order Low-order

Reset (Note 2)

1

2

3

Non-maskable

FFFD16

FFFB16

FFF916

FFFC16

FFFA16

FFF816

Serial I/O1 receive

Serial I/O1 transmit

At completion of serial I/O1 data receive

Valid only when serial I/O1 is selected

At completion of serial I/O1 transmit shift or

when transmit buffer is empty

Valid only when serial I/O1 is

selected

INT0

4

5

6

7

8

At detection of either rising or falling edge of External interrupt

FFF716

FFF516

FFF316

FFF116

FFEF16

FFF616

FFF416

FFF216

FFF016

FFEE16

INT0 input

(active edge selectable)

INT1 (Note 3)

Key-on wake-up

CNTR0

At detection of either rising or falling edge of External interrupt

INT1 input

(active edge selectable)

At falling of conjunction of input logical level External interrupt (valid at falling)

for port P0 (at input)

At detection of either rising or falling edge of External interrupt

CNTR0 input

(active edge selectable)

CNTR1

At detection of either rising or falling edge of External interrupt

CNTR1 input

(active edge selectable)

Timer X

9

At timer X underflow

FFED16

FFEB16

FFE916

FFE716

FFE516

FFE316

FFE116

FFDF16

FFDD16

FFEC16

FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016

FFDE16

FFDC16

Timer Y

10

11

12

13

14

15

16

17

At timer Y underflow

Timer Z

At timer Z underflow

Timer A

At timer A underflow

Serial I/O2

A/D conversion

Timer 1

At completion of transmit/receive shift

At completion of A/D conversion

At timer 1 underflow

STP release timer underflow

Reserved area

BRK instruction

Not available

At BRK instruction execution

Non-maskable software interrupt

Note 1: Vector addressed contain internal jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

3: It is an interrupt which can use only for 36 pin version.

Rev.4.00 Jun 21, 2004 page 20 of 82

REJ03B0011-0400Z

7540 Group

Interrupt request bit

Interrupt enable bit

Interrupt disable flag I

BRK instruction

Reset

Interrupt request

Fig. 19 Interrupt control

b7

b0

Interrupt edge selection register

(INTEDGE : address 003A16, initial value : 0016

)

INT

0 interrupt edge selection bit

0 : Falling edge active

1 : Rising edge active

1

interrupt edge selection bit

0 : Falling edge active

1 : Rising edge active

Not used (returns “0” when read)

P00

key-on wakeup enable bit

0 : Key-on wakeup enabled

1 : Key-on wakeup disabled

b7

b0

Interrupt request register 1

(IREQ1 : address 003C16, initial value : 0016

)

Serial I/O1 receive interrupt request bit

Serial I/O1 transmit interrupt request bit

INT

0

1

interrupt request bit

Key-on wake up interrupt request bit

CNTR

0

1

interrupt request bit

CNTR

0 : No interrupt request issued

1 : Interrupt request issued

Timer X interrupt request bit

b7

b0

Interrupt request register 2

(IREQ2 : address 003D16, initial value : 0016

)

Timer Y interrupt request bit

Timer Z interrupt request bit

Timer A interrupt request bit

Serial I/O2 interrupt request bit

A/D conversion interrupt request bit

Timer 1 interrupt request bit

Not used (returns “0” when read)

0 : No interrupt request issued

1 : Interrupt request issued

b7

b0

Interrupt control register 1

(ICON1 : address 003E16, initial value : 0016

)

Serial I/O1 receive interrupt enable bit

Serial I/O1 transmit interrupt enable bit

INT

0

1

interrupt enable bit

interrupt enable bit (Do not write “1” to this bit for 32-pin version)

Key-on wake up interrupt enable bit

CNTR

0

1

interrupt enable bit

Timer X interrupt enable bit

0 : Interrupts disabled

1 : Interrupts enabled

b7

b0

Interrupt control register 2

(ICON2 : address 003F16, initial value : 0016

)

Timer Y interrupt enable bit

Timer Z interrupt enable bit

Timer A interrupt enable bit

Serial I/O2 interrupt enable bit

A/D conversion interrupt enable bit

Timer 1 interrupt enable bit

Not used (returns “0” when read)

(Do not write “1” to this bit)

0 : Interrupts disabled

1 : Interrupts enabled

Fig. 20 Structure of Interrupt-related registers

Rev.4.00 Jun 21, 2004 page 21 of 82

REJ03B0011-0400Z

7540 Group

Key Input Interrupt (Key-On Wake-Up)

A key-on wake-up interrupt request is generated by applying “L”

level to any pin of port P0 that has been set to input mode.

In other words, it is generated when the AND of input level goes

from “1” to “0”. An example of using a key input interrupt is shown

in Figure 21, where an interrupt request is generated by pressing

one of the keys provided as an active-low key matrix which uses

ports P00 to P03 as input ports.

Port PXx

“L” level output

PULL register

bit 3 = “0”

Port P0

Direction register = “1”

7

Key input interrupt request

*

**

Port P0

latch

7

6

5

4

3

2

1

0

P0

7

6

5

4

output

Falling edge

detection

PULL register

bit 3 = “0”

Port P0

6

Direction register = “1”

**

Port P0

latch

Falling edge

detection

PULL register

bit 3 = “0”

Port P0

5

Direction register = “1”

**

Port P0

latch

Falling edge

detection

PULL register

bit 3 = “0”

Port P0

4

Direction register = “1”

**

Port P0

latch

Falling edge

detection

PULL register

bit 2 = “1”

Port P0

3

Port P0

Input read circuit

Direction register = “0”

**

Port P0

latch

P0

3

2

1

0

input

Falling edge

detection

PULL register

bit 2 = “1”

Port P0

2

Direction register = “0”

**

Port P0

latch

Falling edge

detection

PULL register

bit 1 = “1”

Port P0

1

Direction register = “0”

**

Port P0

latch

Falling edge

detection

PULL register

bit 0 = “1”

Port P0

0

Direction register = “0”

*

**

Port P0

latch

Falling edge

detection

Port P00 key-on wakeup

selection bit

* P-channel transistor for pull-up

** CMOS output buffer

Fig. 21 Connection example when using key input interrupt and port P0 block diagram

Rev.4.00 Jun 21, 2004 page 22 of 82

REJ03B0011-0400Z

7540 Group

✕Timer A

Timers

Timer A is a 16-bit timer and counts the signal which is the oscil-

lation frequency divided by 16. When Timer A underflows, the

timer A interrupt request bit is set to “1”.

The 7540 Group has 5 timers: timer 1, timer A, timer X, timer Y

and timer Z.

The division ratio of every timer and prescaler is 1/(n+1) provided

that the value of the timer latch or prescaler is n.

All the timers are down count timers. When a timer reaches “0”, an

underflow occurs at the next count pulse, and the corresponding

timer latch is reloaded into the timer. When a timer underflows, the

interrupt request bit corresponding to each timer is set to “1”.

Timer A consists of the low-order of Timer A (TAL) and the high-or-

der of Timer A (TAH).

Timer A has the timer A latch to retain the reload value. The value

of timer A latch is set to Timer A at the timing shown below.

• When Timer A undeflows.

• When an active edge is input from CNTR1 pin (valid only when

period measurement mode and pulse width HL continuously mea-

surement mode).

✕Timer 1

Timer 1 is an 8-bit timer and counts the prescaler output.

When Timer 1 underflows, the timer 1 interrupt request bit is set to

“1”.

When writing to both the low-order of Timer A (TAL) and the high-

order of Timer A (TAH) is executed, the value is written to both the

timer A latch and Timer A.

Prescaler 1 is an 8-bit prescaler and counts the signal which is the

oscillation frequency divided by 16.

When reading from the low-order of Timer A (TAL) and the high-or-

der of Timer A (TAH) is executed, the following values are read out

according to the operating mode.

Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1

latch to retain the reload value, respectively. The value of

prescaler 1 latch is set to Prescaler 1 when Prescaler 1

underflows.The value of timer 1 latch is set to Timer 1 when Timer

1 underflows.

• In timer mode, event counter mode:

The count value of Timer A is read out.

• In period measurement mode, pulse width HL continuously mea-

surement mode:

When writing to Prescaler 1 (PRE1) is executed, the value is writ-

ten to both the prescaler 1 latch and Prescaler 1.

The measured value is read out.

When writing to Timer 1 (T1) is executed, the value is written to

both the timer 1 latch and Timer 1.

Be sure to write to/read out the low-order of Timer A (TAL) and the

high-order of Timer A (TAH) in the following order;

Read

When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is ex-

ecuted, each count value is read out.

Read the high-order of Timer A (TAH) first, and the low-order of

Timer A (TAL) next and be sure to read out both TAH and TAL.

Write

Timer 1 always operates in the timer mode.

Prescaler 1 counts the signal which is the oscillation frequency di-

vided by 16. Each time the count clock is input, the contents of

Prescaler 1 is decremented by 1. When the contents of Prescaler

1 reach “0016”, an underflow occurs at the next count clock, and

the prescaler 1 latch is reloaded into Prescaler 1 and count contin-

ues. The division ratio of Prescaler 1 is 1/(n+1) provided that the

value of Prescaler 1 is n.

Write to the low-order of Timer A (TAL) first, and the high-order of

Timer A (TAH) next and be sure to write to both TAL and TAH.

Timer A can be selected in one of 4 operating modes by setting

the timer A mode register.

The contents of Timer 1 is decremented by 1 each time the under-

flow signal of Prescaler 1 is input. When the contents of Timer 1

reach “0016”, an underflow occurs at the next count clock, and the

timer 1 latch is reloaded into Timer 1 and count continues. The di-

vision ratio of Timer 1 is 1/(m+1) provided that the value of Timer

1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is

1/((n+1)✕(m+1)) provided that the value of Prescaler 1 is n and

the value of Timer 1 is m.

(1) Timer mode

Timer A counts the oscillation frequency divided by 16. Each time

the count clock is input, the contents of Timer A is decremented by

1. When the contents of Timer A reach “000016”, an underflow oc-

curs at the next count clock, and the timer A latch is reloaded into

Timer A. The division ratio of Timer A is 1/(n+1) provided that the

value of Timer A is n.

Timer 1 cannot stop counting by software.

(2) Period measurement mode

In the period measurement mode, the pulse period input from the

P00/CNTR1 pin is measured.

CNTR1 interrupt request is generated at rising/falling edge of

CNTR1 pin input singal. Simultaneousuly, the value in the timer A

latch is reloaded inTimer A and count continues. The active edge

of CNTR1 pin input signal can be selected from rising or falling by

the CNTR1 active edge switch bit .The count value when trigger

input from CNTR1 pin is accepted is retained until Timer A is read

once.

Rev.4.00 Jun 21, 2004 page 23 of 82

REJ03B0011-0400Z

7540 Group

(3) Event counter mode

✕Timer X

Timer A counts signals input from the P00/CNTR1 pin.

Except for this, the operation in event counter mode is the same

as in timer mode.

Timer X is an 8-bit timer and counts the prescaler X output.

When Timer X underflows, the timer X interrupt request bit is set

to “1”.

The active edge of CNTR1 pin input signal can be selected from

rising or falling by the CNTR1 active edge switch bit .

Prescaler X is an 8-bit prescaler and counts the signal selected by

the timer X count source selection bit.

Prescaler X and Timer X have the prescaler X latch and the timer

X latch to retain the reload value, respectively. The value of

prescaler X latch is set to Prescaler X when Prescaler X

underflows.The value of timer X latch is set to Timer X when Timer

X underflows.

(4) Pulse width HL continuously measurement mode

In the pulse width HL continuously measurement mode, the pulse

width (“H” and “L” levels) input to the P00/CNTR1 pin is measured.

CNTR1 interrupt request is generated at both rising and falling

edges of CNTR1 pin input signal. Except for this, the operation in

pulse width HL continuously measurement mode is the same as in

period measurement mode.

When writing to Prescaler X (PREX) is executed, the value is writ-

ten to both the prescaler X latch and Prescaler X.

When writing to Timer X (TX) is executed, the value is written to

both the timer X latch and Timer X.

The count value when trigger input from the CNTR1 pin is ac-

cepted is retained until Timer A is read once.

When reading from Prescaler X (PREX) and Timer X (TX) is ex-

ecuted, each count value is read out.

Timer A can stop counting by setting “1” to the timer A count stop

bit in any mode.

Timer X can can be selected in one of 4 operating modes by set-

ting the timer X operating mode bits of the timer X mode register.

Also, when Timer A underflows, the timer A interrupt request bit is

set to “1”.

(1) Timer mode

Note on Timer A is described below;

Prescaler X counts the count source selected by the timer X count

source selection bits. Each time the count clock is input, the con-

tents of Prescaler X is decremented by 1. When the contents of

Prescaler X reach “0016”, an underflow occurs at the next count

clock, and the prescaler X latch is reloaded into Prescaler X and

count continues. The division ratio of Prescaler X is 1/(n+1) pro-

vided that the value of Prescaler X is n.

✕✕Note on Timer A

CNTR1 interrupt active edge selection

CNTR1 interrupt active edge depends on the CNTR1 active edge

switch bit.

When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at

the falling edge of the CNTR1 pin input signal. When this bit is “1”,

the CNTR1 interrupt request bit is set to “1” at the rising edge of

the CNTR1 pin input signal.

The contents of Timer X is decremented by 1 each time the under-

flow signal of Prescaler X is input. When the contents of Timer X

reach “0016”, an underflow occurs at the next count clock, and the

timer X latch is reloaded into Timer X and count continues. The di-

vision ratio of Timer X is 1/(m+1) provided that the value of Timer

X is m. Accordingly, the division ratio of Prescaler X and Timer X is

1/((n+1)✕(m+1)) provided that the value of Prescaler X is n and

the value of Timer X is m.

However, in the pulse width HL continuously measurement mode,

CNTR1 interrupt request is generated at both rising and falling

edges of CNTR1 pin input signal regardless of the setting of

CNTR1 active edge switch bit.

b7

b0

(2) Pulse output mode

Timer A mode register

In the pulse output mode, the waveform whose polarity is inverted

each time timer X underflows is output from the CNTR0 pin.

The output level of CNTR0 pin can be selected by the CNTR0 ac-

tive edge switch bit. When the CNTR0 active edge switch bit is “0”,

the output of CNTR0 pin is started at “H” level. When this bit is “1”,

the output is started at “L” level.

(TAM : address 001D¹⁶, initial value: 0016

)

Not used (return “0” when read)

Timer A operating mode bits

b5 b4

0

1

0 : Timer mode

1 : Period measurement mode

0 : Event counter mode

1 : Pulse width HL continuously

measurement mode

Also, the inverted waveform of pulse output from CNTR0 pin can

be output from TXOUT pin by setting “1” to the P03/TXOUT output

valid bit.

CNTR1 active edge switch bit

0 : Count at rising edge in event counter mode

Measure the falling edge period in period

measurement mode

When using a timer in this mode, set the port P14 and P03 direc-

tion registers to output mode.

Falling edge active for CNTR1 interrupt

1 : Count at falling edge in event counter mode

Measure the rising edge period in period

measurement mode

(3) Event counter mode

Rising edge active for CNTR

Timer A count stop bit

0 : Count start

1 interrupt

The timer A counts signals input from the P14/CNTR0 pin.

Except for this, the operation in event counter mode is the same

as in timer mode.

1 : Count stop

The active edge of CNTR0 pin input signal can be selected from

rising or falling by the CNTR0 active edge switch bit .

Fig. 22 Structure of timer A mode register

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(4) Pulse width measurement mode

b7

b0

In the pulse width measurement mode, the pulse width of the sig-

nal input to P14/CNTR0 pin is measured.

Timer X mode register

(TXM : address 002B16, initial value: 0016

)

Timer X operating mode bits

b1 b0

The operation of Timer X can be controlled by the level of the sig-

nal input from the CNTR0 pin.

0

1

0 : Timer mode

1 : Pulse output mode

0 : Event counter mode

When the CNTR0 active edge switch bit is “0”, the signal selected

by the timer X count source selection bit is counted while the input

signal level of CNTR0 pin is “H”. The count is stopped while the

pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the

signal selected by the timer X count source selection bit is

counted while the input signal level of CNTR0 pin is “L”. The count

is stopped while the pin is “H”.

1 : Pulse width measurement mode

CNTR

0

active edge switch bit

0 : Interrupt at falling edge

Count at rising edge

(in event counter mode)

1 : Interrupt at rising edge

Count at falling edge

(in event counter mode)

Timer X count stop bit

0 : Count start

1 : Count stop

Timer X can stop counting by setting “1” to the timer X count stop

bit in any mode.

P03/TXOUT output valid bit

0 : Output invalid (I/O port)

1 : Output valid (Inverted CNTR0 output)

Also, when Timer X underflows, the timer X interrupt request bit is

set to “1”.

Not used (return “0” when read)

Note on Timer X is described below;

Fig. 23 Structure of timer X mode register

✕✕Note on Timer X

b7

b0

CNTR0 interrupt active edge selection

Timer count source set register

(TCSS : address 002E16, initial value: 0016

)

CNTR0 interrupt active edge depends on the CNTR0 active edge

switch bit.

Timer X count source selection bits

b1 b0

When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at

the falling edge of CNTR0 pin input signal. When this bit is “1”, the

CNTR0 interrupt request bit is set to “1” at the rising edge of

CNTR0 pin input signal.

0

1

0 : f(XIN)/16

1 : f(XIN)/2

0 : f(XIN) (Note 1)

1 : Not available

Timer Y count source selection bits

b3 b2

0

1

0 : f(XIN)/16

1 : f(XIN)/2

0 : On-chip oscillator output (Note 2)

1 : Not available

Timer Z count source selection bits

b5 b4

0

1

0 : f(XIN)/16

1 : f(XIN)/2

0 : Timer Y underflow

1 : Not available

Fix this bit to “0”.

Not used (return “0” when read)

Notes 1: f(XIN) can be used as timer X count source when using

a ceramic resonator or on-chip oscillator.

Do not use it at RC oscillation.

2: System operates using an on-chip oscillator as a count source

by setting the on-cihp oscillator to oscillation enabled by bit 3

of CPUM.

Fig. 24 Timer count source set register

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✕Timer Y

(2) Programmable waveform generation mode

Timer Y is an 8-bit timer and counts the prescaler Y output.

When Timer Y underflows, the timer Y interrupt request bit is set to

“1”.

In the programmable waveform generation mode, timer counts the

setting value of timer Y primary and the setting value of timer Y

secondary alternately, the waveform inverted each time Timer Y

underflows is output from TYOUT pin.

Prescaler Y is an 8-bit prescaler and counts the signal selected by

the timer Y count source selection bit.

When using this mode, be sure to set “1” to the timer Y write con-

trol bit to select “write to latch only”. Also, set the port P01 direction

registers to output mode.

Prescaler Y has the prescaler Y latch to retain the reload value.

Timer Y has the timer Y primary latch and timer Y secondary latch

to retain the reload value.

The active edge of output waveform is set by the timer Y output

level latch (b5) of the timer Y, Z waveform output control register

(PUM). When “0” is set to b5 of PUM, “H” interval by the setting

value of TYP or “L” interval by the setting value of TYS is output

alternately. When “1” is set to b5 of PUM, “L” interval by the setting

value of TYP or “H” interval by the setting value of TYS is output

alternately.

The value of prescaler Y latch is set to Prescaler Y when

Prescaler Y underflows.The value of timer Y primary latch or timer

Y secondary latch are set to Timer Y when Timer Y underflows.

As for the value to transfer to Timer Y, either of timer Y primary or

timer Y secondary is selected depending on the timer Y operating

mode.

Also, in this mode, the primary interval and the secondary interval

of the output waveform can be extended respectively for 0.5 cycle

of timer count source clock by setting the timer Y primary wave-

form extension control bit (b2) and the timer Y secondary

waveform extension control bit (b3) of PUM to “1”. As a result, the

waveforms of more accurate resolution can be output.

When b2 and b3 of PUM are used, the frequency and duty of the

output waveform are as follows;

When writing to Prescaler Y (PREY), timer Y primary (TYP) or

timer Y secondary (TYS) is executed, writing to “latch only” or

“latch and prescaler (timer)” can be selected by the setting value

of the timer Y write control bit. Be sure to set the timer Y write con-

trol bit because there are some notes according to the operating

mode.

When reading from Prescaler Y (PREY) is executed, the count

value of Prescaler Y is read out. When reading from timer Y pri-

mary (TYP) is executed, the count value of Timer Y is read out.

The count value of Timer Y can be read out by reading from the

timer Y primary (TYP) even when the value of timer Y primary

latch or timer Y secondary latch is counted. When reading the

timer Y secondary (TYS) is executed, the undefined value is read

out.

Waveform frequency:

2✕TMYCL

FYOUT=

2✕(TYP+1)+2✕(TYS+1)+(EXPYP+EXPYS)

Duty:

2✕(TYP+1)+EXPYP

Timer Y can be selected in one of 2 operating modes by setting

the timer Y operating mode bits of the timer Y, Z mode register.

DYOUT=

(2✕(TYP+1)+EXPYP)+(2✕(TYS+1)+EXPYS)

(1) Timer mode

TMYCL: Timer Y count source (frequency)

TYP: Timer Y primary (8bit)

Prescaler Y counts the count source selected by the timer Y count

source selection bits. Each time the count clock is input, the con-

tents of Prescaler Y is decremented by 1. When the contents of

Prescaler Y reach “0016”, an underflow occurs at the next count

clock, and the prescaler Y latch is reloaded into Prescaler Y. The

division ratio of Prescaler Y is 1/(n+1) provided that the value of

Prescaler Y is n.

TYS: Timer Y secondary (8bit)

EXPYP: Timer Y primary waveform extension control bit (1bit)

EXPYS: Timer Y secondary waveform extension control bit (1bit)

In the programmable waveform generation mode, when values of

the TYP, TYS, EXPYP and EXPYS are changed, the output wave-

form is changed at the beginning (timer Y primary waveform

interval) of waveform period.

The contents of Timer Y is decremented by 1 each time the under-

flow signal of Prescaler Y is input. When the contents of Timer Y

reach “0016”, an underflow occurs at the next count clock, and the

timer Y primary latch is reloaded into Timer Y and count continues.

(In the timer mode, the contents of timer Y primary latch is

counted. Timer Y secondary latch is not used in this mode.)

The division ratio of Timer Y is 1/(m+1) provided that the value of

Timer Y is m. Accordingly, the division ratio of Prescaler Y and

Timer Y is 1/((n+1)✕(m+1)) provided that the value of Prescaler Y

is n and the value of Timer Y is m.

When the count values are changed, set values to the TYS,

EXPYP and EXPYS first. After then, set the value to TYP. The val-

ues are set all at once at the beginning of the next waveform

period when the value is set to TYP. (When writing at timer stop is

executed, writing to TYP at last is required.)

Notes on programmable waveform generation mode is described

below;

In the timer mode, writing to “latch only” or “latches and Prescaler

Y and timer Y primary” can be selected by the setting value of the

timer Y write control bit.

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✕ Notes on programmable generation waveform mode

• Count set value

In the programmable waveform generation mode, values of TYS,

EXPYP, and EXPYS are valid by writing to TYP because the set-

ting to them is executed all at once by writing to TYP. Even when

changing TYP is not required, write the same value again.

• Write timing to TYP

In the programmable waveform generation mode, when the set-

ting value is changed while the waveform is output, set by

software in order not to execute the writing to TYP and the timing

of timer underflow during the secondary interval simultanesously.

• Usage of waveform extension function

The waveform extension function by the timer Y waveform exten-

sion control bit can be used only when “0016” is set to Prescaler Y.

When the value other than “0016” is set to Prescaler Y, be sure to

set “0” to EXPYP and EXPYS.

• Timer Y write mode

When using this mode, be sure to set “1” to the timer Y write con-

trol bit to select “write to latch only”.

Timer Y can stop counting by setting “1” to the timer Y count stop

bit in any mode.

Also, when Timer Y underflows, the timer Y interrupt request bit is

set to “1”.

Timer Y reloads the value of latch when counting is stopped by the

timer Y count stop bit. (When timer is read out while timer is

stopped, the value of latch is read. The value of timer can be read

out only while timer is operating.)

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(2) Programmable waveform generation mode

✕Timer Z

In the programmable waveform generation mode, timer counts the

setting value of timer Z primary and the setting value of timer Z

secondary alternately, the waveform inverted each time Timer Z

underflows is output from TZOUT pin.

Timer Z is an 8-bit timer and counts the prescaler Z output.

When Timer Z underflows, the timer Z interrupt request bit is set to

“1”.

Prescaler Z is an 8-bit prescaler and counts the signal selected by

the timer Z count source selection bit.

When using this mode, be sure to set “1” to the timer Z write con-

trol bit to select “write to latch only”. Also, set the port P02 direction

registers to output mode.

Prescaler Z has the prescaler Z latch to retain the reload value.

Timer Z has the timer Z primary latch and timer Z secondary latch

to retain the reload value.

The active edge of output waveform is set by the timer Z output

level latch (b4) of the timer Y, Z waveform output control register

(PUM). When “0” is set to b4 of PUM, “H” interval by the setting

value of TZP or “L” interval by the setting value of TZS is output al-

ternately. When “1” is set to b4 of PUM, “L” interval by the setting

value of TZP or “H” interval by the setting value of TZS is output

alternately.

The value of prescaler Z latch is set to Prescaler Z when Prescaler

Z underflows.The value of timer Z primary latch or timer Z second-

ary latch are set to Timer Z when Timer Z underflows.

As for the value to transfer to Timer Z, either of timer Z primary or

timer Z secondary is selected depending on the timer Z operating

mode.

Also, in this mode, the primary interval and the secondary interval

of the output waveform can be extended respectively for 0.5 cycle

of timer count source clock by setting the timer Z primary wave-

form extension control bit (b0) and the timer Z secondary

waveform extension control bit (b1) of PUM to “1”. As a result, the

waveforms of more accurate resolution can be output.

When b0 and b1 of PUM are used, the frequency and duty of the

output waveform are as follows;

When writing to Prescaler Z (PREZ), timer Z primary (TZP) or

timer Z secondary (TZS) is executed, writing to “latch only” or

“latches and Prescaler Z and Timer Z” can be selected by the set-

ting value of the timer Z write control bit. Be sure to set the write

control bit because there are some notes according to the operat-

ing mode.

When reading from Prescaler Z (PREZ) is executed, the count

value of Prescaler Z is read out. When reading from timer Z pri-

mary (TZP) is executed, the count value of Timer Z is read out.

The count value of Timer Z can be read out by reading from the

timer Z primary (TZP) even when the value of timer Z primary

latch or timer Z secondary latch is counted. When reading the

timer Z secondary (TZS) is executed, the undefined value is read

out.

Waveform frequency:

2✕TMZCL

FZOUT=

2✕(TZP+1)+2✕(TZS+1)+(EXPZP+EXPZS)

Duty:

2✕(TZP+1)+EXPZP

DZOUT=

Timer Z can be selected in one of 4 operating modes by setting

the timer Z operating mode bits of the timer Y, Z mode register.

(2✕(TZP+1)+EXPZP)+(2✕(TZS+1)+EXPZS

TMZCL: Timer Z count source (frequency)

TZP: Timer Z primary (8bit)

(1) Timer mode

Prescaler Z counts the count source selected by the timer Z count

source selection bits. Each time the count clock is input, the con-

tents of Prescaler Z is decremented by 1. When the contents of

Prescaler Z reach “0016”, an underflow occurs at the next count

clock, and the prescaler Z latch is reloaded into Prescaler Z. The

division ratio of Prescaler Z is 1/(n+1) provided that the value of

Prescaler Z is n.

TZS: Timer Z secondary (8bit)

EXPZP: Timer Z primary waveform extension control bit (1bit)

EXPZS: Timer Z secondary waveform extension control bit (1bit)

In the programmable waveform generation mode, when values of

the TZP, TZS, EXPZP and EXPZS are changed, the output wave-

form is changed at the beginning (timer Z primary waveform

interval) of waveform period.

The contents of Timer Z is decremented by 1 each time the under-

flow signal of Prescaler Z is input. When the contents of Timer Z

reach “0016”, an underflow occurs at the next count clock, and the

timer Z primary latch is reloaded into Timer Z and count continues.

(In the timer mode, the contents of timer Z primary latch is

counted. Timer Z secondary latch is not used in this mode.)

The division ratio of Timer Z is 1/(m+1) provided that the value of

Timer Z is m. Accordingly, the division ratio of Prescaler Z and

Timer Z is 1/((n+1)✕(m+1)) provided that the value of Prescaler Z

is n and the value of Timer Z is m.

When the count values are changed, set values to the TZS,

EXPZP and EXPZS first. After then, set the value to TZP. The val-

ues are set all at once at the beginning of the next waveform

period when the value is set to TZP. (When writing at timer stop is

executed, writing to TZP at last is required.)

In the timer mode, writing to “latch only” or “latches and Prescaler

Z and timer Z primary” can be selected by the setting value of the

timer Z write control bit.

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Notes on the programmable waveform generation mode are de-

scribed below;

The falling or rising can be selected as the edge of the valid trig-

ger of INT0 pin by the INT0 pin one-shot trigger edge selection bit.

During the one-shot pulse output interval, the one-shot pulse out-

put can be stopped forcibly by writing “0” to the timer Z one-shot

start bit.

✕✕Notes on programmable waveform generation mode

• Count set value

In the programmable waveform generation mode, values of TZS,

EXPZP, and EXPZS are valid by writing to TZP because the set-

ting to them is executed all at once by writing to TZP. Even when

changing TZP is not required, write the same value again.

• Write timing to TZP

In the programmable one-shot generation mode, when the count

values are changed, set value to the EXPZP first. After then, set

the value to TZP. The values are set all at once at the beginning of

the next one-shot pulse when the value is set to TZP. (When writ-

ing at timer stop is executed, writing to TZP at last is required.)

In the programmable waveform generation mode, when the set-

ting value is changed while the waveform is output, set by

software in order not to execute the writing to TZP and the timing

of timer underflow during the secondary interval simultanesously.

• Usage of waveform extension function

Notes on the programmable one-shot generation mode are de-

scribed below;

The waveform extension function by the timer Z waveform exten-

sion control bit can be used only when “0016” is set to Prescaler Z.

When the value other than “0016” is set to Prescaler Z, be sure to

set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is

selected as the count source, the waveform extension function

cannot be used.

✕ Notes on programmable one-shot generation mode

• Count set value

In the programmable one-shot generation mode, the value of

EXPZP becomes valid by writing to TZP. Even when changing

TZP is not required, write the same value again.

• Write timing to TZP

• Timer Z write mode

In the programmable one-shot generation mode, when the setting

value is changed while the waveform is output, set by software in

order not to execute the writing to TZP and the timing of timer un-

derflow simultanesously.

When using this mode, be sure to set “1” to the timer Z write con-

trol bit to select “write to latch only”.

(3) Programmable one-shot generation mode

• Usage of waveform extension function

In the programmable one-shot generation mode, the one-shot

pulse by the setting value of timer Z primary can be output from

TZOUT pin by software or external trigger. When using this mode,

be sure to set “1” to the timer Z write control bit to select “write to

latch only”. Also, set the port P02 direction registers to output

mode. In this mode, TZS is not used.

The waveform extension function by the timer Z waveform exten-

sion control bit can be used only when “0016” is set to Prescaler Z.

When the value other than “0016” is set to Prescaler Z, be sure to

set “0” to EXPZP. Also, when the timer Y underflow is selected as

the count source, the waveform extension function cannot be

used.

The active edge of output waveform is set by the timer Z output

level latch (b5) of the timer Y, Z waveform output control register

(PUM). When “0” is set to b5 of PUM, “H” pulse during the interval

of the TZP setting value is output. When “1” is set to b5 of PUM,

“L” pulse during the interval of the TZP setting value is output.

Also, in this mode, the interval of the one-shot pulse output can be

extended for 0.5 cycle of timer count source clock by setting the

timer Z primary waveform extension control bit (b2) of PUM to “1”.

As a result, the waveforms of more accurate resolution can be

output.

• Timer Z write mode

When using this mode, be sure to set “1” to the timer Z write con-

trol bit to select “write to latch only”.

In the programmable one-shot generation mode, the trigger by

software or the external INT0 pin can be accepted by writing “0” to

the timer Z count stop bit after the count value is set. (At the time

when “0” is written to the timer Z count stop bit, Timer Z stops.)

By writing “1” to the timer Z one-shot start bit, or by inputting the

valid trigger to the INT0 pin after the trigger to the INT0 pin be-

comes valid by writing “1” to the INT0 pin one-shot trigger control

bit, Timer Z starts counting, at the same time, the output of TZOUT

pin is inverted. When Timer Z underflows, the output of TZOUT pin

is inverted again and Timer Z stops. When also the trigger of INT0

pin is accepted, the contents of the one-shot start bit is changed to

“1” by hardware.

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(4) Programmable wait one-shot generation mode

✕✕Notes on programmable wait one-shot generation mode

• Count set value

In the programmable wait one-shot generation mode, the one-shot

pulse by the setting value of timer Z secondary can be output from

TZOUT pin by software or external trigger to INT0 pin after the wait

by the setting value of the timer Z primary. When using this mode,

be sure to set “1” to the timer Z write control bit to select “write to

latch only”. Also, set the port P02 direction registers to output

mode.

In the programmable wait one-shot generation mode, values of

TZS, EXPZP and EXPZS are valid by writing to TZP. Even when

changing TZP is not required, write the same value again.

• Write timing to TZP

In the programmable wait one-shot generation mode, when the

setting value is changed while the waveform is output, set by soft-

ware in order not to execute the writing to TZP and the timing of

timer underflow during the secondary interval simultanesously.

• Usage of waveform extension function

The active edge of output waveform is set by the timer Z output

level latch (b5) of the timer Y, Z waveform output control register

(PUM). When “0” is set to b5 of PUM, after the wait during the in-

terval of the TZP setting value, “H” pulse during the interval of the

TZS setting value is output. When “1” is set to b5 of PUM, after the

wait during the interval of the TZP setting value, “L” pulse during

the interval of the TZS setting value is output.

The waveform extension function by the timer Z waveform exten-

sion control bit can be used only when “0016” is set to Prescaler Z.

When the value other than “0016” is set to Prescaler Z, be sure to

set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is

selected as the count source, the waveform extension function

cannot be used.

Also, in this mode, the intervals of the wait and the one-shot pulse

output can be extended for 0.5 cycle of timer count source clock

by setting EXPZP and EXPZS of PUM to “1”. As a result, the

waveforms of more accurate resolution can be output.

• Timer Z write mode

When using this mode, be sure to set “1” to the timer Z write con-

trol bit to select “write to latch only”.

In the programmable one-shot generation mode, the trigger by

software or the external INT0 pin can be accepted by writing “0” to

the timer Z count stop bit after the count value is set. (At the time

when “0” is written to the timer Z count stop bit, Timer Z stops.)

By writing “1” to the timer Z one-shot start bit, or by inputting the

valid trigger to the INT0 pin after the trigger to the INT0 pin be-

comes valid by writing “1” to the INT0 pin one-shot trigger control

bit, Timer Z starts counting.

Timer Z can stop counting by setting “1” to the timer Z count stop

bit in any mode.

Also, when Timer Z underflows, the timer Z interrupt request bit is

set to “1”.

Timer Z reloads the value of latch when counting is stopped by the

timer Z count stop bit. (When timer is read out while timer is

stopped, the value of latch is read. The value of timer can be read

out only while timer is operating.)

While Timer Z counts the TZP, the initial value of the TZOUT pin

output is retained. When Timer Z underflows, the value of TZS is

reloaded, at the same time, the output of TZOUT pin is inverted.

When Timer Z underflows, the output of TZOUT pin is inverted

again and Timer Z stops. When also the trigger of INT0 pin is ac-

cepted, the contents of the one-shot start bit is changed to “1” by

hardware.

The falling or rising can be selected as the edge of the valid trig-

ger of INT0 pin by the INT0 pin one-shot trigger edge selection bit.

During the wait interval and the one-shot pulse output interval, the

one-shot pulse output can be stopped forcibly by writing “0” to the

timer Z one-shot start bit.

In the programmable wait one-shot generation mode, when the

count values are changed, set values to the TZS, EXPZP and

EXPZS first. After then, set the value to TZP. The values are set all

at once at the beginning of the next wait interval when the value is

set to TZP. (When writing at timer stop is executed, writing to TZP

at last is required.)

Notes on the programmable wait one-shot generation mode are

described below;

Rev.4.00 Jun 21, 2004 page 30 of 82

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b7

b0

Timer Y, Z mode register

(TYZM : address 002016, initial value: 0016

)

Timer Y operating mode bit

0 : Timer mode

1 : Programmable waveform generation mode

Not used (return “0” when read)

Timer Y write control bit

0 : Write to latch and timer simultaneously

1 : Write to only latch

Timer Y count stop bit

0 : Count start

1 : Count stop

Timer Z operating mode bits

b5 b4

0

1

0 : Timer mode

1 : Programmable waveform generation mode

0 : Programmable one-shot generation mode

1 : Programmable wait one-shot generation mode

Timer Z write control bit

0 : Write to latch and timer simultaneously

1 : Write to only latch

Timer Z count stop bit

0 : Count start

1 : Count stop

Fig. 25 Structure of timer Y, Z mode register

b7

b0

Timer Y, Z waveform output control register

(PUM : address 002416, initial value: 0016

)

Timer Y primary waveform extension control bit

0 : Waveform not extended

1 : Waveform extended

Timer Y secondary waveform extension control bit

0 : Waveform not extended

1 : Waveform extended

Timer Z primary waveform extension control bit

0 : Waveform not extended

1 : Waveform extended

Timer Z secondary waveform extension control bit

0 : Waveform not extended

1 : Waveform extended

Timer Y output level latch

0 : “L” output

1 : “H” output

Timer Z output level latch

0 : “L” output

1 : “H” output

INT0 pin one-shot trigger control bit

0 : INT

1 : INT

0

pin one-shot trigger invalid

pin one-shot trigger valid

INT0 pin one-shot trigger active edge selection bit

0 : Falling edge trigger

1 : Rising edge trigger

Fig. 26 Structure of timer YZ waveform output control register

b7

b0

One-shot start register

(ONS : address 002A16, initial value: 0016

)

Timer Z one-shot start bit

0 : One-shot stop

1 : One-shot start

Not used (return “0” when read)

Fig. 27 Structure of one-shot start register

Rev.4.00 Jun 21, 2004 page 31 of 82

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Data bus

Timer 1 latch (8)

Prescaler 1 latch (8)

Prescaler 1 (8)

Timer 1 interrupt

request bit

Timer 1 (8)

f(XIN)/16

Pulse width HL

continuously

measurement mode

Rising edge detected

Falling edge detected

Period measurement mode

CNTR

edge switch bit

1 active

Data bus

P00/CNTR1

Timer A (high-order) latch (8)

Timer A (low-order) latch (8)

Timer A interrupt

request bit

Timer A (low-order) (8)

Timer A (high-order) (8)

Timer A count

stop bit

f(X^IN)/16

Timer A operation mode bit

Fig. 28 Block diagram of timer 1 and timer A

Rev.4.00 Jun 21, 2004 page 32 of 82

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7540 Group

Data bus

f(XIN)/16

f(X^IN)/2

Prescaler X latch (8)

Prescaler X (8)

Timer X latch (8)

Timer X (8)

Pulse width

measurement

mode

f(XIN

)

Timer mode

Pulse output

mode

Timer X count

source selection bits

Timer X

interrupt

request bit

CNTR0 active

edge switch bit

“0”

Event

counter

mode

Timer X count stop bit

P14/CNTR0

CNTR

0

interrupt

request bit

“1”

CNTR0 active

edge switch bit

“1”

“0”

Q

Toggle flip-flop

R

T

Q

Port P1

latch

4

Writing to timer X latch

Pulse output mode

Port P14 direction

register

Pulse output mode

P0

3/

TX^OUT

Port P03 latch

Data bus

P03/TXOUT output valid

Port P0

3

direction

register

Prescaler Y latch (8)

Prescaler Y (8)

Timer Y primary latch (8)

Timer Y secondary latch (8)

Timer Y (8)

Timer Y count

source selection bits

Timer Y

interrupt

f(XIN)/16

f(XIN)/2

request bit

Timer Y count

stop bit

On-chip oscillator clock RING

(on-chip oscillator output

in Fig. 51, 52)

Timer Y primary waveform

extension control bit

Q

T

Toggle flip-flop

Waveform extension function

P01/TYOUT

Port P01 latch

Timer Y output level latch

Timer Y secondary

waveform extension

control bit

Port P0

direction

register

1

Programmable waveform

gengeration mode

Data bus

Prescaler Z latch (8)

Prescaler Z (8)

Timer Z primary latch (8)

Timer Z secondary latch (8)

Timer Z count

source selection bits

f(XIN)/16

f(XIN)/2

Timer Z

interrupt

request bit

Timer Z (8)

Programmable one-shot generation mode

Programmable wait one-shot generation mode

Timer Z count

stop bit

Timer Z one-shot start bit

INT

0 pin trigger active edge

selection bit

INT0

P37/INT0

interrupt

request bit

One-shot pulse

trigger input

Timer Z primary waveform

extenstion control bit

Q

T

Toggle flip flop

Waveform extension function

P02/TZOUT

Timer Z output

level latch

Port P02 latch

Timer Z secondary waveform

extenstion control bit

Port P0

register

2 direction

Programmable waveform generation mode

Programmable one-shot generation mode

Programmable wait one-shot generation mode

Fig. 29 Block diagram of timer X, timer Y and timer Z

Rev.4.00 Jun 21, 2004 page 33 of 82

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Serial I/O

(1) Clock Synchronous Serial I/O Mode

✕Serial I/O1

Clock synchronous serial I/O1 mode can be selected by setting

the serial I/O1 mode selection bit of the serial I/O1 control register

(bit 6) to “1”.

Serial I/O1 can be used as either clock synchronous or asynchro-

nous (UART) serial I/O. A dedicated timer is also provided for

baud rate generation.

For clock synchronous serial I/O1, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the TB/RB.

Data bus

Serial I/O1 control register

Address 001A¹⁶

Address 0018¹⁶

Receive buffer register

Receive buffer full flag (RBF)

Receive shift register

Receive interrupt request (RI)

P10/RXD1

Shift clock

Clock control circuit

P12/SCLK1

Serial I/O1 synchronous

clock selection bit

Frequency division ratio 1/(n+1)

BRG count source selection bit

1/4

X

IN

Baud rate generator

Address 001C¹⁶

1/4

Clock control circuit

P1

3

/SRDY1

Falling-edge detector

F/F

Shift clock

Transmit shift register

Transmit buffer register

Transmit shift completion flag (TSC)

Transmit interrupt source selection bit

P11/TXD1

Transmit interrupt request (TI)

Transmit buffer empty flag (TBE)

Serial I/O1 status register

Address 0019¹⁶

Address 001816

Data bus

Fig. 30 Block diagram of clock synchronous serial I/O1

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial output TxD

Serial input RxD

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

Receive enable signal SRDY1

Write pulse to receive/transmit

buffer register (address 0018¹⁶

)

RBF = 1

TSC = 1

TBE = 0

TBE = 1

TSC = 0

Overrun error (OE)

detection

Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after

the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the

serial I/O1 control register.

2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial

data is output continuously from the TxD pin.

3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Fig. 31 Operation of clock synchronous serial I/O1 function

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The transmit and receive shift registers each have a buffer, but the

two buffers have the same address in memory. Since the shift reg-

ister cannot be written to or read from directly, transmit data is

written to the transmit buffer register, and receive data is read

from the receive buffer register.

(2) Asynchronous Serial I/O (UART) Mode

Clock asynchronous serial I/O mode (UART) can be selected by

clearing the serial I/O1 mode selection bit of the serial I/O1 control

register to “0”.

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

Data bus

Address 001816

Serial I/O1 control register Address 001A¹⁶

Receive buffer register

OE

Character length selection bit

Receive buffer full flag (RBF)

Receive interrupt request (RI)

P10/RXD1

ST detector

7 bits

8 bits

Receive shift register

PE FE SP detector

1/16

UART control register

Address 001B¹⁶

Clock control circuit

Serial I/O1 synchronous clock selection bit

P12/SCLK1

Frequency division ratio 1/(n+1)

BRG count source selection bit

1/4

X

IN

Baud rate generator

Address 001C¹⁶

ST/SP/PA generator

1/16

Transmit shift completion flag (TSC)

Transmit interrupt source selection bit

P11/TXD1

Transmit shift register

Transmit interrupt request (TI)

Character length selection bit

Transmit buffer empty flag (TBE)

Transmit buffer register

Address 001816

Address 001916

Serial I/O1 status register

Data bus

Fig. 32 Block diagram of UART serial I/O1

Transmit or receive clock

Transmit buffer write

signal

TBE=0

TSC=0

TBE=1

TBE=0

TSC=1^✕

SP

TBE=1

Serial output TXD

ST

D0

D1

ST

D0

D1

SP

^✕Generated at 2nd bit in 2-stop-bit mode

1 start bit

7 or 8 data bit

1 or 0 parity bit

1 or 2 stop bit (s)

Receive buffer read

signal

RBF=0

RBF=1

SP

RBF=1

SP

ST

Serial input RXD

D0

D1

ST

D0

D1

Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).

2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit

interrupt source selection bit (TIC) of the serial I/O1 control register.

3: The receive interrupt (RI) is set when the RBF flag becomes “1.”

4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Fig. 33 Operation of UART serial I/O1 function

Rev.4.00 Jun 21, 2004 page 35 of 82

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[Transmit buffer register/receive buffer register (TB/RB)]

001816

✕✕Notes on serial I/O

• Serial I/O interrupt

The transmit buffer register and the receive buffer register are lo-

cated at the same address. The transmit buffer is write-only and

the receive buffer is read-only. If a character bit length is 7 bits, the

MSB of data stored in the receive buffer is “0”.

When setting the transmit enable bit to “1”, the serial I/O transmit

interrupt request bit is automatically set to “1”. When not requiring

the interrupt occurrence synchronized with the transmission en-

abled, take the following sequence.

✕ Set the serial I/O transmit interrupt enable bit to “0” (disabled).

✕ Set the transmit enable bit to “1”.

[Serial I/O1 status register (SIO1STS)] 001916

The read-only serial I/O1 status register consists of seven flags

(bits 0 to 6) which indicate the operating status of the serial I/O1

function and various errors.

✕ Set the serial I/O transmit interrupt request bit to “0” after 1 or

more instructions have been executed.

✕ Set the serial I/O transmit interrupt enable bit to “1” (enabled).

Three of the flags (bits 4 to 6) are valid only in UART mode.

The receive buffer full flag (bit 1) is cleared to “0” when the receive

buffer register is read.

• I/O pin function when serial I/O1 is enabled.

The functions of P12 and P13 are switched with the setting values

of a serial I/O1 mode selection bit and a serial I/O1 synchronous

clock selection bit as follows.

If there is an error, it is detected at the same time that data is

transferred from the receive shift register to the receive buffer reg-

ister, and the receive buffer full flag is set. A write to the serial I/O1

status register clears all the error flags OE, PE, FE, and SE (bit 3

to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE

(bit 7 of the serial I/O1 control register) also clears all the status

flags, including the error flags.

(1) Serial I/O1 mode selection bit → “1” :

Clock synchronous type serial I/O is selected.

Setup of a serial I/O1 synchronous clock selection bit

“0” : P12 pin turns into an output pin of a synchronous clock.

“1” : P12 pin turns into an input pin of a synchronous clock.

Setup of a SRDY1 output enable bit (SRDY)

Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at

reset, but if the transmit enable bit of the serial I/O1 control regis-

ter has been set to “1”, the transmit shift completion flag (bit 2)

and the transmit buffer empty flag (bit 0) become “1”.

“0” : P13 pin can be used as a normal I/O pin.

“1” : P13 pin turns into a SRDY output pin.

[Serial I/O1 control register (SIO1CON)] 001A16

The serial I/O1 control register consists of eight control bits for the

serial I/O1 function.

(2) Serial I/O1 mode selection bit → “0” :

Clock asynchronous (UART) type serial I/O is selected.

Setup of a serial I/O1 synchronous clock selection bit

“0”: P12 pin can be used as a normal I/O pin.

[UART control register (UARTCON)] 001B16

“1”: P12 pin turns into an input pin of an external clock.

When clock asynchronous (UART) type serial I/O is selected, it is

P13 pin. It can be used as a normal I/O pin.

The UART control register consists of four control bits (bits 0 to 3)

which are valid when asynchronous serial I/O is selected and set

the data format of an data transfer and one bit (bit 4) which is al-

ways valid and sets the output structure of the P11/TXD1 pin.

[Baud rate generator (BRG)] 001C16

The baud rate generator determines the baud rate for serial transfer.

The baud rate generator divides the frequency of the count source

by 1/(n + 1), where n is the value written to the baud rate generator.

Rev.4.00 Jun 21, 2004 page 36 of 82

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7540 Group

b7

b0

b7

b0

Serial I/O1 status register

(SIO1STS : address 0019 16, initial value: 0016)

Serial I/O1 control register

(SIO1CON : address 001A 16, initial value: 0016)

BRG count source selection bit (CSS)

0: f(XIN)

1: f(XIN)/4

Transmit buffer empty flag (TBE)

0: Buffer full

1: Buffer empty

Serial I/O1 synchronous clock selection bit (SCS)

0: BRG output divided by 4 when clock synchronous

serial I/O is selected, BRG output divided by 16

when UART is selected.

Receive buffer full flag (RBF)

0: Buffer empty

1: Buffer full

1: External clock input when clock synchronous serial

I/O is selected, external clock input divided by 16

when UART is selected.

Transmit shift completion flag (TSC)

0: Transmit shift in progress

1: Transmit shift completed

SRDY1 output enable bit (SRDY)

0: P13 pin operates as ordinary I/O pin

1: P13 pin operates as SRDY1 output pin

Overrun error flag (OE)

0: No error

1: Overrun error

Transmit interrupt source selection bit (TIC)

0: Interrupt when transmit buffer has emptied

1: Interrupt when transmit shift operation is completed

Parity error flag (PE)

0: No error

1: Parity error

Transmit enable bit (TE)

0: Transmit disabled

1: Transmit enabled

Framing error flag (FE)

0: No error

1: Framing error

Receive enable bit (RE)

0: Receive disabled

1: Receive enabled

Summing error flag (SE)

0: (OE) U (PE) U (FE)=0

1: (OE) U (PE) U (FE)=1

Serial I/O1 mode selection bit (SIOM)

0: Clock asynchronous (UART) serial I/O

1: Clock synchronous serial I/O

Not used (returns “1” when read)

b7

b0

Serial I/O1 enable bit (SIOE)

0: Serial I/O1 disabled

(pins P10 to P13 operate as ordinary I/O pins)

1: Serial I/O1 enabled

(pins P10 to P13operate as serial I/O pins)

UART control register

(UARTCON : address 001B 16, initial value: E016)

Character length selection bit (CHAS)

0: 8 bits

1: 7 bits

Parity enable bit (PARE)

0: Parity checking disabled

1: Parity checking enabled

Parity selection bit (PARS)

0: Even parity

1: Odd parity

Stop bit length selection bit (STPS)

0: 1 stop bit

1: 2 stop bits

P11/TXD1 P-channel output disable bit (POFF)

0: CMOS output (in output mode)

1: N-channel open drain output (in output mode)

Not used (return “1” when read)

Fig. 34 Structure of serial I/O1-related registers

Rev.4.00 Jun 21, 2004 page 37 of 82

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✕Serial I/O2

The serial I/O2 function can be used only for clock synchronous

b7

b0

Serial I/O2 control register

(SIO2CON: address 003016, initila value: 0016)

serial I/O.

For clock synchronous serial I/O2 the transmitter and the receiver

must use the same clock. When the internal clock is used, transfer

is started by a write signal to the serial I/O2 register.

Note: Serial I/O2 can be used in the following cases;

(1) Serial I/O1 is not used,

Internal synchronous clock selection bits

000 : f(XIN)/8

001 : f(XIN)/16

010 : f(XIN)/32

011 : f(XIN)/64

110 : f(XIN)/128

111 : f(XIN)/256

(2) Serial I/O1 is used as UART and BRG output divided by 16 is

selected as the synchronized clock.

SDATA2 pin selection bit (Note)

0 : I/O port / SDATA2 input

1 : SDATA2 output

Not used

[Serial I/O2 control register] SIO2CON

The serial I/O2 control register contains 8 bits which control vari-

ous serial I/O functions.

(returns “0” when read)

Transfer direction selection bit

0 : LSB first

1 : MSB first

SCLK2 pin selection bit

0 : External clock (SCLK2 is an input)

1 : Internal clock (SCLK2 is an output)

• Set “0” to bit 3 to receive.

• At reception, clear bit 7 to “0” by writing a dummy data to the se-

rial I/O2 register after completion of shift.

Transmit / receive shift completion flag

0 : shift in progress

1 : shift completed

Note : When using it as a SDATA input, set the port P13

direction register to “0”.

Fig. 35 Structure of serial I/O2 control registers

Data bus

1/8

1/16

1/32

1/64

1/128

1/256

X

IN

S

CLK2 pin

selection bit “1”

S

CLK

Internal synchronous

clock selection bits

“0”

S

CLK2 pin selection bit

“0”

P12 latch

P12/SCLK2

Serial I/O2

interrupt request

Serial I/O counter 2 (3)

“1”

S

DATA2 pin selection bit

“0”

P13 latch

P13/SDATA2

“1”

DATA2 pin selection bit

S

Serial I/O shift register 2 (8)

Fig. 36 Block diagram of serial I/O2

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Serial I/O2 operation

By writing to the serial I/O2 register (address 003116) the serial I/

O2 counter is set to “7”.

After writing, the SDATA2 pin outputs data every time the transfer

clock shifts from “H” to “L”. And, as the transfer clock shifts from

“L” to “H”, the SDATA2 pin reads data, and at the same time the

contents of the serial I/O2 register are shifted by 1 bit.

When the internal clock is selected as the transfer clock source,

the following operations execute as the transfer clock counts up to

8.

• Serial I/O2 counter is cleared to “0”.

• Transfer clock stops at an “H” level.

• Interrupt request bit is set.

• Shift completion flag is set.

Also, the SDATA2 pin is in a high impedance state after the data

transfer is completed (refer to Fig.37).

When the external clock is selected as the transfer clock source,

the interrupt request bit is set as the transfer clock counts up to 8,

but external control of the clock is required since it does not stop.

Notice that the SDATA2 pin is not in a high impedance state on the

completion of data transfer.

Also, after the receive operation is completed, the transmit/receive

shift completion flag is cleared by reading the serial I/O2 register.

At transmit, the transmit/receive shift completion flag is cleared

and the transmit operation is started by writing to serial I/O2 regis-

ter.

Synchronous clock

Transfer clock

Serial I/O2 register

write signal

(Note)

S

DATA2 at serial I/O2

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D7

output transmit

S

DATA2 at serial I/O2

input receive

Serial I/O2 interrupt request bit set

Transmit/receive shift completion flag set

Note : When the internal clock is selected as the transfer and the direction register of P1

3/SDATA2 pin is set to the input mode,

the SDATA2 pin is in a high impedance state after the data transfer is completed.

Fig. 37 Serial I/O2 timing (LSB first)

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(2) When VREF voltage is lower than [3.0 V], the accuracy at the

low temperature may become extremely low compared with

that at room temperature When the system would be used at

low temperature, the use at VREF=3.0 V or more is recom-

mended.

A/D Converter

The functional blocks of the A/D converter are described below.

[A/D conversion register] AD

The A/D conversion register is a read-only register that stores the

result of A/D conversion. Do not read out this register during an A/

D conversion.

b7

b0

A/D control register

(ADCON : address 003416, initial value: 1016)

[A/D control register] ADCON

Analog input pin selection bits

000 : P20/AN0

001 : P21/AN1

010 : P22/AN2

011 : P23/AN3

100 : P24/AN4

101 : P25/AN5

110 : P26/AN6 (Note)

111 : P27/AN7 (Note)

The A/D control register controls the A/D converter. Bit 2 to 0 are

analog input pin selection bits. Bit 4 is the AD conversion comple-

tion bit. The value of this bit remains at “0” during A/D conversion,

and changes to “1” at completion of A/D conversion.

A/D conversion is started by setting this bit to “0”.

Not used (returns “0” when read)

[Comparison voltage generator]

AD conversion completion bit

0 : Conversion in progress

1 : Conversion completed

The comparison voltage generator divides the voltage between

AVSS and VREF by 1024, and outputs the divided voltages.

Not used (returns “0” when read)

Note: These can be used only for 36 pin version.

[Channel selector]

The channel selector selects one of ports P27/AN7 to P20/AN0,

and inputs the voltage to the comparator.

Fig. 38 Structure of A/D control register

[Comparator and control circuit]

Read 8-bit (Read only address 003516

b7

)

The comparator and control circuit compares an analog input volt-

age with the comparison voltage and stores its result into the A/D

conversion register. When A/D conversion is completed, the con-

trol circuit sets the AD conversion completion bit and the AD

interrupt request bit to “1”. Because the comparator is constructed

linked to a capacitor, set f(XIN) to 500 kHz or more during A/D con-

version.

b0

(Address 003516

)

b9 b8 b7 b6 b5 b4 b3 b2

Read 10-bit (read in order address 003616, 003516

b7

)

b0

b9 b8

(Address 003616

)

b7

b0

✕✕Note on A/D converter

(Address 003516

)

b7 b6 b5 b4 b3 b2 b1 b0

As for AD translation accuracy, on the following operating condi-

tions, accuracy may become low.

(1) Since the analog circuit inside a microcomputer becomes sensi-

tive to noise when VREF voltage is set up lower than Vcc

voltage, accuracy may become low rather than the case where

VREF voltage and Vcc voltage are set up to the same value.

Note: High-order 6-bit of address 003616 returns “0” when read.

Fig. 39 Structure of A/D conversion register

Data bus

b7

b0

A/D control register

(Address 003416

)

3

A/D interrupt request

A/D control circuit

P20/AN0

P21

P22

P23

P24

P25

P26

P27

/AN

1

2

3

4

5

6

7

A/D conversion register (high-order)

(Address 003616

(Address 003516

)

Comparator

A/D conversion register (low-order)

10

Resistor ladder

V

REF

VSS

Fig. 40 Block diagram of A/D converter

Rev.4.00 Jun 21, 2004 page 40 of 82

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Watchdog Timer

Operation of watchdog timer H count source selection bit

A watchdog timer H count source can be selected by bit 7 of the

watchdog timer control register (address 003916). When this bit is

“0”, the count source becomes a watchdog timer L underflow sig-

nal. The detection time is 131.072 ms at f(XIN)=8 MHz.

When this bit is “1”, the count source becomes f(XIN)/16. In this

case, the detection time is 512 µs at f(XIN)=8 MHz.

The watchdog timer gives a means for returning to a reset status

when the program fails to run on its normal loop due to a runaway.

The watchdog timer consists of an 8-bit watchdog timer H and an

8-bit watchdog timer L, being a 16-bit counter.

Standard operation of watchdog timer

The watchdog timer stops when the watchdog timer control regis-

ter (address 003916) is not set after reset. Writing an optional

value to the watchdog timer control register (address 003916)

causes the watchdog timer to start to count down. When the

watchdog timer H underflows, an internal reset occurs. Accord-

ingly, it is programmed that the watchdog timer control register

(address 003916) can be set before an underflow occurs.

When the watchdog timer control register (address 003916) is

read, the values of the high-order 6-bit of the watchdog timer H,

STP instruction disable bit and watchdog timer H count source se-

lection bit are read.

This bit is cleared to “0” after reset.

Operation of STP instruction disable bit

When the watchdog timer is in operation, the STP instruction can

be disabled by bit 6 of the watchdog timer control register (ad-

dress 003916).

When this bit is “0”, the STP instruction is enabled.

When this bit is “1”, the STP instruction is disabled, and an inter-

nal reset occurs if the STP instruction is executed.

Once this bit is set to “1”, it cannot be changed to “0” by program.

This bit is cleared to “0” after reset.

Initial value of watchdog timer

By a reset or writing to the watchdog timer control register (ad-

dress 003916), the watchdog timer H is set to “FF16” and the

watchdog timer L is set to “FF16”.

Data bus

Write “FF16” to the

watchdog timer

control register

Write "FF16" to the

watchdog timer

control register

“0”

“1”

Watchdog timer L (8)

Watchdog timer H (8)

1/16

X

IN

Watchdog timer H count

source selection bit

STP Instruction disable bit

STP Instruction

Reset

circuit

Internal reset

RESET

Fig. 41 Block diagram of watchdog timer

b7

b0

Watchdog timer control register

(WDTCON: address 003916, initial value: 3F16

)

Watchdog timer H (read only for high-order 6-bit)

STP instruction disable bit

0 : STP instruction enabled

1 : STP instruction disabled

Watchdog timer H count source selection bit

0 : Watchdog timer L underflow

1 : f(XIN)/16

Fig. 42 Structure of watchdog timer control register

Rev.4.00 Jun 21, 2004 page 41 of 82

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Reset Circuit

Poweron

(Note)

The microcomputer is put into a reset status by holding the RE-

SET pin at the “L” level for 2 µs or more when the power source

voltage is 2.2 to 5.5 V and XIN is in stable oscillation.

After that, this reset status is released by returning the RESET pin

to the “H” level. The program starts from the address having the

contents of address FFFD16 as high-order address and the con-

tents of address FFFC16 as low-order address.

Power source

voltage

0 V

RESET

VCC

Reset input

voltage

0 V

0.2 VCC

In the case of f(φ) ≤ 6 MHz, the reset input voltage must be 0.9 V

or less when the power source voltage passes 4.5 V.

In the case of f(φ) ≤ 4 MHz, the reset input voltage must be 0.8 V

or less when the power source voltage passes 4.0 V.

In the case of f(φ) ≤ 2 MHz, the reset input voltage must be 0.48 V

or less when the power source voltage passes 2.4 V.

In the case of f(φ) ≤ 1 MHz, the reset input voltage must be 0.44 V

or less when the power source voltage passes 2.2 V.

Note : Reset release voltage Vcc = 2.2 V

RESET

VCC

Power source

voltage

detection circuit

Fig. 43 Example of reset circuit

Clock from on-chip

oscillator RING

φ

RESET

RESETOUT

SYNC

AD

H

H,ADL

?

FFFC

FFFD

Address

Reset address from the

vector table

?

ADL

AD

Data

Notes

1 : An on-chip oscillator applies about RING•2 MHz, φ•250 kHz frequency clock

at average of Vcc = 5 V.

8-13 clock cycles

2 : The mark “?” means that the address is changeable depending on the previous state.

3 : These are all internal signals except RESET.

Fig. 44 Timing diagram at reset

Rev.4.00 Jun 21, 2004 page 42 of 82

REJ03B0011-0400Z

7540 Group

Address

Register contents

0016

000116

(1)

(2)

(3)

(4)

(5)

(6)

(7)

Port P0 direction register

Port P1 direction register

Port P2 direction register

Port P3 direction register

X

0

000316

000516

000716

001616

001716

001916

001A16

001B16

0016

00¹⁶

Pull-up control register

Port P1P3 control register

1

0

1

0

1

0

Serial I/O1 status register

0016

(8) Serial I/O1 control register

0

(9)

UART control register

0016

001D16

001E16

001F16

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

003016

003116

003416

003816

003916

003A16

003B16

003C16

(10)

Timer A mode register

(11) Timer A (low-order)

(12)

FF16

0016

FF16

0016

FF16

Timer A (high-order)

(13) Timer Y, Z mode register

(14)

(15)

(16)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26)

Prescaler Y

Timer Y secondary

Timer Y primary

Timer Y, Z waveform output control register

Prescaler Z

Timer Z secondary

Timer Z primary

Prescaler 1

FF16

0116

0016

Timer 1

One-shot start register

Timer X mode register

Prescaler X

FF16

0016

Timer X

(27) Timer count source set register

(28) Serial I/O2 control register

(29) Serial I/O2 register

0016

1016

0016

(30) A/D control register

(31) MISRG

0

1

0

1

0

1

0

1

0

1

0

(32) Watchdog timer control register

0016

Interrupt edge selection register

(33)

(34)

(35)

(36)

(37)

(38)

(39)

(40)

0

CPU mode register

0016

Interrupt request register 1

Interrupt request register 2

Interrupt control register 1

Interrupt control register 2

Processor status register

003D16

003E16

003F16

X

1

X

(PS)

Contents of address FFFD16

Contents of address FFFC16

Note X : Undefined

Program counter

(PCH

)

(PCL

)

Fig. 45 Internal status of microcomputer at reset

Rev.4.00 Jun 21, 2004 page 43 of 82

REJ03B0011-0400Z

7540 Group

Clock Generating Circuit

Note:

Externally connect a

damping resistor Rd de-

p e n d i n g o n t h e

oscillation frequency.

(A feedback resistor is

built-in.)

Use the resonator

manufacturer’s recom-

mended value because

constants such as ca-

pacitance depend on the

resonator.

An oscillation circuit can be formed by connecting a resonator be-

tween XIN and XOUT, and an RC oscillation circuit can be formed

by connecting a resistor and a capacitor.

M37540

Use the circuit constants in accordance with the resonator

manufacturer's recommended values.

X

IN

XOUT

Rd

(1) On-chip oscillator operation

When the MCU operates by the on-chip oscillator for the main

clock, connect XIN pin to VSS and leave XOUT pin open.

The clock frequency of the on-chip oscillator depends on the sup-

ply voltage and the operation temperature range.

Be careful that variable frequencies when designing application

products.

C

OUT

C

IN

Fig. 46 External circuit of ceramic resonator

Note:

Connect the external

circuit of resistor R

and the capacitor C at

the shortest distance.

The frequency is af-

fected by a capacitor,

a resistor and a micro-

computer.

(2) Ceramic resonator

When the ceramic resonator is used for the main clock, connect

the ceramic resonator and the external circuit to pins XIN and

XOUT at the shortest distance. A feedback resistor is built in be-

tween pins XIN and XOUT.

M37540

X

IN

XOUT

R

C

(3) RC oscillation

So, set the constants

within the range of the

frequency limits.

When the RC oscillation is used for the main clock, connect the

XIN pin and XOUT pin to the external circuit of resistor R and the

capacitor C at the shortest distance.

The frequency is affected by a capacitor, a resistor and a micro-

computer.

Fig. 47 External circuit of RC oscillation

So, set the constants within the range of the frequency limits.

(4) External clock

M37540

When the external signal clock is used for the main clock, connect

the XIN pin to the clock source and leave XOUT pin open.

XIN

XOUT

Open

External oscillation

circuit

V

CC

SS

V

Fig. 48 External clock input circuit

Note:

The clock frequency of the

on-chip oscillator depends

on the supply voltage and

the operation temperature

range.

M37540

Be careful that variable fre-

quencies and obtain the

sufficient margin.

X

IN

XOUT

Open

Fig. 49 Processing of XIN and XOUT pins at on-chip oscillator

operation

Rev.4.00 Jun 21, 2004 page 44 of 82

REJ03B0011-0400Z

7540 Group

(1) Oscillation control

✕ Oscillation stop detection circuit (Note)

The oscillation stop detection circuit is used for reset occurrence

when a ceramic resonator or an oscillation circuit stops by discon-

nection. When internal reset occurs, reset because of oscillation

stop can be detected by setting “1” to the oscillation stop detection

status bit.

• Stop mode

When the STP instruction is executed, the internal clock φ stops at

an “H” level and the XIN oscillator stops. At this time, timer 1 is set

to “0116” and prescaler 1 is set to “FF16” when the oscillation sta-

bilization time set bit after release of the STP instruction is “0”. On

the other hand, timer 1 and prescaler 1 are not set when the

above bit is “1”. Accordingly, set the wait time fit for the oscillation

stabilization time of the oscillator to be used. f(XIN)/16 is forcibly

connected to the input of prescaler 1. When an external interrupt

is accepted, oscillation is restarted but the internal clock φ remains

at “H” until timer 1 underflows. As soon as timer 1 underflows, the

internal clock φ is supplied. This is because when a ceramic oscil-

lator is used, some time is required until a start of oscillation. In

case oscillation is restarted by reset, no wait time is generated. So

apply an “L” level to the RESET pin while oscillation becomes

stable.

Also, when using the oscillation stop detection circuit, an on-chip

oscillator is required.

Figure 53 shows the state transition.

Note: The oscillation stop detection circuit is not included in the

emulator MCU “M37540RSS”.

b7

b0

MISRG(address 003816, initial value: 0016

)

Oscillation stabilization time set bit after

release of the STP instruction

Also, the STP instruction cannot be used while CPU is operating

by an on-chip oscillator.

0: Set “0116” in timer1, and “FF16

in prescaler 1 automatically

1: Not set automatically

”

• Wait mode

Ceramic or RC oscillation stop detection

function active bit

0: Detection function inactive

1: Detection function active

If the WIT instruction is executed, the internal clock φ stops at an

“H” level, but the oscillator does not stop. The internal clock re-

starts if a reset occurs or when an interrupt is received. Since the

oscillator does not stop, normal operation can be started immedi-

ately after the clock is restarted. To ensure that interrupts will be

received to release the STP or WIT state, interrupt enable bits

must be set to “1” before the STP or WIT instruction is executed.

Reserved bits (return “0” when read)

(Do not write “1” to these bits)

Not used (return “0” when read)

Oscillation stop detection status bit

0: Oscillation stop not detected

1: Oscillation stop detected

✕ Notes on clock generating circuit

Fig. 50 Structure of MISRG

For use with the oscillation stabilization set bit after release of the

STP instruction set to “1”, set values in timer 1 and prescaler 1 af-

ter fully appreciating the oscillation stabilization time of the

oscillator to be used.

• Switch of ceramic and RC oscillations

After releasing reset the operation starts by starting an on-chip os-

cillator. Then, a ceramic oscillation or an RC oscillation is selected

by setting bit 5 of the CPU mode register.

• Double-speed mode

When a ceramic oscillation is selected, a double-speed mode can

be used. Do not use it when an RC oscillation is selected.

• CPU mode register

Bits 5, 1 and 0 of CPU mode register are used to select oscillation

mode and to control operation modes of the microcomputer. In or-

der to prevent the dead-lock by error-writing (ex. program

run-away), these bits can be rewritten only once after releasing re-

set. After rewriting it is disable to write any data to the bit. (The

emulator MCU “M37540RSS” is excluded.)

Also, when the read-modify-write instructions (SEB, CLB) are ex-

ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.

• Clock division ratio, XIN oscillation control, on-chip oscillator control

The state transition shown in Fig. 52 can be performed by setting

the clock division ratio selection bits (bits 7 and 6), XIN oscillation

control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of

CPU mode register. Be careful of notes on use in Fig. 52.

Rev.4.00 Jun 21, 2004 page 45 of 82

REJ03B0011-0400Z

7540 Group

XIN

XOUT

Rf

Clock division ratio selection bit

Middle-, high-, low-speed mode

Timer 1

Prescaler 1

1/2

1/4

On-chip oscillator mode

Clock division

ratio selection bit

Middle-speed mode

Timing φ

(Internal clock)

High-speed mode

Double-speed mode

On-chip oscillator mode

RING

1/8

On-chip oscillator

Q

S

R

S

R

Q

S

R

RESET

WIT

instruction

STP instruction

Reset

Interrupt disable flag l

Interrupt request

Fig. 51 Block diagram of internal clock generating circuit (for ceramic resonator)

XOUT

XIN

Clock division ratio selection bit

Middle-, high-, low-speed mode

Timer 1

Prescaler 1

1/2

1/4

1/2

On-chip

oscillator

mode

Delay

Clock division

ratio selection bit

Middle-speed mode

Timing φ

(Internal clock)

High-speed mode

Double-speed mode

RING

1/8

On-chip oscillator

On-chip oscillator mode

Q

S

R

S

R

Q

S

R

RESET

WIT

instruction

STP instruction

Reset

Interrupt disable flag l

Interrupt request

Fig. 52 Block diagram of internal clock generating circuit (for RC oscillation)

Rev.4.00 Jun 21, 2004 page 46 of 82

REJ03B0011-0400Z

7540 Group

Stop mode

Wait mode

Interrupt

WIT

instruction

Interrupt

STP

instruction

Interrupt

WIT

instruction

State 1

Operation clock source:

f(XIN) (Note 1)

f(XIN) oscillation enabled

On-chip oscillator stop

State 2

Operation clock source:

f(XIN) (Note 1)

f(XIN) oscillation enabled

On-chip oscillator enabled

State 3

State 4

CPUM76←102

Operation clock source:

On-chip oscillator (Note 3)

f(XIN) oscillation enabled

On-chip oscillator enalbed

Operation clock source:

On-chip oscillator (Note 3)

f(XIN) oscillation stop

CPUM3←02

CPUM3←12

CPUM4←12

CPUM4←02

On-chip oscillator enalbed

CPUM76←002

012

112

(Note 2)

Notes on switch of clock

(1) In operation clock source = f(XIN), the following can be

selected for the CPU clock division ratio.

MISRG1←12

MISRG1←02

✕ f(XIN)/2 (high-speed mode)

MISRG1←12

MISRG1←02

✕ f(XIN)/8 (middle-speed mode)

✕ f(XIN) (double-speed mode, only at a ceramic oscillation)

(2) Execute the state transition state 3 to state 2 or

state 3’ to state 2’ after stabilizing XIN oscillation.

(3) In operation clock source = on-chip oscillator, the middle-

speed mode is selected for the CPU clock division ratio.

(4) When the state transition state 2 → state 3 → state 4

is performed, execute the NOP instruction as shown below

according to the division ratio of CPU clock.

State 3’

State 2’

Operation clock source:

f(XIN) (Note 1)

CPUM76←102

Operation clock source:

On-chip oscillator (Note 3)

f(XIN) oscillation enabled

On-chip oscillator enalbed

On-chip oscillator enabled

CPUM76←002

012

112

(Note 2)

• CPUM76 → 10

• NOP instruction

• CPUM4 → 1 (State 3 → state 4)

2 (State 2 → state 3)

Oscillation stop detection circuit valid

2

Reset released

Double-speed mode at on-chip oscillator: NOP ✕ 3

High-speed mode at on-chip oscillator: NOP ✕ 1

Middle-speed mode at on-chip oscillator: NOP ✕ 0

Reset state

Fig. 53 State transition

Rev.4.00 Jun 21, 2004 page 47 of 82

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NOTES ON PROGRAMMING

State transition

Do not stop the clock selected as the operation clock because of

Processor Status Register

setting of CM3, 4.

The contents of the processor status register (PS) after reset are

undefined except for the interrupt disable flag I which is “1”. After

reset, initialize flags which affect program execution. In particular,

it is essential to initialize the T flag and the D flag because of their

effect on calculations.

NOTES ON HARDWARE

Handling of Power Source Pin

In order to avoid a latch-up occurrence, connect a capacitor suit-

able for high frequencies as bypass capacitor between power

source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the

capacitor to as close as possible. For bypass capacitor which

should not be located too far from the pins to be connected, a ce-

ramic capacitor of 0.01 µF to 0.1 µF is recommended.

Interrupts

The contents of the interrupt request bit do not change even if the

BBC or BBS instruction is executed immediately after they are

changed by program because this instruction is executed for the

previous contents. For executing the instruction for the changed

contents, execute one instruction before executing the BBC or

BBS instruction.

One Time PROM Version

The CNVss pin is connected to the internal memory circuit block

by a low-ohmic resistance, since it has the multiplexed function to

be a programmable power source pin (VPP pin) as well.

To improve the noise reduction, connect a track between CNVss

pin and Vss pin with 1 to 10 kΩ resistance.

Decimal Calculations

• For calculations in decimal notation, set the decimal mode flag

D to “1”, then execute the ADC instruction or SBC instruction. In

this case, execute SEC instruction, CLC instruction or CLD in-

struction after executing one instruction before the ADC instruction

or SBC instruction.

The mask ROM version track of CNVss pin has no operational in-

terference even if it is connected via a resistor.

• In the decimal mode, the values of the N (negative), V (overflow)

and Z (zero) flags are invalid.

Ports

• The values of the port direction registers cannot be read.

That is, it is impossible to use the LDA instruction, memory opera-

tion instruction when the T flag is “1”, addressing mode using

direction register values as qualifiers, and bit test instructions such

as BBC and BBS.

It is also impossible to use bit operation instructions such as CLB

and SEB and read/modify/write instructions of direction registers

for calculations such as ROR.

For setting direction registers, use the LDM instruction, STA in-

struction, etc.

A/D Conversion

Do not execute the STP instruction during A/D conversion.

Instruction Execution Timing

The instruction execution time can be obtained by multiplying the

frequency of the internal clock φ by the number of cycles men-

tioned in the machine-language instruction table.

The frequency of the internal clock φ is the same as that of the XIN

in double-speed mode, twice the XIN cycle in high-speed mode

and 8 times the XIN cycle in middle-speed mode.

CPU Mode Register

The oscillation mode selection bit and processor mode bits can be

rewritten only once after releasing reset. However, after rewriting it

is disable to write any value to the bit. (Emulator MCU is ex-

cluded.)

When a ceramic oscillation is selected, a double-speed mode of

the clock division ratio selection bits can be used. Do not use it

when an RC oscillation is selected.

Rev.4.00 Jun 21, 2004 page 48 of 82

REJ03B0011-0400Z

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NOTES ON PERIPHERAL FUNCTIONS

• Timer Y write mode

When using this mode, be sure to set “1” to the timer Y write con-

trol bit to select “write to latch only”.

✕ Interrupt

When setting the followings, the interrupt request bit may be set to “1”.

•When setting external interrupt active edge

Related register: Interrupt edge selection register (address 003A16)

Timer X mode register (address 2B16)

Timer Y can stop counting by setting “1” to the timer Y count stop bit

in any mode.

Also, when Timer Y underflows, the timer Y interrupt request bit is

set to “1”.

Timer A mode register (address 1D16)

When not requiring the interrupt occurrence synchronized with

these setting, take the following sequence.

Timer Y reloads the value of latch when counting is stopped by the

timer Y count stop bit. (When timer is read out while timer is

stopped, the value of latch is read. The value of timer can be read

out only while timer is operating.)

✕ Set the corresponding interrupt enable bit to “0” (disabled).

✕ Set the interrupt edge select bit (active edge switch bit) to “1”.

✕ Set the corresponding interrupt request bit to “0” after 1 or

more instructions have been executed.

✕ Timer Z: Programmable Waveform

Generation Mode

✕ Set the corresponding interrupt enable bit to “1” (enabled).

• Count set value

✕ Timers

In the programmable waveform generation mode, values of TZS,

EXPZP, and EXPZS are valid by writing to TZP because the set-

ting to them is executed all at once by writing to TZP. Even when

changing TZP is not required, write the same value again.

• Write timing to TZP

• When n (0 to 255) is written to a timer latch, the frequency divi-

sion ratio is 1/(n+1).

• When a count source of timer X, timer Y or timer Z is switched,

stop a count of timer X.

In the programmable waveform generation mode, when the set-

ting value is changed while the waveform is output, set by

software in order not to execute the writing to TZP and the timing

of timer underflow during the secondary interval simultanesously.

• Usage of waveform extension function

✕ Timer A

CNTR1 interrupt active edge selection

CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit.

When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at

the falling edge of the CNTR1 pin input signal. When this bit is “1”,

the CNTR1 interrupt request bit is set to “1” at the rising edge of

the CNTR1 pin input signal.

However, in the pulse width HL continuously measurement mode,

CNTR1 interrupt request is generated at both rising and falling

edges of CNTR1 pin input signal regardless of the setting of

CNTR1 active edge switch bit.

The waveform extension function by the timer Z waveform extension

control bit can be used only when “0016” is set to Prescaler Z. When

the value other than “0016” is set to Prescaler Z, be sure to set “0” to

EXPZP and EXPZS. Also, when the timer Y underflow is selected as

the count source, the waveform extension function cannot be used.

• Timer Z write mode

When using this mode, be sure to set “1” to the timer Z write con-

trol bit to select “write to latch only”.

✕ Timer X

CNTR0 interrupt active edge selection

✕ Timer Z: Programmable One-shot

Generation Mode

CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit.

When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at the falling

edge of CNTR0 pin input signal. When this bit is “1”, the CNTR0 interrupt re-

quest bit is set to “1” at the rising edge of CNTR0 pin input signal.

• Count set value

In the programmable one-shot generation mode, the value of

EXPZP becomes valid by writing to TZP. Even when changing

TZP is not required, write the same value again.

• Write timing to TZP

✕ Timer Y: Programmable Generation

Waveform Mode

In the programmable one-shot generation mode, when the setting

value is changed while the waveform is output, set by software in

order not to execute the writing to TZP and the timing of timer un-

derflow simultanesously.

• Count set value

In the programmable waveform generation mode, values of TYS,

EXPYP, and EXPYS are valid by writing to TYP because the set-

ting to them is executed all at once by writing to TYP. Even when

changing TYP is not required, write the same value again.

• Write timing to TYP

• Usage of waveform extension function

The waveform extension function by the timer Z waveform extension con-

trol bit can be used only when “0016” is set to Prescaler Z. When the

value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP.

Also, when the timer Y underflow is selected as the count source, the

waveform extension function cannot be used.

In the programmable waveform generation mode, when the set-

ting value is changed while the waveform is output, set by

software in order not to execute the writing to TYP and the timing

of timer underflow during the secondary interval simultanesously.

• Usage of waveform extension function

• Timer Z write mode

When using this mode, be sure to set “1” to the timer Z write con-

trol bit to select “write to latch only”.

The waveform extension function by the timer Y waveform exten-

sion control bit can be used only when “0016” is set to Prescaler Y.

When the value other than “0016” is set to Prescaler Y, be sure to

set “0” to EXPYP and EXPYS.

Rev.4.00 Jun 21, 2004 page 49 of 82

REJ03B0011-0400Z

7540 Group

(2) Serial I/O1 mode selection bit → “0” :

ꢀ Timer Z: Programmable Wait One-shot

Generation Mode

Clock asynchronous (UART) type serial I/O is selected.

Setup of a serial I/O1 synchronous clock selection bit

“0”: P12 pin can be used as a normal I/O pin.

• Count set value

In the programmable wait one-shot generation mode, values of

TZS, EXPZP and EXPZS are valid by writing to TZP. Even when

changing TZP is not required, write the same value again.

• Write timing to TZP

“1”: P12 pin turns into an input pin of an external clock.

When clock asynchronous (UART) type serial I/O is selected, it is

P13 pin. It can be used as a normal I/O pin.

In the programmable wait one-shot generation mode, when the

setting value is changed while the waveform is output, set by soft-

ware in order not to execute the writing to TZP and the timing of

timer underflow during the secondary interval simultanesously.

• Usage of waveform extension function

ꢀ A/D Converter

• The comparator uses internal capacitors whose charge will be

lost if the clock frequency is too low.

Make sure that f(XIN) is 500kHz or more during A/D conversion.

The waveform extension function by the timer Z waveform exten-

sion control bit can be used only when “0016” is set to Prescaler Z.

When the value other than “0016” is set to Prescaler Z, be sure to

set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is

selected as the count source, the waveform extension function

cannot be used.

• As for AD translation accuracy, on the following operating condi-

tions, accuracy may become low.

(1) Since the analog circuit inside a microcomputer becomes sensi-

tive to noise when VREF voltage is set up lower than Vcc

voltage, accuracy may become low rather than the case where

VREF voltage and Vcc voltage are set up to the same value.

(2) When VREF voltage is lower than [3.0 V], the accuracy at the low

temperature may become extremely low compared with that at

room temperature When the system would be used at low tem-

perature, the use at VREF=3.0 V or more is recommended.

• Timer Z write mode

When using this mode, be sure to set “1” to the timer Z write con-

trol bit to select “write to latch only”.

Timer Z can stop counting by setting “1” to the timer Z count stop

bit in any mode.

ꢀ Notes on clock generating circuit

Also, when Timer Z underflows, the timer Z interrupt request bit is

set to “1”.

For use with the oscillation stabilization set bit after release of the

STP instruction set to “1”, set values in timer 1 and prescaler 1 after fully

appreciating the oscillation stabilization time of the oscillator to be used.

• Switch of ceramic and RC oscillations

Timer Z reloads the value of latch when counting is stopped by the

timer Z count stop bit. (When timer is read out while timer is

stopped, the value of latch is read. The value of timer can be read

out only while timer is operating.)

After releasing reset the operation starts by starting an on-chip os-

cillator. Then, a ceramic oscillation or an RC oscillation is selected

by setting bit 5 of the CPU mode register.

ꢀ Serial I/O

• Serial I/O interrupt

• Double-speed mode

When a ceramic oscillation is selected, a double-speed mode can

be used. Do not use it when an RC oscillation is selected.

When setting the transmit enable bit to “1”, the serial I/O transmit

interrupt request bit is automatically set to “1”. When not requiring

the interrupt occurrence synchronized with the transmission en-

abled, take the following sequence.

• CPU mode register

Bits 5, 1 and 0 of CPU mode register are used to select oscillation

mode and to control operation modes of the microcomputer. In or-

der to prevent the dead-lock by error-writing (ex. program

run-away), these bits can be rewritten only once after releasing re-

set. After rewriting it is disable to write any data to the bit. (The

emulator MCU “M37540RSS” is excluded.)

ꢀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).

ꢀ Set the transmit enable bit to “1”.

ꢀ Set the serial I/O transmit interrupt request bit to “0” after 1 or

more instructions have been executed.

ꢀ Set the serial I/O transmit interrupt enable bit to “1” (enabled).

Also, when the read-modify-write instructions (SEB, CLB) are ex-

ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.

• I/O pin function when serial I/O1 is enabled.

The functions of P12 and P13 are switched with the setting values

of a serial I/O1 mode selection bit and a serial I/O1 synchronous

clock selection bit as follows.

• Clock division ratio, XIN oscillation control, on-chip oscillator control

The state transition shown in Fig. 53 can be performed by setting

the clock division ratio selection bits (bits 7 and 6), XIN oscillation

control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of

CPU mode register. Be careful of notes on use in Fig. 53.

(1) Serial I/O1 mode selection bit → “1” :

Clock synchronous type serial I/O is selected.

Setup of a serial I/O1 synchronous clock selection bit

“0” : P12 pin turns into an output pin of a synchronous clock.

“1” : P12 pin turns into an input pin of a synchronous clock.

Setup of a SRDY1 output enable bit (SRDY)

• On-chip oscillator operation

The clock frequency of the on-chip oscillator depends on the sup-

ply voltage and the operation temperature range.

Be careful that variable frequencies when designing application

products.

“0” : P13 pin can be used as a normal I/O pin.

“1” : P13 pin turns into a SRDY output pin.

Rev.4.00 Jun 21, 2004 page 50 of 82

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ꢀ Note on Power Source Voltage

ROM PROGRAMMING METHOD

When the power source voltage value of a microcomputer is less

than the value which is indicated as the recommended operating

conditions, the microcomputer does not operate normally and may

perform unstable operation.

The built-in PROM of the blank One Time PROM version can be

read or programmed with a general-purpose PROM programmer

using a special programming adapter. Set the address of PROM

programmer in the user ROM area.

In a system where the power source voltage drops slowly when

the power source voltage drops or the power supply is turned off,

reset a microcomputer when the supply voltage is less than the

recommended operating conditions and design a system not to

cause errors to the system by this unstable operation.

Table 7 Special programming adapter

Package

32P4B

Name of Programming Adapter

PCA7435SPG02

32P6U-A

36P2R-A

PCA7435GPG03

PCA7435FPG02

ꢀ Electric Characteristic Differences Among

Mask ROM and One TIme PROM Version

MCUs

There are differences in electric characteristics, operation margin,

noise immunity, and noise radiation among mask ROM and One

Time PROM version MCUs due to the differences in the manufac-

turing processes.

The PROM of the blank One Time PROM version is not tested or

screened in the assembly process and following processes. To en-

sure proper operation after programming, the procedure shown in

Figure 54 is recommended to verify programming.

When manufacturing an application system with One Time PROM

version and then switching to use of the mask ROM version, per-

form sufficient evaluations for the commercial samples of the

mask ROM version.

Programming with

PROM programmer

DATA REQUIRED FOR MASK ORDERS

The following are necessary when ordering a mask ROM produc-

tion:

Screening (Caution)

(150 °C for 40 hours)

1.Mask ROM Order Confirmation Form *

2.Mark Specification Form *

Verification with PROM

programmer

3.Data to be written to ROM, in EPROM form (three identical cop-

ies) or one floppy disk.

DATA REQUIRED FOR ROM PROGRAMMING

ORDERS

Functional check in

target device

The following are necessary when ordering a One Time PROM

production:

Caution:

The screening temperature is far higher

than the storage temperature. Never

expose to 150 °C exceeding 100 hours.

1.ROM Programming Order Confirmation Form *

2.Mark Specification Form *

3.Data to be written to ROM, in EPROM form (three identical cop-

ies) or one floppy disk.

* For the mask ROM confirmation and the mark specifications,

refer to the "Renesas Technology Corp." Homepage

(http://www.renesas.com/en/rom).

Fig. 54 Programming and testing of One Time PROM version

Rev.4.00 Jun 21, 2004 page 51 of 82

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ELECTRICAL CHARACTERISTICS

1.7540Group (General purpose)

Applied to: M37540M2-XXXFP/SP/GP, M37540M4-XXXFP/SP/GP, M37540E2FP/SP/GP, M37540E8FP/SP/GP

Absolute Maximum Ratings (General purpose)

Table 8 Absolute maximum ratings

Symbol

Parameter

Conditions

Ratings

Unit

V

VCC

Power source voltage

Input voltage

–0.3 to 6.5 (Note 1)

–0.3 to VCC + 0.3

VI

V

P00–P07, P10–P14, P20–P27, P30–P37, VREF

Input voltage RESET, XIN

Input voltage CNVSS (Note 2)

Output voltage

All voltages are

based on VSS.

Output transistors

are cut off.

VI

–0.3 to VCC + 0.3

–0.3 to 13

V

VI

VO

–0.3 to VCC + 0.3

P00–P07, P10–P14, P20–P27, P30–P37, XOUT

Power dissipation

Pd

Ta = 25°C

300 (Note 3)

–20 to 85

mW

°C

Topr

Tstg

Operating temperature

Storage temperature

–40 to 125

°C

Notes 1: This is the rating value for the Mask ROM version.

The rating value for the One Time PROM version is –0.3 to 7.0 V.

2: It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version.

3: 200 mW for the 32P6U package product.

Rev.4.00 Jun 21, 2004 page 52 of 82

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Recommended Operating Conditions (General purpose)

Table 9 Recommended operating conditions (1) (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

Parameter

Unit

Min.Typ.Max.

VCC

Power source voltage (ceramic)

f(XIN) = 8 MHz (High-, Middle-speed mode)

f(XIN) = 4 MHz (High-, Middle-speed mode)

f(XIN) = 2 MHz (High-, Middle-speed mode)

f(XIN) = 6 MHz (Double-speed mode)

f(XIN) = 4 MHz (Double-speed mode)

4.0

2.4

2.2

4.5

4.0

2.4

2.2

4.0

2.4

2.2

5.0

5.5

V

5.0

0

f(XIN) = 2 MHz (Double-speed mode)

f(XIN) = 1 MHz (Double-speed mode)

Power source voltage (RC)

f(XIN) = 4 MHz (High-, Middle-speed mode)

f(XIN) = 2 MHz (High-, Middle-speed mode)

f(XIN) = 1 MHz (High-, Middle-speed mode)

VSS

VREF

VIH

Power source voltage

Analog reference voltage

“H” input voltage

2.0

VCC

0.8VCC

P00–P07, P10–P14, P20–P27, P30–P37

“H” input voltage (TTL input level selected)

P10, P12, P13, P36, P37 (Note 1)

“H” input voltage

VCC

0.3VCC

0.8

VIH

2.0

V

VIH

0.8VCC

RESET, XIN

VIL

“L” input voltage

0

V

P00–P07, P10–P14, P20–P27, P30–P37

“L” input voltage (TTL input level selected)

P10, P12, P13, P36, P37 (Note 1)

“L” input voltage

VIL

V

0.2VCC

0.16VCC

–80

VIL

V

RESET, CNVSS

VIL

“L” input voltage

V

XIN

∑IOH(peak)

∑IOL(peak)

∑IOH(avg)

∑IOL(avg)

“H” total peak output current (Note 2)

P00–P07, P10–P14, P20–P27, P30–P37

“L” total peak output current (Note 2)

P00–P07, P10–P14, P20–P27, P37

“L” total peak output current (Note 2)

P30–P36

mA

80

60

–40

“H” total average output current (Note 2)

P00–P07, P10–P14, P20–P27, P30–P37

40

“L” total average output current (Note 2)

P00–P07, P10–P14, P20–P27, P37

“L” total average output current (Note 2)

P30–P36

30

Note 1: Vcc = 4.0 to 5.5V

2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured

over 100 ms. The total peak current is the peak value of all the currents.

Rev.4.00 Jun 21, 2004 page 53 of 82

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Recommended Operating Conditions (General purpose)(continued)

Table 10 Recommended operating conditions (2) (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

Parameter

P00–P07, P10–P14, P20–P27, P30–P37

Unit

Min.

Typ.

Max.

–10

10

30

–5

5

“H” peak output current (Note 1)

“L” peak output current (Note 1)

mA

MHz

IOH(peak)

IOL(peak)

IOH(avg)

IOL(avg)

f(XIN)

P00–P07, P10–P14, P20–P27, P37

P30–P36

“H” average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37

“L” average output current (Note 2)

P00–P07, P10–P14, P20–P27, P37

P30–P36

15

6

Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V

at ceramic oscillation or external clock input Double-speed mode

Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V

at ceramic oscillation or external clock input Double-speed mode

Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V

at ceramic oscillation or external clock input Double-speed mode

Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V

at ceramic oscillation or external clock input Double-speed mode

Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V

at ceramic oscillation or external clock input High-, Middle-speed mode

Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V

at ceramic oscillation or external clock input High-, Middle-speed mode

Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V

at ceramic oscillation or external clock input High-, Middle-speed mode

Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V

4

2

1

8

4

2

4

2

1

MHz

at RC oscillation

High-, Middle-speed mode

Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V

at RC oscillation

High-, Middle-speed mode

Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V

at RC oscillation

High-, Middle-speed mode

Notes 1: The peak output current is the peak current flowing in each port.

2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.

3: When the oscillation frequency has a duty cycle of 50 %.

Rev.4.00 Jun 21, 2004 page 54 of 82

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Electrical Characteristics (General purpose)

Table 11 Electrical characteristics (1) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

Parameter

Test conditions

IOH = –5 mA

Unit

V

Min.Typ.Max.

VCC–1.5

VOH

“H” output voltage

VCC = 4.0 to 5.5 V

P00–P07, P10–P14, P20–P27, P30–P37 (Note 1)

IOH = –1.0 mA

VCC = 2.2 to 5.5 V

VCC–1.0

V

VOL

“L” output voltage

IOL = 5 mA

VCC = 4.0 to 5.5 V

1.5

0.3

1.0

2.0

0.3

1.0

P00–P07, P10–P14, P20–P27, P37

IOL = 1.5 mA

VCC = 4.0 to 5.5 V

IOL = 1.0 mA

VCC = 2.2 to 5.5 V

VOL

“L” output voltage

P30–P36

IOL = 15 mA

VCC = 4.0 to 5.5 V

IOL = 1.5 mA

VCC = 4.0 to 5.5 V

IOL = 10 mA

VCC = 2.2 to 5.5 V

VT+–VT–

Hysteresis

0.4

CNTR0, CNTR1, INT0, INT1(Note 2)

P00–P07 (Note 3)

VT+–VT–

IIH

Hysteresis

RXD, SCLK1, SCLK2, SDATA2 (Note 2)

0.5

V

Hysteresis

RESET

VI = VCC

(Pin floating. Pull up

transistors “off”)

5.0

µA

“H” input current

P00–P07, P10–P14, P20–P27, P30–P37

IIH

IIL

“H” input current

RESET

VI = VCC

µA

VI = VCC

4.0

“H” input current

XIN

VI = VSS

(Pin floating. Pull up

transistors “off”)

–5.0

“L” input current

P00–P07, P10–P14, P20–P27, P30–P37

IIL

“L” input current

RESET, CNVSS

VI = VSS

µA

VI = VSS

–4.0

–0.2

“L” input current

XIN

VI = VSS

–0.5

mA

“L” input current

(Pull up transistors “on”)

P00–P07, P30–P37

VRAM

ROSC

DOSC

RAM hold voltage

When clock stopped

2.0

5.5

V

VCC = 5.0 V, Ta = 25 °C

1000

62.5

2000

125

3000

187.5

kHz

On-chip oscillator oscillation frequency

Oscillation stop detection circuit detection frequency

Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level).

3: It is available only when operating key-on wake up.

Rev.4.00 Jun 21, 2004 page 55 of 82

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Electrical Characteristics (General purpose)(continued)

Table 12 Electrical characteristics (2) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

ICC

Parameter

Test conditions

Unit

mA

Min.Typ.Max.

5.0

8.0

1.5

Power source

current

One Time PROM

version

High-speed mode, f(XIN) = 8 MHz

Output transistors “off”

0.5

6.0

2.0

350

1.6

mA

µA

High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V

Output transistors “off”

10.0

5.0

Double-speed mode, f(XIN) = 6 MHz

Output transistors “off”

Middle-speed mode, f(XIN) = 8 MHz

Output transistors “off”

1000

3.2

On-chip oscillator operation mode, VCC = 5 V

Output transistors “off”

mA

f(XIN) = 8 MHz (in WIT state),

functions except timer 1 disabled,

Output transistors “off”

0.2

mA

f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state),

functions except timer 1 disabled,

Output transistors “off”

150

0.5

0.1

450

µA

On-chip oscillator operation mode, VCC = 5V

Output transistors “off”

mA

Increment when A/D conversion is executed

f(XIN) = 8 MHz, VCC = 5 V

1.0

10

µA

All oscillation stopped

(in STP state)

Output transistors “off”

Ta = 25 °C

Ta = 85 °C

Mask ROM version

3.5

0.4

4.5

2.0

300

1.6

6.5

1.2

8.0

5.0

900

3.2

mA

µA

High-speed mode, f(XIN) = 8 MHz

Output transistors “off”

High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V

Output transistors “off”

Double-speed mode, f(XIN) = 6 MHz

Output transistors “off”

Middle-speed mode, f(XIN) = 8 MHz

Output transistors “off”

On-chip oscillator operation mode, VCC = 5 V

Output transistors “off”

mA

f(XIN) = 8 MHz (in WIT state),

functions except timer 1 disabled,

Output transistors “off”

0.2

mA

f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state),

functions except timer 1 disabled,

Output transistors “off”

150

0.5

0.1

450

µA

On-chip oscillator operation mode, VCC = 5V

Output transistors “off”

mA

Increment when A/D conversion is executed

f(XIN) = 8 MHz, VCC = 5 V

Ta = 25 °C

1.0

10

µA

All oscillation stopped

(in STP state)

Output transistors “off”

Ta = 85 °C

Rev.4.00 Jun 21, 2004 page 56 of 82

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A/D Converter Characteristics (General purpose)

Table 13 A/D Converter characteristics

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

Parameter

Test conditions

Unit

Min.

Typ.Max.

—

Resolution

10

±3

Bits

—

Linearity error

VCC = 2.7 to 5.5 V

Ta = 25 °C

LSB

—

Differential nonlinear error

Zero transition voltage

Full scale transition voltage

Conversion time

VCC = 2.7 to 5.5 V

Ta = 25 °C

±0.9

LSB

VOT

VFST

tCONV

VCC = VREF = 5.12 V

VCC = VREF = 3.072 V

VCC = VREF = 5.12 V

VCC = VREF = 3.072 V

0

5

20

15

mV

0

3

One Time

5105

3060

5115

3069

5125

3075

122

mV

PROM version

mV

tc(XIN)

kΩ

RLADDER Ladder resistor

55

150

70

IVREF

Reference power source input current

VREF = 5.0 V

VREF = 3.0 V

50

200

120

5.0

10

µA

II(AD)

—

A/D port input current

Resolution

µA

Bits

LSB

—

Linearity error

VCC = 2.7 to 5.5 V

Ta = 25 °C

±3

—

Differential nonlinear error

Zero transition voltage

Full scale transition voltage

Conversion time

VCC = 2.7 to 5.5 V

Ta = 25 °C

±1.5

LSB

VOT

VFST

tCONV

VCC = VREF = 5.12 V

VCC = VREF = 3.072 V

VCC = VREF = 5.12 V

VCC = VREF = 3.072 V

0

15

9

35

21

mV

0

Mask ROM version

5105

3060

5125

3075

5150

3090

122

mV

tc(XIN)

kΩ

RLADDER Ladder resistor

55

150

70

IVREF

II(AD)

Reference power source

VREF = 5.0 V

VREF = 3.0 V

50

200

120

5.0

µA

input current

A/D port input current

µA

Rev.4.00 Jun 21, 2004 page 57 of 82

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Timing Requirements (General purpose)

Table 14 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Min.Typ.Max.

Symbol

tW(RESET)

Parameter

Unit

Reset input “L” pulse width

2

µs

ns

tC(XIN)

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0 input cycle time

125

50

tWH(XIN)

tWL(XIN)

50

tC(CNTR0)

200

80

tWH(CNTR0)

tWL(CNTR0)

tC(CNTR1)

CNTR0, INT0, INT1, input “H” pulse width

CNTR0, INT0, INT1, input “L” pulse width

CNTR1 input cycle time

80

2000

800

370

220

100

1000

400

200

tWH(CNTR1)

tWL(CNTR1)

tC(SCLK1)

CNTR1 input “H” pulse width

CNTR1 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input set up time

tWH(SCLK1)

tWL(SCLK1)

tsu(RxD1–SCLK1)

th(SCLK1–RxD1)

tC(SCLK2)

Serial I/O1 input hold time

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 input set up time

tWH(SCLK2)

tWL(SCLK2)

tsu(SDATA2–SCLK2)

th(SCLK2–SDATA2)

Serial I/O2 input hold time

Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).

When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.

Table 15 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

tW(RESET)

Parameter

Unit

Min.Typ.Max.

2

µs

ns

Reset input “L” pulse width

tC(XIN)

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0 input cycle time

250

tWH(XIN)

100

tWL(XIN)

100

tC(CNTR0)

500

tWH(CNTR0)

tWL(CNTR0)

tC(CNTR1)

CNTR0, INT0, INT1, input “H” pulse width

CNTR0, INT0, INT1, input “L” pulse width

CNTR1 input cycle time

230

4000

1600

2000

950

tWH(CNTR1)

tWL(CNTR1)

tC(SCLK1)

CNTR1 input “H” pulse width

CNTR1 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input set up time

tWH(SCLK1)

tWL(SCLK1)

tsu(RxD1–SCLK1)

th(SCLK1–RxD1)

tC(SCLK2)

950

400

Serial I/O1 input hold time

200

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 input set up time

2000

950

tWH(SCLK2)

tWL(SCLK2)

tsu(SDATA2–SCLK2)

th(SCLK2–SDATA2)

950

400

Serial I/O2 input hold time

400

Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).

When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.

Rev.4.00 Jun 21, 2004 page 58 of 82

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Table 16 Timing requirements (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

tW(RESET)

Parameter

Unit

Min.Typ.Max.

Reset input “L” pulse width

2

µs

ns

tC(XIN)

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0 input cycle time

500

tWH(XIN)

200

tWL(XIN)

200

tC(CNTR0)

1000

460

tWH(CNTR0)

tWL(CNTR0)

tC(CNTR1)

CNTR0, INT0, INT1, input “H” pulse width

CNTR0, INT0, INT1, input “L” pulse width

CNTR1 input cycle time

460

8000

3200

4000

1900

800

tWH(CNTR1)

tWL(CNTR1)

tC(SCLK1)

CNTR1 input “H” pulse width

CNTR1 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input set up time

tWH(SCLK1)

tWL(SCLK1)

tsu(RxD1–SCLK1)

th(SCLK1–RxD1)

tC(SCLK2)

Serial I/O1 input hold time

400

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 input set up time

4000

1900

800

tWH(SCLK2)

tWL(SCLK2)

tsu(SDATA2–SCLK2)

th(SCLK2–SDATA2)

Serial I/O2 input hold time

800

Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).

When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.

Rev.4.00 Jun 21, 2004 page 59 of 82

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Switching Characteristics (General purpose)

Table 17 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

Parameter

Unit

MinM.Tayxp..

tC(SCLK1)/2–30

tWH(SCLK1)

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time

ns

tWL(SCLK1)

td(SCLK1–TxD1)

tv(SCLK1–TxD1)

tr(SCLK1)

140

Serial I/O1 output valid time

–30

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

30

tf(SCLK1)

tWH(SCLK2)

tWL(SCLK2)

td(SCLK2–SDATA2)

tv(SCLK2–SDATA2)

tr(SCLK2)

tC(SCLK2)/2–30

140

Serial I/O2 output valid time

0

Serial I/O2 clock output rising time

Serial I/O2 clock output falling time

CMOS output rising time (Note 1)

CMOS output falling time (Note 1)

30

tf(SCLK2)

tr(CMOS)

10

tf(CMOS)

Note 1: Pin XOUT is excluded.

Table 18 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

tWH(SCLK1)

Parameter

Unit

MinM.Tayxp..

tC(SCLK1)/2–50

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time

ns

tWL(SCLK1)

td(SCLK1–TxD1)

tv(SCLK1–TxD1)

tr(SCLK1)

350

Serial I/O1 output valid time

–30

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

50

tf(SCLK1)

tWH(SCLK2)

tWL(SCLK2)

td(SCLK2–SDATA2)

tv(SCLK2–SDATA2)

tr(SCLK2)

tC(SCLK2)/2–50

350

Serial I/O2 output valid time

0

Serial I/O2 clock output rising time

Serial I/O2 clock output falling time

CMOS output rising time (Note 1)

CMOS output falling time (Note 1)

50

tf(SCLK2)

tr(CMOS)

20

tf(CMOS)

Note 1: Pin XOUT is excluded.

Rev.4.00 Jun 21, 2004 page 60 of 82

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Table 19 Switching characteristics (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

tWH(SCLK1)

Parameter

Unit

MinM.Tayxp..

tC(SCLK1)/2–70

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time

ns

tWL(SCLK1)

td(SCLK1–TxD1)

tv(SCLK1–TxD1)

tr(SCLK1)

450

Serial I/O1 output valid time

–30

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

70

tf(SCLK1)

tWH(SCLK2)

tWL(SCLK2)

td(SCLK2–SDATA2)

tv(SCLK2–SDATA2)

tr(SCLK2)

tC(SCLK2)/2–70

450

Serial I/O2 output valid time

0

Serial I/O2 clock output rising time

Serial I/O2 clock output falling time

CMOS output rising time (Note 1)

CMOS output falling time (Note 1)

70

tf(SCLK2)

tr(CMOS)

25

tf(CMOS)

Note 1: Pin XOUT is excluded.

Measured

output pin

100 pF

/ / /

CMOS output

Switching characteristics measurement circuit diagram (Gen-

eral purpose)

Rev.4.00 Jun 21, 2004 page 61 of 82

REJ03B0011-0400Z

7540 Group

t

C

(CNTR

0

)

t

WL(CNTR

0

)

t

WH(CNTR

0

)

0.8VCC

CNTR

0

0.2VCC

tC

1

WL(CNTR

1

tWH(CNTR1

0.8VCC

0.2VCC

CNTR

1

WL(CNTR

0

tWH(CNTR0

0.8VCC

INT

0, INT

1

0.2VCC

tW(RESET)

0.8VCC

RESET

0.2VCC

tC(XIN)

tWL(XIN

)

tWH(XIN)

0.8VCC

XIN

0.2VCC

t

C

(SCLK1

)

t

r

t

f

tWL(SCLK1

)

tWH(SCLK1)

0.8VCC

SCLK1

0.2VCC

tsu(RxD

1

-SCLK1

)

th(SCLK1-RxD1)

0.8VCC

0.2VCC

R

X

D

1

(at receive)

(at transmit)

td

(SCLK1-TxD

1

)

tv(SCLK1-TxD1)

T

X

D

1

t

C

(SCLK2

)

t

r

t

f

tWL(SCLK2

)

tWH(SCLK2)

0.8VCC

S

CLK2

0.2VCC

t

su(SDATA2-SCLK2

)

th(SCLK2-SDATA2)

0.8VCC

0.2VCC

DATA2 (at receive)

DATA2 (at transmit)

td(SCLK2-SDATA2)

tv(SCLK2-SDATA2)

Fig. 55 Timing chart (General purpose)

Rev.4.00 Jun 21, 2004 page 62 of 82

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ELECTRICAL CHARACTERISTICS

2.7540Group (Extended operating temperature version)

Applied to: M37540M2T-XXXFP/GP, M37540M4T-XXXFP/GP, M37540E8T-XXXFP/GP

Absolute Maximum Ratings (Extended operating temperature version)

Table 20 Absolute maximum ratings

Symbol

Parameter

Conditions

Ratings

Unit

V

VCC

Power source voltage

Input voltage

–0.3 to 6.5 (Note 1)

–0.3 to VCC + 0.3

VI

V

All voltages are

based on VSS.

Output transistors

are cut off.

P00–P07, P10–P14, P20–P27, P30–P37, VREF

Input voltage RESET, XIN, CNVSS

Output voltage

VI

–0.3 to VCC + 0.3

V

VO

P00–P07, P10–P14, P20–P27, P30–P37, XOUT

Power dissipation

Ta = 25°C

Pd

300 (Note 2)

–40 to 85

mW

°C

Topr

Tstg

Operating temperature

Storage temperature

–65 to 150

°C

Notes 1: This is the rating value for the Mask ROM version.

The rating value for the One Time PROM version is –0.3 to 7.0 V.

2: 200 mW for the 32P6U package product.

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Recommended Operating Conditions (Extended operating temperature version)

Table 21 Recommended operating conditions (1) (VCC = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)

Limits

Symbol

Parameter

Unit

Min.

4.0

2.4

4.5

4.0

2.4

4.0

2.4

Typ.Max.

5.0

VCC

Power source voltage (ceramic)

f(XIN) = 8 MHz (High-, Middle-speed mode)

f(XIN) = 4 MHz (High-, Middle-speed mode)

f(XIN) = 6 MHz (Double-speed mode)

f(XIN) = 4 MHz (Double-speed mode)

f(XIN) = 2 MHz (Double-speed mode)

f(XIN) = 4 MHz (High-, Middle-speed mode)

f(XIN) = 2 MHz (High-, Middle-speed mode)

5.5

V

5.0

Power source voltage (RC)

5.0

VSS

VREF

VIH

Power source voltage

Analog reference voltage

“H” input voltage

0

2.0

VCC

0.8VCC

P00–P07, P10–P14, P20–P27, P30–P37

“H” input voltage (TTL input level selected)

P10, P12, P13, P36, P37 (Note 1)

“H” input voltage

VIH

2.0

VCC

0.3VCC

0.8

V

VIH

0.8VCC

RESET, XIN

VIL

“L” input voltage

0

V

P00–P07, P10–P14, P20–P27, P30–P37

“L” input voltage (TTL input level selected)

P10, P12, P13, P36, P37 (Note 1)

“L” input voltage

VIL

V

0.2VCC

0.16VCC

–80

VIL

V

RESET, CNVSS

VIL

“L” input voltage

V

XIN

∑IOH(peak)

∑IOL(peak)

∑IOH(avg)

∑IOL(avg)

“H” total peak output current (Note 2)

P00–P07, P10–P14, P20–P27, P30–P37

“L” total peak output current (Note 2)

P00–P07, P10–P14, P20–P27, P37

“L” total peak output current (Note 2)

P30–P36

mA

80

60

–40

“H” total average output current (Note 2)

P00–P07, P10–P14, P20–P27, P30–P37

40

“L” total average output current (Note 2)

P00–P07, P10–P14, P20–P27, P37

“L” total average output current (Note 2)

P30–P36

30

Note 1: Vcc = 4.0 to 5.5V

2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured

over 100 ms. The total peak current is the peak value of all the currents.

Rev.4.00 Jun 21, 2004 page 64 of 82

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Recommended Operating Conditions (Extended operating temperature version)(continued)

Table 22 Recommended operating conditions (2) (VCC = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)