ACS11D/SAMPLE-03 [RENESAS]
AC SERIES, TRIPLE 3-INPUT AND GATE, CDIP14, SIDE BRAZED, CERAMIC, DIP-14;
| 型号： | ACS11D/SAMPLE-03 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | AC SERIES, TRIPLE 3-INPUT AND GATE, CDIP14, SIDE BRAZED, CERAMIC, DIP-14 CD 输入元件 |
| 文件： | 总2页 (文件大小：52K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACS11MS
Data Sheet
November 1998
File Number 4543
Radiation Hardened Triple 3-Input AND
Gate
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
The Radiation Hardened ACS11MS is a Triple 3-Input AND
Gate. When all three inputs to one of the gates are at a
HIGH level, the corresponding Y output will be HIGH. A LOW
level on any input will cause the output for that gate to be
LOW. All inputs are buffered and the outputs are designed
for balanced propagation delay and transition times.
• Radiation Environment
- Latch-Up Free Under any Conditions
5
- Total Dose. . . . . . . . . . . . . . . . . . . . . . 3 x 10 RAD (Si)
-10
- SEU Immunity. . . . . . . . . . . . . <1 x 10
Errors/Bit/Day
2
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm )
The ACS11MS is fabricated on a CMOS Silicon on Sapphire
(SOS) process, which provides an immunity to Single Event
Latch-up and the capability of highly reliable performance in
any radiation environment. These devices offer significant
power reduction and faster performance when compared to
ALSTTL types.
• Input Logic Levels . . . . V = (0.3)(V ), V = (0.7)(V
)
IL CC IH CC
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±8mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . 100µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .12ns (Max)
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Applications
• High Speed Control Circuits
• Sensor Monitoring
Detailed Electrical Specifications for the ACS11MS are
contained in SMD 5962-98622. A “hot-link” is provided
on our homepage with instructions for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
• Low Power Designs
Ordering Information
o
ORDERING NUMBER
INTERNAL MKT. NUMBER
ACS11DMSR-03
TEMP. RANGE ( C)
PACKAGE
14 Ld SBDIP
DESIGNATOR
CDIP2-T14
CDIP2-T14
CDFP4-F14
CDFP4-F14
N/A
5962F9862201VCC
-55 to 125
ACS11D/SAMPLE-03
5962F9862201VXC
ACS11K/SAMPLE-03
5962F9862201V9A
ACS11D/SAMPLE-03
ACS11KMSR-03
25
-55 to 125
25
14 Ld SBDIP
14 Ld Flatpack
14 Ld Flatpack
Die
ACS11K/SAMPLE-03
ACS11HMSR-03
25
Pinouts
ACS11MS
ACS11MS
(SBDIP)
(FLATPACK)
TOP VIEW
TOP VIEW
A1
B1
1
2
3
4
5
6
7
14
V
CC
A1
1
2
3
4
5
6
7
14 V
CC
13
12
11
10
9
C1
Y1
C3
B3
A3
Y3
B1
A2
13 C1
12 Y1
11 C3
10 B3
A2
B2
B2
C2
Y2
C2
GND
8
Y2
9
8
A3
Y3
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
ACS11MS
PASSIVATION:
Die Characteristics
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
DIE DIMENSIONS:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils 1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
SPECIAL INSTRUCTIONS:
Bond V
First
ADDITIONAL INFORMATION:
CC
METALLIZATION: AI
5
2
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
Worst Case Current Density: <2.0 x 10 A/cm
Transistor Count: 97
SUBSTRATE POTENTIAL
Unbiased Insulator
Metallization Mask Layout
ACS11MS
B1
(2)
A1
(1)
V
(14)
C1
(13)
CC
A2 (3)
(12) Y1
(11) C3
NC
B2 (4)
NC
C2 (5)
(10) B3
(6)
Y2
(7)
GND
(8)
Y3
(9)
A3
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