ACS174D/SAMPLE-03 [RENESAS]
AC SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, SIDE BRAZED, CERAMIC, DIP-16;
| 型号： | ACS174D/SAMPLE-03 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | AC SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, SIDE BRAZED, CERAMIC, DIP-16 CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总2页 (文件大小：41K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACS174MS
Data Sheet
July 1999
File Number 4762
Radiation Hardened Hex D-Type Flip-Flop
with Reset
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
The Radiation Hardened ACS174MS is a Hex D-Type Flip-
Flop with Reset. Information at the D input is transferred to
the Q output on the positive-going transition of the clock. All
six flip-flops are controlled by a common clock (CP) and a
common reset (MR). Resetting is accomplished by a LOW
level independent of the clock. All inputs are buffered and
the outputs are designed for balanced propagation delay
and transition times.
• Radiation Environment
- Latch-Up Free Under Any Conditions
5
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10 RAD(Si)
-10
- SEU Immunity. . . . . . . . . . . . . <1 x 10
Errors/Bit/Day
2
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm )
• Input Logic Levels. . . . V = (0.3)(V ), V = (0.7)(V
IL CC IH
)
CC
The ACS174MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .23ns (Max)
Applications
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
Detailed Electrical Specifications for the ACS174MS are
contained in SMD 5962-98634. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/spaceselect.htm
Ordering Information
INTERNAL MARKETING
o
ORDERING NUMBER
5962F9863401VCC
NUMBER
TEMP. RANGE ( C)
PACKAGE
16 Ld SBDIP
DESIGNATOR
CDIP2-T16
CDIP2-T16
CDFP4-F16
CDFP4-F16
NA
ACS174DMSR-03
-55 to 125
ACS174D/SAMPLE-03
5962F9863401VXC
ACS174K/SAMPLE-03
5962F9863401V9A
ACS174D/SAMPLE-03
ACS174KMSR-03
25
-55 to 125
25
16 Ld SBDIP
16 Ld Flatpack
16 Ld Flatpack
Die
ACS174K/SAMPLE-03
ACS174HMSR-03
25
Pinouts
ACS174MS
ACS174MS
(SBDIP)
(FLATPACK)
TOP VIEW
TOP VIEW
MR
Q0
1
2
3
4
5
6
7
8
16 V
CC
MR
Q0
1
2
3
4
5
6
7
8
16
V
CC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
15
14
13
12
11
10
9
Q5
D5
D4
Q4
D3
Q3
CP
D0
D0
D1
D1
Q1
Q1
D2
D2
Q2
Q2
GND
9
CP
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
ACS174MS
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
SPECIAL INSTRUCTIONS
METALLIZATION: AI
Bond V
First
ADDITIONAL INFORMATION:
CC
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
5
2
Worst Case Current Density: <2.0 x 10 A/cm
Transistor Count: 358
SUBSTRATE POTENTIAL
Unbiased Insulator
Metallization Mask Layout
ACS174MSX
Q0
(2)
MR
(1)
V
(16)
Q5
(15)
CC
(14) D5
(13) D4
(12) Q4
(11) D3
D0 (3)
D1 (4)
Q1 (5)
D2 (6)
(7)
Q2
(8)
(9)
(10)
Q3
GND
CP
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out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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2
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