ACTS541K/SAMPLE-02-T

更新时间:2024-09-18 18:09:59
品牌:RENESAS
描述:ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20

ACTS541K/SAMPLE-02-T 概述

ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20 总线驱动器/收发器

ACTS541K/SAMPLE-02-T 规格参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.04
其他特性:WITH DUAL OUTPUT ENABLE系列:ACT
JESD-30 代码:R-CDFP-F20逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装形状:RECTANGULAR
封装形式:FLATPACK传播延迟(tpd):21 ns
认证状态:Not Qualified最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
端子形式:FLAT端子位置:DUAL
Base Number Matches:1

ACTS541K/SAMPLE-02-T 数据手册

通过下载ACTS541K/SAMPLE-02-T数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。

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ACTS541T  
Semiconductor  
Data Sheet  
January 1999  
File Number 4612  
Radiation Hardened Octal Three-State  
Buffer/Line Driver  
Features  
• QML Class T, Per MIL-PRF-38535  
Harris’ Satellite Applications FlowTM (SAF) devices are fully  
tested and guaranteed to 100kRAD total dose. These QML  
Class T devices are processed to a standard flow intended  
to meet the cost and shorter lead-time needs of large  
volume satellite manufacturers, while maintaining a high  
level of reliability.  
• Radiation Performance  
5
- Gamma Dose (γ) 1 x 10 RAD(Si)  
- Latch-Up Free Under Any Conditions  
-10  
- Single Event Upset (SEU) Immunity: <1 x 10  
Errors/Bit/Day (Typ)  
2
- SEU LET Threshold . . . . . . . . . . . . .>100 MEV-cm /mg  
• 1.25 Micron Radiation Hardened SOS CMOS  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range. . . . . . . . . . . . 4.5V to 5.5V  
• Input Logic Levels  
The Harris ACTS541T is a Radiation Hardened Octal  
Buffer/Line Driver, with three-state outputs. The output  
enable pins OE1, OE2 control the three-state outputs. If  
either enable is high the output will be in a high impedance  
state. For data output both enables must be low.  
Specifications  
- V = 0.8V Max  
IL  
- V = VCC/2 Min  
IH  
Specifications for Rad Hard QML devices are controlled by  
the Defense Supply Center in Columbus (DSCC). The SMD  
numbers listed below must be used when ordering.  
• Fast Propagation Delay . . . . . . . . 21ns (Max), 14ns (Typ)  
Pinouts  
Detailed Electrical Specifications for the ACTS541T are  
contained in SMD 5962-96726. A “hot-link” is provided from  
our website for downloading.  
ACTS541T (SBDIP), CDIP2-T20  
TOP VIEW  
http://www.semi.harris.com/families/smdrh.htm  
1
2
3
4
5
6
7
8
9
V
OE1  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
20  
19  
CC  
Harris’ Quality Management Plan (QM Plan), listing all Class  
T screening operations, is also available on our website.  
http://www.semi.harris.com/quality/manuals.htm  
OE2  
18 Y0  
17 Y1  
16 Y2  
15 Y3  
14 Y4  
13 Y5  
Ordering Information  
TEMP.  
ORDERING  
NUMBER  
PART  
NUMBER  
RANGE  
o
( C)  
12  
Y6  
5962R9672602TRC  
ACTS541D/Sample-02  
5962R9672602TXC  
ACTS541K/Sample-02  
ACTS541DTR-02  
-55 to 125  
25  
GND 10  
11 Y7  
ACTS541D/Sample-02  
ACTS541KTR-02  
-55 to 125  
25  
ACTS541T (FLATPACK), CDFP4-F20  
TOP VIEW  
ACTS541K/Sample-02  
V
OE1  
A0  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
NOTE: Minimum order quantity for -T is 1000 units  
Orders must be placed through Harris Sales or Rep Offices.  
CC  
OE2  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
Y6  
Y7  
GND  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-800-4-HARRIS | Copyright © Harris Corporation 1999  
1
Satellite Applications Flow™ (SAF) is a trademark of Harris Corporation.  
ACTS541T  
Functional Diagram  
V
CC  
2
18  
17  
16  
15  
A0  
Y0  
Y1  
Y2  
Y3  
1
OE1  
GND  
19  
V
OE2  
CC  
3
A1  
GND  
V
CC  
4
A2  
GND  
V
CC  
5
A3  
GND  
V
CC  
6
14  
13  
A4  
Y4  
Y5  
GND  
V
CC  
7
A5  
GND  
V
CC  
8
12  
11  
A6  
Y6  
Y7  
GND  
V
CC  
9
GND V  
10  
A7  
CC  
20  
GND  
TRUTH TABLE  
INPUTS  
OUTPUTS  
OE1  
L
OE2  
L
An  
H
L
Yn  
H
L
L
L
H
X
X
Z
X
H
X
Z
NOTE: L = Low Logic Level, H = High Logic Level, Z = High Impedance.  
2
ACTS541T  
Die Characteristics  
DIE DIMENSIONS:  
PASSIVATION:  
Type: Silox (S O )  
(2600µm x 2600µm x 533µm ±51µm)  
102 x 102 x 21mils ±2mil  
i
2
Thickness: 8.0kÅ ±1.0kÅ  
METALLIZATION:  
Type: Al Si Cu  
WORST CASE CURRENT DENSITY:  
2
< 2.0e5 A/cm  
Thickness: 10.0kÅ ±2kÅ  
TRANSISTOR COUNT:  
SUBSTRATE POTENTIAL:  
182  
Unbiased (Silicon on Sapphire)  
PROCESS:  
Bond Pad #20 (V ) First  
CC  
CMOS SOS  
BACKSIDE FINISH:  
Sapphire  
Metallization Mask Layout  
ACTS541T  
(17) Y1  
A2 (4)  
A3 (5)  
NC  
(16) Y2  
NC  
NC  
NC  
A4 (6)  
A5 (7)  
(15) Y3  
(14) Y4  
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time  
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate  
and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may  
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.  
For information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS or see web site http://www.semi.harris.com  
3

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