CD40160BDMSR [RENESAS]
SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16, BRAZE SEALED, DIP-16;
| 型号： | CD40160BDMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16, BRAZE SEALED, DIP-16 CD 逻辑集成电路 触发器 |
| 文件： | 总13页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD40160BMS, CD40161BMS, CD40162BMS,
CD40163BMS
December 1992
File Number 3358
CMOS Synchronous Programmable 4-Bit
Counters
Features
• High-Voltage Types (20V Rating)
• CD40160BMS Decade with Asynchronous Clear
• CD40161BMS Binary with Asynchronous Clear
• CD40162BMS Decade with Synchronous Clear
• CD40163BMS Binary with Synchronous Clear
• Internal Look-Ahead for Fast Counting
CD40160BMS,
CD40161BMS,
CD40162BMS
and
CD40163BMS are 4-bit synchronous programmable
counters. The CLEAR function of the CD40162BMS and
CD40163BMS is synchronous and a low level at the CLEAR
input sets all four outputs low on the next positive CLOCK
edge. The CLEAR function of the CD40160BMS and
CD40161BMS is asychronous and a low level at the CLEAR
input sets all four outputs low regardless of the state of the
CLOCK, LOAD, or ENABLE inputs. A low level at the LOAD
input disables the counter and causes the output to agree
with the setup data after the next CLOCK pulse regardless of
the conditions of the ENABLE inputs.
• Carry Output for Cascading
• Synchronously Programmable
• Clear Asynchronous Input (CD40160BMS, CD40161BMS)
• Clear Synchronous Input (CD40162BMS, CD40163BMS)
• Synchronous Load Control Input
• Low Power TTL Compatibility
The carry look-ahead circuitry provides for cascading counters
for n-bit synchronous applications without additional gating.
Instrumental in accomplishing this function are two count-enable
inputs and a carry output (COUT). Counting is enabled when
both PE and TE inputs are high. The TE input is fed forward to
enable COUT. This enabled output produces a positive output
pulses with a duration approximately equal to the positive portion
of the Q1 output. This positive overflow carry pulse can be used
to enable successive cascaded stages. Logic transitions at the
PE or TE inputs may occur when the clock is either high or low.
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package
o
Temperature Range; 100nA at 18V and +25 C
• Noise Margin (Over Full Package Temperature Range):
-
-
-
1V at VDD = 5V
2V at VDD = 10V
2.5V at VDD = 15V
The CD40160BMS through CD40163BMS types are functionally
equivalent to and pin-compatible with the TTL counter series
74LS160 through 74LS163 respectively.
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series CMOS
Devices”
The CD40160BMS, CD40161BMS, CD40162BMS and
CD40163BMS are supplied in these 16 lead outline packages:
Applications
• Programmable Binary and Decade Counting
CD40160 CD40161 CD40162 CD40163
Braze Seal DIP
Frit Seal DIP
H4W
H1F
H6P
H4X
H1F
H6W
H4X
H1L
H6P
H4W
H1F
• Counter Control/Timers
• Frequency Dividing
Ceramic Flatpack
H6W
Pinout
Functional Diagram
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TOP VIEW
7
10
1
14
13
PE
TE
Q1
Q2
CLEAR
CLOCK
P1
1
2
3
4
5
6
7
8
16 VDD
15 CARRY OUT
14 Q1
CLEAR
LOAD
CLOCK
P1
9
12
2
Q3
Q4
P2
13 Q2
3
P3
12 Q3
11
15
4
P2
P4
11 Q4
5
P3
10 TE
PE
6
VDD = 16
VSS = 8
CARRY
OUT
P4
9
LOAD
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
4-1
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . .-0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance. . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . .
Flatpack Package. . . . . . . . . . . . . . . .
θ
θ
jc
ja
o
o
80 C/W
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
70 C/W
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For T = -55 C to +100 C (Package Type D, F, K). . . . . . .500mW
A
o
o
For T = +100 C to +125 C (Package Type D, F, K) . . . . . Derate
A
o
o
o
Storage Temperature Range (TSTG). . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
For T = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175 C
A
o
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
IIH
VIN = VDD or GND
VIN = VDD or GND
VDD = 15V, No Load
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C 14.95
o
-
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VDD = 5V, VOUT = 0.4V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
1
+25 C
-
o
1
+25 C
-
o
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
VDD = 5V, VOUT = 2.5V
1
+25 C
-
o
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
1
+25 C
-
o
1
1
+25 C
-
o
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
VIH
+25 C, +125 C, -55 C
-
3.5
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
o
o
o
Input Voltage High
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
NOTES: 1. All voltages referenced to device GND, 100% testing being im- 3. For accuracy, voltage is measured differentially to VDD. Limit is
plemented.
0.050V max.
2. Go/No Go test with limits applied to inputs.
4-2
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS (NOTE 1, 2)
MAX
400
540
450
608
250
338
500
675
UNITS
ns
o
Propagation Delay
Clock to Q
TPHL1
TPLH1
VDD = 5V, VIN = VDD or GND
9
10, 11
9
+25 C
o
-
-
-
-
-
-
-
-
o
+125 C, -55 C
ns
o
Propagation Delay
Clock to COut
TPHL2
TPLH2
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Propagation Delay
TE to COut
TPHL3
TPLH3
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Propagation Delay
CD40160BMS,
CD40161BMS Clear to Q
TPHL4
+25 C
ns
o
o
10, 11
+125 C, -55 C
ns
o
Transition Time
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
9
+25 C
o
-
-
200
ns
ns
o
10, 11
9
+125 C, -55 C
270
o
Maximum Clock Input Fre-
quency
FCL
+25 C
2
-
-
MHz
MHz
o
o
10, 11
+125 C, -55 C
1.48
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C, -
mV
o
55 C
o
o
+25 C, +125 C, -
-
50
-
mV
V
o
55 C
o
o
+25 C, +125 C, -
4.95
9.95
o
55 C
o
o
+25 C, +125 C, -
-
V
o
55 C
o
+125 C
0.36
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
o
-55 C
0.64
-
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
IOH5A
IOH5B
IOH10
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
+125 C
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
o
-55 C
o
+125 C
o
-55 C
o
+125 C
o
-55 C
4-3
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MAX
-2.4
-4.2
3
UNITS
mA
o
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125 C
-
-
-
o
-55 C
mA
o
o
Input Voltage Low
Input Voltage High
VIL
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
1, 2
+25 C, +125 C, -
V
o
55 C
o
o
VIH
+25 C, +125 C, -
7
-
V
o
55 C
o
Propagation Delay
Clock to Q
TPHL1
TPLH1
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+25 C
-
-
-
-
-
-
-
-
160
120
190
140
110
80
ns
ns
ns
ns
ns
ns
ns
ns
o
+25 C
o
Propagation Delay
Clock to C Out
TPHL2
TPLH2
+25 C
o
+25 C
o
Propagation Delay
TE to C Out
TPHL3
TPLH3
+25 C
o
+25 C
o
Propagation Delay
CD40160BMS,
CD40161BMS Clear to Q
TPHL4
+25 C
220
160
o
+25 C
o
Transition Time
TTHL
TTLH
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+25 C
-
-
100
80
ns
ns
MHz
MHz
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
o
+25 C
o
Maximum Clock Input Fre-
quency
FCL
+25 C
5.5
8
-
-
o
+25 C
-
o
Maximum Clock Rise or
Fall Time
TRCL
TFCL
+25 C
200
70
o
+25 C
-
o
+25 C
-
15
o
Minimum Data Hold Time
Clock Operation
TH
TW
TS
TS
TS
TW
TS
+25 C
-
0
o
+25 C
-
0
o
+25 C
-
0
o
Minimum Clock Pulse
Width
Clock Operation
+25 C
-
170
70
o
+25 C
-
o
+25 C
-
50
o
Minimum Setup Time
Data to Clock
+25 C
-
240
90
o
+25 C
-
o
+25 C
-
60
o
Minimum Setup Time
Load to Clock
+25 C
-
240
90
o
+25 C
-
o
+25 C
-
60
o
Minimum Setup Time PE
to TE to Clock
+25 C
-
340
140
100
170
70
o
+25 C
-
o
+25 C
-
o
Minimum Clear Pulse
Width (CD40160BMS,
CD40161BMS)
+25 C
-
o
+25 C
-
o
+25 C
-
50
o
Minimum Setup Time
Clear to Clock
(CD40162BMS,
CD40163BMS)
+25 C
-
340
140
100
o
+25 C
-
o
+25 C
-
o
Minimum Hold Time
Clear to Clock
(CD40162BMS,
CD40163BMS)
TH
VDD = 5V
VDD = 10V
VDD = 15V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C
-
-
-
0
0
0
ns
ns
ns
o
+25 C
o
+25 C
4-4
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS
VDD = 5V
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
TEMPERATURE
MAX
200
100
70
UNITS
ns
o
Minimum Clear Removal
Time
(CD40160BMS,
CD40161BMS)
TREM
+25 C
-
-
-
o
VDD = 10V
VDD = 15V
+25 C
ns
o
+25 C
ns
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of
the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES
1, 4
1, 4
1, 4
1, 4
1, 4
1
TEMPERATURE
MIN
MAX
25
UNITS
o
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
N Threshold Voltage Delta
P Threshold Voltage
P Threshold Voltage Delta
Functional
VNTH
∆VTN
VTP
+25 C
-0.2
±1
o
+25 C
V
o
+25 C
0.2
-
2.8
±1
V
o
∆VTP
F
+25 C
V
o
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
o
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
4-5
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1 Note 1
Static Burn-In 2 Note 1
Dynamic Burn-In Note 1
Irradiation Note 2
NOTE:
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
11 - 15
11 - 15
-
1 - 10
16
8
8
8
1 - 7, 9, 10, 16
1, 7, 9, 10, 16
1 - 7, 9, 10, 16
11 - 15
2 - 6
-
11 - 15
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagrams
CD40160BMS AND CD40162BMS BCD DECADE COUNTERS
*
7
*
10
*
3
*
4
*
5
*
16
*
6
CD40160BMS
ASYNCHRONOUS
CLEAR
PE
TE
P1
P2
P3
VDD
Q1
P4
Q1
Q4
Q1
Q4
LOAD*
9
CLOCK*
2
CLEAR*
1
Q1
CD40162BMS
SYNCHRONOUS
CLEAR
LOAD*
LD PI
T
LD PI
T
LD PI
T
LD PI
T
Q1
Q1
Q2
Q2
Q3
Q4
9
CLOCK*
2
CL
CL
CL
CL
CLR
CLR
CLR
CLR
Q3
Q4
CLEAR*
1
VDD
*INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
14 Q1
13 Q2
12 Q3
11 Q4
15 COUT
VSS
FIGURE 1. LOGIC DIAGRAM FOR CD40160BMS AND CD40162BMS BCD DECADE COUNTERS
4-6
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
Logic Diagrams (Continued)
CD40161BMS AND CD40163BMS BINARY COUNTERS
*
7
*
10
*
3
*
4
*
5
*
6
16
CD40161BMS
ASYNCHRONOUS
CLEAR
PE
TE
P1
VDD
P2
P3
P4
Q1
Q2
Q1
Q2
Q2
Q1
LOAD*
9
CLOCK*
2
Q4
Q3
Q2
CLEAR*
1
CD40163BMS
SYNCHRONOUS
CLEAR
Q1
LOAD*
9
LD PI
T
LD PI
T
LD PI
T
LD PI
T
Q1
Q1
Q2
Q3
Q4
CLOCK*
2
CL
CLR
CL
CLR
CL
CLR
CL
CLR
Q2
Q3
Q4
CLEAR*
1
*INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VDD
14 Q1
13 Q2
12 Q3
11 Q4
15 COUT
VSS
FIGURE 2. LOGIC DIAGRAM FOR CD40161BMS AND CD40163BMS BINARY COUNTERS
TRUTH TABLE
CLOCK
CLR
LOAD
PE
X
0
TE
X
X
0
OPERATION
1
1
1
1
0
0
1
0
1
Preset
NC
1
X
1
NC
1
1
Count
X
X
X
X
X
X
X
X
X
X
Reset (CD40160BMS, CD40161BMS)
Reset (CD40162BMS, CD40163BMS)
NC (CD40162BMS, CD40163BMS)
1 = High Level
0 = Low Level
X = Don’t Care
NC = No Change
4-7
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
Typical Performance Characteristics
o
o
AMBIENT TEMPERATURE (T ) = +25 C
AMBIENT TEMPERATURE (T ) = +25 C
A
A
15.0
12.5
10.0
7.5
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 4. MIMIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
o
-5
0
-15
-10
o
-5
0
0
0
AMBIENT TEMPERATURE (T ) = +25 C
AMBIENT TEMPERATURE (T ) = +25 C
A
A
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
-5
-10V
-10V
-10
-15
-10
-15
-15V
-15V
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
o
AMBIENT TEMPERATURE (T ) = +25 C
A
o
AMBIENT TEMPERATURE (T ) = +25 C
A
300
200
150
100
50
SUPPLY VOLTAGE (VDD) = 5V
200
SUPPLY VOLTAGE (VDD) = 5V
10V
10V
15V
100
15V
0
0
20
40
60
80
100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNC-
TION OF LOAD CAPACITANCE (CLOCK TO Q)
FIGURE 8. TYPICAL TRANSISTION TIME AS A FUNCTION OF
LOAD CAPACITANCE
4-8
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
Typical Performance Characteristics (Continued)
5
10
8
6
AMBIENT TEMPERATURE (T )
A
o
= +25 C
4
2
4
10
SUPPLY VOLTAGE (VDD)
= 15V
8
6
4
2
10V
3
2
10
10
8
6
4
10V
5V
2
8
6
CL = 50pF
CL = 15pF
4
2
10
2
4
6 8
2
4
6 8
2
4
6 8
2
4
6 8
2
4 6 8
2
3
4
1
10
10
10
10
CLOCK FREQUENCY (fCL) (kHz)
FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY
CLEAR (CD40160BMS)
ASYNCHRONOUS
SYNCHRONOUS
CLEAR (CD40162BMS)
LOAD
P1
P2
DATA INPUTS
P3
P4
CLOCK (CD40160BMS)
CLOCK (CD40162BMS)
PE
ENABLES
TE
Q1
Q2
OUTPUTS
Q3
Q4
CARRY OUT
0
7
8
9
0
1
2
3
COUNT
INHIBIT
CLEAR PRESET
FIGURE 10. TIMING DIAGRAM FOR CD40160BMS, CD40162BMS
4-9
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
CLEAR (CD40161BMS)
ASYNCHRONOUS
SYNCHRONOUS
CLEAR (CD40163BMS)
LOAD
P1
P2
DATA INPUTS
P3
P4
CLOCK (CD40161BMS)
CLOCK (CD40163BMS)
PE
ENABLES
TE
Q1
Q2
OUTPUTS
Q3
Q4
CARRY OUT
0
12
13
14
15
0
1
2
COUNT
INHIBIT
CLEAR PRESET
FIGURE 11. TIMING DIAGRAM FOR CD40161BMS AND CD40163BMS
4-10
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TN
PN
LD
CL
CL
CLR
p
n
CL
p
n
CL
CL
p
n
p
n
CL
CL
p
n
p
n
p
n
QN
QN
CL
CL
FIGURE 12. DETAIL OF FLIP-FLOPS OF CD40160BMS AND CD40161BMS (ASYNCHRONOUS CLEAR)
TN CLR
PN
LD
CL
CL
p
n
CL
CL
CL
p
n
p
n
p
n
CL
CL
p
n
QN
QN
p
n
p
n
CL
CL
FIGURE 13. DETAIL OF FLIP-FLOPS OF CD40162BMS AND CD40163BMS (SYNCHRONOUS CLEAR)
4-11
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
LOAD
VDD
P1 P2 P3 P4
P1 P2 P3 P4
P1 P2 P3 P4
VDD
PE
TE
LD
PE
TE
LD
PE
TE
LD
CD
CD
CD
CLK CLR
CLK CLR
CLK CLR
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
CLOCK
CLEAR
FIGURE 14. CASCADED COUNTER PACKAGES IN THE PARALLEL-CLOCKED MODE
LOAD
VDD
VDD
VDD
P1 P2 P3 P4
P1 P2 P3 P4
P1 P2 P3 P4
PE
TE
LD
PE
TE
LD
PE
TE
LD
CD
CD
CD
CLK CLR
CLK CLR
CLK CLR
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
CLOCK
CLEAR
FIGURE 15. CASCADED COUNTER PACKAGES IN THE RIPPLE-CLOCKED MODE
Chip Dimensions and Pad Layout
Dimensions and pad layout for CD40160BMSH.
Dimensions and pad layout for CD40161BMS,
CD40162BMSH, and CD40163BMSH are identical.
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
-3
as indicated. Grid graduations are in mils (10 inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
4-12
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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4-13
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