CD40174BFMSR [RENESAS]
4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, FRIT SEALED, CERAMIC, DIP-16;
| 型号： | CD40174BFMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, FRIT SEALED, CERAMIC, DIP-16 CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD40174BMS
CMOS Hex ‘D’-Type Flip-Flop
December 1992
Features
Pinout
CD40174BMS
TOP VIEW
• High Voltage Type (20V Rating)
• 5V, 10V and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
CLEAR
Q1
1
2
3
4
5
6
7
8
16 VDD
15 Q6
14 D6
13 D5
12 Q5
11 D4
10 Q4
• Maximum Input Current of 1µA at 18V Over Full Pack-
D1
age Temperature Range, 100nA at 18V and +25oC
D2
• Noise Margin (Over full Package Temperature Range):
- 1V at VDD = 5V
Q2
D3
- 2V at VDD = 10V
Q3
- 2.5V at VDD = 15V
9
CLOCK
VSS
• Meets All Requirements of JEDEC Tentative Standard
No. 13A, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Functional Diagram
• Shift Registers
3
2
5
D1
Q1
Q2
• Buffer/Storage Registers
• Pattern Generators
F/F1
F/F2
4
D2
Description
CD40174BMS consists of six identical ‘D’-Type flip-flops
having independent DATA inputs. The CLOCK and CLEAR
inputs are common to all six units. Data is transferred to the
Q outputs on the positive going transition of the clock pulse.
All six flip-flops are simultaneously reset by a low level on the
CLEAR input.
6
7
D3
Q3
Q4
Q5
Q6
F/F3
F/F4
F/F5
F/F6
11
10
12
15
D4
The CD40174BMS is supplied in these 16 lead outline pack-
ages:
13
D5
Braze Seal DIP
Frit Seal DIP
H4T
H1E
14
D5
Ceramic Flatpack H6W
9
CLOCK
1
CLEAR
VSS = 8
VDD = 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3359
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1384
Specifications CD40174BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
Linearity at 12mW/ C to 200mW
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
2
200
2
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
VIN = VDD or GND
1
+25 C
-
-
-
-
100
1000
100
50
-
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL5
VIH5
VIL15
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V,
VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VIH15 VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1385
Specifications CD40174BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS (Note 1, 2)
MAX
300
405
200
270
200
270
-
UNITS
ns
o
Propagation Delay
Clock to Output
TPHL1 VDD = 5V, VIN = VDD or GND
TPLH1
9
10, 11
9
+25 C
-
o
o
+125 C, -55 C
-
ns
o
Propagation Delay
CLEAR to Output
TPHL2 VDD = 5V, VIN = VDD or GND
+25 C
-
ns
o
o
10, 11
9
+125 C, -55 C
-
-
ns
o
Transition Time
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Maximum Clock Input
Frequency
FCL
+25 C
3.5
MHz
MHz
o
o
10, 11
+125 C, -55 C 3.5/1.35
-
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
1
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
30
2
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
60
2
µA
o
o
-55 C, +25 C
µA
o
+125 C
120
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
VOH
VOH
IOL5B
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
o
-55 C
0.64
-
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
o
-55 C
o
+125 C
o
-55 C
o
IOH10
VDD = 10V, VOUT = 9.5V
+125 C
o
-55 C
7-1386
Specifications CD40174BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MAX
-2.4
-4.2
3
UNITS
mA
o
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125 C
-
-
-
o
-55 C
mA
o
o
Input Voltage Low
Input Voltage High
VIL
VDD = 10V, VOH > 9V,
VOL < 1V
1, 2
1, 2
+25 C, +125 C,
V
o
-55 C
o
o
VIH
VDD = 10V, VOH > 9V,
VOL < 1V
+25 C, +125 C,
+7
-
V
o
-55 C
o
Propagation Delay
Clock to Output
TPHL1 VDD = 10V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
+25 C
-
-
140
100
100
80
100
80
-
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
pF
pF
TPLH1
o
VDD = 15V
+25 C
o
Propagation Delay
CLEAR to Output
TPHL2 VDD = 10V
VDD = 15V
+25 C
-
o
+25 C
-
o
Transition Time
TTHL
TTLH
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
CLEAR
+25 C
-
o
+25 C
-
o
Maximum Clock Input
Frequency
FCL
TS
+25 C
6
8
-
o
+25 C
-
o
Minimum Data Setup
Time
+25 C
40
20
10
80
40
30
130
60
40
-
o
+25 C
-
o
+25 C
-
o
Minimum Data Hold Time
TH
+25 C
-
o
+25 C
-
o
+25 C
-
o
Minimum Clock Pulse
Width
TW
+25 C
-
o
+25 C
-
o
+25 C
-
o
Maximum Clock Rise and
Fall Time
TRCL
TFCL
+25 C
15
15
15
-
o
+25 C
-
o
+25 C
-
o
Minimum CLEAR
Removal Time
TREM
TW
+25 C
0
o
+25 C
-
0
o
+25 C
-
0
o
Minimum CLEAR Pulse
Width
+25 C
-
100
50
40
40
7.5
o
+25 C
-
o
+25 C
-
o
Input Capacitance
NOTES:
CIN
+25 C
-
o
All others
1, 2
+25 C
-
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
7-1387
Specifications CD40174BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
7.5
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
O
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 0.2µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Table 4
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
7-1388
Specifications CD40174BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1
(Note 1)
2, 5, 7, 10, 12, 15 1, 3, 4, 6, 8, 9, 11,
13, 14
16
Static Burn-In 2
(Note 1)
2, 5, 7, 10, 12, 15
8
8
8
1, 3, 4, 6, 9, 11,
13, 14, 16
Dynamic Burn-In
(Note 1)
-
1, 16
2, 5, 7, 10, 12, 15
9
3, 4, 6, 11, 13, 14
Irradiation
(Note 2)
2, 5, 7, 10, 12, 15
1, 3, 4, 6, 9, 11,
13, 14, 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
CL
p
CL
p
Q
VDD
D
n
n
3 (4, 6, 11, 13, 14)
CL
p
CL
p
2 (5, 7, 10, 12, 15)
CL
CL
n
n
CL
CL
VSS
CLR*
1
CL
* All inputs (terms 1, 3, 4, 6, 9, 11, 13, 14)
protected by COS/MOS protection network
CLK*
9
CL
FIGURE 1. 1 OF 6 FLIP-FLOPS
TRUTH TABLE FOR 1 OF 6 FLIP-FLOPS
INPUTS
OUTPUT
CLOCK
DATA
CLEAR
Q
0
0
1
1
1
1
0
1
X
X
NC
0
X
1 = High Level
2 = Low Level
X = Don’t Care
NC = No Change
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
1389
CD40174BMS
Typical Performance Curves
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
200
SUPPLY VOLTAGE (VDD) = 5V
150
20
15
100
50
0
10V
10V
15V
10
5
5V
0
5
10
15
0
20
40
60
80
100
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
LOAD CAPACITANCE (CL) (pF)
FIGURE 2. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
AMBIENT TEMPERATURE (TA) = +25oC
-15
-10
-5
0
0
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
-10
-15
-20
-25
-30
10.0
-10V
10V
7.5
5.0
-15V
2.5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
105
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
AMBIENT TEMPERATURE (TA) = +25oC
8
6
4
-15
-10
-5
0
0
AMBIENT TEMPERATURE (TA) = +25oC
2
SUPPLY VOLTAGE (VDD) = 15V
104
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
8
6
4
10V
-5
2
10V
103
8
5V
6
4
-10V
-10
-15
2
102
CL = 50pF
CL = 15pF
8
6
-15V
4
2
10
2
4
6
8
10
2
4
6
8
2
4
6
8
2
4
6
8
1
102
103
104
CLOCK INPUT FREQUENCY (fCL) (kHz)
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF CLOCK FREQUENCY
7-1390
CD40174BMS
Typical Performance Curves (Continued)
200
175
150
125
100
75
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
50
25
0
0
10
20
30
40
50
60
70
80
90 100
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME (CLOCK TO OUTPUT) AS A FUNCTION OF LOAD CAPACITANCE
Waveform
Pad Layout
VDD
tr CL
CLOCK
INPUT
tf CL
90%
50%
10%
0
tH(HL)*
tH(LH)*
DATA
INPUT
VDD
50%
0
tSU(HL)*
tTHL
tSU(LH)*
OUTPUT
VDD
tTLH
90%
50%
10%
0
tPLH
tREM
tPHL
*(LH) OR (HL) OPTIONAL
VDD
CLEAR
0
50%
FIGURE 9. DEFINITION OF SETUP, HOLD, PROPAGATION
DELAY, AND REMOVAL TIMES
DIMENSIONS AND PAD LAYOUT FOR CD40174BMSH
The photographs and dimensions of each CMOS chip represent a chip when
it is part of the wafer. When the wafer is separated into individual chips, the an-
gle of cleavage may vary with respect to the chip face for different chips. The
actual dimensions of the isolated chip, therefore, may differ slightly from the
nominal dimensions shown. The user should consider a tolerance of -3 mils to
+16 mils applicable to the nominal dimensions shown.
Dimension in parenthesis are in millimeters and are derived from the basic inch
dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1391
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