CD40192BFMSR [RENESAS]
4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDIP16;
| 型号： | CD40192BFMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDIP16 CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD40192BMS
CD40193BMS
CMOS Presettable Up/Down Counters
(Dual Clock With Reset)
December 1992
Features
Description
• CD40192BMS - BCD Type
• CD40193BMS - Binary Type
• High Voltage Type (20V Rating)
CD40192BMS Presettable BCD Up/Down Counter and the
CD40193BMS Presettable Binary Up/Down Counter each con-
sist of 4 synchronously clocked, gated “D” type flip-flops con-
nected as a counter. The inputs consist of 4 individual jam lines,
a PRESET ENABLE control, individual CLOCK UP and
CLOCK DOWN signals and a master RESET. Four buffered Q
signal outputs as well as CARRY and BORROW outputs for
multiple-stage counting schemes are provided.
• Individual Clock Lines for Counting Up or Counting
Down
• Synchronous High-Speed Carry and Borrow Propaga-
tion Delays for Cascading
The counter is cleared so that all outputs are in a low state by a
high on the RESET line. A RESET is accomplished asynchro-
nously with the clock. Each output is individually programmable
asynchronously with the clock to the level on the corresponding
jam input when the PRESET ENABLE control is low.
• Asynchronous Reset and Preset Capability
• Medium Speed Operation
- fCL = 8MHz (typ.) at 10V
• 5V, 10V and 15V Parametric Ratings
• Standardize Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
The counter counts up one count on the positive clock edge of
the CLOCK UP signal provided the CLOCK DOWN line is high.
The counter counts down one count on the positive clock edge
of the CLOCK DOWN signal provided the CLOCK UP line is
high.
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
The CARRY and BORROW signals are high when the counter
is counting up or down. The CARRY signal goes low one-half
clock cycle after the counter reaches its maximum count in the
count-up mode. The BORROW signal goes low one-half clock
cycle after the counter reaches its minimum count in the count-
down mode. Cascading of multiple packages is easily accom-
plished without the need for additional external circuitry by tying
the BORROW and CARRY outputs to the CLOCK DOWN and
CLOCK UP inputs, respectively, of the succeeding counter
package.
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Up/Down Difference Counting
• Multistage Ripple Counting
• Synchronous Frequency Dividers
• A/D and D/A Conversion
The CD40192BMS and CD40193BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
*H4W, †H4X
H1F
Ceramic Flatpack
* CD40192B Only
*H6P,
†CD40193B Only
†H6W
• Programmable Binary or BCD Counting
Functional Diagram
Pinout
CD40192BMS, CD40193BMS
PRESET
ENABLE
TOP VIEW
11
15
J1
3
2
J2
Q2
Q1
1
2
3
4
5
6
7
8
16 VDD
Q1
1
Q2
15 J1
J2
6
10
Q3
14 RESET
13 BORROW
12 CARRY
11 PRESET ENABLE
10 J3
J3
7
9
Q4
J4
CLOCK DOWN
CLOCK UP
13
12
5
CLOCK UP
4
BORROW
CARRY
CLOCK DOWN
Q3
Q4
14
VDD = 16
VSS = 8
RESET
9
J4
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3363
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1419
Specifications CD40192BMS, CD40193BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For T = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
A
o
o
For T = +100 C to +125 C (Package Type D, F, K). . . . . .Derate
A
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
For T = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
A
o
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20V
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20V
3
-55 C
-100
-
o
IIH
VIN = VDD or GND
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
VIH
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1420
Specifications CD40192BMS, CD40193BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS (NOTES 1, 2)
SUBGROUPS TEMPERATURE
MIN
MAX
500
UNITS
ns
o
Propagation Delay
Clock Up or Clock Down
to Q
TPHL1 VDD = 5V, VIN = VDD or GND
TPLH1
9
+25 C
-
-
o
o
10, 11
+125 C, -55 C
675
ns
o
Propagation Delay
Reset to Q
TPHL2 VDD = 5V, VIN = VDD or GND
9
+25 C
-
-
-
-
-
-
500
675
400
540
320
432
ns
ns
ns
ns
ns
ns
o
o
10, 11
9
+125 C, -55 C
o
Propagation Delay
PE to Q
TPHL3 VDD = 5V, VIN = VDD or GND
TPLH3
+25 C
o
o
10, 11
9
+125 C, -55 C
o
Propagation Delay
Clock Up to Carry, Clock
Down to Borrow
TPHL4 VDD = 5V, VIN = VDD or GND
TPLH4
+25 C
o
o
10, 11
+125 C, -55 C
o
Propagation Delay
PE to Borrow or Carry
TPHL5 VDD = 5V, VIN = VDD or GND
TPLH5
9
10, 11
9
+25 C
-
600
810
600
810
200
270
-
ns
ns
o
o
+125 C, -55 C
-
o
Propagation Delay
Reset to Borrow or Carry TPLH6
TPHL6 VDD = 5V, VIN = VDD or GND
+25 C
-
ns
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Transition Time
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
+25 C
-
-
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Maximum Clock Input
Frequency
FCL
+25 C
2
MHz
MHz
o
o
10, 11
+125 C, -55 C
1.48
-
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
0.64
0.9
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
o
-55 C
o
Output Current (Sink)
Output Current (Sink)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
+125 C
o
-55 C
1.6
o
+125 C
2.4
o
-55 C
4.2
7-1421
Specifications CD40192BMS, CD40193BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MAX
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
3
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
V
o
Output Current (Source)
IOH5A VDD = 5V, VOUT = 4.6V
1, 2
+125 C
-
-
-
-
-
-
-
-
-
o
-55 C
o
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOH5B VDD = 5V, VOUT = 2.5V
1, 2
1, 2
1, 2
+125 C
o
-55 C
o
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
+125 C
o
-55 C
o
+125 C
o
-55 C
o
o
Input Voltage Low
Input Voltage High
VIL
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
1, 2
+25 C, +125 C,
o
-55 C
o
o
VIH
+25 C, +125 C,
7
-
V
o
-55 C
o
Propagation Delay
Clock Up or Down to Q
TPHL1 VDD = 10V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+25 C
-
-
-
-
-
-
-
-
240
180
240
180
200
140
160
120
ns
ns
ns
ns
ns
ns
ns
ns
TPLH1
o
VDD = 15V
+25 C
o
Propagation Delay
Reset to Q
TPHL2 VDD = 10V
VDD = 15V
+25 C
o
+25 C
o
Propagation Delay
PE to Q
TPHL3 VDD = 10V
+25 C
TPLH3
o
VDD = 15V
+25 C
o
Propagation Delay
Clock Up to Carry, Clock
Down to Borrow
TPHL4 VDD = 10V
+25 C
TPLH4
o
VDD = 15V
+25 C
o
Propagation Delay
PE to Borrow or Carry
TPHL5 VDD = 10V
1, 2, 3
1, 2, 3
+25 C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
300
220
300
220
100
80
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPLH5
o
VDD = 15V
+25 C
o
Propagation Delay
Reset to Borrow or Carry
TPHL6 VDD = 10V
1, 2, 3
+25 C
TPLH6
o
VDD = 15V
1, 2, 3
+25 C
o
Transition Time
TTHL1 VDD = 10V
1, 2, 3
+25 C
TTLH1
o
VDD = 15V
1, 2, 3
+25 C
o
Maximum Clock Rise and
Fall Time
TRCL
TFCL
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 5
1, 2, 3, 5
1, 2, 3, 5
1, 2, 3
+25 C
15
o
+25 C
15
o
+25 C
5
o
Minimum Removal Time
Reset or PE
TREM
TW
+25 C
80
o
+25 C
40
o
+25 C
30
o
Minimum Pulse Width
Reset
+25 C
480
300
260
240
170
140
o
1, 2, 3
+25 C
o
1, 2, 3
+25 C
o
Minimum Pulse Width PE
TW
1, 2, 3
+25 C
o
1, 2, 3
+25 C
o
1, 2, 3
+25 C
7-1422
Specifications CD40192BMS, CD40193BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
VDD = 5V
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
MIN
MAX
180
90
UNITS
ns
o
Minimum Clock Pulse
Width
TW
+25 C
-
-
-
-
-
o
VDD = 10V
VDD = 15V
Reset
+25 C
ns
o
+25 C
60
ns
o
Input Capacitance
Input Capacitance
NOTES:
CIN
CIN
+25 C
15
pF
o
All Other Inputs
1, 2
+25 C
7.5
pF
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
5. The time required for RESET or PRESET ENABLE control to be removed before clocking. See timing diagram defining TREM.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
o
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
7-1423
Specifications CD40192BMS, CD40193BMS
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
PART NUMBER CD40192BMS, CD40193BMS
Static Burn-In 1 2, 3, 6, 7, 12, 13 1, 4, 5, 8 - 11, 14,
16
(Note 1)
15
Static Burn-In 2 2, 3, 6, 7, 12, 13
(Note 1)
8
1, 4, 5, 9 - 11,
14 - 16
Dynamic Burn-
In (Note 1)
-
8, 14
8
1, 5, 9 - 11, 15, 16 2, 3, 6, 7, 12, 13
4
-
Irradiation
(Note 2)
2, 3, 6, 7, 12, 13
1, 4, 5, 9 - 11,
14 - 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
7-1424
CD40192BMS, CD40193BMS
Logic Diagrams
*RESET
14
*PE
11
S1
*J1
15
R1
S2
S3
R3
S4
R4
R2
**
**
**
1
10
9
*J2
*J3
*J4
CONTROL LOGIC 1
**SAME AS CONTROL LOGIC 1
CARRY
12
S1
S
S2
S
S3
S4
S
*CLOCK UP
5
S
Q1
Q1
Q2
Q2
Q3
Q4
Q4
CL
CL
CL
CL
Q3
R
4
R
R
R
*CLOCK DOWN
R1
R2
R3
R4
13
BORROW
VDD
3
2
6
7
Q1
Q2
Q3
Q4
*ALL INPUTS PROTECTED BY
COS/MOS PROTECTION NETWORK
VSS
FIGURE 1. CD40192BMS LOGIC DIAGRAM (BCD)
7-1425
CD40192BMS, CD40193BMS
Logic Diagrams (Continued)
*RESET
14
*PE
11
S1
*J1
15
R1
S2
S3
R3
S4
R4
R2
**
**
**
1
10
9
*J2
*J3
*J4
CONTROL LOGIC 1
**SAME AS CONTROL LOGIC 1
VSS
CARRY
12
VDD
S1
S2
S
S3
S4
S
*CLOCK UP
S
R
S
5
Q1
Q1
Q2
Q2
Q3
Q4
Q4
CL
CL
CL
CL
Q3
R
4
R
R
*CLOCK DOWN
R1
R2
R3
R4
13
BORROW
VDD
VDD
VDD
3
2
6
7
Q1
Q2
Q3
Q4
*ALL INPUTS PROTECTED BY
COS/MOS PROTECTION NETWORK
VSS
FIGURE 2. CD40193BMS LOGIC DIAGRAM (BINARY)
7-1426
CD40192BMS, CD40193BMS
CL
CL
CL
R
CL
S
CL
p
n
p
n
Q
S
R
R
Q
Q
S
CL
=
CL
CL
CL
CL
p
n
p
n
Q
CL
CL
FIGURE 3. INTERNAL LOGIC OF FLIP-FLOP
TRUTH TABLE
CLOCK UP
CLOCK DOWN
PRESET ENABLE
RESET
ACTION
1
1
1
0
0
0
0
0
1
Count Up
No Count
Count Down
No Count
Preset
1
1
1
1
1
X
X
X
X
0
X
Reset
1 = High Level
0 = Low Level
X = Don’t Care
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
12.5
10.0
7.5
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 5. MIMIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
7-1427
CD40192BMS, CD40193BMS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15 -10 -5
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
0
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
15.0
12.5
10.0
7.5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
-5
-10V
10V
-10
-15
5.0
-15V
2.5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
400
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
350
300
SUPPLY VOLTAGE (VDD) = 5V
200
250
200
SUPPLY VOLTAGE (VDD) = 5V
150
150
10V
100
10V
15V
100
50
15V
50
0
0
20
40
60
80
100
0
10
20
30
40
50
60
70
80
90 100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
106
AMBIENT TEMPERATURE (TA) = +25oC
8
6
4
CL = 50pF
CL = 15pF
2
105
104
103
8
6
4
2
8
6
4
2
8
6
4
2
102
2
4
6 8
104
2
4
6 8
2
4 6 8
2
4 6 8
2
4 6 8
1
10
102
103
105
INPUT FREQUENCY (fIN) (kHz)
FIGURE 10. DYNAMIC POWER DISSIPATION
7-1428
CD40192BMS, CD40193BMS
1
0
RESET
1
RESET
0
1
0
1
PE
J1
PE
0
1
J1
0
1
0
1
J2
J3
J4
1
0
J2
0
1
J3
0
1
0
1
J4
0
1
0
CLK
UP
CLK
UP
1
0
1
0
CLK
DN
CLK
DN
1
0
1
0
1
0
Q1
Q1
Q2
1
0
1
0
Q2
Q3
Q4
1
0
1
0
1
0
Q3
1
0
1
0
Q4
1
0
CARRY
1
0
CARRY
1
0
BORROW
COUNT
1
0
BORROW
COUNT
0
13 14 15 0
1
2
1 0 15 14 13
0
7
8
9
0
1
2
1
0
9
8
7
FIGURE 11. CD40192BMS TIMING DIAGRAM
FIGURE 12. CD40193BMS TIMING DIAGRAM
tWH
tWL
CLOCK
RESET
PRESET ENABLE
trem*
*RESET OR PRESET ENABLE
REMOVAL TIME
FIGURE 13. TIMING DIAGRAM DEFINING trem
J1 J2 J3 J4
J1 J2 J3 J4
CARRY
CLOCK UP
CLOCK UP
CARRY
CD40192BMS
CD40192BMS
OR
OR
BORROW CLOCK DOWN
CD40193BMS
CD40193BMS
CLOCK DOWN
BORROW
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
RESET
PRESET
ENABLE
FIGURE 14. CASCADED COUNTER PACKAGES
7-1429
CD40192BMS, CD40193BMS
Chip Dimensions and Pad Layout
Dimensions and pad layout for the CD40192BMSH
(dimensions and pad layout for the CD40193BMSH
are identical).
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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FAX: (321) 724-7240
1430
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