CD4035BDMSR [RENESAS]
4000/14000/40000 SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, CONFIGURABLE OUTPUT, CDIP16, BRAZE SEALED, DIP-16;
| 型号： | CD4035BDMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4000/14000/40000 SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, CONFIGURABLE OUTPUT, CDIP16, BRAZE SEALED, DIP-16 CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4035BMS
CMOS 4 -Stage Parallel
In/Parallel Out Shift Register
December 1992
Features
Description
• J - K Serial Inputs and True/Complement Outputs
• High Voltage Type (20V Rating)
CD4035BMS is a four stage clocked signal serial register
with provision for synchronous PARALLEL inputs to each
stage and SERIAL inputs to the first stage via JK logic. Reg-
ister stages 2, 3, and 4 are coupled in a serial D flip-flop con-
figuration when the register is in the serial mode
(PARALLEL/SERIAL control low).
• 4-Stage Clocked Shift Operation
• Synchronous Parallel Entry on All 4 Stages
• JK Inputs on First Stage
Parallel entry into each register stage is permitted when the
PARALLEL/SERIAL control is high.
• Asynchronous True/Complement Control on All Out-
puts
In the parallel or serial mode information is transferred on
positive clock transitions.
• Static Flip-Flop Operation; Master-Slave Configura-
tion
When the TRUE/COMPLEMENT control is high, the true
contents of the register are available at the output terminals.
When the TRUE/COMPLEMENT control is low, the outputs
are the complements of the data in the register. The TRUE/
COMPLEMENT control functions asynchronously with
respect to the CLOCK signal.
• Buffered Inputs and Outputs
• High Speed Operation 12MHz (Typ) at VDD = 10V
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
JK input logic is provided on the first stage SERIAL input to
minimize logic requirements particularly in counting and
sequence-generation applications. With JK inputs connected
together, the first stage becomes a D flip-flop. An asynchro-
nous common, RESET is also provided.
• Meets All Requirements of JEDEC Tentative Standard
Number 13A, “Standard Specifications for Description
of ‘B’ Series CMOS Devices”
Applications
The CD4035BMS series type is supplied in these 16 lead
outline packages
• Counters, Registers
Braze Seal DIP
Frit Seal DIP
H4T
H1F
- Arithmetic-Unit Registers
- Shift Left/Shift Right Registers
- Serial-to-Parallel/Parallel-to-Serial Conversions
Ceramic Flatpack H6W
• Sequence Generation
• Control Circuits
• Code Conversion
Functional Diagram
Pinout
FIRST STAGE TRUTH TABLE
CD4035BMS
TOP VIEW
PARALLEL IN
tn
tn-1 (INPUT)
(OUTPUT)
1
2
3
4
9
10
11
12
CL
J
0
1
X
1
K
X
X
0
R
0
0
0
0
Qn-1
Qn
0
4
3
6
7
2
5
Q1/Q1
1
2
3
4
5
6
7
8
16 VDD
15 Q2/Q2
14 Q3/Q3
13 Q4/Q4
12 PI-4
J
0
0
SER
IN
TRUE/
COMP.
K
1
CLK
P/S
K
J
4-STAGE REGISTER
1
0
0
Qn-1
Qn-1
Toggle
Mode
T/C
RESET
CLOCK
P/S
RESET
11 PI-3
1
15
14
13
X
X
X
1
X
X
0
0
1
1
Qn-1
X
1
Qn-1
0
VDD = 16
VSS = 8
10 PI-2
Q1/Q1 Q2/Q2 Q3/Q3 Q4/Q4
T/C OUT
9
PI-1
VSS
X
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3308
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-851
Specifications CD4035BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
VIN = VDD or GND
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
VIH
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-852
Specifications CD4035BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS (NOTE 1, 2)
MAX
500
675
460
621
200
270
-
UNITS
ns
o
Propagation Delay
Clock to Q
TPHL1 VDD = 5V, VIN = VDD or GND
TPLH1
9
10, 11
9
+25 C
-
o
o
+125 C, -55 C
-
ns
o
Propagation Delay
Reset to Q
TPHL2 VDD = 5V, VIN = VDD or GND
TPLH2
+25 C
-
ns
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Transition Time
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
+25 C
-
-
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Maximum Clock Input
Frequency
FCL
VDD = 5V, VIN = VDD or GND
+25 C
2
MHz
MHz
o
o
10, 11
+125 C, -55 C
1.48
-
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
o
-55 C
0.64
-
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Input Voltage Low
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-
o
-55 C
o
+125 C
o
-55 C
o
IOH10
IOH15
VIL
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
VDD = 10V, VOH > 9V, VOL < 1V
+125 C
o
-55 C
o
+125 C
o
-55 C
o
o
+25 C, +125 C,
3
o
-55 C
7-853
Specifications CD4035BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
o
o
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25 C, +125 C,
7
-
V
o
-55 C
o
Propagation Delay
Clock to Q
TPHL1 VDD = 10V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
+25 C
-
-
-
-
-
-
-
-
-
6
8
-
-
-
-
-
-
-
-
-
-
-
-
-
200
150
200
160
100
80
ns
ns
TPLH1
o
VDD = 15V
+25 C
o
Propagation Delay
Reset tO Q
TPHL2 VDD = 10V
+25 C
ns
TPLH2
o
VDD = 15V
+25 C
ns
o
Transition Time
TTHL
TTLH
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
+25 C
ns
o
+25 C
ns
o
Minimum Reset Pulse
Width
TW
+25 C
250
110
40
ns
o
+25 C
ns
o
+25 C
ns
o
Maximum Clock Input
Frequency
FCL
+25 C
-
MHz
MHz
µs
µs
µs
ns
o
+25 C
-
o
Maximum Clock Rise and
Fall Time (Note 4)
TRCL
TFCL
+25 C
15
o
+25 C
15
o
+25 C
15
o
Minimum Data Setup
Time
J/K Lines
TS
TS
+25 C
220
80
o
+25 C
ns
o
+25 C
60
ns
o
Minimum Data Setup
Time
Parallel-In Lines
+25 C
140
50
ns
o
+25 C
ns
o
+25 C
40
ns
o
Minimum Clock Pulse
Width
TW
CIN
+25 C
200
90
ns
o
+25 C
ns
o
+25 C
60
ns
o
Input Capacitance
NOTES:
+25 C
7.5
pF
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, tRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
7-854
Specifications CD4035BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Functional
SYMBOL
CONDITIONS
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES
TEMPERATURE
MIN
MAX
UNITS
o
F
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
O
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
NOTE:
1, 2, 3, 8A, 8B, 9
1. 5% parametric, 3% functional; cumulative for static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
CONFORMANCE GROUPS
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1
Note 1
1, 13 - 15
2 - 12
16
Static Burn-In 2
Note 1
1, 13 - 15
1, 3, 4
8
2, 5, 7 - 12
8
2 - 7, 9 - 12, 16
16
Dynamic Burn-
In Note 1
13 - 15
6
-
Irradiation
Note 2
1, 13 - 15
2 - 7, 9 - 12, 16
7-855
Specifications CD4035BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
50kHz 25kHz
FUNCTION
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
OPEN
GROUND
VDD
9V ± -0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
Logic Diagram
*
9
*
10
*
12
*
11
*ALL INPUTS PROTECTED
BY CMOS INPUT
PROTECTION NETWORK
*
4
VDD
J
*
3
K
P
P
P
P
D
R
Q
Q
D
R
Q
Q
D
R
Q
Q
D
R
Q
Q
*
5
VSS
RESET
CLOCK
CL
PS
CL
PS
CL
PS
CL
PS
*
6
*
7
PARALLEL/
SERIAL CONTROL
T
T
T
T
T
T
T
T
p
n
p
n
p
n
p
n
p
n
p
n
p
n
p
n
T
T
*
2
T
T
T
T
T
T
T
T
TRUE/COMPLEMENT
1
15
Q2/Q2
14
Q3/Q3
13
P/S = 0 = SERIAL MODE
T/C = 1= TRUE OUTPUTS
Q1/Q1
Q4/Q4
PS
P
p
n
D
Q
CL
CL
P
D
Q
p
n
p
n
≡
PS
R
Q
p
n
CL
CL
CL
CL
Q
p
n
CL
PS
PS
p
n
CL
CL
CL
PS
R
CL
PS
PS
CL
FIGURE 1. TYPICAL STAGE DETAIL LOGIC
7-856
CD4035BMS
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
7.5
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 1 . TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
CLOCKED OPERATION
AMBIENT TEMPERATURE (TA) = +25oC
300
200
SUPPLY VOLTAGE (VDD) = 5V
150
SUPPLY VOLTAGE (VDD) = 5V
200
100
10V
10V
15V
100
15V
50
0
0
20
40
60
80
100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 5. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE (Q OUTPUT)
7-857
CD4035BMS
Typical Performance Characteristics (Continued)
106
20
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
8
6
4
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50PF
2
105
104
15
8
6
4
2
10
5
10V
10V
8
6
4
2
103
102
5V
8
6
4
CL = 50pF
CL = 15pF
2
0
2
4
6 8
2
4
6 8
2
4
6 8
2
4
6 8
104
2
4 6 8
102
103
0
5
10
15
20
1
10
INPUT FREQUENCY (fI) (kHz)
SUPPLY VOLTAGE (VDD) (V)
FIGURE 7. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY
AS A FUNCTION OF SUPPLY VOLTAGE
FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF CLOCK INPUT FREQUENCY
LEFT
Q1Q2Q3
Q4
SHIFT
INPUT
9
10
PI-2
11
PI-3
12
PI-4
LEFT/RIGHT
7
4
3
6
2
5
PI-1
P/S
J
RIGHT
SHIFT
INPUT
P/S
K
CLK
T/C
CL
T/C
R
CARRY
FORWARD
RESET
Q1
Q2
15
Q3
14
Q4
13
VDD
LEFT
SHIFT
OUTPUT
1
RIGHT
SHIFT
OUTPUT
PI-2
TRUE/COMP CONTROL IN TRUE MODE
PI-3
FIGURE 9. SHIFT LEFT/SHIFT RIGHT REGISTER
PI-4
Using Couleur’s Technique (BIDEC)*, a binary number (most
significant bit, MSB) first is shifted and processed, such that
the BCD equivalent is obtained when the last binary bit is
clocked into the register. The CD4035BMS, with the correct
conversion logic, can also be used as a BCD-to-binary con-
verter.
*NOTE: The basic rule is: If a 4 or less is in a decade, shift with the
next clock pulse; if a 5 or greater is in a decade, add 3 and
then shift at the next clock pulse. For more information
refer to “IRE TRANSACTIONS ON ELECTRONIC COM-
PUTERS”, Dec. 1958, pages 313-316.
FIGURE 10. BIDEC LOGIC
7-858
CD4035BMS
VDD
Control = E = 0
1
9
10
PI-2
11
PI-3
12
PI-4
7
2
6
4
3
5
Q1
A
Q2
B
Q3
C
Q4
D
Q1
A
Q2
B
Q3
C
Q4
D
PI-1
P/S
T/C
CL
J
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
1
15
14
13
10
5
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
0
1
0
1
1
0
0
1
0
0
0
4 STAGE REGISTER
K
2
R
Q1
Q2
15
Q3
14
Q4
13
1
5
10
4
11
6
9
2 3 4 5
1/2
5
4
CD4002
1/2
2
3
“E” CONTROL
3
12
9
CD4012
1
1
6
13
11
7
2
4
9,10 11,12
1/2
9,10 11,12
CD4002
1/2
8
CD4012
13
1
2
1/2
13
CD4030
3
14
12
8
1
1
3
7
5
1/2
CD4030
4
Using a control line (E) two different state sequences can
be generated. For example, suppose the following two
sequences are desired on command (control line E).
6
FIGURE 11(a). DOUBLE SEQUENCE GENERATOR
FIGURE 11(b). STATE SEQUENCES
9
10
PI-2
11
PI-3
12
PI-4
9
10
PI-2
11
PI-3
12
PI-4
7
6
4
3
2
5
7
6
4
3
2
5
PI-1
PI-1
P/S
CL
J
P/S
CL
J
CLOCK
CARRY
INPUT
TENS REGISTER
UNITS REGISTER
K
K
VDD
VDD
T/C
R
T/C
R
Q1
Q2
15
Q3
14
Q4
13
RESET
Q1
Q2
15
Q3
14
Q4
13
1
1
BCD
TENS
OUT
BCD
UNITS
OUT
P/S
P/S
CARRY
FORWARD
CARRY
FORWARD
BCD TENS
(BIDEC LOGIC)
BCD UNITS
(BIDEC LOGIC)
TO
NEXT
DECADE
FIG 7
FIG 7
PI-2
PI-3
PI-4
PI-2
PI-3
PI-4
TO
TENS
REGISTER
TO
UNITS
REGISTER
FIGURE 12. BINARY-TO-BCD CONVERTER
7-859
CD4035BMS
Chip Dimensions and Pad Layout
Dimensions in parantheses are in millimeters and
are derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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860
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