CD4046BDMS [RENESAS]
PHASE LOCKED LOOP, CDIP16, SIDE BRAZED, CERAMIC, DIP-16;
| 型号： | CD4046BDMS |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | PHASE LOCKED LOOP, CDIP16, SIDE BRAZED, CERAMIC, DIP-16 CD |
| 文件： | 总11页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4046BMS
CMOS Micropower Phase Locked Loop
December 1992
Features
Description
CD4046BMS CMOS Micropower Phase-Locked Loop (PLL)
consists of a low power linear voltage-controlled oscillator (VCO)
and two different phase comparators having a common signal-
input amplifier and a common comparator input. A 5.2V zener
diode is provided for supply regulation if necessary.
• Very Low Power Consumption:
70µW (typ.) at VCO fo = 10kHz, VDD = 5V
• Operating Frequency Range Up to 1.4 MHz (typ.) at
VDD = 10V, RI = 5kΩ
• Low Frequency Drift: 0.04%/oC (typ.) at VDD = 10V
The CD4046BMS is supplied in these 16-lead outline packages:
• Choice of Two Phase Comparators:
- Exclusive-OR Network (I)
Braze Seal DIP H4W
Frit Seal DIP
H1F
- Edge-Controlled Memory Network with Phase-Pulse
Output for Lock Indication (II)
Ceramic Flatpack H6W
VCO Section
• High VCO Linearity: <1% (typ.) at VDD = 10V
The VCO requires one external capacitor C1 and one or two
external resistors (R1 or R1 and R2). Resistor R1 and capacitor
C1 determine the frequency range of the VCO and resistor R2
enables the VCO to have a frequency offset if required. The high
input impedance (1012Ω) of the VCO simplifies the design of low
pass filters by permitting the designer a wide choice of resistor-
to-capacitor ratios. In order not to load the low-pass filter, a
source-follower output of the VCO input voltage is provided at ter-
minal 10 (DEMODULATED OUTPUT). If this terminal is used, a
load resistor (RS) of 10kΩ or more should be connected from
this terminal to VSS. If unused this terminal should be left open.
The VCO can be connected either directly or through frequency
dividers to the comparator input of the phase comparators. A full
CMOS logic swing is available at the output of the VCO and
allows direct coupling to CMOS frequency dividers such as the
Intersil CD4024, CD4018, CD4020, CD4029, and CD4050. One
or more CD4018 (Preset Table Divide-By-N Counter) or CD4029
(Presettable Up/Down Counter) or CD4029 (Presettable Divide-
by-N Counter) or CD4029 (Presettable Up/Down Counter), or
CD4059A (Programmable Divide-by “N” Counter), together with
the CD4046BMS (Phase-Locked Loop) can be used to build a
micropower low-frequency synthesizer. A logic 0 on the INHIBIT
input “enables” the VCO and the source follower, while a logic 1
“turns off” both to minimize stand-by power consumption.
• VCO Inhibit Control for ON-OFF Keying and Ultra-Low
Standby Power Consumption
• Source-Follower Output of VCO Control Input
(Demod. Output)
• Zener Diode to Assist Supply Regulation
• Standardize, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of ‘B’
Series CMOS Devices”
Applications
• FM Demodulator and Modulator
• Frequency Synthesis and Multiplication
• Frequency Discriminator
• Data Synchronization
• Voltage-to-Frequency Conversion
• Tone Decoding
Pinout
CD4046BMS
TOP VIEW
• FSK - Modems
• Signal Conditioning
PHASE PULSES
PHASE COMP I OUT
COMPARATOR IN
VCO OUT
1
2
3
4
5
6
7
8
16 VDD
15 ZENER
14 SIGNAL IN
13 PHASE COMP II OUT
12 R2 TO VSS
11 R1 TO VSS
10 DEMODULATOR OUT
INHIBIT
CI(1)
C1 (2)
9
VCO IN
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3312
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-886
CD4046BMS
Phase Comparators
SIGNAL INPUT (TERM. 14)
The phase-comparator signal input (terminal 14) can be
direct-coupled provided the signal swing is within CMOS
logic levels (logic “0” ≤30% (VDD-VSS). logic “1” ≥70% (VDD
- VSS)]. For smaller swings the signal must be capacitively
coupled to the self-biasing amplifier at the signal input.
VCO OUTPUT (TERM 4) =
COMPARATOR INPUT (TERM 3)
PHASE COMPARATOR I
OUTPUT (TERM 2)
VDD
VSS
Phase-comparator I is an exclusive -OR network; it operates
analogously to an overdriven balanced mixer. To maximize
the lock range, the signal and comparator-input frequencies
must have a 50% duty cycle. With no signal or noise on the
signal input, this phase comparator has an average output
voltage equal to VDD/2. The low-pass filter connected to the
output of phase-comparator I supplies the averaged voltage
to the VCO input, and causes the VCO to oscillate at the
center frequency (fo).
VCO INPUT (TERM 9) =
= LOW-PASS FILTER OUTPUT
FIGURE 2. TYPICAL WAVEFORMS FOR CMOS PHASE-
LOCKED LOOP EMPLOYING PHASE COMPARA-
TOR IN LOCKED CONDITION OF f .
o
Phase comparator II is an edge-controlled digital memory
network. It consists of four flip-flop stages, control gating,
and a three-state output circuit comprising p- and n- type
drivers having a common output node. When the p-MOS or
n-MOS drivers are ON they pull the output up to VDD or
down to VSS, respectively. This type of phase comparator
acts only on the positive edges of the signal and comparator
inputs. The duty cycles of the signal and comparator inputs
are not important since positive transitions control the PLL
system utilizing this type of comparator. If the signal-input
frequency is higher than the comparator-input frequency, the
p-type output driver is maintained ON most of the time, and
both the n and p drivers OFF (3state) the remainder of the
time. If the signal-input frequency is lower than the compara-
tor-input frequency, the n-type output driver is maintained
ON most of the time, and both the n and p drivers OFF (3
state) the remainder of the time. If the signal and comparator
input frequencies are the same, but the signal input lags the
comparator input in phase, the n-type output driver is main-
tained ON for a time corresponding to the phase differences.
If the signal and comparator-input frequencies are the same,
but the comparator input lags the signal in phase, the p-type
output driver is maintained ON for a time corresponding to
the phase difference. Subsequently, the capacitor voltage of
the low-pass filter connected to this phase comparator is
adjusted until the signal and comparator inputs are equal in
both phase and frequency. At this stable point both p- and n-
type output drivers remain OFF and thus the phase compar-
ator output becomes an open circuit and holds the voltage
on the capacitor of the low-pass filter constant. Moreover the
signal at the “phase pulses” output is a high level which can
be used for indicating a locked condition. Thus, for phase
comparator II, no phase difference exists between signal and
comparator input over the full VCO frequency range. More-
over, the power dissipation due to the low-pass filter is
reduced when this type of phase comparator is used
because both the p- and n-type output drivers are OFF for
most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range, independent of the low-pass filter. With
no signal present at the signal input, the VCO is adjusted to
its lowest frequency for phase comparator II. Figure 15
shows typical waveforms for a CMOS PLL employing phase
comparator II in a locked condition.
The frequency range of input signals on which the PLL will
lock if it was initially out of lock is defined as the frequency
capture range (2fc).
The frequency range of input signals on which the loop will
stay locked if it was initially in lock is defined as the fre-
quency lock range (2fL). The capture range is ≤ the lock
range.
With phase-comparator I the range of frequencies over
which the PLL can acquire lock (capture range) is dependent
on the low-pass-filter characteristics, and can be made as
large as the lock range. Phase-comparator I enables a PLL
system to remain in lock in spite of high amounts of noise in
the input signal.
One characteristic of this type of phase comparator is that it
may lock onto input frequencies that are close to harmonics of
the VCO center-frequency. A second characteristic is that the
phase angle between the signal and the comparator input var-
ies between 0o and 180o, and is 90o at the center frequency.
Figure
1 shows the typical, triangular, phase-to-output
response characteristic of phase comparator I. Typical wave-
forms for a CMOS phase-locked-loop employing phase com-
parator I in locked condition of fo is shown in Figure 2.
AVERAGE OUTPUT
VOLTAGE
VDD
VDD/2
0
90o
180o
SIGNAL-TO-COMPARATOR
INPUTS PHASE DIFFERENCE
FIGURE 1. PHASE-COMPARATOR I CHARACTERISTICS AT
LOW-PASS FILTER OUTPUT
7-887
Specifications CD4046BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VIH
IOZL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
o
3 State Leakage
Current
VIN = VDD or GND
VOUT = 0V
VDD = 20V
1
2
3
1
2
3
+25 C
-100
-
-
nA
nA
nA
nA
nA
nA
o
+125 C
-1000
o
VDD = 18V
VDD = 20V
-55 C
-100
-
o
3 State Leakage
Current
IOZH
VIN = VDD or GND
VOUT = VDD
+25 C
-
-
-
100
1000
100
o
+125 C
o
VDD = 18V
-55 C
7-888
Specifications CD4046BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
GROUP A
LIMITS
MIN MAX UNITS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
SUBGROUPS
TEMPERATURE
o
Quiescent Leakage
Phase Comparator
(Bias Amp Leakage)
BIAS LKG VDD = 20V, VIN = VDD or GND
PIN 14 Open
1
3
+25 C
-
-
4
4
mA
mA
o
-55 C
Pin 5 = VDD
o
VDD = 20V, VIN = VDD or GND
PIN 14 = VSS or VDD
Pin 5 = VDD
1
3
+25 C
-
-
160
160
µA
µA
o
-55 C
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
SUBGROUPS TEMPERATURE
MIN
MAX
UNITS
o
AC Coupled Signal Input
Voltage Sensitivity
(Peak to Peak)
VS
VDD = 5V, Input Frequency =
100kHz Sine Wave
9
+25 C
-
360
mV
NOTES:
1. Go/No Go test with limits applied to inputs.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
VDD = 5V, No Load
NOTES
TEMPERATURE
MIN
MAX
UNITS
o
o
Output Voltage
VOL
1, 2
+25 C, +125 C,
-
50
mV
o
-55 C
o
o
Output Voltage
VOL
VOH
VOH
IOL5
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
Output Voltage
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
Output Voltage
+25 C, +125 C,
-
V
o
-55 C
o
Output Current (Sink)
+125 C
0.36
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
o
-55 C
0.64
o
Output Current (Sink)
Output Current (Sink)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
-
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
Output Current
(Source)
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
3
o
-55 C
o
Output Current
(Source)
+125 C
o
-55 C
o
Output Current
(Source)
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
+125 C
o
-55 C
o
Output Current
(Source)
+125 C
o
-55 C
o
o
Input Voltage Low
Input Voltage High
VIL
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
1, 2
+25 C, +125 C,
o
-55 C
o
o
VIH
+25 C, +125 C,
+7
-
V
o
-55 C
7-889
Specifications CD4046BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
o
o
Quiescent Leakage
Phase Comparator
(Bias Amp Leakage)
BIAS LKG VDD = 5 Pin 14 Open
1, 2
+25 C/-55 C
-
-
-
-
-
-
-
-
0.2
mA
VIN =
VDD or
GND
Pin 5 = VDD
o
o
Pin 14 = VSS or VDD
Pin 5 = VDD
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C/-55 C
20
1.0
40
µA
mA
µA
o
o
VDD = 10 Pin 14 Open
+25 C/-55 C
VIN =
VDD or
GND
Pin 5 = VDD
o
o
Pin 14 = VSS or VDD
Pin 5 = VDD
+25 C/-55 C
o
o
VDD = 15 Pin 14 Open
+25 C/-55 C
1.5
80
mA
µA
VIN =
VDD or
GND
Pin 5 = VDD
o
o
Pin 14 = VSS or VDD
Pin 5 = VDD
+25 C/-55 C
o
AC Coupled Signal In-
put Voltage Sensitivity
(Peak to Peak)
VS
VDD = 10V, Input Frequency =
100kHz Sine Wave
+25 C
660
1800
mV
mV
o
VDD = 15V, Input Frequency =
100kHz Sine Wave
+25 C
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
AC Coupled Signal Input
Voltage Sensitivity
VS
VDD = 5V
Input Frequency = 100kHz
Sine Wave
1, 2, 3
+25 C
-
1.35 x
+25 C
Limit
mV
o
NOTES: 1. All voltages referenced to device GND.
2. Go/No Go test with limits applied to inputs.
o
3. See Table 2 for +25 C limit.
O
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
7-890
Specifications CD4046BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
GROUP A SUBGROUPS
1, 7, 9
READ AND RECORD
IDD, IOL5, IOH5A
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
CONFORMANCE GROUPS
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1 1, 2, 4, 6, 7, 10, 11,
Note 1 13, 15
Static Burn-In 2 1, 2, 4, 6, 7, 10, 11,
Note 1 13, 15
Dynamic Burn- 1, 2, 4, 6, 7, 10, 11,
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
3, 5, 8, 9, 14
12, 16
8
8, 9
8
3, 5, 9, 12, 14, 16
3, 5, 12, 16
2
14
-
In Note 1
13, 15
Irradiation
Note 2
1, 2, 4, 6, 7, 10, 11,
13, 15
3, 5, 9, 12, 14, 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
7-891
CD4046BMS
Design Information
This information is a guide for approximating the values of external components for the CD4046BMS in a Phase-Locked-
Loop system. The selected external components must be within the following ranges:
5kΩ ≤ R1, R2, RS ≤ 1MΩ
C1 ≥ 100pF at VDD ≥ 5V
C1 ≥ 50pF at VDD ≥ 10V
PHASE
CHARACTERISTICS
COMPARATOR USED
DESIGN INFORMATION
VCO Frequency
1
VCO Without Offset R2 = ∞
VCO With Offset
fO
fMAX
fMAX
fMIN
2fL
fO
2fL
fMIN
VDD/2 VDD
VDD/2 VDD
VCO INPUT VOLTAGE
VCO INPUT VOLTAGE
2
1
Same as for Number 1
For Number Signal Input
Frequency Lock Range, 2fL
Frequency Capture Range, 2fC
VCO will adjust to center frequency, fo
2
VCO will adjust to lowest operating frequency, fmin
2fL = full VCO frequency range
2fL = fmax - fmin
1, 2
1, 2
1
IN R3
OUT
C2
(1), (2)
2πfL
τ1
2fC ≈ 1
τI = R3C2
π
√
IN R3
OUT
Loop Filter Component Selection
R4
C2
For 2 fC, see Ref. (2)
2
1
fC = fL
o
o
o
Phase Angle Between Signal and
Comparator
90 at center frequency (fo) approximating 0 and 180 at ends of lock
range (2fL)
o
2
1
2
1
2
Always 0 in lock
Locks On Harmonic of Center
Frequency
Yes
No
Signal Input Noise Rejection
High
Low
For further information, see
(1) F. Gardner, “Phase-Lock Techniques” John Wiley and Sons, New York 1966
(2) G. S. Moschytz, “Miniaturized RC Filters Using Phase-Locked Loop”, BSTJ, May, 1965
7-892
CD4046BMS
Block Diagram
*
SIGNAL 14
IN
16 VDD
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
PHASE
COMPARATOR I
COMPARATOR
VDD
PHASE COMP. I OUT
IN
*
2
3
PHASE COMP. II OUT
13
PHASE
COMPARATOR
II
÷ N
VCO
OUT
1
PHASE PULSES
R3
C2
4
VSS
6
*VCO IN
9
LOW
C1
PASS
FILTER
7
VCO
R1
R2
VSS
VSS
11
12
5
DEMODULATOR OUT
10
SOURCE
FOLLOWER
VSS
RS
*
INHIBIT
VSS
8
15 ZENER
VSS
FIGURE 3. CMOS PHASE-LOCKED LOOP BLOCK DIAGRAM
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
RI = 10kΩ
VCOIN = VDD/2, R2 = ∞, INHIBIT = VSS
106
105
104
SUPPLY VOLTAGE
(VDD) = 15V
SUPPLY VOLTAGE (VDD) = 10V
103
VCOIN = VDD/2, R = ∞, INHIBIT = VSS
106
105
10V
RI = 10kΩ
RI = 1MΩ
5V
AMBIENT TEMPERATURE (TA) = -55oC
102 RI = 100kΩ
5V
15V
10V
5V
-55oC
10
RI = 100kΩ
RI = 1MΩ
+125oC
104
103
102
10
10V
10-2
15V
1
-55oC
10-5
10-4
10-3
10-1
1
10
+125oC
VCO TIMING CAPACITOR (CI) (µF)
-55oC
TYPICAL CENTER FREQUENCY UNIT-TO-UNIT
VARIATION
+125oC
VDD (V)
∆f/fO (%)
±50
5
1
10
15
±30
10-5
10-4
10-3
10-2
10-1
1
10
±35
VCO TIMING CAPACITOR (CI) (µF)
FIGURE 4. TYPICAL CENTER FREQUENCY AS A FUNCTION
OF C1 AND R1 AT VDD = 5V, 10V, AND 15V
FIGURE 5. CENTER FREQUENCY AS A FUNCTION OF C1 AND
o
R1 FOR AMBIENT TEMPERATURE OF -55 C to
o
+125 C
7-893
CD4046BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25oC
VCOIN = VSS INHIBIT = VSS
R2 = 10kΩ
106
105
SUPPLY VOLTAGE
SUPPLY VOLTAGE (VDD) = 10V
VCOIN = VSS INHIBIT = VSS
R2 = 10kΩ
(VDD) = 15V
104
103
106
105
R2 = 1MΩ
AMBIENT TEMPERATURE
(TA) = -55oC
10V
5V
15V
10V
5V
15V
10V
5V
R2 = 100kΩ
102
10
1
+125oC
104
103
102
10
-55oC
R2 = 1MΩ
+125oC
R2 = 100kΩ
-55oC
10-5
10-4
10-3
10-2
10-1
1
10
VCO TIMING CAPACITOR (CI) (µF)
+125oC
TYPICAL fMIN UNIT-TO-UNIT VARIATION
VDD (V)
∆fMIN/fMIN (%)
1
10-5
10-4
10-3
10-2
10-1
1
10
5
±25
±20
±25
10
15
VCO TIMING CAPACITOR (CI) (µF)
FIGURE 6. TYPICAL FREQUENCY OFFSET AS A FUNCTION
OF C1 AND R2 FOR VDD = 5V, 10V, AND 15V
FIGURE 7. FREQUENCY OFFSET AS A FUNCTION OF C1 AND
o
R2 FOR AMBIENT TEMPERATURES OF -55 C to
o
125 C
8
6
4
AMBIENT TEMPERATURE (TA) = +25oC
fMAX WHEN VCOIN = VDD INHIBIT = VSS
fMIN WHEN VCOIN = VSS
2
100
AMBIENT TEMPERATURE (TA) = +25oC
VCOIN = VDD/2, R2 = ∞
INHIBIT = VSS CL = 50pF
8
6
4
SUPPLY VOLTAGE (VDD) = 5V, 10V
105
2
15V
SUPPLY VOLTAGE (VDD) = 15V
10
1
104
8
6
4
CL = 50pF
10V
1µF
103
50pF
2
1µF
5V
2
4 6 8
2
4
6 8
2
4
6 8
2
4 6 8
102
0.01
0.1
1
10
100
50pF
1µF
R2/R1
TYPICAL fMAX/fMIN UNIT-TO-UNIT VARIATION
10
VDD (V)
fMAX/fMIN (%)
2
4
6
8
2
4
6
8
2
4
6
8
10
102
103
104
5
±12
±8
R1 (kΩ)
10
15
±12
FIGURE 8. TYPICAL fMAX/fMIN AS A FUNCTION OF R2/R1
FIGURE 9. TYPICAL VCO POWER DISSIPATION AT CENTER
FREQUENCY AS A FUNCTION OF R1
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
894
CD4046BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25oC
VCOIN = VSS CL = 50pF
AMBIENT TEMPERATURE (TA) = +25oC
VCOIN = VDD/2, R1 = R2 = ∞
104
103
102
105
SUPPLY VOLTAGE (VDD) = 15V
SUPPLY VOLTAGE (VDD) = 15V
104
CL = 50pF
10V
5V
10V
5V
1µF
50pF
1µF
103
50pF
1µF
102
10
101
1
2
4
6
8
102
2
4
6
8
103
2
4
6
8
104
2
4
6
8
102
2
4
6
8
103
2
4
6
8
104
10
10
R2 (kΩ)
Rs (kΩ)
FIGURE 10. TYPICAL VCO POWER DISSIPATION AT fMIN AS A
FUNCTION OF R2
FIGURE 11. TYPICAL SOURCE FOLLOWER POWER
DISSIPATION AS A FUNCTION OF RS
VDD
AMBIENT TEMPERATURE (TA) = +25oC
8
8
6
4
VDD = 10V, VCOIN = 5V ± 1V, R2 = ∞
6
4
SUPPLY VOLTAGE
(VDD) = 15V
2kΩ
2
20kΩ
2
104
103
13
8
6
4
VOUT
2kΩ
10
8
6
4
10V
5V
2
VSS
OUTPUT CIRCUIT
CL = 50pF
2
100pF
1000pF
8
6
4
0.1µF
f(4V) + f(6V)
1
f0 =
2
2
1
8
6
4
102
10
8
6
4
f0 - f(5V)
f0
2
0.01µF
% LINEARITY =
x 100
4
AMBIENT TEMPERATURE (TA) = +25oC
PHASE COMPARATOR II
10-1
2
2
4
6
8
2
4
6
8
2
6
8
102
2
4
6 8
103
10-1
1
10
R1 (kΩ)
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
1
10
102
103
104
SIGNAL INPUT FREQUENCY (fIN) (kHz)
FIGURE 12. AC-COUPLED SIGNAL INPUT VOLTAGE AS A
FUNCTION OF SIGNAL INPUT FREQUENCY
FIGURE 13. TYPICAL VCO LINEARITY AS A FUNCTION OF R1
AND C1 AT VDD = 10V
AMBIENT TEMPERATURE (TA) = +25oC
VDD = 10V, VCOIN = 5V ± 1V, R2 = ∞
8
6
4
2
10
8
6
4
CL = 50pF
100pF
0.1µF
2
f(6V) + f(9V)
2
1
f0 =
8
6
1000pF
4
f0 - f(7.5V)
f0
0.01µF
0.1µF
2
% LINEARITY =
x 100
10-1
2
4
6
8
2
4
6
8
2
4
6
8
102
2
4
6 8
103
10-1
1
10
R1 (kΩ)
FIGURE 14. TYPICAL VCO LINEARITY AS A FUNCTION
OF R1 AND C1 AT VDD = 15V
7-895
CD4046BMS
I
II
III
SIGNAL INPUT (TERM 14)
VDD
VCO OUTPUT (TERM 4) =
COMPARATOR INPUT (TERM 3)
2KΩ
PHASE 13 20KΩ
COMPARATOR II
OUTPUT
PHASE COMPARATOR II
OUTPUT (TERM 13)
-VDD
-VSS
VCO INPUT (TERM 9) =
∆ LOW-PASS FILTER
OUTPUT
-VDD
-VSS
2KΩ
VSS
-VDD
-VSS
PHASE PULSE (TERM 1)
NOTE: DASHED LINE IS AN OPEN
CIRCUIT CONDITION
(3RD STATE)
FIGURE 15. TYPICAL WAVEFORMS FOR COS/MOS PHASE-LOCKED LOOP
EMPLOYING PHASE COMPARATOR II IN LOCKED CONDICTION
FIGURE 16. PHASE COMPARATOR II
OUTPUT LOADING CIRCUIT
Chip Dimensions and Pad Layout
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-896
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