CD4053BFMS [RENESAS]
TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, CDIP16, FRIT SEALED, DIP-16;
| 型号： | CD4053BFMS |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, CDIP16, FRIT SEALED, DIP-16 CD |
| 文件： | 总12页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4051BMS, CD4052BMS
CD4053BMS
CMOS Analog
Multiplexers/Demultiplexers*
December 1992
Features
Description
• Logic Level Conversion
CD4051BMS, CD4052BMS and CD4053BMS analog multi-
plexers/demultiplexers are digitally controlled analog
switches having low ON impedance and very low OFF leak-
age current. Control of analog signals up to 20V peak-to-
peak can be achieved by digital signal amplitudes of 4.5V to
20V (if VDD-VSS = 3V, a VDD-VEE of up to 13V can be con-
trolled; for VDD-VEE level differences above 13V, a VDD-
VSS of at least 4.5V is required). For example, if VDD =
+4.5V, VSS = 0, and VEE = -13.5V, analog signals from -
13.5V to +4.5V can be controlled by digital inputs of 0 to 5V.
These multiplexer circuits dissipate extremely low quiescent
power over the full VDD-VSS and VDD-VEE supply voltage
• High-Voltage Types (20V Rating)
• CD4051BMS Signal 8-Channel
• CD4052BMS Differential 4-Channel
• CD4053BMS Triple 2-Channel
• Wide Range of Digital and Analog Signal Levels:
- Digital 3V to 20V
- Analog to 20Vp-p
• Low ON Resistance: 125Ω (typ) Over 15Vp-p Signal
Input Range for VDD - VEE = 15V
ranges, independent of the logic state of the control signals.
When a logic “1” is present at the inhibit input terminal all
channels are off.
• High OFF Resistance: Channel Leakage of ±100pA
(typ) at VDD - VEE = 18V
The CD4051BMS is a single 8 channel multiplexer having
three binary control inputs, A, B, and C, and an inhibit input.
The three binary signals select 1 of 8 channels to be turned
on, and connect one of the 8 inputs to the output.
• Logic Level Conversion:
- Digital Addressing Signals of 3V to 20V (VDD - VSS
= 3V to 20V)
- Switch Analog Signals to 20Vp-p (VDD - VEE = 20V);
See Introductory Text
The CD4052BMS is a differential 4 channel multiplexer hav-
ing two binary control inputs, A and B, and an inhibit input.
The two binary input signals select 1 of 4 pairs of channels
to be turned on and connect the analog inputs to the out-
puts.
• Matched Switch Characteristics: RON = 5Ω (typ) for
VDD - VEE = 15V
• Very Low Quiescent Power Dissipation Under All Digi-
tal Control Input and Supply Conditions: 0.2µW (typ)
at VDD - VSS = VDD - VEE = 10V
The CD4053BMS is a triple 2 channel multiplexer having
three separate digital control inputs, A, B, and C, and an
inhibit input. Each control input selects one of a pair of chan-
nels which are connected in a single pole double-throw con-
figuration.
• Binary Address Decoding on Chip
• 5V, 10V and 15V Parametric Ratings
The CD4051BMS, CD4052BMS and CD4053BMS are supplied
in these 16 lead outline packages:
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
Braze Seal DIP
*H4X
H1E
†H4T
• Break-Before-Making Switching Eliminates Channel Frit Seal DIP
Overlap
Ceramic Flatpack
*CD4051B Only
H6W
†CD4052B, CD4053 Only
Applications
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
* When these devices are used as demultiplexers the “CHANNEL
IN/OUT” terminals are the outputs and the “COMMON OUT/IN” ter-
minals are the inputs.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3316
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-937
CD4051BMS, CD4052BMS, CD4053BMS
Pinouts
CD4051BM
TOP VIEW
CD4052BMS
TOP VIEW
4
6
1
2
3
4
5
6
7
8
16 VDD
15 2
0
2
1
2
3
4
5
6
7
8
16 VDD
15 2
CHANNELS
IN/OUT
Y CHANNELS
IN/OUT
X CHANNELS
IN/OUT
COM OUT/IN
7
14 1
COMMON “Y” OUT/IN
14 1
CHANNELS
IN/OUT
13 0
3
13 COMMON “X” OUT/IN
CHANNELS
Y CHANNELS
IN/OUT
IN/OUT
5
12 3
1
12 0
X CHANNELS
IN/OUT
INH
VEE
VSS
11
A
INH
VEE
VSS
11
3
10 B
10 A
9
C
9 B
CD4053BMS
TOP VIEW
by
bx
cy
1
2
3
4
5
6
7
8
16 VDD
15 OUT/IN bx or by
14 OUT/IN ax or ay
IN/OUT
OUT/IN CX or CY
13 ay
IN/OUT
12 ax
IN/OUT CX
INH
11
A
10 B
VEE
9
C
VSS
Functional Diagrams
CHANNEL IN/OUT
7
4
6
2
5
5
4
1
3
2
1
0
16
VDD
12 15 14 13
TG
TG
TG
TG
TG
TG
TG
TG
*
11
A
B
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 8
DECODER
WITH
INHIBIT
*
10
3
COMMON
OUT/IN
*
9
C
*
6
INH
VDD
* ALL INPUTS PROTECTED BY
STANDARD CMOS PROTECTION
NETWORK
8
VSS
7
VEE
VSS
CD4051BMS
7-938
CD4051BMS, CD4052BMS, CD4053BMS
Functional Diagrams (Continued)
X CHANNELS IN/OUT
3
2
1
0
11 15 14 12
TG
TG
TG
TG
TG
TG
TG
TG
16
VDD
COMMON X
OUT/IN
*
10
13
A
B
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
3
*
9
COMMON Y
OUT/IN
*
6
INH
1
0
5
1
2
2
4
3
8
VSS
7
VEE
Y CHANNELS IN/OUT
CD4052BMS
VDD
* ALL INPUTS PROTECTED BY
STANDARD CMOS PROTECTION
NETWORK
VSS
BINARY TO 1 OF 2
DECODERS WITH
INHIBIT
IN/OUT
cy cx by bx ay ax
LOGIC
LEVEL
CONVERSION
3
5
1
2
13 12
16
VDD
OUT/IN
ax or ay
TG
14
*
TG
TG
TG
TG
TG
A
B
C
11
OUT/IN
bx or by
*
10
15
*
9
OUT/IN
cx or cy
4
*
INH
6
8
VSS
7
VEE
CD4053BMS
7-939
Specifications CD4051BMS, CD4052BMS, CD4053BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
Ω
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
IIH
VIN = VDD or GND
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
1
+25 C
-
100
1000
100
1050
1300
800
400
550
310
240
320
220
-0.7
2.8
o
2
+125 C
-
o
VDD = 18V
3
-55 C
-
o
On-State Resistance
RL = 10K Returned to
VDD - VSS/2
RON
VDD = 5V
VIS = VSS to VDD
1
+25 C
-
o
2
+125 C
-
Ω
o
3
-55 C
-
Ω
o
VDD = 10V
VIS = VSS to VDD
1
+25 C
-
Ω
o
2
+125 C
-
Ω
o
3
-55 C
-
Ω
o
VDD = 15V
VIS = VSS to VDD
1
+25 C
-
-
Ω
o
2
+125 C
Ω
o
3
1
-55 C
-
Ω
o
N Threshold Voltage
P Threshold Voltage
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
V
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
Functional
(Note 4)
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
VDD = 5V = VIS thru 1k,
VEE = VSS
RL = 1k to VSS, |IIS| < 2µA
OFF Channels
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V = VIS thru 1K
VEE = VSS
RL = 1K to VSS, |ISS|, <2µA
On All OFF Channels
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VIH
IOZL
+25 C, +125 C, -55 C
11
o
Off Channel Leakage
Any Channel OFF
Or
All Channels Off
(Common Out/In)
VIN = VDD or GND
VOUT = 0V
VDD = 20V
1
2
3
1
2
3
+25 C
-0.1
-
µA
µA
µA
µA
µA
µA
o
+125 C
-1.0
-
o
VDD = 18V
VDD = 20V
-55 C
-0.1
-
o
IOZH
VIN = VDD or GND
VOUT = VDD
+25 C
-
-
-
0.1
1.0
0.1
o
+125 C
o
VDD = 18V
-55 C
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
4. VDD = 2.8V/3.0V, RL = 200k to VDD
VDD = 20V/18V, RL = 10k to VDD
7-940
Specifications CD4051BMS, CD4052BMS, CD4053BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS (Notes 1, 2)
SUBGROUPS TEMPERATURE
MIN
MAX
720
UNITS
ns
o
Propagation Delay
(Note 1)
Address to Signal Out
Channels On or Off
TPHL
TPLH
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
9
+25 C
-
-
o
o
10, 11
+125 C, -55 C
972
ns
o
Propagation Delay
(Note 1)
Inhibit to Signal Out
(Channel Turning On)
TPZH
TPZL
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
9
+25 C
-
-
720
972
ns
ns
o
o
10, 11
+125 C, -55 C
o
Propagation Delay
(Note 1)
Inhibit to Signal Out
(Channel Turning Off)
TPHZ
TPLZ
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
9
+25 C
-
-
450
608
ns
ns
o
o
10, 11
+125 C, -55 C
NOTES:
o
o
1. -55 C and +125 C limits guaranteed, 100% testing being implemented.
2. CL = 50pF, RL = 10KΩ, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
3
µA
o
o
Input Voltage Low
Input Voltage High
VIL
VDD = VIS = 10V, VEE = VSS
RL = 1K to VSS
|IIS|, 2µA On/Off Channel
1, 2
1, 2
+25 C, +125 C,
V
o
-55 C
o
o
VIH
+25 C, +125 C,
+7
-
V
o
-55 C
o
Propagation Delay
Address to Signal Out
(Channels On or Off)
TPHL
TPLH
VDD = 10V
VDD = 15V
VEE = VSS = 0V
VEE = VSS = 0V
VEE = VSS = 0V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C
-
-
-
320
240
450
ns
ns
ns
o
+25 C
o
VDD = 5V
VEE = -5V
+25 C
o
Propagation Delay
Inhibit to Signal Out
(Channel Turning On)
TPZH
TPZL
VDD = 10V
VDD = 15V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C
-
-
-
320
240
400
ns
ns
ns
o
+25 C
o
VDD = 5V
VEE = -10V
+25 C
o
Propagation Delay
Inhibit to Signal Out
(Channel Turning Off)
TPHZ
TPLZ
VDD = 10V
VDD = 15V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C
-
-
-
210
160
300
ns
ns
ns
o
+25 C
o
VDD = 5V
+25 C
VEE = -15V
o
Input Capacitance
NOTES:
CIN
Any Address or Inhibit Input
1, 2
+25 C
-
7.5
pF
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are char-
acterized on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 10K, Input TR, TF < 20ns.
7-941
Specifications CD4051BMS, CD4052BMS, CD4053BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
O
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
ON Resistance
SYMBOL
DELTA LIMIT
IDD
± 1.0µA
RONDEL10 ± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
GROUP A SUBGROUPS
READ AND RECORD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
IDD, IOL5, IOH5A, RONDEL10
IDD, IOL5, IOH5A, RONDEL10
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
PART NUMBER CD4051BMS
7-942
Specifications CD4051BMS, CD4052BMS, CD4053BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1
Note 1
3
1, 2, 4 - 6, 7, 8,
9 - 15
16
Static Burn-In 2
Note 1
3
-
7, 8
4 - 6, 7, 8, 9, 12, 14
7, 8
1, 2, 4 - 6, 9 - 16
1, 2, 13, 15, 16
1, 2, 4 - 6, 9 - 16
Dynamic Burn-
In Note 1
3
11
10
Irradiation
Note 2
3
PART NUMBER CD4052BMS
Static Burn-In 1
Note 1
3, 13
3, 13
-
1, 2, 4 - 6, 7, 8,
9 - 12, 14, 15
16
Static Burn-In 2
Note 1
7, 8
4 - 6, 7, 8, 12, 15
7, 8
1, 2, 4 - 6, 9 - 12,
14 - 16
Dynamic Burn-
In Note 1
1, 2, 11, 14, 16
3, 13
10
9
Irradiation
Note 2
3, 13
1, 2, 4 - 6, 9 - 12,
14 - 16
PART NUMBER CD4053BMS
Static Burn-In 1
Note 1
4, 14, 15
4, 14, 15
-
1 - 3, 5 - 8, 9 - 13
7, 8
16
Static Burn-In 2
Note 1
1 - 3, 5, 6, 9 - 13,
16
Dynamic Burn-
In Note 1
1, 5 - 8, 12
7, 8
2, 3, 13, 16
4, 14, 15
9 - 11
Irradiation
Note 2
4, 14, 15
1 - 3, 5, 6, 9 - 13,
16
NOTE:
1. Each pin except pin 7 VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except pin 7 VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Typical Performance Characteristics
SUPPLY VOLTAGE (VDD - VEE) = 10V
SUPPLY VOLTAGE (VDD - VEE) = 5V
300
250
200
150
100
50
600
500
400
300
200
100
0
AMBIENT TEMPERATURE
(TA) = +125oC
AMBIENT TEMPERATURE
(TA) = +125oC
+25oC
-55oC
+25oC
-55oC
0
-4
-3
-2
-1
0
1
2
3
4
-10.0 -7.5 -5.0 -2.5
0
2.5
5.0
7.5 10.0
INPUT SIGNAL VOLTAGE (VIS) (V)
INPUT SIGNAL VOLTAGE (VIS) (V)
FIGURE 1. TYPICAL CHANNEL ON RESISTANCE vs INPUT
SIGNAL VOLTAGE (ALL TYPES)
FIGURE 2. TYPICAL CHANNEL ON RESISTANCE vs INPUT
SIGNAL VOLTAGE (ALL TYPES)
7-943
CD4051BMS, CD4052BMS, CD4053BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE
(TA) = +25oC
SUPPLY VOLTAGE (VDD - VEE) = 15V
600
500
400
300
200
100
0
300
250
200
150
100
50
SUPPLY VOLTAGE (VDD - VEE) = 5V
AMBIENT TEMPERATURE
(TA) = +125oC
+25oC
-55oC
10V
15V
0
-10.0 -7.5 -5.0 -2.5
0
2.5
5.0
7.5 10.0
-10.0 -7.5 -5.0 -2.5
0
2.5
5.0
7.5 10.0
INPUT SIGNAL VOLTAGE (VIS) (V)
INPUT SIGNAL VOLTAGE (VIS) (V)
FIGURE 3. TYPICAL CHANNEL ON RESISTANCE vs INPUT
SIGNAL VOLATGE (ALL TYPES)
FIGURE 4. TYPICAL CHANNEL ON RESISTANCE vs INPUT
SIGNAL VOLTAGE (ALL TYPES)
105
6
AMBIENT TEMPERATURE (TA)
= +25oC
ALTERNATING “O” AND
“I” PATTERN
LOAD CAPICATANCE (CL)
= 50pF
TEST CIRCUIT
VDD
LOAD RESISTANCE
SUPPLY VOLTAGE (VDD) = 5V
VSS = 0V VEE = -5V
AMBIENT TEMPERATURE (TA)
= +25oC
(RL) = 100kΩ, 10kΩ
1kΩ
1500Ω
100Ω
4
2
B/D
f
104
103
102
10
CD4029
VDD
A
B
C
9
100Ω
11 10
SUPPLY VOLTAGE
(VDD) (15V)
13
14
15
12
1
0
CD4051
10V
-2
-4
-6
5
2
10V
3
5V
4
8
7
6
CL = 15pF
100Ω
Ι
CL
102
103
104
105
-6
-4
-2
0
2
4
6
1
10
INPUT SIGNAL VOLTAGE (VIS) (V)
SWITCHING FREQUENCY (f) (kHz)
FIGURE 5. TYPICAL ON CHARACTERISTICS FOR 1 OF 8
CHANNELS (CD4051BMS)
FIGURE 6. TYPICAL DYNAMIC POWER DISSIPATION vs
SWITCHING FREQUENCY (CD4051BMS)
105
105
AMBIENT TEMPERATURE (TA)
TEST CIRCUIT
AMBIENT TEMPERATURE (TA)
= +25oC
= +25oC
VDD
ALTERNATING “O” AND
ALTERNATING “O” AND
TEST CIRCUIT
“I” PATTERN
LOAD CAPICATANCE (CL)
= 50pF
“I” PATTERN
VDD
CD4029
B/D
f
104
103
102
10
104
LOAD CAPICATANCE (CL)
f
VDD
= 50pF
A
10
B
9
9
CL
4
100
Ω
100Ω
SUPPLY VOLTAGE
(VDD) (15V)
CL
SUPPLY VOLTAGE
(VDD) (15V)
3
3
5
12
1
5
2
4
1
13
103
102
10
13
2
12
14
15
11
100Ω
CD4051
CD4051
1
10
11
10V
10V
100Ω
6
7
15
14
10V
10V
6
7
5V
5V
8
CL = 15pF
CL = 15pF
8
Ι
Ι
1
10
102
103
104
105
1
10
102
103
104
105
SWITCHING FREQUENCY (f) (kHz)
SWITCHING FREQUENCY (f) (kHz)
FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION vs
SWITCHING FREQUENCY (CD4052BMS)
FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION vs
SWITCHING FREQUENCY (CD4053BMS)
7-944
CD4051BMS, CD4052BMS, CD4053BMS
VDD = +15V
VDD = +7.5V
VDD = +5V
5V
VDD = +5V
5V
16
16
16
16
7.5V
VSS = 0V
VSS = 0V
VSS = 0V
VEE = 0V
7
8
7
8
7
8
7
8
VEE = -7.5V
VEE = -10V
VEE = -5V
VSS = 0V
(a)
(b)
(c)
(d)
The ADDRESS (digital-control inputs) and INHIBIT logic levels are:
“0” = VSS and “1” = VDD. The analog signal (through the TG) may
swing from VEE to VDD
FIGURE 9. TYPICAL BIAS VOLTAGES
7-945
CD4051BMS, CD4052BMS, CD4053BMS
TRUTH TABLE
INPUT STATES
CD4051BMS
INHIBIT
tf = 20ns
10%
tr = 20ns
90%
“ON” CHANNEL(S)
90%
50%
50%
C
0
0
0
0
1
1
1
1
X
B
0
0
1
1
0
0
1
1
X
A
0
1
0
1
0
1
0
1
X
10%
tPZL
0
0
0
0
0
0
0
0
1
0
TURN-ON
TIME
1
90%
50%
2
3
10%
TURN-OFF TIME
10%
4
tPLZ
5
6
7
FIGURE 10. WAVEFORM, CHANNEL BEING TURNED ON, OFF
(RL = 1kΩ)
NONE
CD4052BMS
tr = 20ns
90%
tf = 20ns
10%
INHIBIT
B
0
0
1
1
x
A
0
1
0
1
x
90%
50%
0
0x, 0y
1x, 1y
2x, 2y
3x, 3y
NONE
50%
0
10%
0
90%
0
1
10%
TURN-ON
TIME
CD4053BMS
TURN-OFF TIME
INHIBIT
A OR B OR C
tPZH
tPHZ
0
0
1
ax or bx or cx
ay or by or cy
NONE
FIGURE 11. WAVEFORM, CHANNEL BEING TURNED OFF, ON
0
1
(RL = 1kΩ)
X
X = Don’t Care
VDD
OUTPUT
OUTPUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CL
RL
RL
CL
VDD
VDD
VEE
VEE
VDD
VSS
VDD
VSS
VEE
VSS
VEE
CLOCK
IN
CLOCK
IN
VSS
VSS
VSS
CD4051
CD4052
VDD
OUTPUT
1
2
3
4
5
16
15
14
13
12
11
10
9
RL
CL
VEE
VDD
VSS
6
VEE
CLOCK
IN
7
8
VSS
VSS
CD4053
FIGURE 12. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT
7-946
CD4051BMS, CD4052BMS, CD4053BMS
VDD
VDD
OUTPUT
OUTPUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RL
50pF
VEE
RL
50pF
VEE
VDD
VDD
VDD
VSS
VDD
VSS
CLOCK
IN
VEE
VSS
CLOCK
IN
VEE
VSS
VSS
VSS
tPHL AND tPLH
CD4052
tPHL AND tPLH
CD4051
OUTPUT
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RL
50pF
VEE
VDD
VDD
VSS
CLOCK
IN
VEE
VSS
VSS
tPHL AND tPLH
CD4053
FIGURE 13. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT
DIFFERENTIAL
SIGNALS
CD4052
CD4052
COMMUNICATIONS
LINK
DIFF
DIFF
AMPLIFIER/
RECEIVER
LINE DRIVER
DIFF
DEMULTIPLEXING
MULTIPLEXING
FIGURE 14. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052BMS
7-947
CD4051BMS, CD4052BMS, CD4053BMS
Chip Dimensions and Pad Layouts
CD4051BMSH
CD4052BMSH
CD4053BMSH
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
-3
Grid graduations are in mils (10 inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
948
相关型号：
©2020 ICPDF网 联系我们和版权申明