CD4063BDMSR [RENESAS]
4000/14000/40000 SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, CDIP16, BRAZE SEALED, DIP-16;
| 型号： | CD4063BDMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4000/14000/40000 SERIES, 4-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, CDIP16, BRAZE SEALED, DIP-16 CD 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4063BMS
CMOS 4-Bit Magnitude Comparator
December 1992
Features
Pinout
CD4063BMS
TOP VIEW
• High Voltage Type (20V Rating)
• Expansion to 8, 12, 16 . . . 4N Bits by Cascading Units
• Medium Speed Operation
B3
(A < B) IN
(A = B) IN
(A > B) IN
(A > B) OUT
(A = B) OUT
(A < B) OUT
VSS
1
2
3
4
5
6
7
8
16 VDD
15 A3
14 B2
13 A2
12 A1
11 B1
10 A0
- Compares Two 4-Bit Words in 250ns (Typ.) at 10V
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Full Package Temperature Range)
- 1V at VDD = 5V
9
B0
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Functional Diagram
4
Applications
WORD A
• Servo Motor Controls
• Process Controllers
A > B
A > B
A = B
A < B
CASCADING
A = B
INPUTS
A < B
Description
CD4063BMS is a 4-bit magnitude comparator designed for use
in computer and logic applications that require the comparison of
two 4-bit words. This logic circuit determines whether one 4-bit
word (Binary or BCD) is “less than”, “equal to”, or “greater than” a
second 4-bit word.
4
WORD B
The CD4063BMS has eight comparing inputs (A3, B3, through
A0, B0), three outputs (A < B, A = B, A > B) and three cascading
inputs (A < B, A = B, A > B) that permit systems designers to
expand the comparator function to 8, 12, 16 . . . 4N bits. When a
single CD4063BMS is used, the cascading inputs are connected
as follows: (A < B) = low, (A = B) = high, (A > B) = low.
For words longer than 4 bits, CD4063BMS devices may be cas-
caded by connecting the outputs of the less significant compara-
tor to the corresponding cascading inputs of the more significant
comparator. Cascading inputs (A < B, A = B, and A > B) on the
least significant comparator are connected to a low, a high, and a
low level, respectively.
The CD4063BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
H4T
H1E
Ceramic Flatpack H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3318
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-958
Specifications CD4063BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP Package . . . . . . . . . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 20 C/W
θ
θ
jc
ja
o
20C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
VIH
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
NOTES:
3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
is 0.050V max.
1. All voltages referenced to device GND. 100% testing being implemented
2. Go/No Go test with limit applied to inputs
7-959
Specifications CD4063BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
(NOTE 1, 2)
CONDITIONS
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
MAX
1250
1688
1000
1350
200
UNITS
ns
o
Propagation Delay Com-
parator Input to Output
TPHL
TPLH
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
9
+25 C
-
-
-
-
-
-
o
o
10, 11
9
+125 C, -55 C
ns
o
Propagation Delay
Cascade Input to Output
TPHL
TPLH
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Transition Time
NOTES:
TTHL
+25 C
ns
o
o
10, 11
+125 C, -55 C
270
ns
1. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
o
-55 C
0.64
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Input Voltage Low
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
-
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-2.6
-2.4
-4.2
3
o
-55 C
o
+125 C
o
-55 C
o
IOH10
IOH15
VIL
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
+125 C
o
-55 C
o
+125 C
o
-55 C
o
o
VDD = 10V, VOH > 9V, VOL <
1V
+25 C, +125 C,
o
-55 C
7-960
Specifications CD4063BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
o
o
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL <
1V
1, 2
+25 C, +125 C,
+7
-
V
o
-55 C
o
Propagation Delay
Comparator Input to Output TPLH1
TPHL1 VDD = 10V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
+25 C
-
-
-
-
-
-
-
500
350
400
280
100
80
ns
ns
ns
ns
ns
ns
pF
o
VDD = 15V
+25 C
o
Propagation Delay
Cascade Input to Output
TPHL2 VDD = 10V
+25 C
TPLH2
o
VDD = 15V
+25 C
o
Transition Time
TTHL
TTLH
VDD = 10V
VDD = 15V
+25 C
o
+25 C
o
Input Capacitance
NOTES:
CIN
+25 C
7.5
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K; input TR, TF < 20ns
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
∆VNTH VDD = 10V, ISS= -10µA
1, 4
+25 C
V
o
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VPTH VSS = 0V, IDD = 10µA
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 3V, VIN = VDD or GND
VDD = 5V (Worst Case)
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
NOTES:
1. All voltages referenced to device GND.
2. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF = 20ns
o
3. See Table 2 for +25 C limit.
4. Read and record
O
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
METHOD
100% 5004
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
Initial Test (Pre Burn-In)
1, 7, 9
7-961
Specifications CD4063BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
GROUP A SUBGROUPS
1, 7, 9
READ AND RECORD
IDD, IOL5, IOH5A
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 5% parametric, 3% functional; cumulative for static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
CONFORMANCE GROUPS
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9, Deltas
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1
Note 1
5-7
1, 2, 4, 8-15
3, 16
Static Burn-In 2
Note 1
5-7
-
3, 8
1, 2, 4, 9-16
3, 16
Dynamic Burn-
In Note 1
1, 2, 4, 8, 10, 11,
13
5-7
12, 15
9, 14
Irradiation
Note 2
5-7
3, 8
1, 2, 4, 9-16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
A0 A1 A2 A3
A4 A5 A6 A7
CD4063
A8 A9 A10 A11
CD4063
CD4063
VDD
(A < B) OUT
(A = B) OUT
(A > B) OUT
(A < B) IN
(A = B) IN
(A > B) IN
B0 B1 B2 B3
B4 B5 B6 B7
B8 B9 B10 B11
tP TOTAL = tP (COMPARE INPUTS) + 2 x tP (CASCADE INPUTS), AT VDD = 10V
(3 STAGES)
= 250 + (2 x 200) = 650ns (TYP.)
FIGURE 1. TYPICAL SPEED CHARACTERISTICS OF A 12-BIT COMPARATOR
7-962
CD4063BMS
Logic Diagram
A3
B3
A < B
A0
A0
A1
A1
A3
B3
*
*
*
*
*
*
*
*
*
*
*
10
12
13
15
9
A0
A1
A2
A3
B0
B1
B2
B3
A2
B2
A2
B2
A2
A2
A3
A3
B0
B0
B1
B1
A1
B1
A1
B1
COMPARING
INPUTS
A0
B0
(A < B) OUT
7
A0
B0
11
14
1
B2
B2
(A < B) i - I
B3
B3
(A = B) OUT
(A > B) OUT
6
5
B3
A3
(A < B) i - I
(A > B) i - I
2
(A < B) IN
(A > B) IN
(A = B) IN
A > B
B3
A3
CASCADING
INPUTS
4
B2
A2
3
B2
A2
B1
A1
VDD
B1
A1
ALL INPUTS PROTECTED
BY THE CMOS
*
PROTECTION NETWORK
B0
A0
INPUT
TERMINAL
B0
A0
VSS
(A > B) i - I
FIGURE 2. LOGIC DIAGRAM
TRUTH TABLE
INPUTS
COMPARING
CASCADING
OUTPUTS
A = B
A3, B3
A2, B2
A1, B1
A0, B0
A <B
A = B
A > B
A < B
A > B
A3 > B3
A3 = B3
A3 = B3
A3 = B3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
A2 > B2
A2 = B2
A2 = B2
A1 > B1
A1 = B1
A0 > B0
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A2 = B2
A2 = B2
A1 = B1
A1 = B1
A1 = B1
A0 = B0
A0 = B0
A0 = B0
0
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
0
A3 = B3
A3 = B3
A3 = B3
A3 < B3
A2 = B2
A2 = B2
A2 < B2
X
A1 = B1
A1 < B1
A0 < B0
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
0
0
0
0
0
0
0
0
X
X
X
X
X
X = Don’t Care
Logic 1 = High Level
Logic 0 = Low Level
7-963
CD4063BMS
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
7.5
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
1750
AMBIENT TEMPERATURE (TA) = +25oC
700
SUPPLY VOLTAGE (VDD) = 5V
LOAD CAPACITANCE (CL) = 50pF
1500
600
1250
1000
750
500
AMBIENT TEMPERATURE (TA) = +25oC
400
10V
15V
300
200
500
250
100
0
10
20
30
40
50
60
70
80
90
0
2.5
5.0
7.5 10.0 12.5 15.0 17.5 20.0
SUPPLY VOLTAGE (VDD) (V)
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE (“COMPARING INPUTS” TO OUTPUTS)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs SUPPLY
VOLTAGE (“COMPARING INPUTS” TO OUTPUTS)
7-964
CD4063BMS
Typical Performance Characteristics (Continued)
104
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
6
4
2
103
SUPPLY VOLTAGE (VDD) = 15V
LOAD CAPACITANCE (CL) = 50pF
6
4
200
2
10V, 50pF
SUPPLY VOLTAGE (VDD) = 5V
102
150
6
4
10V, 15pF
100
2
10V
15V
10
5V, 50pF
6
4
50
2
1
2
4
6 8
103
2
4 6 8
2
4
6 8
2
4
6 8
2
4 6 8
0
0
20
40
60
80
100
0.1
1
10
102
LOAD CAPACITANCE (CL) (pF)
INPUT FREQUENCY (f) (kHz)
FIGURE 9. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE
FIGURE 10. TYPICAL POWER DISSIPATION vs FREQUENCY
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
965
相关型号：
©2020 ICPDF网 联系我们和版权申明