CD4076BFMSR [RENESAS]
4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, FRIT SEALED, CERAMIC, DIP-16;
| 型号： | CD4076BFMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, FRIT SEALED, CERAMIC, DIP-16 CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4076BMS
CMOS 4 -Bit D-Type Registers
December 1992
Features
Pinout
CD4076BMS
TOP VIEW
• High Voltage Type (20V Rating)
• Three State Outputs
• Input Disabled Without Gating the Clock
M
N
1
2
3
4
5
6
7
8
16 VDD
OUTPUT
DISABLE
• Gated Output Control Lines for Enabling or Disabling
the Outputs
15 RESET
14 DATA 1
13 DATA 2
12 DATA 3
11 DATA 4
Q1
Q2
Q3
Q4
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
DATA
INPUT
DISABLE
10 G2
G1
CLOCK
VSS
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
9
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
Functional Diagram
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
DATA INPUT
DISABLE
OUTPUT
DISABLE
G1
G2
CLOCK
7
M
N
Description
9
10
1
2
CD4076BMS types are four-bit registers consisting of D-type
flip-flops that feature three-state outputs. Data Disable inputs
are provided to control the entry of data into the flip-flops.
When both Data Disable inputs are low, data at the D inputs
are loaded into their respective flip-flops on the next positive
transition of the clock input. Output Disable inputs are also
provided. When the Output Disable inputs are both low, the
normal logic states of the four outputs are available to the
load. The outputs are disabled independently of the clock by
a high logic level at either Output Disable input, and present
a high impedance.
14
13
3
4
D1
D2
D3
D4
Q1
Q2
Q3
Q4
4D - TYPE
FLIP-FLOPS
WITH
AND-OR
LOGIC
12
11
5
6
15
VSS = 8
VDD = 16
The CD4076BMS is supplied in these 16 lead outline pack-
ages:
RESET
Braze Seal DIP
Frit Seal DIP
H4T
H1E
H6W
Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3325
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1029
Specifications CD4076BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
SUBGROUP
S
UNIT
S
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
MIN
MAX
10
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
o
2
+125 C
-
1000
10
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
VIN = VDD or GND
1
+25 C
-
-
-
-
100
1000
100
50
o
2
3
+125 C
o
VDD = 18V
-55 C
o
o
Output Voltage
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25 C, +125 C, -
o
55 C
o
o
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -
14.95
-
V
o
55 C
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
1
1
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
o
+25 C
-
-
o
+25 C
o
Output Current
(Source)
IOH5A VDD = 5V, VOUT = 4.6V
+25 C
-0.53
o
Output Current
(Source)
IOH5B VDD = 5V, VOUT = 2.5V
1
1
1
+25 C
-
-
-
-1.8
-1.4
-3.5
mA
mA
mA
o
Output Current
(Source)
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
+25 C
o
Output Current
(Source)
+25 C
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
1
1
+25 C
-2.8
0.7
-0.7
2.8
V
V
V
o
VSS = 0V, IDD = 10µA
+25 C
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH> VOL
VDD/2
o
<
7
+25 C
VDD/2
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
+25 C, +125 C, -
-
3.5
-
1.5
V
V
V
V
o
55 C
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -
-
4
-
o
55 C
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -
o
55 C
o
o
Input Voltage High
(Note 2)
VIH
IOZL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -
11
o
55 C
o
Tri-State Output
Leakage
VIN = VDD or GND
VOUT = 0V
VDD = 20V
1
2
3
+25 C
-0.4
-12
-
-
-
µA
µA
µA
o
+125 C
o
VDD = 18V
-55 C
-0.4
7-1030
Specifications CD4076BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
SUBGROUP
UNIT
S
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
S
1
2
3
TEMPERATURE
MIN
MAX
0.4
12
o
Tri-State Output
Leakage
IOZH
VIN = VDD or GND
VOUT = VDD
VDD = 20V
+25 C
-
-
-
µA
µA
µA
o
+125 C
o
VDD = 18V
-55 C
0.4
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD.
implemented.
Limit is 0.050V max.
2. Go/No Go test with limits applied to inputs.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS (Notes 1, 2)
MAX
600
810
200
270
UNITS
ns
o
Propagation Delay
Clock to Q Output
TPHL
TPLH
VDD = 5V, VIN = VDD or GND
9
+25 C
-
-
-
-
o
o
10, 11
9
+125 C, -55 C
ns
o
Transition Time
NOTES:
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
+25 C
ns
o
o
10, 11
+125 C, -55 C
ns
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
o
-55 C
0.64
-
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-2.6
o
-55 C
o
+125 C
o
-55 C
o
IOH10
VDD = 10V, VOUT = 9.5V
+125 C
o
-55 C
7-1031
Specifications CD4076BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MAX
-2.4
-4.2
3
UNITS
mA
o
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125 C
-
-
-
o
-55 C
mA
o
o
Input Voltage Low
Input Voltage High
VIL
VDD = 10V, VOH > 9V, VOL <
1V
1, 2
1, 2
+25 C, +125 C,
V
o
-55 C
o
o
VIH
VDD = 10V, VOH > 9V, VOL <
1V
+25 C, +125 C,
7
-
V
o
-55 C
o
Propagation Delay
Clock to Q Output
TPHL1 VDD = 10V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 5
1, 2, 3, 5
1, 2, 3, 5
1, 2
+25 C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
6
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
250
180
460
200
150
300
150
120
300
150
120
100
80
ns
ns
TPLH1
o
VDD = 15V
+25 C
o
Propagation Delay
Reset
TPHL2 VDD = 5V
VDD = 10V
+25 C
ns
o
+25 C
ns
o
VDD = 15V
+25 C
ns
o
Propagation Delay
3 - State
TPHZ
TPLZ
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
+25 C
ns
o
+25 C
ns
o
+25 C
ns
o
Propagation Delay
3 - State
TPZH
TPZL
+25 C
ns
o
+25 C
ns
o
+25 C
ns
o
Transition Time
Transition Time
TTHL
TTLH
+25 C
ns
o
+25 C
ns
o
TTLH
FCL
+25 C
-
ns
o
+25 C
-
ns
o
Maximum Clock Input
Frequency
+25 C
-
MHz
MHz
MHz
ns
o
+25 C
-
o
+25 C
-
o
Minimum Data Setup
Time
TS
TW
TW
TS
+25 C
200
80
o
+25 C
ns
o
+25 C
60
ns
o
Minimum Data Hold Time
Reset Pulse Width
+25 C
120
50
ns
o
+25 C
ns
o
+25 C
40
ns
o
Minimum Clock Pulse
Width
+25 C
200
100
80
ns
o
+25 C
ns
o
+25 C
ns
o
Minimum Data Input Set-
Up Time
+25 C
180
100
70
ns
o
+25 C
ns
o
+25 C
ns
o
Maximum Clock Input
Rise and Fall Time
TRCL
TFCL
+25 C
15
µs
µs
µs
pF
o
+25 C
5
o
+25 C
5
o
Input Capacitance
CIN
+25 C
7.5
7-1032
Specifications CD4076BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN MAX
PARAMETER
NOTES:
1. All voltages referenced to device GND.
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
UNITS
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
O
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
7-1033
Specifications CD4076BMS
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
PRE-IRRAD POST-IRRAD
1, 9 Table 4
MIL-STD-883
CONFORMANCE GROUPS
METHOD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1 Note 1
Static Burn-In 2 Note 1
Dynamic Burn-In Note 1
Irradiation (Note 2)
NOTE:
OPEN
3 - 6
3 - 6
-
GROUND
VDD
16
9V ± -0.5V
50kHz
25kHz
1, 2, 7 - 15
8
1, 2, 7, 9 -16
16
1, 2, 8 - 10, 15
8
3 - 6
7
11 - 14
3 - 6
1, 2, 7, 9 - 16
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V
*
M
N
1
2
OUTPUT
DISABLE
*
16 VDD
D
Q
*
DATA
1
14
9
CL Q
R
3
4
5
Q1
Q2
Q3
*
*
DATA
INPUT
DISABLE
G1
G2 10
D
Q
*
*
DATA
2
13
7
CL Q
R
CLOCK
D
Q
*
DATA
3
12
CL Q
R
* ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VDD
D
Q
*
*
DATA
4
11
CL Q
R
6
8
Q4
VSS
VSS
RESET 15
FIGURE 1. CD4076BMS LOGIC DIAGRAM
7-1034
CD4076BMS
TRUTH TABLE
NEXT STATE
OUTPUT
DATA INPUT DISABLE
DATA
RESET
CLOCK
G1
X
X
1
G2
X
X
X
1
D
X
X
X
X
1
Q
0
1
0
0
0
0
0
0
0
X
0
Q
Q
Q
1
NC
NC
NC
X
0
0
0
0
0
0
1
X
X
X
X
X
X
Q
Q
NC
NC
When either Output Disable M or N is high, the outputs are disabled (high impedance state), however sequential operation of the flip-flops is not affected.
1 = High Level
0 = Low Level
X = Don’t Care
NC = No Change
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
7.5
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
7-1035
CD4076BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
500
400
300
200
150
100
50
SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 5V
200
100
10V
15V
10V
5V
0
0
20
40
60
80
100
0
20
40
60
80
100
120
140
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE (CLOCK TO Q)
FIGURE 7. TYPICAL TRANSITION TIME vs LOAD
CAPACITANCE
105
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50pF
15
AMBIENT TEMPERATURE (TA) = +25oC
8
6
4
2
SUPPLY VOLTAGE (VDD) = 15V
104
8
6
4
2
10V
103
102
10V
8
6
4
10
5
5V
2
8
6
4
2
10
1
8
6
4
CL = 50pF
CL = 15pF
2
2
4 6 8
2
4 6 8
2
4 6 8
2
4 6 8
103
2
4 6 8
2 4 6 8
0
5
10
15
20
10-1
1
10
INPUT FREQUENCY (f) (kHz)
102
104
SUPPLY VOLTAGE (VDD) (V)
FIGURE8. TYPICALMAXIMUMCLOCKINPUTFREQUENCYvs
SUPPLY VOLTAGE
FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION vs
FREQUENCY
tW
tW
CLOCK
50%
50%
tS
tS
tS
DATA
INPUT
DIABLE
50%
tW
50%
RESET
tTHL
tTLH
90%
50%
10%
Q
OUTPUT
tPHL
tPLH
tPHL
FIGURE 10. FUNCTIONAL WAVEFORM
7-1036
CD4076BMS
VDD
VSS
TEST
AT D
VDD
VSS
VSS
VDD
VOLTAGE
AT Q
VSS
50%
50%
OUTPUT DISABLE
CHARACTER
tPLZ
tPZL
90%
VDD
tPHZ
tPLZ
tPZL
tPZH
10%
90%
VDD
VOL
VOH
Q OUTPUT
Q OUTPUT
VDD
10%
tPZH
VSS
VSS
tPHZ
FIGURE 11. FUNCTIONAL WAVEFORM
Chip Dimensions and Pad Layout
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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1037
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