CD4089BFMSR [RENESAS]
4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, FRIT SEALED, DIP-16;
| 型号： | CD4089BFMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, FRIT SEALED, DIP-16 CD 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4089BMS
CMOS Binary Rate Multiplier
December 1992
conjunction with an up/down counter and control logic used
to perform arithmetic operations (adds, subtract, divide, raise
to a power), solve algebraic and differential equations,
generate natural logarithms and trigometric functions, A/D
and D/A conversions, and frequency division.
Features
• High Voltage Type (20V Rating)
• Cascadable in Multiples of 4 Bits
• Set to “15” Input and “15” Detect Output
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
For words of more than 4 bits, CD4089BMS devices may be
cascaded in two different modes: an Add mode and a Multi-
ply mode (see Figures 3 and 4). In the Add mode some of
the gaps left by the more significant unit at the count of 15
are filled in by the less significant units. For example, when
two units are cascaded in the Add mode and programmed to
11 and 13, respectively, the more significant unit will have 11
output pulses for every 16 input pulses and the other unit will
have 13 output pulses for every 256 input pulses for a total of
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
11
16
13
189
256
- 2V at VDD = 10V
+
=
256
- 2.5V at VDD = 15V
In the Multiply mode the fraction programmed into the first
rate multiplier is multiplied by the fraction programmed into
the second multiplier. Thus the output rate will be
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
11
16
13
16
143
256
x
=
Applications
• Numerical Control
• Instrumentation
• Digital Filtering
The CD4089BMS has an internal synchronous 4 bit counter
which, together with one of the four binary input bits, pro-
duces pulse trains as shown in Figure 6.
If more than one binary input bit is high, the resulting pulse
train is a combination of the separate pulse trains as shown
in Figure 6.
• Frequency Synthesis
Description
The CD4089BMS is supplied in these 16-lead outline packages:
CD4089BMS is a low power 4 bit digital rate multiplier that
provides an output pulse rate that is the clock-input-pulse
rate multiplied by /16 times the binary input. For example,
when the binary input number is 13, there will be 13 output
pulses for every 16 input pulses. This device may be used in
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H2R
H6P
1
Functional Diagram
Pinout
CD4089BMS
TOP VIEW
BINARY RATE
SELECT INPUTS
CLOCK
STROBE
10
9
INHIBIT
B
14 15
A
C
2
D
3
CASCADE
12
“15” OUT
1
2
3
4
5
6
7
8
16 VDD
(CARRY) IN
C
15 B
OUT
OUT
RATE
RATE
SELECT
LOGIC
11
6
5
D
14 A
SET TO
4 BIT
“15”
SET TO “15”
13 CLEAR
12 CASCADE
11 INHIBIT IN (CARRY)
10 STROBE
BINARY
COUNTER
4
OUT
OUTPUTS
OUT
INHIBIT OUT (CARRY)
VSS
CLEAR
13
“15” OUT
1
7
9
CLOCK
INHIBIT (CARRY) OUT
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3329
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1064
Specifications CD4089BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
VIH
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1065
Specifications CD4089BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS (NOTES 1, 2)
SUBGROUPS TEMPERATURE
MAX
300
405
760
1026
180
243
200
270
-
UNITS
ns
o
Propagation Delay
Clock to Output
TPHL1 VDD = 5V, VIN = VDD or GND
TPLH1
9
10, 11
9
+25 C
-
o
o
+125 C, -55 C
-
ns
o
Propagation Delay
Clear to Out
TPHL2 VDD = 5V, VIN = VDD or GND
TPLH2
+25 C
-
ns
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Propagation Delay
Cascade to Out
TPHL3 VDD = 5V, VIN = VDD or GND
TPLH3
+25 C
-
-
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Transition Time
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
+25 C
-
ns
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Maximum Clock Input
Frequency
FCL
VDD = 5V, VIN = VDD or GND
+25 C
1.2
.89
MHz
MHz
o
o
10, 11
+125 C, -55 C
-
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
VDD = 5V, No Load
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL5
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
VOL10 VDD = 10V, No Load
VOH5 VDD = 5V, No Load
VOH10 VDD = 10V, No Load
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
+125 C
0.36
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
o
-55 C
0.64
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
-
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
o
-55 C
o
+125 C
o
-55 C
o
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
+125 C
o
-55 C
o
+125 C
o
-55 C
7-1066
Specifications CD4089BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
o
o
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25 C, +125 C,
-
3
V
o
-55 C
o
o
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25 C, +125 C,
+7
-
V
o
-55 C
o
Propagation Delay
Clock to Out
TPHL4 VDD = 5V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
+25 C
-
-
220
110
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
TPLH4
o
VDD = 10V
+25 C
o
VDD = 15V
+25 C
-
o
Propagation Delay
Clock to Out
TPHL1 VDD = 10V
+25 C
-
150
120
720
320
220
500
200
150
350
260
90
TPLH1
o
VDD = 15V
+25 C
-
o
Propagation Delay
Clock to Inhibit Out
TPHL5 VDD = 5V
VDD = 10V
+25 C
-
o
+25 C
-
o
VDD = 15V
+25 C
-
o
Propagation Delay
Clock to Inhibit Out
TPLH5 VDD = 5V
VDD = 10V
+25 C
-
o
+25 C
-
o
VDD = 15V
+25 C
-
o
Propagation Delay
Clear to Out
TPHL2 VDD = 10V
+25 C
-
TPLH2
o
VDD = 15V
+25 C
-
o
Propagation Delay
Cascade to Out
TPHL3 VDD = 10V
+25 C
-
TPLH3
o
VDD = 15V
+25 C
-
70
o
Propagation Delay
Clock to “9” or “15” Out
TPHL6 VDD = 5V
+25 C
-
600
250
180
320
150
110
660
300
220
100
80
TPLH6
o
VDD = 10V
+25 C
-
o
VDD = 15V
+25 C
-
o
Propagation Delay
Inhibit In to Inhibit Out
TPHL7 VDD = 5V
+25 C
-
TPLH7
o
VDD = 10V
+25 C
-
o
VDD = 15V
+25 C
-
o
Propagation Delay Set
to Out
TPHL8 VDD = 5V
+25 C
-
TPLH8
o
VDD = 10V
+25 C
-
o
VDD = 15V
+25 C
-
o
Transition Time
TTHL
TTLH
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
+25 C
-
o
+25 C
-
o
Maximum Clock Input
Frequency
FCL
+25 C
2.5
3.5
-
-
o
+25 C
-
o
Minimum Inhibit-In Setup
Time
TSU
+25 C
100
40
o
+25 C
-
o
+25 C
-
20
o
Minimum Inhibit-In
Removal Time
TREM
TW
+25 C
-
240
130
110
330
170
100
15
o
+25 C
-
o
+25 C
-
o
Minimum Clock Pulse
Width
+25 C
-
o
+25 C
-
o
+25 C
-
o
Maximum Clock Rise and
Fall Time
TRCL
TFCL
+25 C
-
o
+25 C
-
15
o
+25 C
-
15
7-1067
Specifications CD4089BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
VDD = 5V
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
MIN
MAX
150
80
UNITS
ns
o
Minimum Set Removal
Time
TREM
+25 C
-
-
-
-
-
-
-
-
-
-
o
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
+25 C
ns
o
+25 C
50
ns
o
Minimum Clear Removal
Time
TREM
TW
+25 C
60
ns
o
+25 C
40
ns
o
+25 C
30
ns
o
Minimum Set or Clear
Pulse Width
+25 C
160
90
ns
o
+25 C
ns
o
+25 C
60
ns
o
Input Capacitance
NOTES:
CIN
+25 C
7.5
pF
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
o
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
METHOD
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
7-1068
Specifications CD4089BMS
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
1, 7, 9
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1
(Note 1)
1, 5-7
2-4, 8-15
16
Static Burn-In 2
(Note 1)
1, 5-7
-
8
2-4, 9-16
3, 16
Dynamic Burn-
In (Note 1)
2, 4, 8, 10, 12-15
8
1, 5-7
9
11
Irradiation
(Note 2)
1, 5-7
2-4, 9-16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-1069
CD4089BMS
Logic Diagram
A
*14
B
*15
C
*2
*10 *12
STROBE
CASCADE
Qd
Qc
Qb
Qa
D
OUT
OUT
*3
6
5
CLOCK
*9
Qc
Qa
Qa
Qb
Qb
Qc
Qc
Qd
Qd
Qb
Qa
CLEAR
*13
SYNCHRO-
NOUS 4 BIT
BINARY
Qb
Qa
COUNTER
SET TO “15”
*4
Qa
Qb
Qc
Qd
“15”
1
Qa
INHIBIT IN
*11
INHIBIT OUT
7
Qa
Qb
Qc
Qd
VDD
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
FIGURE 1. LOGIC DIAGRAM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
1070
CD4089BMS
TRUTH TABLE
INPUTS
OUTPUTS
NUMBER OF PULSES OR INPUT LOGIC LEVEL
NUMBER OF PULSES OR OUTPUT LOGIC LEVEL
(0 = Low; 1 = High; X = Don’t Care)
(L = Low; H = High)
D
C
B
A
CLK
INH IN
STR
CAS
CLR
SET
OUT
OUT
INH OUT
“15” OUT
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
16
16
16
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L
1
2
3
H
1
2
3
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
16
16
16
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
5
6
7
4
5
6
7
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
16
16
16
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
9
10
11
8
9
10
11
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16
16
16
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12
13
14
15
12
13
14
15
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
16
16
16
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
**
L
H
**
H
*
H
1
1
**
1
1
1
0
X
X
X
X
X
X
X
X
X
X
16
16
16
0
0
0
0
0
0
0
0
0
1
1
X
0
0
1
16
L
L
16
H
H
H
H
L
L
L
H
* Output same as the first 16 lines of this truth table (depending on values A, B, C, D)
** Depends on internal state of counter
MOST SIGNIFICANT
DIGIT
LEAST SIGNIFICANT
DIGIT
MOST SIGNIFICANT
DIGIT
LEAST SIGNIFICANT
DIGIT
1
1
0
1
1
0
1
1
1
1
0
1
1
0
1
1
A
A
A
A
B
C
D
OUT
OUT
B
C
D
OUT
OUT
B
C
D
OUT
OUT
B
C
D
OUT
OUT
DRM
1
DRM
2
DRM
1
DRM 2
INH OUT
“15”
S
INH OUT
“15”
S
INH OUT
“15”
S
INH OUT
“15”
S
CLOCK
CASC
CLOCK
CASC
CLOCK
CASC
CLOCK
CASC
INH IN
INH IN
INH IN
INH IN
ST
CLEAR
ST
CLEAR
ST
CLEAR
ST
CLEAR
CLOCK
CLOCK
FIGURE 2. TWO CD4089BMS’s CASCADED IN THE “ADD”
MODE WITH A PRESET NUMBER
FIGURE 3. TWO CD4089BMS’s CASCADED IN THE “MULTI-
PLY” MODE WITH A PRESET NUMBER
11
16
13
256
189
256
11
16
13
16
143
256
+
=
+
=
OF 189
OF 143
7-1071
CD4089BMS
CLOCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
COUNTER STATE
*
(LSB) INPUT A = H
INPUT B = H
OUTPUT
WAVE TRAINS
(TERM 6)
INPUT C = H
(MSB) INPUT D = H
AN OUTPUT BIT MAY BE FILLED IN THIS COUNTER STATE
BY A LESS SIGNIFICANT CD4089 CASCADED IN THE ADD MODE
*
FIGURE 4. TIMING DIAGRAM
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
12.5
10.0
7.5
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 5. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 6. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 7. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 8. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
7-1072
CD4089BMS
Typical Performance Characteristics (Continued)
200
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
150
200
SUPPLY VOLTAGE (VDD) = 15V
10V
SUPPLY VOLTAGE (VDD) = 5V
150
100
50
100
50
5V
10V
15V
0
0
20
40
60
80
100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE9. TYP.PROPAGATIONDELAYTIMESASFUNCTIONOF
LOAD CAPACITANCE (CLOCK OR STROBE TO OUT)
FIGURE 10. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
105
8
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
6
4
2
104
103
8
6
4
10V
10V
2
5V
8
6
4
2
102
10
8
6
4
CL = 50pF
CL = 15pF
2
2
4
6 8
2
4
6 8
102
2
4
6 8
103
2
4
6 8
104
2
4 6 8
1
10
INPUT FREQUENCY (fIN) (kHz)
FIGURE 11. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1073
相关型号：
CD4089BMJ
4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-16
TI
CD4089BMJ
IC 4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-16, Counter
NSC
CD4089BMN
4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16, PLASTIC, DIP-16
TI
CD4089BPW
4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, GREEN, PLASTIC, TSSOP-16
TI
CD4089BPWE4
IC 4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, GREEN, PLASTIC, TSSOP-16, Counter
TI
CD4089BPWG4
4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, GREEN, PLASTIC, TSSOP-16
TI
©2020 ICPDF网 联系我们和版权申明