CD4504BHMSR [RENESAS]
HEX TTL/CMOS TO CMOS TRANSLATOR, TRUE OUTPUT, UUC16, DIE-16;
| 型号： | CD4504BHMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | HEX TTL/CMOS TO CMOS TRANSLATOR, TRUE OUTPUT, UUC16, DIE-16 输出元件 接口集成电路 锁存器 |
| 文件： | 总8页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4504BMS
CMOS Hex Voltage Level Shifter for
TTL-to-CMOS or CMOS-to-CMOS Operation
December 1992
Features
Pinout
CD4504BMS
TOP VIEW
• High Voltage Type (20V Rating)
• Independence of Power Supply Sequence Consider-
ations
VCC
AOUT
AIN
1
2
3
4
5
6
7
8
16 VDD
- VCC can Exceed VDD
15 FOUT
14 FIN
- Input Signals can Exceed Both VCC and VDD
• Up and Down Level Shifting Capability
BOUT
BIN
13 SELECT
12 EOUT
11 EIN
• Shiftable Input Threshold for Either CMOS or TTL
Compatibility
COUT
CIN
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
10 DOUT
9
DIN
VSS
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Functional Diagram
VCC
VDD
Description
* IN
OUT
CD4504BMS hex voltage level shifter consists of six circuits
which shift input signals from the VCC logic level to the VDD
logic level. To shift TTL signals to CMOS logic levels, the
SELECT input is at the VCC HIGH logic state. When the
SELECT input is at a LOW logic state, each circuit translates
signals from one CMOS level to another.
LEVEL
SHIFTER
(3, 5, 7, 9, 11, 14)
(2, 4, 6, 10, 12, 15)
VCC = PIN 1
VDD = PIN 16
VSS = PIN 8
TTL/CMOS
MODE SELECT
*
SELECT
13
The CD4504BMS is supplied in these 16-lead outline packages:
Frit Seal DIP
H1F
Ceramic Flatpack
H6W
VDD
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
*
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3336
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1140
Specifications CD4504BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
2
200
2
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
1
+25 C
-
-
-
-
100
1000
100
50
-
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
1
1
1
1
1
1
1
1
7
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
+25 C
-
o
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
+25 C
-
o
+25 C
-
o
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
+25 C
-2.8
0.7
o
+25 C
V
o
VDD = 4.5V, VCC = 2.8,
VIN = VDD or GND
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
VDD = 4.5V, VCC = 3.0,
VIN = VDD or GND
8B
8A
8A
8A
7
-55 C
o
VDD = 18V, VCC = 18V,
VIN = GND or VCC
+125 C
o
VDD = 18V, VCC = 4.5V,
VIN = VCC or GND
+125 C
o
VDD = 4.5V, VCC = 18V,
VIN = VCC or GND
+125 C
o
VDD = 20V, VCC = 20V,
VIN = GND or VCC
+25 C
o
VDD = 20V, VCC = 4.5V,
VIN = VCC or GND
7
+25 C
o
VDD = 4.5V, VCC = 20V,
VIN = VCC or GND
7
+25 C
7-1141
Specifications CD4504BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
o
o
Input Voltage Low
(Note 2) TTL-CMOS
VIL
VDD = 15V, VOH > 13.5V, VOL < 1V
VCC = 5V
1, 2, 3
+25 C, +125 C, -55 C
-
2
-
0.8
V
V
V
V
V
V
o
o
o
Input Voltage High
(Note 2) TTL-CMOS
VIH
VIL
VIH
VIL
VIH
VDD = 15V, VOH > 13.5V, VOL < 1V
VCC = 5V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C
-
1.5
-
o
o
o
Input Voltage Low
(Note 2) CMOS-CMOS
VDD = 10V, VOH > 9V, VOL < 1V
VCC = 5V
+25 C, +125 C, -55 C
o
o
o
Input Voltage High
(Note 2)CMOS-CMOS
VDD = 10V, VOH > 9V, VOL < 1V
VCC = 5V
+25 C, +125 C, -55 C 3.5
o
o
o
Input Voltage Low
(Note 2) CMOS-CMOS
VDD = 15V, VOH > 13.5V, VOL <
1.5V, VCC = 10V
+25 C, +125 C, -55 C
-
3
o
o
o
Input Voltage High
(Note 2) CMOS-CMOS
VDD = 15V, VOH > 13.5V, VOL <
1.5V, VCC = 10V
+25 C, +125 C, -55 C
7
-
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1, 2)
SUBGROUPS TEMPERATURE
MIN
MAX
280
UNITS
ns
o
Propagation Delay
TTL to CMOS
VDD > VCC
TPHL1 VDD = 10V, VIN = VCC or GND
VCC = 5V
9
+25 C
-
-
o
o
10, 11
+125 C, -55 C
378
ns
o
Propagation Delay
CMOS to CMOS VDD >
VCC
TPHL2 VDD = 10V, VIN = VCC or GND
VCC = 5V
9
+25 C
-
-
240
324
ns
ns
o
o
10, 11
+125 C, -55 C
o
Propagation Delay
CMOS to CMOS VCC >
VDD
TPHL3 VDD = 5V, VIN = VCC or GND
VCC = 10V
9
+25 C
-
-
550
743
ns
ns
o
o
10, 11
+125 C, -55 C
o
Propagation Delay
TTL to CMOS
VDD > VCC
TPLH1 VDD = 10V, VIN = VCC or GND
VCC = 5V
9
+25 C
-
-
280
378
ns
ns
o
o
10, 11
+125 C, -55 C
o
Propagation Delay
CMOS to CMOS VDD >
VCC
TPLH2 VDD = 10V, VIN = VCC or GND
VCC = 5V
9
+25 C
-
-
240
324
ns
ns
o
o
10, 11
+125 C, -55 C
o
Propagation Delay
CMOS to CMOS VCC >
VDD
TPLH3 VDD = 5V, VIN = VCC or GND
VCC = 10V
9
+25 C
-
-
400
540
ns
ns
o
o
10, 11
+125 C, -55 C
o
Transition Time
TTHL
TTLH
All Modes
9
+25 C
-
-
200
270
ns
ns
o
o
10, 11
+125 C, -55 C
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
7-1142
Specifications CD4504BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
1
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
30
2
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
60
2
µA
o
o
-55 C, +25 C
µA
o
+125 C
120
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
o
-55 C
0.64
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
-
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
0.8
o
-55 C
o
+125 C
o
-55 C
o
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
+125 C
o
-55 C
o
+125 C
o
-55 C
o
o
Input Voltage Low
TTL - CMOS
VIL
VIH
VIL
VIH
VDD = 10V, VOH > 9V,
VOL < 1V, VCC = 5V
1, 2
1, 2
+25 C, +125 C,
o
-55 C
o
o
Input Voltage High
TTL - CMOS
VDD = 10V, VOH > 9V,
VOL < 1V, VCC = 5V
+25 C, +125 C,
2
-
-
1.5
-
V
V
o
-55 C
o
o
Input Voltage Low
CMOS - CMOS
VDD = 15V, VOH > 13.5V,
VOL < 1.5V, VCC = 5V
1, 2
+25 C, +125 C,
o
-55 C
o
o
Input Voltage High
CMOS - CMOS
VDD = 15V, VOH > 13.5V,
VOL < 1.5V, VCC = 5V
1, 2
+25 C, +125 C,
3.5
-
V
o
-55 C
o
Propagation Delay
TPHL1 VDD = 15V, VCC = 5V
1, 2, 3
+25 C
280
ns
TTL - CMOS, VDD > VCC
o
Propagation Delay
CMOS - CMOS,
VDD > VCC
TPHL2 VDD = 15V, VCC = 5V
VDD = 15V, VCC = 10V
1, 2, 3
1, 2, 3
+25 C
-
-
240
140
ns
ns
o
+25 C
o
Propagation Delay
CMOS - CMOS,
VCC > VDD
TPHL3 VDD = 5V, VCC = 15V
VDD = 10V, VCC = 15V
1, 2, 3
1, 2, 3
+25 C
-
-
550
140
ns
ns
o
+25 C
o
Propagation Delay
TPLH1 VDD = 15V, VCC = 5V
1, 2, 3
+25 C
-
280
ns
TTL - CMOS, VDD > VCC
7-1143
Specifications CD4504BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
1, 2, 3
1, 2, 3
TEMPERATURE
MIN
MAX
240
UNITS
ns
o
Propagation Delay
CMOS - CMOS,
VDD > VCC
TPLH2 VDD = 15V, VCC = 5V
VDD = 15V, VCC = 10V
+25 C
-
-
o
+25 C
140
ns
o
Propagation Delay
CMOS - CMOS
VCC > VDD
TPLH3 VDD = 5V, VCC = 15V
VDD = 10V, VCC = 15V
1, 2, 3
1, 2, 3
+25 C
-
-
400
120
ns
ns
o
+25 C
o
Transition Time
TTHL
TTLH
VDD = 10V
VDD = 15V
Any Input
1, 2, 3
1, 2, 3
1, 2
+25 C
-
-
-
100
80
ns
ns
pF
o
+25 C
o
Input Capacitance
NOTES:
CIN
+25 C
7.5
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
7.5
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
o
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 0.2µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
7-1144
Specifications CD4504BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
MIL-STD-883
CONFORMANCE GROUP
Interim Test 3 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 2, 4, 6, 10, 12, 15
(Note 1)
3, 5, 7-9, 11, 14
16
1, 13
Static Burn-In 2 2, 4, 6, 10, 12, 15
(Note 1)
8
8
8
16
16
1, 3, 5, 7, 9, 11,
13, 14
Dynamic Burn-
In (Note 1, 3)
-
1, 2, 4, 6, 10, 12,
15
3, 5, 7, 9, 11, 14
Irradiation
(Note 2)
2, 4, 6, 10, 12, 15
1, 3, 5, 7, 9, 11, 13,
14, 16
NOTES:
1. Each pin except VCC, VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VCC, VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
3. Oscillator output to be VDD/2.
7-1145
CD4504BMS
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
7.5
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
*VSWITCH = INPUT VOLTAGE
AT WHICH OUTPUT LEVEL
IS 50% OF VDD - VSS
VCC
VCC
10
10
VIN
*VSWITCH
VIN
*VSWITCH
VSS
VCC = 15V
VSS
8
8
VDD
VDD
50%
50%
VOUT
6
6
4
2
0
VOUT
VSS
VSS
ENABLE = VCC
VCC = 10V
4
ENABLE = VCC
2
0
VCC = 5V
*VSWITCH = INPUT VOLTAGE
AT WHICH OUTPUT LEVEL
IS 50% OF VDD - VSS
AMBIENT TEMPERATURE (TA) = +25oC
2.5
5
7.5
10
12.5
15
17.5
20
2.5
5
7.5
10
12.5
15
17.5
20
SUPPLY VOLTAGE (VDD) (V)
SUPPLY VOLTAGE (VDD) (V)
FIGURE 5. TYPICAL INPUT SWITCHING AS A FUNCTION OF
HIGH LEVEL SUPPLY VOLTAGE (SELECT AT
VCC-CMOS MODE)
FIGURE 6. TYPICAL INPUT SWITCHING AS A FUNCTION OF
HIGH LEVEL SUPPLY VOLTAGE (SELECT AT
VSS-TTL MODE)
7-1146
CD4504BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE
(TA) = +25oC
CMOS MODE =
RECOMMENDED
OPERATING
CONDITIONS
25
20
15
10
5
TTL MODE =
0
5
10
15
20
25
SUPPLY VOLTAGE (VCC) (V)
FIGURE 7. HIGH LEVEL SUPPLY VOLTAGE vs LOW LEVEL SUPPLY VOLTAGE
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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