CD4536BHMSR [RENESAS]
4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 24-BIT UP BINARY COUNTER, UUC16, DIE-16;
| 型号： | CD4536BHMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 24-BIT UP BINARY COUNTER, UUC16, DIE-16 |
| 文件： | 总13页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4536BMS
CMOS Programmable Timer
December 1992
Features
Description
• High Voltage Type (20V Rating)
• 24 Flip-Flop Stage - Counts from 20 to 224
• Last 16 Stages Selectable by BCD Select Code
• Bypass Input Allows Bypassing First 8 Stages
• On-Chip RC Oscillator Provision
• Clock Inhibit Input
CD4536BMS is a programmable timer consisting of 24 ripple
binary counter stages. The salient feature of this device is its
flexibility. The device can count from 1 to 224 or the first 8
stages can be bypassed to allow an output, selectable by a
4-bit code, from any one of the remaining 16 stages. It can
be driven by an external clock or an RC oscillator that can be
constructed using on-chip components. Input IN1 serves as
either the external clock input or the input to the on-chip RC
oscillator. OUT1 and OUT2 are connection terminals for the
external RC components. In addition, an on-chip monostable
circuit is provided to allow a variable pulse width output. Var-
ious timing functions can be achieved using combinations of
these capabilities.
• Schmitt Trigger in clock Line Permits Operation with
Very Long Rise and Fall Times
• On-Chip Monostable Output Provision
• Typical fCL = 3MHz at VDD = 10V
• Test Mode Allows Fast Test Sequence
• Set and Reset Inputs
A logic 1 on the 8-BYPASS input enables a bypass of the
first 8 stages and makes stage 9 the first counter stage of
the last 16 stages. Selection of 1 of 16 outputs is accom-
plished by the decoder and the BCD inputs A, B, C and D.
MONO IN is the timing input for the on-chip monostable
oscillator. Grounding of the MONO IN terminal through a
resistor of 10kΩ or higher, disables the one-shot circuit and
connects the decoder directly to the DECODE OUT terminal.
A resistor to VDD and a capacitor to ground from the MONO
IN terminal enables the one-shot circuit and controls its
pulse width.
• Capable of Driving Two Low Power TTL Loads, One
Lower Power Schottky Load, or Two HTL Loads Over
the Rated Temperature Range
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
A fast test mode is enabled by a logic 1 on 8-BYPASS, SET,
and RESET. This mode divides the 24-stage counter into
three 8-stage sections to facilitate a fast test sequence.
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
The CD4536BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
Functional Diagram
Pinout
CD4536BMS
TOP VIEW
CLOCK
INHIBIT
IN 1
OSC
INHIBIT
RS
SET
RESET
1
2
3
4
5
6
7
8
16 VDD
8-BYPASS
6
14
7
3
15 MONO IN
14 OSC INHIBIT
13 DECODE OUT
12 D
IN 1
9
4
A
RT
OUT 1
OUT 1
10
B
BINARY
SELECT
11
12
1
5
OUT 2
C
D
OUT 2
8-BYPASS
CLOCK INHIBIT
VSS
11
C
BINARY
SELECT
13
DECODE
OUT
10 B
SET
2
RESET
9
A
15
VSS = 8
VDD = 16
MONO IN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3345
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1236
Specifications CD4536BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For T = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
A
o
o
For T = +100 C to +125 C (Package Type D, F, K). . . . . .Derate
A
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
For T = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
A
o
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
VIN = VDD or GND
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
VIH
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1237
Specifications CD4536BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1, 2)
SUBGROUPS TEMPERATURE
MIN
MAX
2000
2700
UNITS
ns
o
Propagation Delay
Clock to Q1 8-Bypass
High
TPHL1 VDD = 5V, VIN = VDD or GND
TPLH1
9
+25 C
-
-
o
o
10, 11
+125 C, -55 C
ns
o
Propagation Delay
Clock to Q1 8-Bypass
Low
TPHL2 VDD = 5V, VIN = VDD or GND
TPLH2
9
+25 C
-
-
5000
6750
ns
ns
o
o
10, 11
+125 C, -55 C
o
Propagation Delay
Clock to Q16
TPHL3 VDD = 5V, VIN = VDD or GND
TPLH3
9
10, 11
9
+25 C
-
-
8000
10800
6000
8100
200
270
-
ns
ns
o
o
+125 C, -55 C
o
Propagation Delay
Reset to QN
TPHL4 VDD = 5V, VIN = VDD or GND
+25 C
-
ns
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Transition Time
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
+25 C
-
ns
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Maximum Clock Input
Frequency
FCL
+25 C
.5
.37
MHz
MHz
o
o
10, 11
+125 C, -55 C
-
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C, -
mV
o
55 C
o
o
+25 C, +125 C, -
-
50
-
mV
V
o
55 C
o
o
+25 C, +125 C, -
4.95
9.95
o
55 C
o
o
+25 C, +125 C, -
-
V
o
55 C
o
+125 C
0.36
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
o
-55 C
0.64
-
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
o
-55 C
o
+125 C
o
-55 C
o
IOH10
VDD = 10V, VOUT = 9.5V
+125 C
o
-55 C
7-1238
Specifications CD4536BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MAX
-2.4
-4.2
3
UNITS
mA
mA
V
o
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125 C
-
o
-55 C
-
o
o
o
Input Voltage Low
Input Voltage High
Propagation Delay
VIL
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25 C, +125 C, -55 C
-
o
o
o
VIH
1, 2
+25 C, +125 C, -55 C
+7
-
V
o
TPHL1 VDD = 10V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+25 C
-
1000
700
1600
1200
3000
2000
300
150
100
600
250
160
2000
1500
100
80
ns
Clock to Q1 8-Bypass High TPLH1
o
VDD = 15V
TPHL2 VDD = 10V
Clock to Q1 8-Bypass Low TPLH2
+25 C
-
ns
o
Propagation Delay
+25 C
-
ns
o
VDD = 15V
+25 C
-
ns
o
Propagation Delay
Clock to Q16
TPHL3 VDD = 10V
TPLH3
+25 C
-
ns
o
VDD = 15V
+25 C
-
ns
o
Propagation Delay
Qn to Qn+1
TPHL
TPLH
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
+25 C
-
o
+25 C
-
o
+25 C
-
o
Propagation Delay
Set to Qn
TPLH
+25 C
-
o
+25 C
-
o
+25 C
-
o
Propagation Delay
Reset to Qn
TPHL4 VDD = 10V
VDD = 15V
+25 C
-
-
ns
ns
o
+25 C
o
Transition Time
TTHL
TTLH
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
+25 C
-
ns
o
+25 C
-
ns
o
Maximum Clock Input
Frequency. Unlimited In-
put Rise or Fall Time
FCL
+25 C
1.5
2.5
-
MHz
MHz
o
+25 C
-
o
Minimum Clock Pulse
Width
TW
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
+25 C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
150
100
400
200
120
6
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
pF
o
+25 C
o
+25 C
o
Minimum Set Pulse Width
TW
TW
+25 C
o
+25 C
o
+25 C
o
Minimum Reset Pulse
Width
+25 C
o
+25 C
2
o
+25 C
1.5
5
o
Minimum Set Recovery
Time
TREM
TREM
CIN
+25 C
o
+25 C
2
o
+25 C
1.6
7
o
Minimum Reset Recov-
ery Time
+25 C
o
+25 C
3
o
+25 C
2
o
Input Capacitance
NOTES:
+25 C
7.5
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
7-1239
Specifications CD4536BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
o
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Table 4
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
7-1240
Specifications CD4536BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
50kHz 25kHz
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
Static Burn-In 1
Note 1
4, 5, 13
1-3, 6-12, 14, 15
16
Static Burn-In 2
Note 1
4, 5, 13
-
8
1-3, 6, 7, 9-12,
14-16
Dynamic Burn-
In Note 1
1, 2, 6-8, 14, 15
8
9-12, 16
4, 5, 13
3
Irradiation
Note 2
4, 5, 13
1-3, 6, 7, 9-12,
14-16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V
Logic Diagram
6
8-BYPASS
*
VDD
VSS
*
RESET
SET
2
*
1
*INPUTS PROTECTED BY CMOS
PROTECTION NETWORK
S
Q
CLOCK
INH
*
CLDIS
CL
R
p
n
7
A
B
FF25
p
n
C
D
E
F
R
R
D
Q
φ R
φ
Q
Q
φ R
φ
Q
Q
CLEN
Q
CL
Q
CL Q
FF2
FF1
FF3
FF8
CL
OSC
INH
*
14
*
IN 1
OUT 1
OUT 2
3
RS
RT
CT
*
4
*
5
1
NOTE: f ≈
, RS ≈ (5 → 10) x RT
3RT CT
G
FIGURE 1.
7-1241
CD4536BMS
Logic Diagram (Continued)
A
p
n
B
p
n
C
D
E
F
R
Q
R
φR
φ
D
Q
φ R
φ
Q
Q
φ R
φ
Q
Q
Q
Q
φ R
φ
Q
Q
φ R
φ
Q
Q
CLDIS
CL
Q
CL Q
FF10
FF9
FF11
FF16
FF17
FF18
FF24
1 OF 16 DECODER (TRANSMISSION-GATE TREE LOGIC)
VSS
N
P
DECODE
OUT
13
9
11
10
*
*
*
*
12
D
A
B
C
15
MONO IN
*
G
DETAIL FOR
FF3-8, 11-16, 17-24
DETAIL FOR
FF1, FF2, FF10, FF9, FF25
CLEN (CLDIS FOR FF9 AND FF25)
Q
Q
Q
Q
φ
φ
S
φ
Q
p
e
n
R
φ
R
R
VDD
p
c
n
p
a
n
c
D
b
d
f
N
φ
φ
p
f
P
P
P
φ
p
d
n
φ
Q
p
b
n
n
φ
φ
φ
a
P
N
p
n
Q
φ
N
φ
φ
CL
e
φ
R
φ
N
P
R
φ
N
φ
p
n
φ
P
R
R
R
R
CLEN
D
Q
Q
CLDIS
Q
Q
CLDIS
Q
Q
N
CL
Q
CL
CL
CL
S
N
R
Q
FF1
FF2, 10
FF9
FF25
N
FF1: AS SHOWN EXCEPT Q NOT BROUGHT OUT
FF9: SAME AS FF1 EXCEPT Q IS BROUGHT OUT AND Q, Q GO TO TGf AND TGe RESP.
φ
VSS
FF2, FF10: DELETE TGe, TGf, AND INVf; FEED Q TO D; DELETE CLEN, CLDIS
FF25: INVa AND INVd BECOME 2-INPUT NAND GATES, WITH ADDED INPUTS S; FEED Q
TO TGf VSS TO TGe PREVIOUS Q INPUT; DELETE Q OUTPUT
FIGURE 1. (Continued)
7-1242
CD4536BMS
TRUTH TABLE
IN
SET
0
RESET
CLOCK INH
OSC INH
OUT1
OUT2
DECODE OUT
No Change
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
X
0
Advance to Next State
X
X
X
0
1
0
0
1
1
1
0
0
0
No Change
No Change
Advance to Next State
0
0
1
1
0
0 = Low Level 1 = High Level X = Don’t Care
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
12.5
10.0
7.5
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
20
15
10V
10V
10
5
5.0
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
7-1243
CD4536BMS
Typical Performance Characteristics (Continued)
2
1.5
1
4
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 5V
3
2
1
0
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
10V
15V
0.5
0
0
20
40
60
80
100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
(CLOCK TO Q1, 8-BYPASS HIGH)
(CLOCK TO Q1, 8-BYPASS LOW)
200
2
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 5V
150
1.5
SUPPLY VOLTAGE (VDD) = 5V
1
100
10V
15V
10V
50
0.5
15V
0
0
0
20
40
60
80
100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
(QN TO QN + 1)
(CLOCK TO Q16, 8-BYPASS HIGH)
103
8
AMBIENT TEMPERATURE (TA) = +25oC
6
60
4
2
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 10V
1
EXTERNAL RESISTANCE (RE) = 56kΩ
EXTERNAL CAPACITANCE (CX) = 1000pF
102
50
40
30
20
10
0
f =
8
6
4
2
3Rtc CT
f vs Rtc
CT = 1000pF
RS = 2Rtc
10
0
8
6
4
2
RS = 0, f = 7900Hz
f vs CT
Rtc = 56kΩ
RS = 120kΩ
8
6
4
2
10-1
10-2
RS = 120kΩ, f = 5900Hz
8
6
4
2
2
4
6 8
2
4
6 8
2
4
6 8
2
4 6 8
-10
-20
102
103
104
105
106
EXTERNAL CAPACITANCE (CT) (pF)
5
6
7
8
9
10
11
12
13
14
15
1
10
EXTERNAL RESISTANCE (Rtc) (kΩ)
102 103
104
SUPPLY VOLTAGE (VDD) (V)
FIGURE 10. TYPICAL RC OSCILLATOR FREQUENCY
DEVIATION AS A FUNCTION OF SUPPLY
VOLTAGE
FIGURE 11. TYPICAL RC OSCILLATOR FREQUENCY
DEVIATION AS A FUNCTION OF TIME CONSTANT
RESISTANCE AND CAPACITANCE
7-1244
CD4536BMS
Typical Performance Characteristics (Continued)
10.0
10.0
7.5
Rtc = 56kΩ
RS = 0
Rtc = 56kΩ
RE = 120kΩ
CX = 1000pF
7.5
5.0
CX = 1000pF
5.0
SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 5V
2.5
2.5
10V
15V
10V
15V
15V
15V
10V
0
0
10V
5V
-2.5
-5.0
-7.5
-10.0
-2.5
-5.0
-7.5
-10.0
5V
-50
0
50
100
150
-50
0
50
100
150
AMBIENT TEMPERATURE (TA) o
C
AMBIENT TEMPERATURE (TA) o
C
FIGURE 12. TYPICAL RC OSCILLATOR FREQUENCY
DEVIATION AS A FUNCTION OF AMBIENT
TEMPERATURE (RS = 0)
FIGURE 13. TYPICAL RC OSCILLATOR FREQUENCY
DEVIATION AS A FUNCTION OF AMBIENT
TEMPERATURE (RS = 120kΩ)
103
8
103
8
AMBIENT TEMPERATURE (TA) = +25oC
6
AMBIENT TEMPERATURE (TA) = +25oC
6
4
4
SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 10V
2
2
102
102
8
6
4
8
6
4
2
2
RX = 1mΩ
10
8
6
4
10
RX = 1mΩ
8
6
4
2
2
100K
100kΩ
50kΩ
1
8
1
8
6
4
50K
6
4
2
2
10K
10kΩ
0.1
0.1
2
4
6 8
2
4
6 8
2
4
6 8
2
4
6 8
2
4
6 8
2
4
6 8
2
4
6 8
2
4
6 8
2
4
6 8
2
4 6 8
1
10
EXTERNAL CAPACITANCE (CX) (pF)
102
103
104
105
1
10
EXTERNAL CAPACITANCE (CX) (pF)
102
103
104
105
FIGURE 14. TYPICAL PULSE WIDTH AS A FUNCTION OF
EXTERNAL CAPACITANCE (VDD = 5V)
FIGURE 15. TYPICAL PULSE WIDTH AS A FUNCTION OF
EXTERNAL CAPACITANCE (VDD = 10V)
103
8
AMBIENT TEMPERATURE (TA) = +25oC
6
AMBIENT TEMPERATURE (TA) = +25oC
4
SUPPLY VOLTAGE (VDD) = 15V
2
102
8
6
4
200
2
SUPPLY VOLTAGE (VDD) = 5V
150
10
RX = 1mΩ
8
6
4
2
100
10V
15V
1
100kΩ
50kΩ
8
6
4
50
2
10kΩ
0.1
2
4
6 8
2
4
6 8
2
4
6 8
2
4
6 8
2
4 6 8
0
1
10
EXTERNAL CAPACITANCE (CX) (pF)
102
103
104
105
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 16. TYPICAL PULSE WIDTH AS A FUNCTION OF
EXTERNAL CAPACITANCE (VDD = 15V)
FIGURE 17. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
7-1245
CD4536BMS
Typical Performance Characteristics (Continued)
105
8
AMBIENT TEMPERATURE (TA) = +25oC
6
4
2
104
8
SUPPLY VOLTAGE (VDD) = 15V
10V
6
4
2
103
5V
8
6
4
2
102
10
8
6
4
CL = 50pF
CL = 15pF
2
2
4
6 8
2
4
6 8
10
2
4
6 8
2
4 6 8
0.1
1
102
103
PULSE INPUT FREQUENCY (kHz)
FIGURE 18. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT PULSE FREQUENCY
Applications
VDD
VDD
16
CX
9
10
11
12
1
RX
A
B
OUT 1
1
2
16
Q1
C
4
5
R
+TR
-TR
D
SET
3
CL
R
2
RESET
8-BYPASS
C INH
MONO IN
OUT 2
12
11
13
+TR
6
CODE OUT
-TR
R
(CL ÷ 8)
15
14
Q1 OUTPUT
CD4098BMS
15 14
8
DECODE
OUT
OSC INH
IN 1
>10K
8
VSS
FIGURE 19. APPLICATION SHOWING USE OF CD4098BMS AND CD4536BMS TO GET DECODE PULSE 8 CLOCK PULSES AFTER
RESET PULSE
VDD
VDD
A
B
C
D
A
B
C
D
OUT 1
OUT 2
OUT 1
SET
SET
RESET
8-BYPASS
C INH
RESET
8-BYPASS
C INH
OUT 2
R
t
MONO IN
MONO IN
≥10kΩ
DECODE
OUT
DECODE
OUT
CL
OSC INH
IN 1
OSC INH
IN 1
t
CLOCK
CLOCK
VSS
VSS
FIGURE 20. TIME INTERVAL CONFIGURATION USING EXTER-
NAL CLOCK; SET AND CLOCK INHIBIT FUNCTIONS
FIGURE 21. TIME INTERVAL CONFIGURATION USING EXTER-
NAL CLOCK; RESET AND OUTPUT MONOSTABLE
TO ACHIEVE A PULSE OUTPUT
7-1246
CD4536BMS
Applications (Continued)
VDD
A
B
RS
C
3µs MIN
R
OUT 1
C
D
Rtc
CLOCK
SET
DCBA
0000 (÷2)
0001 (÷4)
RESET
8-BYPASS
C INH
OUT 2
START
0010 (÷8)
MONO IN
1
2.3
DECODE
OUT
f
Rtc C
OSC INH
IN 1
NOTE:
t
SHADED PULSE REPRESENTS DECODE OUTPUT
IN MONOSTABLE MODE. IF AN OUTPUT PULSE
IS REQUIRED 1 FULL COUNTDOWN AFTER
REMOVAL OF RESET PULSE, SEE FIGURE 19
RS ≥ 2Rtc
f IN Hz,
R IN Ω,
C IN F
VSS
FOR USE OF CD4098BMS
FIGURE 22. TIME INTERVAL CONFIGURATION USING ON-
CHIP RC OSCILLATOR AND RESET INPUT
TO INITIATE TIME INTERVAL
FIGURE 23. TIMING DIAGRAM
DECODE OUT SELECTION TABLE
NUMBER OF STAGES IN DIVIDER CHAIN
D
C
B
A
8-BYPASS = 0
8-BYPASS = 1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
9
1
2
3
4
10
11
12
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
13
14
15
16
5
6
7
8
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
17
18
19
20
9
10
11
12
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
21
22
23
24
13
14
15
16
0 = Low Level
1 = High Level
Functional Block Diagram
8-BYPASS
1
6
SET
2
RESET
14
OSC
INHIBIT
OSC INHIBIT
LOGIC
STAGES 9-24
Q9 - - - Q24
3
4
5
7
8-BYPASS
LOGIC
CLOCK INHIBIT
LOGIC
STAGES
1-8
IN
OUT 1
OUT 2
9
13
DECODE
OUT
A
10
11
12
15
B
C
D
BINARY
SELECT
CLOCK
INHIBIT
DECODER
VSS = 8
VDD = 16
MONO IN
FIGURE 24.
7-1247
CD4536BMS
FUNCTIONAL TEST SEQUENCE
INPUTS
OUTPUTS
COMMENTS
DECODE OUT
IN 1
1
SET
0
RESET
8-BYPASS
Q1 THRU 24
1
1
0
ALL 24 STEPS ARE IN RESET MODE
1
1
1
1
0
Counter is in three 8-stage section in parallel
mode
0
1
1
1
1
1
1
0
First “1” to “0” transition of clock
1
0
-
255 “1” to “0” transitions are clocked in the
counter
-
-
0
0
1
0
1
0
1
0
1
1
The 255 “1” to “0” transition
Counter converted back to 24 stages in series
mode.
Set and Reset must be connected together
and simultaneously go from “1” to “0”
1
0
0
0
0
0
0
0
1
0
In1 Switches to a “1”
Counter Ripples from an all “1” state to an all
“0” state
Functional Test Sequence
Test Function has been included for the reduction of test allel. All flip-flops are now at a “1”. The counter is now
time required to exercise all 24 counter stages. This test returned to the normal 24 steps in series configuration. One
function divides the counter into three 8-stage sections and more pulse is entered into In1 which will cause the counter
255 counts are loaded in each of the 8-stage sections in par- to ripple from an all “1” state to an all “0” state.
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from
the basic inch dimensions as indicated. Grid graduations are in mils
(10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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