CDP68HCL05C4D_技术文档

CDP68HC05C4, CDP68HC05C8,

CDP68HCL05C4, CDP68HCL05C8,

CDP68HSC05C4, CDP68HSC05C8

Semiconductor

October 1995

8-Bit Microcontroller Series

The following are some of the hardware and software

highlights of the CDP68HC05C4 family of HCMOS Micro-

computers.

Hardware Features (All Types)

• HCMOS Technology

Software Features

• Similar to MC6800

• 8-Bit Architecture

• 8 x 8 Unsigned Multiply Instruction

• Efﬁcient Use of Program Space

• Versatile Interrupt Handling

• True Bit Manipulation

• Power-Saving STOP, WAIT and Data Retention Modes

• Fully Static Operation

• On-Chip Memory

- CDP68HC05C4, CDP68HCL05C4, CDP68HSC05C4

- 176 Bytes of RAM

- 4160 Bytes of User ROM

• Addressing Modes with Indexed Addressing for Table

• Efﬁcient Instruction Set

• Memory Mapped I/O

- CDP68HC05C8, CDP68HCL05C8, CDP68HSC05C8

- 176 Bytes of RAM

- 7744 Bytes of User ROM

• Two Power-Saving Standby Modes

• Upward Software Compatible with the CDP6805

CMOS Family

• 24 Bidirectional I/O Lines and 7 Input-Only Lines

• Internal 16-Bit Timer

Description

• Serial Communications Interface (SCI) System

• Serial Peripheral Interface (SPI) System

• Self-Check Mode

The CDP68HC05C4 HCMOS Microcomputer is a member of

the CDP68HC05 family of low-cost single chip microcomput-

ers. This 8-bit microcomputer unit (MCU) contains an on-

chip oscillator, CPU, 176 bytes of RAM, 4160 bytes of user

ROM, I/O, two serial interface systems, and timer. The fully

static design allows operation at frequencies down to DC,

further reducing its already low-power consumption.

• External, Timer, SCI, and SPI Interrupts

• Master Reset and Power-On Reset

• On-Chip Oscillator with RC or Crystal Mask Options

The CDP68HC05C8 is similar to the CDP68HC05C4 except

for the size of on-chip ROM. The CDP68HC05C8 has 7744

bytes of on-chip user ROM. All information pertaining to the

CDP68HC05C4 MCU applies to the CDP68HC05C8 with

the exception of the memory description.

• 40 Lead Dual-In-Line, 44 Lead† Plastic Chip Carrier,

and 44 Lead Metric Plastic Quad Flatpack Packages

• CDP68HC05C4, CDP68HC05C8

- 4.2MHz Operating Frequency (2.1MHz Internal Bus

Frequency) at 5V; 2.0MHz (1.0MHz Internal Bus) at

3.0V

The CDP68HCL05C4 and CDP68HCL05C8 MCU devices

are low-power versions of the CDP68HC05C4 and

CDP68HC05C8, respectively. They contain all the features

of the CDP68HC05C4 and CDP68HC05C8 with additional

features of lower power consumption in the RUN, WAIT and

STOP modes; and low voltage operation down to 2.4V.

- Single 3.0V to 6.0V Supply (2.0V Data Retention

Mode)

• CDP68HCL05C4, CDP68HCL05C8

- Lower Supply Current, I_DDin RUN, WAIT and STOP

Modes at 5.5V, 3.6V and 2.4V

The CDP68HSC05C4 and CDP68HSC05C8 MCU devices

are high-speed versions of the CDP68HC05C4 and

CDP68HC05C8, respectively. They also contain all the fea-

tures of the CDP68HC05C4 and CDP68HC05C8 with the

additional capability of higher frequency operation at

8.0MHz.

- Single 2.4V to 6.0V Supply (2V Data Retention

Mode)

• CDP68HSC05C4, CDP68HSC05C8

- 8.0MHz Operating Frequency (4.0MHz Internal Bus

Frequency)

† Pin number references throughout this speciﬁcation refer to the 40

lead DIP. See pinouts for cross reference.

• Single 3.0V to 6.0V Supply (2.0V Data Retention Mode)

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.

File Number 2748.3

2-3

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

Pinouts

D SUFFIX (SBDIP), E SUFFIX (DIP)

N SUFFIX (PLCC)

TOP VIEW

RESET

1

2

3

4

5

6

7

8

9

40 V_DD

IRQ

NC

39 OSC1

38 OSC2

37 TCAP

36 PD7

6

5

4

3

2

1 44 43 42 41 40

PA7

PA6

PA5

PA4

PA3

PA2

7

39

38

37

36

35

34

33

32

31

30

29

PA5

PA4

PA3

PA2

PA1

PA0

PB0

PB1

PB2

PB3

PB4

PD7

8

TCMP

9

PD5/SS

PD4/SCK

PD3/MOSI

PD2/MISO

PD1/TDO

PD0/RDI

PC0

35 TCMP

34 PD5/SS

33 PD4/SCK

32 PD3/MOSI

31 PD2/MISO

30 PD1/TDO

29 PD0/RDI

28 PC0

10

11

12

13

14

15

16

17

PA1 10

PA0 11

PB0 12

PB1 13

PB2 14

PB3 15

PB4 16

PB5 17

PB6 18

PB7 19

V_SS20

PC1

PC2

18 19 20 21 22 23 24 25 26 27 28

27 PC1

26 PC2

25 PC3

24 PC4

23 PC5

22 PC6

21 PC7

Q SUFFIX (MQFP)

TOP VIEW

44 43 42 41 40 39 38 37 36 35 34

1

TCMP

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PB0

PB1

PB2

PB3

33

2

PD5/SS

PD4/SCK

PD3/MOSI

PD2/MISO

PD1/TDO

PD0/RDI

PC0

32

31

30

29

3

4

5

6

7

8

9

28

27

26

25

24

23

PC1

10

11

PC2

PC3

12 13 14 15 16 17 18 19 20 21 22

2-4

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

Microcomputer Block Diagram

OSC1

39

OSC2

38

INTERNAL

PROCESSOR

CLOCK

TCMP

35

37

INTERNAL PROCESSOR CLOCK

1

2

OSCILLATOR

^AND÷ 2

RESET

IRQ

TCAP

TIMER SYSTEM

11

10

9

28

27

26

25

24

23

22

21

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

ACCUMULATOR

8

5

6

5

A

X

PORT A

I/O

LINES

PORT C

I/O

LINES

CPU

CONTROL

PORT

A

REG

DATA

DIR

REG

DATA

DIR

REG

PORT

C

REG

7

INDEX

REGISTER

6

5

CONDITION CODE

REGISTER

4

CC

S

CPU

ALU

STACK

POINTER

12

13

14

15

16

17

18

19

36

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PD7

PORT D

29

30

31

32

33

34

PROGRAM COUNTER

RDI (PD0)

SCI SYSTEM

HIGH

PCH

PORT

B

REG

DATA

DIR

REG

PORT B

I/O

LINES

TDO (PD1)

MISO (PD2)

MOSI (PD3)

SCK (PD4)

SS (PD5)

PROGRAM

COUNTER LOW PCL

8

SPI SYSTEM

4160† x 8

ROM

176 x 8

STATIC RAM

BAUD RATE

GENERATOR

240 x 8

SELF-CHECK

ROM

INTERNAL PROCESSOR

CLOCK

† 7744 bytes of ROM for: CDP68HC05C8, CDP68HCL05C8, CDP68HSC05C8.

Power Considerations

The average chip-junction temperature, T_J, in ^oC can be

obtained from:

PINS

R1

R2

C

V

= 4.5V

DD

T_J= T_A+ (P_D• θ_JA

)

(EQ. 1)

Where: T_A= Ambient Temperature, ^oC

θ_JA= Package Thermal Resistance,

Junction-to-Ambient, ^oC/W

PA0-7, PB0-7, PC0-7, PD6

PD1-4

3.26kΩ

1.9kΩ

2.38kΩ

2.26kΩ

50pF

200pF

P_D= P_INT+ P_I/O

V

= 3.0V

DD

P_INT= I_CCx V_CC, Watts - Chip Internal Power

P_I/O= Power Dissipation on Input and Output

Pins - User Determined

PA0-7, PB0-7, PC0-7, PD6

PD1-4

10.19kΩ 6.32kΩ

50pF

6kΩ

200pF

For most applications P_I/O< P_INTand can be neglected.

An approximate relationship between P_Dand T_J(if P_I/Ois

neglected) is:

V_DD

P_D= K ÷ (T_J+ 273^oC)

(EQ. 2)

R₂

R₁

Solving Equation 1 and Equation 2 for K gives:

K = P_D• (T_A+ 273^oC) + θ_JA• P_D2

TEST

POINT

(EQ. 3)

C

Where K is a constant pertaining to the particular part. K can

be determined from Equation 3 by measuring P_D(at equilib-

rium) for a known T_A. Using this value of K the values of P_D

and T_Jcan be obtained by solving Equation 1 and Equation 2

iteratively for any value of T_A.

EQUIVALENT TEST LOAD

2-5

Speciﬁcations CDP68HC05C4, CDP68HC05C8

Absolute Maximum Ratings Voltages Referenced to V

Thermal Information

SS

Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Thermal Resistance

θ

JA

DD

o

Input Voltage, V . . . . . . . . . . . . . . . . . . . .V - 0.3V to V + 0.3V

Ceramic Dual-In-Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 C/W

IN

SS

DD

o

Self-Check Mode (IRQ Pin Only), V . .V - 0.3V to 2 x V + 0.3V

Plastic Dual-In-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 C/W

IN

SS

DD

o

Current Drain Per Pin Excluding V and V , I . . . . . . . . . . .25mA

Plastic Chip Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 C/W

DD

SS

o

Operating Temperature Range, T

CDP68HC05C4, CDP68HC05C8 . . . . . . . . . . . . -40 C to +125 C

CDP68HCL05C4, CDP68HCL05C8 . . . . . . . . . . . . .0 C to +70 C

CDP68HSC05C4, CDP68HSC05C8 . . . . . . . . . . . .0 C to +70 C

Metric Plastic Quad Flat Pack . . . . . . . . . . . . . . . . . . . . 120 C/W

A

o

Storage Temperature Range, T

. . . . . . . . . . . . -65 C to +150 C

STG

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

o

DC Electrical Speciﬁcations

V

= 5V ±10%, V = 0V, T = -40 C to +125 C, Unless Otherwise Speciﬁed.

DD SS A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

0.1

-

UNITS

Output Voltage

V

I

< 10µA

LOAD

-

V

OL

V

-0.1

OH

DD

Output High Voltage

PA0-7, PB0-7, PC0-7, TCMP

V

I

= -0.8mA

= -1.6mA

= 1.6mA

V

-0.8

-

V

OH

LOAD

DD

PD1-4

DD

Output Low Voltage

V

-

0.4

OL

PA0-7, PB0-7, PC0-7, PD1-4, TCMP

Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.7•V

V

DD

V

IH

DD

-

Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.2•V

-

IL

SS

-

DD

o

Data Retention Mode

V

T

= 0 C to +70 C

2

-

RM

A

Supply Current (See Notes)

Run

I

-

3.5

7

4

mA

µA

DD

WAIT

STOP

1.6

o

T

= 25 C

2

-

50

A

o

= 0 C to +70 C

140

180

250

±10

o

= -40 C to +85 C

-

o

= -40 C to +125 C

-

I/O Ports Hi-Z Leakage Current

PA0-7, PB0-7, PC0-7, PD1-4

I

-

IL

Input Current

I

-

±1

µA

IN

RESET, IRQ, TCAP, OSC1, PD0, PD5, PD7

Capacitance Ports (As Input or Output)

RESET, IRQ, TCAP, OSC1, PD0-5, PD7

C

-

12

8

pF

OUT

C

IN

NOTES:

1. This device contains circuitry to protect the inputs against damage due to high static voltages of electric ﬁelds; however, it is advised that

normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For

proper operation it is recommended that V and V

be constrained to the range V <(V or V

)<V . Reliability of operation is

IN

OUT

SS

IN

OUT DD

enhanced if unused inputs except OSC2 are connected to an appropriate logic voltage level (e.g., either V or V ).

SS

DD

2. All values shown reflect average measurement.

o

3. Typical values at midpoint of voltage range, 25 C only.

4. WAIT I : Only timer system active (SPE = TE = RE = 0). If SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.

DD

5. Run (Operating) I , WAIT I : Measured using external square-wave clock source (f = 4.2MHz), all inputs 0.2V from rail, no DC

OSC

DD

loads, less than 50pF on all outputs, C = 20pF on OSC2.

L

6. WAIT, STOP I : All ports configured as inputs, V = 0.2V, V = V -0.2V.

DD

IL

IH

DD

7. STOP I measured with OSC1 = V

.

DD

SS

8. WAIT I is affected linearly by the OSC2 capacitance.

DD

2-6

Speciﬁcations CDP68HC05C4, CDP68HC05C8

o

DC Electrical Speciﬁcations

V

= 3.3V ±10%, V = 0V, T = -40 C to +125 C, Unless Otherwise Speciﬁed.

DD

SS

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

0.1

-

UNITS

Output Voltage

V

I

≤ 10µA

LOAD

-

V

OL

V

-0.1

OH

DD

Output High Voltage

PA0-7, PB0-7, PC0-7, TCMP

PD1-4

V

I

= -0.2mA

= -0.4mA

= 0.4mA

V

-0.3

-

V

OH

LOAD

DD

Output Low Voltage

V

-

0.3

OL

PA0-7, PB0-7, PC0-7, PD1-4, TCMP

Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.7•V

V

DD

V

IH

DD

-

Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.2•V

-

IL

SS

-

DD

o

Data Retention Mode

V

T

= 0 C to +70 C

2

-

RM

A

Supply Current (See Notes)

Run

I

-

1

0.5

1

-

2.5

1.4

30

mA

µA

DD

WAIT

STOP

o

T

= 25 C

A

o

= 0 C to +70 C

80

o

= -40 C to +85 C

-

120

175

±10

o

= -40 C to +125 C

-

I/O Ports Hi-Z Leakage Current

PA0-7, PB0-7, PC0-7, PD1-4

I

-

IL

Input Current

I

-

±1

µA

IN

RESET, IRQ, TCAP, OSC1, PD0, PD5, PD7

Capacitance Ports (As Input or Output)

RESET, IRQ, TCAP, OSC1, PD0-5, PD7

C

-

12

8

pF

OUT

C

IN

NOTES:

1. All values shown reﬂect average measurement.

o

2. Typical values at midpoint of voltage range, 25 C only.

3. WAIT I : Only timer system active (SPE = TE = RE = 0). If SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.

DD

4. Run (Operating) I , WAIT I : Measured using external square-wave clock source (f = 4.2MHz), all inputs 0.2V from rail, no DC

OSC

DD

loads, less than 50pF on all outputs, C = 20pF on OSC2.

L

5. WAIT, STOP I : All ports configured as inputs, V = 0.2V, V = V -0.2V.

DD

IL

IH

DD

6. STOP I measured with OSC1 = V

.

DD

SS

7. WAIT I is affected linearly by the OSC2 capacitance.

DD

2-7

Speciﬁcations CDP68HC05C4, CDP68HC05C8

o

Control Timing

V

= 5V ±10%, V = 0V, T = -40 C to +125 C, Unless Otherwise Speciﬁed.

DD SS A

PARAMETER

SYMBOL

MIN

MAX

UNITS

Frequency Of Operation

Crystal Option

f

-

4.2

MHz

OSC

External Clock Option

DC

Internal Operating Frequency

Crystal (f

+ 2)

f

-

DC

480

-

2.1

-

MHz

ns

OSC

OP

External Clock (f

+ 2)

OSC

Cycle Time (See Figure 11)

t

CYC

Crystal Oscillator Start-up Time for AT-cut Crystal (See Figure 11)

Stop Recovery Start-up Time (AT-cut Crystal Oscillator) (See Figure 1)

RESET Pulse Width (See Figure 11)

t

100

-

ms

OXOV

t

-

ms

ILCH

t

1.5

t

RL

CYC

Timer

Resolution (Note 2)

t

4

125

-

t

RES

CYC

Input Capture Pulse Width (See Figure 2)

Input Capture Pulse Period (See Figure 2)

Interrupt Pulse Width Low (Edge-Triggered) (See Figure 14)

Interrupt Pulse Period (See Figure 14)

OSC1 Pulse Width

t

, t

ns

TH TL

t

(Note 3)

125

TLTL

CYC

t

ns

ILIH

t

(Note 1)

90

CYC

t

, t

ns

OH OL

NOTES:

1. The minimum period t

should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t

.

ILIL

CYC

2. Since a 2-bit prescaler in the timer must count four internal cycles (t

), this is the limiting minimum factor in determining the timer resolution.

CYC

3. The minimum period t

should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t

.

CYC

TLTL

o

Control Timing

V

= 3.3V ±10%, V = 0V, T = -40 C to +125 C, Unless Otherwise Speciﬁed.

DD SS A

PARAMETER

SYMBOL

MIN

MAX

UNITS

Frequency Of Operation

Crystal Option

f

-

2.0

MHz

OSC

External Clock Option

DC

Internal Operating Frequency

Crystal (f

+ 2)

f

-

DC

1000

-

1.0

-

MHz

ns

OSC

OP

External Clock (f

+ 2)

OSC

Cycle Time (See Figure 11)

t

CYC

Crystal Oscillator Start-up Time for AT-cut Crystal (See Figure 11)

Stop Recovery Start-up Time (AT-cut Crystal Oscillator) (See Figure 1)

RESET Pulse Width (See Figure 11)

t

100

-

ms

OXOV

t

-

ms

ILCH

t

1.5

t

RL

CYC

Timer

Resolution (Note 2)

t

4

-

t

RES

CYC

Input Capture Pulse Width (See Figure 2)

Input Capture Pulse Period (See Figure 2)

Interrupt Pulse Width Low (Edge-Triggered) (See Figure 14)

Interrupt Pulse Period (See Figure 14)

OSC1 Pulse Width

t

, t

250

ns

TH TL

t

(Note 3)

250

TLTL

CYC

t

ns

ILIH

t

(Note 1)

200

CYC

t

, t

ns

OH OL

NOTES:

1. The minimum period t

should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t

.

ILIL

CYC

2. Since a 2-bit prescaler in the timer must count four internal cycles (t

), this is the limiting minimum factor in determining the timer resolution.

CYC

3. The minimum period t

should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t

.

CYC

TLTL

2-8

Speciﬁcations CDP68HC05C4, CDP68HC05C8

o

Serial Peripheral Interface (SPI) Timing (See Figure 3)

V

= 5V ±10%, V = 0V, T = -40 C to +125 C

DD SS A

Unless Otherwise Speciﬁed.

NUMBER

PARAMETER

SYMBOL

MIN

MAX

UNITS

Operating Frequency

Master

f

DC

0.5

2.1

f

(Note 3)

MHz

OP(M)

OP

Slave

f

OP(S)

1

2

3

4

5

6

7

Cycle Time

Master

t

2.0

-

t

CYC

CYC(M)

Slave

t

480

ns

CYC(S)

Enable Lead Time

Master

t

(Note 1)

240

-

LEAD(M)

Slave

t

ns

LEAD(S)

Enable Lag Time

Master

t

(Note 1)

240

-

LAG(M)

Slave

t

ns

LAG(S)

Clock (SCK) High Time

Master

t

340

190

-

ns

W(SCKH)M

Slave

t

W(SCKH)S

Clock (SCK) Low Time

Master

t

340

190

-

ns

W(SCKL)M

Slave

t

W(SCKL)S

Data Setup Time (Inputs)

Master

t

100

-

ns

SU(M)

Slave

t

SU(S)

Data Hold Time (Inputs)

Master

t

100

-

ns

H(M)

Slave

t

H(S)

8

9

Access Time (Time to Data Active from High Impedance State)

Slave

t

0

-

120

240

ns

A

Disable Time (Hold Time to High Impedance State)

Slave

t

DIS

10

Data Valid Time

Master (Before Capture Edge)

t

0.25

-

t

V(M)

CYC(M)

Slave (After Enable Edge) (Note 2)

t

240

ns

V(S)

11

12

13

Data Hold Time (Outputs)

Master (After Capture Edge)

t

0.25

0

-

HO(M)

CYC(M)

Slave (After Enable Edge)

t

ns

HO(S)

Rise Time (V = 20% to 70%, C = 200pF)

DD

L

SPI Outputs (SCK, MOSI, MISO)

SPI Inputs (SCK, MOSI, MISO, SS)

t

-

100

2.0

ns

R(M)

t

µs

R(S)

Fall Time (V = 20% to 70%, C = 200pF)

DD

L

SPI Outputs (SCK, MOSI, MISO)

SPI Inputs (SCK, MOSI, MISO, SS)

t

-

100

2.0

ns

F(M)

t

µs

F(S)

NOTES:

1. Signal Production depends on software.

2. Assumes 200pF load on all SPI pins.

3. Note that the units this specification uses is f (internal operating frequency), not MHz! In the master mode the SPI bus is capable of

OP

running at one-half of the devices’s internal operating frequency, therefore 1.05MHz maximum.

2-9

Speciﬁcations CDP68HC05C4, CDP68HC05C8

o

Serial Peripheral Interface (SPI) Timing (See Figure 3)

V

= 3.3V ±10%, V = 0V, T = -40 C to +125 C

DD SS A

Unless Otherwise Speciﬁed.

NUMBER

PARAMETER

SYMBOL

MIN

MAX

UNITS

Operating Frequency

Master

f

DC

0.5

1.0

f

(Note 3)

MHz

OP(M)

OP

Slave

f

OP(S)

1

2

3

4

5

6

7

Cycle Time

Master

t

2.0

1.0

-

t

CYC

CYC(M)

Slave

t

µs

CYC(S)

Enable Lead Time

Master

t

(Note 1)

500

-

LEAD(M)

Slave

t

ns

LEAD(S)

Enable Lag Time

Master

t

(Note 1)

500

-

LAG(M)

Slave

t

ns

LAG(S)

Clock (SCK) High Time

Master

t

720

400

-

ns

W(SCKH)M

Slave

t

W(SCKH)S

Clock (SCK) Low Time

Master

t

720

400

-

ns

W(SCKL)M

Slave

t

W(SCKL)S

Data Setup Time (Inputs)

Master

t

200

-

ns

SU(M)

Slave

t

SU(S)

Data Hold Time (Inputs)

Master

t

200

-

ns

H(M)

Slave

t

H(S)

8

9

Access Time (Time to Data Active from High Impedance State)

Slave

t

0

-

250

500

ns

A

Disable Time (Hold Time to High Impedance State)

Slave

t

DIS

10

Data Valid Time

Master (Before Capture Edge)

t

0.25

-

t

V(M)

CYC(M)

Slave (After Enable Edge) (Note 2)

t

500

ns

V(S)

11

12

Data Hold Time (Outputs)

Master (After Capture Edge)

t

0.25

0

-

HO(M)

CYC(M)

Slave (After Enable Edge)

t

ns

HO(S)

Rise Time (V = 20% to 70%, C = 200pF)

DD

L

SPI Outputs (SCK, MOSI, MISO)

SPI Inputs (SCK, MOSI, MISO, SS)

t

-

200

2.0

ns

R(M)

t

µs

R(S)

13

Fall Time (V = 20% to 70%, C = 200pF)

DD L

SPI Outputs (SCK, MOSI, MISO)

t

-

200

2.0

ns

F(M)

SPI Inputs (SCK, MOSI, MISO, SS)

t

µs

F(S)

NOTES:

1. Signal Production depends on software.

2. Assumes 200pF load on all SPI pins.

3. Note that the units this specification uses is f (internal operating frequency), not MHz! In the master mode the SPI bus is capable of

OP

running at one-half of the devices’s internal operating frequency, therefore 0.05MHz maximum.

2-10

Speciﬁcations CDP68HCL05C4, CDP68HCL05C8

o

DC Electrical Speciﬁcations

V

= 5V ±10%, V = 0V, T = 0 C to +70 C, Unless Otherwise Speciﬁed.

DD SS A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

0.1

-

UNITS

Output Voltage

V

I

≤10µA

LOAD

-

V

OL

V

-0.1

OH

DD

Output High Voltage

PA0-7, PB0-7, PC0-7, TCMP

V

I

= -0.8mA

= -1.6mA

= 1.6mA

V

-0.8

-

V

OH

LOAD

DD

PD1-4

DD

Output Low Voltage

V

-

0.4

OL

PA0-7, PB0-7, PC0-7, PD1-4, TCMP

Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.7•V

V

DD

V

IH

DD

-

Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.2•V

-

IL

SS

-

DD

o

Data Retention Mode

V

T

= 0 C to +70 C

2

-

RM

A

Supply Current (See Notes)

Run

I

-

5

mA

µA

DD

WAIT

STOP

2.75

15

o

T

= 25 C

A

o

= 0 C to +70 C

25

I/O Ports Hi-Z Leakage Current

PA0-7, PB0-7, PC0-7, PD1-4

I

±1

IL

Input Current

I

-

±1

µA

IN

RESET, IRQ, TCAP, OSC1, PD0, PD5, PD7

Capacitance Ports (As Input or Output)

RESET, IRQ, TCAP, OSC1, PD0-5, PD7

C

-

12

8

pF

OUT

C

IN

NOTES:

1. All values shown reﬂect average measurement.

o

2. Typical values at midpoint of voltage range, 25 C only.

3. WAIT I : Only timer system active (SPE = TE = RE = 0). If SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.

DD

4. Run (Operating) I , WAIT I : Measured using external square-wave clock source (f = 4.2MHz), all inputs 0.2V from rail, no DC

OSC

DD

loads, less than 50pF on all outputs, C = 20pF on OSC2.

L

5. WAIT, STOP I : All ports configured as inputs, V = 0.2V, V = V - 0.2V.

DD

IL

IH

DD

6. STOP I measured with OSC1 = V

.

DD

SS

7. WAIT I is affected linearly by the OSC2 capacitance.

DD

2-11

Speciﬁcations CDP68HCL05C4, CDP68HCL05C8

o

DC Electrical Speciﬁcations

V

= 2.4V - 3.6V, V = 0V, T = 0 C to +70 C, Unless Otherwise Speciﬁed.

DD

SS

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

0.1

-

UNITS

Output Voltage

V

I

≤ 10µA

LOAD

-

V

OL

V

-0.1

OH

DD

Output High Voltage

PA0-7, PB0-7, PC0-7, TCMP

PD1-4

V

I

= -0.2mA

= -0.4mA

= 0.4mA

V

-0.3

-

V

OH

LOAD

DD

Output Low Voltage

V

-

0.3

OL

PA0-7, PB0-7, PC0-7, PD1-4, TCMP

Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.7•V

V

DD

V

IH

DD

-

Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.2•V

-

IL

SS

-

DD

o

Data Retention Mode

V

T

= 0 C to +70 C

2

-

RM

A

Supply Current (3.6V at f

= 2MHz)

DC

OSC

Run

I

-

1.75

900

5

mA

µA

DD

WAIT

STOP

o

T

= 25 C

A

o

= 0 C to +70 C

10

Supply Current (2.4V at f

= 1MHz)

DC

OSC

Run

I

-

750

400

2.0

5.0

±1

µA

DD

WAIT

STOP

o

T

= 25 C

A

o

= 0 C to +70 C

I/O Ports Hi-Z Leakage Current

PA0-7, PB0-7, PC0-7, PD1-4

I

IL

Input Current

I

-

±1

µA

IN

RESET, IRQ, TCAP, OSC1, PD0, PD5, PD7

Capacitance Ports (As Input or Output)

RESET, IRQ, TCAP, OSC1, PD0-5, PD7

C

-

12

8

pF

OUT

C

IN

NOTES:

1. All values shown reﬂect average measurement.

o

2. Typical values at midpoint of voltage range, 25 C only.

3. WAIT I : Only timer system active (SPE = TE = RE = 0). If SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.

DD

4. Run (Operating) I , WAIT I : Measured using external square-wave clock source, all inputs 0.2V from rail, no DC loads, less than 50pF

DD

on all outputs, C = 20pF on OSC2.

L

5. WAIT, STOP I : All ports configured as inputs, V = 0.2V, V = V -0.2V.

DD

IL

IH

DD

6. STOP I measured with OSC1 = V

.

DD

SS

7. WAIT I is affected linearly by the OSC2 capacitance.

DD

2-12

Speciﬁcations CDP68HCL05C4, CDP68HCL05C8

o

Control Timing

V

= 5V ±10%, V = 0V, T = 0 C to +70 C, Unless Otherwise Speciﬁed.

DD SS A

PARAMETER

SYMBOL

MIN

MAX

UNITS

Frequency Of Operation

Crystal Option

f

-

4.2

MHz

OSC

External Clock Option

DC

Internal Operating Frequency

Crystal (f

+ 2)

f

-

DC

480

-

2.1

-

MHz

ns

OSC

OP

External Clock(f

+ 2)

OSC

Cycle Time (See Figure 11)

t

CYC

Crystal Oscillator Start-up Time for AT-cut Crystal (See Figure 11)

Stop Recovery Start-up Time (AT-cut Crystal Oscillator) (See Figure 1)

RESET Pulse Width (See Figure 11)

t

100

-

ms

OXOV

t

-

ms

ILCH

t

1.5

t

RL

CYC

Timer

Resolution (Note 2)

t

4

125

-

t

RES

CYC

Input Capture Pulse Width (See Figure 2)

Input Capture Pulse Period (See Figure 2)

Interrupt Pulse Width Low (Edge-Triggered) (See Figure 14)

Interrupt Pulse Period (See Figure 14)

OSC1 Pulse Width

t

, t

ns

TH TL

t

(Note 3)

125

TLTL

CYC

t

ns

ILIH

t

(Note 1)

90

CYC

t

, t

ns

OH OL

NOTES:

1. The minimum period t

should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t

.

ILIL

CYC

2. Since a 2-bit prescaler in the timer must count four internal cycles (t

), this is the limiting minimum factor in determining the timer resolution.

CYC

3. The minimum period t

should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t

.

CYC

TLTL

o

Control Timing

V

= 2.4V -3.6V, V = 0V, T = 0 C to +70 C, Unless Otherwise Speciﬁed.

DD SS A

3.6V

2.4V

DC

PARAMETER

SYMBOL

UNITS

MIN

MAX

MIN

MAX

Frequency Of Operation

Crystal Option

f

-

2.0

-

1.0

MHz

OSC

External Clock Option

DC

Internal Operating Frequency

Crystal (f + 2)

f

-

1.0

-

0.5

-

MHz

ns

OSC

OP

External Clock (f

+ 2)

DC

OSC

Cycle Time (See Figure 11)

t

1000

2000

CYC

Crystal Oscillator Start-up Time for AT-cut Crystal (See Figure 11)

Stop Recovery Start-up Time (AT-cut Crystal Oscillator) (See Figure 1)

RESET Pulse Width (See Figure 11)

t

-

100

-

100

-

ms

OXOV

t

ms

ILCH

t

1.5

t

RL

CYC

Timer

Resolution (Note 2)

t

4.0

250

-

4.0

500

-

t

RES

CYC

Input Capture Pulse Width (See Figure 2)

Input Capture Pulse Period (See Figure 2)

Interrupt Pulse Width Low (Edge-Triggered) (See Figure 14)

Interrupt Pulse Period (See Figure 14)

OSC1 Pulse Width

t

, t

ns

TH TL

t

(Note 3)

250

(Note 3)

500

TLTL

CYC

t

ns

ILIH

t

(Note 1)

200

(Note 1)

400

CYC

t

, t

ns

OH OL

NOTES:

1. The minimum period t

should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t

.

CYC

ILIL

2. Since a 2-bit prescaler in the timer must count four internal cycles (t

), this is the limiting minimum factor in determining the timer resolution.

CYC

3. The minimum period t

should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t

.

TLTL

CYC

2-13

Speciﬁcations CDP68HCL05C4, CDP68HCL05C8

o

Serial Peripheral Interface (SPI) Timing (See Figure 3)

V

= 5V ±10%, V = 0V, T = 0 C to +70 C

DD

SS

A

Unless Otherwise Speciﬁed.

NUMBER

PARAMETER

SYMBOL

MIN

MAX

UNITS

Operating Frequency

Master

f

DC

0.5

2.1

f

(Note 3)

MHz

OP(M)

OP

Slave

f

OP(S)

1

2

3

4

5

6

7

Cycle Time

Master

t

2.0

-

t

CYC

CYC(M)

Slave

t

480

ns

CYC(S)

Enable Lead Time

Master

t

(Note 1)

240

-

LEAD(M)

Slave

t

ns

LEAD(S)

Enable Lag Time

Master

t

(Note 1)

240

-

LAG(M)

Slave

t

ns

LAG(S)

Clock (SCK) High Time

Master

t

340

190

-

ns

W(SCKH)M

Slave

t

W(SCKH)S

Clock (SCK) Low Time

Master

t

340

190

-

ns

W(SCKL)M

Slave

t

W(SCKL)S

Data Setup Time (Inputs)

Master

t

100

-

ns

SU(M)

Slave

t

SU(S)

Data Hold Time (Inputs)

Master

t

100

-

ns

H(M)

Slave

t

H(S)

8

9

Access Time (Time to Data Active from High Impedance State)

Slave

t

0

-

120

240

ns

A

Disable Time (Hold Time to High Impedance State)

Slave

t

DIS

10

Data Valid Time

Master (Before Capture Edge)

t

0.25

-

t

V(M)

CYC(M)

Slave (After Enable Edge)(Note 2)

t

240

ns

V(S)

11

12

13

Data Hold Time (Outputs)

Master (After Capture Edge)

t

0.25

0

-

HO(M)

CYC(M)

Slave (After Enable Edge)

t

ns

HO(S)

Rise Time (V = 20% to 70%, C = 200pF)

DD

L

SPI Outputs (SCK, MOSI, MISO)

SPI Inputs (SCK, MOSI, MISO, SS)

t

-

100

2.0

ns

R(M)

t

µs

R(S)

Fall Time (V = 20% to 70%, C = 200pF)

DD

L

SPI Outputs (SCK, MOSI, MISO)

SPI Inputs (SCK, MOSI, MISO, SS)

t

-

100

2.0

ns

F(M)

t

µs

F(S)

NOTES:

1. Signal Production depends on software.

2. Assumes 200pF load on all SPI pins.

3. Note that the units this specification uses is f (internal operating frequency), not MHz! In the master mode the SPI bus is capable of

OP

running at one-half of the devices’s internal operating frequency, therefore 1.05MHz maximum.

2-14

Speciﬁcations CDP68HCL05C4, CDP68HCL05C8

o

Serial Peripheral Interface (SPI) Timing (See Figure 3)

V

= 2.4V -3.6V , V = 0V, T = 0 C to +70 C

DD DC SS A

Unless Otherwise Speciﬁed.

3.6V

2.4V

DC

NUMBER

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

Operating Frequency

Master

f

DC

0.5

1.0

DC

0.5

f

OP

(Note 3)

OP(M)

Slave

f

OP(S)

MHz

1

2

3

4

5

6

7

Cycle Time

Master

t

2.0

1.0

-

2.0

-

t

CYC

CYC(M)

Slave

t

µs

CYC(S)

Enable Lead Time

Master

t

(Note 1)

500

-

(Note 1)

TBD

-

LEAD(M)

Slave

t

ns

LEAD(S)

Enable Lag Time

Master

t

(Note 1)

500

-

(Note 1)

TBD

-

LAG(M)

Slave

t

ns

LAG(S)

Clock (SCK) High Time

Master

t

720

400

-

TBD

-

ns

W(SCKH)M

Slave

t

W(SCKH)S

Clock (SCK) Low Time

Master

t

720

400

-

TBD

-

ns

W(SCKL)M

Slave

t

W(SCKL)S

Data Setup Time (Inputs)

Master

t

200

-

TBD

-

ns

SU(M)

Slave

t

SU(S)

Data Hold Time (Inputs)

Master

t

200

-

TBD

-

ns

H(M)

Slave

t

H(S)

8

9

Access Time (Time to Data Active from High Impedance State)

Slave

t

0

-

250

500

0

-

TBD

ns

A

Disable Time (Hold Time to High Impedance State)

Slave

t

DIS

10

Data Valid Time

Master (Before Capture Edge)

t

0.25

-

TBD

-

t

V(M)

CYC(M)

Slave (After Enable Edge) (Note 2)

t

500

ns

V(S)

11

12

Data Hold Time (Outputs)

Master (After Capture Edge)

t

0.25

0

-

TBD

0

-

HO(M)

CYC(M)

Slave (After Enable Edge)

t

ns

HO(S)

Rise Time (V = 20% to 70%, C = 200pF)

DD

L

SPI Outputs (SCK, MOSI, MISO)

SPI Inputs (SCK, MOSI, MISO, SS)

t

-

200

2.0

-

TBD

ns

R(M)

t

µs

R(S)

13

Fall Time (V = 20% to 70%, C = 200pF)

DD L

SPI Outputs (SCK, MOSI, MISO)

t

-

200

2.0

-

TBD

ns

F(M)

SPI Inputs (SCK, MOSI, MISO, SS)

t

µs

F(S)

NOTES:

1. Signal Production depends on software.

2. Assumes 200pF load on all SPI pins.

3. Note that the units this specification uses is f (internal operating frequency), not MHz! In the master mode the SPI bus is capable of

OP

running at one-half of the devices’s internal operating frequency.

2-15

Speciﬁcations CDP68HSC05C4, CDP68HSC05C8

o

DC Electrical Speciﬁcations

V

= 5V ±10%, V = 0V, T = 0 C to +70 C, Unless Otherwise Speciﬁed.

DD SS A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

0.1

-

UNITS

Output Voltage

V

I

≤10µA

LOAD

-

V

OL

V

-0.1

OH

DD

Output High Voltage

PA0-7, PB0-7, PC0-7, TCMP

V

I

= -0.8mA

= -1.6mA

= 1.6mA

V

-0.8

-

V

OH

LOAD

DD

PD1-4

DD

Output Low Voltage

V

-

0.4

OL

PA0-7, PB0-7, PC0-7, PD1-4, TCMP

Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.7•V

V

DD

V

IH

DD

-

Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.2•V

-

IL

SS

-

DD

o

Data Retention Mode

V

T

= 0 C to +70 C

2

-

RM

A

Supply Current (See Notes)

Run

I

-

6.7

3.0

2.0

-

13.3

7.6

mA

µA

DD

WAIT

STOP

o

T

= 25 C

50

A

o

= 0 C to +70 C

140

±10

I/O Ports Hi-Z Leakage Current

PA0-7, PB0-7, PC0-7, PD1-4

I

-

IL

Input Current

I

-

±1

µA

IN

RESET, IRQ, TCAP, OSC1, PD0, PD5, PD7

Capacitance Ports (As Input or Output)

RESET, IRQ, TCAP, OSC1, PD0-5, PD7

C

-

12

8

pF

OUT

C

IN

NOTES:

1. All values shown reﬂect average measurement.

o

2. Typical values at midpoint of voltage range, 25 C only.

3. WAIT I : Only timer system active (SPE = TE = RE = 0). If SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.

DD

4. Run (Operating) I , WAIT I : Measured using external square-wave clock source (f = 8.0MHz), all inputs 0.2V from rail, no DC

OSC

DD

loads, less than 50pF on all outputs, C = 20pF on OSC2.

L

5. WAIT, STOP I : All ports configured as inputs, V = 0.2V, V = V - 0.2V.

DD

IL

IH

DD

6. STOP I measured with OSC1 = V

.

DD

SS

7. WAIT I is affected linearly by the OSC2 capacitance.

DD

2-16

Speciﬁcations CDP68HSC05C4, CDP68HSC05C8

o

DC Electrical Speciﬁcations

V

= 3.3V ±10%, V = 0V, T = 0 C to +70 C, Unless Otherwise Speciﬁed.

DD

SS

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

0.1

-

UNITS

Output Voltage

V

I

≤10µA

LOAD

-

V

OL

V

-0.1

OH

DD

Output High Voltage

PA0-7, PB0-7, PC0-7, TCMP

V

I

= -0.8mA

= -1.6mA

= 1.6mA

V

-0.3

-

V

OH

LOAD

DD

PD1-4

DD

Output Low Voltage

V

-

0.3

OL

PA0-7, PB0-7, PC0-7, PD1-4, TCMP

Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.7•V

V

DD

V

IH

DD

-

Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,

PD7, TCAP, IRQ, RESET, OSC1

V

0.2•V

-

IL

SS

-

DD

o

Data Retention Mode

V

T

= 0 C to +70 C

2

-

RM

A

Supply Current (See Notes)

Run

I

-

1.0

0.5

1.0

-

2.5

1.4

30

mA

µA

DD

WAIT

STOP

o

T

= 25 C

A

o

= 0 C to +70 C

80

I/O Ports Hi-Z Leakage Current

PA0-7, PB0-7, PC0-7, PD1-4

I

-

±10

IL

Input Current

I

-

±1

µA

IN

RESET, IRQ, TCAP, OSC1, PD0, PD5, PD7

Capacitance Ports (As Input or Output)

RESET, IRQ, TCAP, OSC1, PD0-5, PD7

C

-

12

8

pF

OUT

C

IN

NOTES:

1. All values shown reﬂect average measurement.

o

2. Typical values at midpoint of voltage range, 25 C only.

3. WAIT I : Only timer system active (SPE = TE = RE = 0). If SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.

DD

4. Run (Operating) I , WAIT I : Measured using external square-wave clock source (f = 2.0MHz), all inputs 0.2V from rail, no DC

OSC

DD

loads, less than 50pF on all outputs, C = 20pF on OSC2.

L

5. WAIT, STOP I : All ports configured as inputs, V = 0.2V, V = V - 0.2V.

DD

IL

IH

DD

6. STOP I measured with OSC1 = V

.

DD

SS

7. WAIT I is affected linearly by the OSC2 capacitance.

DD

2-17

Speciﬁcations CDP68HSC05C4, CDP68HSC05C8

o

Control Timing

V

= 5V ±10%, V = 0V, T = 0 C to +70 C, Unless Otherwise Speciﬁed.

DD SS A

PARAMETER

SYMBOL

MIN

MAX

UNITS

Frequency Of Operation

Crystal Option

f

-

8.0

MHz

OSC

External Clock Option

DC

Internal Operating Frequency

Crystal (f

+ 2)

f

-

DC

250

-

4.0

-

MHz

ns

OSC

OP

External Clock (f

+ 2)

OSC

Cycle Time (See Figure 11)

t

CYC

Crystal Oscillator Start-up Time for AT-cut Crystal (See Figure 11)

Stop Recovery Start-up Time (AT-cut Crystal Oscillator) (See Figure 1)

RESET Pulse Width (See Figure 11)

t

100

-

ms

OXOV

t

-

ms

ILCH

t

1.5

t

RL

CYC

Timer

Resolution (Note 2)

t

4

63

-

t

RES

CYC

Input Capture Pulse Width (See Figure 2)

Input Capture Pulse Period (See Figure 2)

Interrupt Pulse Width Low (Edge-Triggered) (See Figure 14)

Interrupt Pulse Period (See Figure 14)

OSC1 Pulse Width

t

, t

ns

TH TL

t

(Note 3)

63

TLTL

CYC

t

ns

ILIH

t

(Note 1)

45

CYC

t

, t

ns

OH OL

NOTES:

1. The minimum period t

should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t

.

ILIL

CYC

2. Since a 2-bit prescaler in the timer must count four internal cycles (t

), this is the limiting minimum factor in determining the timer resolution.

CYC

3. The minimum period t

should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t

.

CYC

TLTL

o

Control Timing

V

= 3.3V ±10%, V = 0V, T = 0 C to +70 C, Unless Otherwise Speciﬁed.

DD SS A

PARAMETER

SYMBOL

MIN

MAX

UNITS

Frequency Of Operation

Crystal Option

f

-

2.0

MHz

OSC

External Clock Option

DC

Internal Operating Frequency

Crystal (f

+ 2)

f

-

DC

1000

-

1.0

-

MHz

ns

OSC

OP

External Clock (f

+ 2)

OSC

Cycle Time (See Figure 11)

t

CYC

Crystal Oscillator Start-up Time for AT-cut Crystal (See Figure 11)

Stop Recovery Start-up Time (AT-cut Crystal Oscillator) (See Figure 1)

RESET Pulse Width (See Figure 11)

t

100

-

ms

OXOV

t

-

ms

ILCH

t

1.5

t

RL

CYC

Timer

Resolution (Note 2)

t

4

-

t

RES

CYC

Input Capture Pulse Width (See Figure 2)

Input Capture Pulse Period (See Figure 2)

Interrupt Pulse Width Low (Edge-Triggered) (See Figure 14)

Interrupt Pulse Period (See Figure 14)

OSC1 Pulse Width

t

, t

250

ns

TH TL

t

(Note 3)

250

TLTL

CYC

t

ns

ILIH

t

(Note 1)

200

CYC

t

, t

ns

OH OL

NOTES:

1. The minimum period t

should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t

.

ILIL

CYC

2. Since a 2-bit prescaler in the timer must count four internal cycles (t

), this is the limiting minimum factor in determining the timer resolution.

CYC

3. The minimum period t

should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t

.

CYC

TLTL

2-18

Speciﬁcations CDP68HSC05C4, CDP68HSC05C8

o

Serial Peripheral Interface (SPI) Timing (See Figure 3)

V

= 5V ±10%, V = 0V, T = 0 C to +70 C

DD

SS

A

Unless Otherwise Speciﬁed.

NUMBER

PARAMETER

SYMBOL

MIN

MAX

UNITS

Operating Frequency

Master

f

DC

0.5

4.0

f

(Note 3)

MHz

OP(M)

OP

Slave

f

OP(S)

1

2

3

4

5

6

7

Cycle Time

Master

t

2.0

-

t

CYC

CYC(M)

Slave

t

250

ns

CYC(S)

Enable Lead Time

Master

t

(Note 1)

TBD

-

LEAD(M)

Slave

t

ns

LEAD(S)

Enable Lag Time

Master

t

(Note 1)

TBD

-

LAG(M)

Slave

t

ns

LAG(S)

Clock (SCK) High Time

Master

t

TBD

-

ns

W(SCKH)M

Slave

t

W(SCKH)S

Clock (SCK) Low Time

Master

t

TBD

-

ns

W(SCKL)M

Slave

t

W(SCKL)S

Data Setup Time (Inputs)

Master

t

TBD

-

ns

SU(M)

Slave

t

SU(S)

Data Hold Time (Inputs)

Master

t

TBD

-

ns

H(M)

Slave

t

H(S)

8

9

Access Time (Time to Data Active from High Impedance State)

Slave

t

0

-

TBD

ns

A

Disable Time (Hold Time to High Impedance State)

Slave

t

DIS

10

Data Valid Time

Master (Before Capture Edge)

t

TBD

-

t

V(M)

CYC(M)

Slave (After Enable Edge) (Note 2)

t

TBD

ns

V(S)

11

12

13

Data Hold Time (Outputs)

Master (After Capture Edge)

t

TBD

0

-

HO(M)

CYC(M)

Slave (After Enable Edge)

t

ns

HO(S)

Rise Time (V = 20% to 70%, C = 200pF)

DD

L

SPI Outputs (SCK, MOSI, MISO)

SPI Inputs (SCK, MOSI, MISO, SS)

t

-

TBD

ns

R(M)

t

µs

R(S)

Fall Time (V = 20% to 70%, C = 200pF)

DD

L

SPI Outputs (SCK, MOSI, MISO)

SPI Inputs (SCK, MOSI, MISO, SS)

t

-

TBD

ns

F(M)

t

µs

F(S)

NOTES:

1. Signal Production depends on software.

2. Assumes 200pF load on all SPI pins.

3. Note that the units this specification uses is f (internal operating frequency), not MHz! In the master mode the SPI bus is capable of

OP

running at one-half of the devices’s internal operating frequency, therefore 2.0MHz maximum.

2-19

Speciﬁcations CDP68HSC05C4, CDP68HSC05C8

o

Serial Peripheral Interface (SPI) Timing (See Figure 3)

V

= 3.3V ±10%, V = 0V, T = 0 C to +70 C

DD

SS

A

Unless Otherwise Speciﬁed.

NUMBER

PARAMETER

SYMBOL

MIN

MAX

UNITS

Operating Frequency

Master

f

DC

0.5

1.0

f

(Note 3)

MHz

OP(M)

OP

Slave

f

OP(S)

1

2

3

4

5

6

7

Cycle Time

Master

t

2.0

1.0

-

t

CYC

CYC(M)

Slave

t

µs

CYC(S)

Enable Lead Time

Master

t

(Note 1)

500

-

LEAD(M)

Slave

t

ns

LEAD(S)

Enable Lag Time

Master

t

(Note 1)

500

-

LAG(M)

Slave

t

ns

LAG(S)

Clock (SCK) High Time

Master

t

720

400

-

ns

W(SCKH)M

Slave

t

W(SCKH)S

Clock (SCK) Low Time

Master

t

720

400

-

ns

W(SCKL)M

Slave

t

W(SCKL)S

Data Setup Time (Inputs)

Master

t

200

-

ns

SU(M)

Slave

t

SU(S)

Data Hold Time (Inputs)

Master

t

200

-

ns

H(M)

Slave

t

H(S)

8

9

Access Time (Time to Data Active from High Impedance State)

Slave

t

0

-

250

500

ns

A

Disable Time (Hold Time to High Impedance State)

Slave

t

DIS

10

Data Valid Time

Master (Before Capture Edge)

t

0.25

-

t

V(M)

CYC(M)

Slave (After Enable Edge) (Note 2)

t

500

ns

V(S)

11

12

Data Hold Time (Outputs)

Master (After Capture Edge)

t

0.25

0

-

HO(M)

CYC(M)

Slave (After Enable Edge)

t

ns

HO(S)

Rise Time (V = 20% to 70%, C = 200pF)

DD

L

SPI Outputs (SCK, MOSI, MISO)

SPI Inputs (SCK, MOSI, MISO, SS)

t

-

200

2.0

ns

R(M)

t

µs

R(S)

13

Fall Time (V = 20% to 70%, C = 200pF)

DD L

SPI Outputs (SCK, MOSI, MISO)

SPI Inputs (SCK, MOSI, MISO, SS)

t

-

200

2.0

ns

F(M)

t

µs

F(S)

NOTES:

1. Signal Production depends on software.

2. Assumes 200pF load on all SPI pins.

3. Note that the units this specification uses is f (internal operating frequency), not MHz! In the master mode the SPI bus is capable of

OP

running at one-half of the devices’s internal operating frequency, therefore 500kHz maximum.

2-20

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

Control Timing Diagrams (All Types)

OSC1

(NOTE 1)

t_RL

RESET

t_ILIH

IRQ

(NOTE 2)

t_ILCH

4064 t_CYC

IRQ

(NOTE 3)

INTERNAL

CLOCK

INTERNAL

ADDRESS

BUS

1FFE

1FFE 1FFE 1FFE

NOTES:

RESET OR INTERRUPT

VECTOR FETCH

1. Represents the internal gating of the OSC1 pin.

2. IRQ pin edge-sensitive mask option.

3. IRQ pin level and edge-sensitive mask option.

FIGURE 1. STOP RECOVERY TIMING DIAGRAM

t_TLTL

t_TH

t_TL

EXTERNAL

(TCAP PIN 37)

FIGURE 2. TIMER RELATIONSHIPS

Serial Peripheral Interface (SPI) Timing Diagrams (All Types)

HELD HIGH ON MASTER

SS (INPUT)

(1)

(13)

(12)

SCK (OUTPUT)

MISO (INPUT)

(4)

(5)

D7I

D6I

D0I

(6)

(7)

D7O

(11)

D6O

D0O

MOSI (OUTPUT)

(10)

FIGURE 3A. SPI MASTER TIMING CPOL = 0, CPHA = 1

FIGURE 3. TIMING DIAGRAMS

2-21

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

Serial Peripheral Interface (SPI) Timing Diagrams (All Types) (Continued)

HELD HIGH ON MASTER

SS (INPUT)

(1)

(12)

(13)

SCK (OUTPUT)

MISO (INPUT)

(5)

(4)

D7I

D6I

D0I

(6)

(7)

D7O

(11)

D6O

D0O

MOSI (OUTPUT)

(10)

NOTE: Measurement points are V , V , V and V

IH

OL

OH

IL

FIGURE 3B. SPI MASTER TIMING CPOL = 1, CPHA = 1

HELD HIGH ON MASTER

(1)

SS (INPUT)

(13)

(12)

SCK (OUTPUT)

(4)

(5)

D7I

D6I

D0I

MISO (INPUT)

(7)

D7O

(11)

(6)

D6O

D0O

MOSI (OUTPUT)

(10)

FIGURE 3C. SPI MASTER TIMING CPOL = 0, CPHA = 0

HELD HIGH ON MASTER

SS (INPUT)

(1)

(13)

(12)

SCK (OUTPUT)

(5)

(4)

D7I

D6I

D0I

MISO (INPUT)

(7)

(6)

D7O

(11)

D6O

D0O

MOSI (OUTPUT)

(10)

NOTE: Measurement points are V , V , V and V

IH

OL

OH

IL

FIGURE 3D. SPI MASTER TIMING CPOL = 1, CPHA = 0

FIGURE 3. TIMING DIAGRAMS (Continued)

2-22

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

Serial Peripheral Interface (SPI) Timing Diagrams (All Types) (Continued)

SS (INPUT)

(2)

(4)

(3)

(1)

(12)

(13)

SCK (INPUT)

LAST

BIT

(5)

TRANSMITTED

HIGH

Z

MISO (OUTPUT)

D7O

D7I

D6O

D6I

D0O

(8)

(10)

(11)

(9)

D0I

MOSI (INPUT)

(6)

(7)

FIGURE 3E. SPI SLAVE TIMING CPOL = 0, CPHA = 1

SS (INPUT)

SCK (INPUT)

(2)

(5)

(1)

(3)

(12)

(13)

LAST

BIT

TRANSMITTED

(4)

D7O

D6O

D0O

MISO (OUTPUT)

MOSI (INPUT)

(8)

(10)

(11)

(9)

D7I

D6I

D0I

(6)

(7)

NOTE: Measurement points are V , V , V and V

IH

OL

OH

IL

FIGURE 3F. SPI SLAVE TIMING CPOL = 1, CPHA = 1

SS

(INPUT)

(1)

(2)

(12)

(13)

(3)

SCK

(INPUT)

(4)

(5)

MISO

(OUTPUT)

D7O

D6O

D6I

D0O

(9)

(8)

(11)

(10)

MOSI

(INPUT)

D7I

D0I

(6)

(7)

FIGURE 3G. SPI SLAVE TIMING CPOL = 0, CPHA = 0

FIGURE 3. TIMING DIAGRAMS (Continued)

2-23

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

Serial Peripheral Interface (SPI) Timing Diagrams (All Types) (Continued)

SS

(INPUT)

(2)

(1)

(12)

(13)

(3)

SCK

(INPUT)

(4)

(5)

MISO

(OUTPUT)

D7O

D6O

D0O

(10)

(8)

(9)

(11)

MOSI

(INPUT)

D7I

D0I

D6I

NOTE: Measurement points are V , V , V and V

IH

(7)

OL

OH

IL

(6)

FIGURE 3H. SPI SLAVE TIMING CPOL = 1, CPHA = 0

FIGURE 3. TIMING DIAGRAMS (Continued)

TCAP

Functional Pin Description, Input/Output

Programming, Memory, CPU Registers,

and Self-Check

This section provides a description of the functional pins,

input/output programming, memory, CPU registers, and self-

check.

The TCAP input controls the input capture feature for the on-

chip programmable timer system. Refer to Input Capture

Register for additional information.

TCMP

The TCMP pin (35) provides an output for the output com-

pare feature of the on-chip timer system. Refer to Output

Compare Register for additional information.

FUNCTIONAL PIN DESCRIPTION

V_DDand V_SS

OSC1, OSC2

Power is supplied to the MCU using these two pins. V_DDis

power and V_SSis ground.

The CDP68HC05C4 family of MCUs can be conﬁgured to

accept either a crystal input or an RC network to control the

internal oscillator. The internal clocks are derived by a

divide-by-two of the internal oscillator frequency (f_OSC).

IRQ (Maskable Interrupt Request)

IRQ is a programmable option which provides two different

choices of interrupt triggering sensitivity. These options are:

1.) Negative edge-sensitive triggering only, or 2.) Both nega- Crystal

tive edge-sensitive and level-sensitive triggering. In the latter

The circuit shown in Figure 4B is recommended when using

case, either type of input to the IRQ pin will produce the

interrupt. The MCU completes the current instruction before

it responds to the interrupt request. When the IRQ pin goes

low for at least one t_ILIH, a logic one is latched internally to

signify an interrupt has been requested. When the MCU

completes its current instruction, the interrupt latch is tested.

If the interrupt latch contains a logic one, and the interrupt

mask bit (I bit) in the condition code register is clear, the

MCU then begins the interrupt sequence.

a crystal. The internal oscillator is designed to interface with

an AT-cut parallel resonant quartz-crystal resonator in the

frequency range speciﬁed for f_OSCin Control Timing. Use of

an external CMOS oscillator is recommended when crystals

outside the speciﬁed ranges are to be used. The crystal and

components should be mounted as close as possible to the

input pins to minimize output distortion and startup stabiliza-

tion time. Refer to DC Electrical Speciﬁcations for V_DD

speciﬁcations.

If the option is selected to include level-sensitive triggering,

then the IRQ input requires an external resistor to V_DDfor

“wire-OR” operation. See INTERRUPTS for more detail con-

cerning interrupts.

Ceramic Resonator

A ceramic resonator may be used in place of the crystal in cost-

sensitive applications. The circuit in Figure 4B is recommended

when using a ceramic resonator. Figure 4A lists the recom-

mended capacitance and feedback resistance values. The

manufacturer of the particular ceramic resonator being consid-

ered should be consulted for speciﬁc information.

RESET

The RESET input is not required for startup but can be used to

reset the MCU internal state and provide an orderly software

startup procedure. Refer to RESETS for a detailed description.

2-24

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

RC

PB0 - PB7

If the RC oscillator option is selected, then a resistor is con- These eight lines comprise port B. The state of any pin is

nected to the oscillator pins as shown in Figure 4D.

software programmable and all port B lines are conﬁgured

as input during power-on or reset. Refer to Input/Output

Programming paragraph for a detailed description of I/O

programming.

External Clock

An external clock should be applied to the OSC1 input with

the OSC2 input not connected, as shown in Figure 4E. An

external clock may be used with either the RC or crystal

PC0 - PC7

oscillator option. The t_OXOVor t_ILCHspeciﬁcations do not These eight lines comprise port C. The state of any pin is

apply when using an external clock input. The equivalent software programmable and all port C lines are conﬁgured

speciﬁcation of the external clock source should be used in as input during power-on reset. Refer to Input/Output

lieu of t_OXOVor t_ILCH

.

Programming paragraph for a detailed description of I/O

programming.

PA0 - PA7

PD0 - PD5, PD7

These eight I/O lines comprise port A. The state of any pin is

software programmable and all port A lines are conﬁgured These seven lines comprise port D, a ﬁxed input port that is

as input during power-on or reset. Refer to Input/Output enabled during power-on. All enabled special functions (SPI

Programming paragraph for a detailed description of I/O and SCI) affect the pins on this port. Four of these lines,

programming.

PD2/MISO, PD3/MOSI, PD4/SCK, and PD5/SS, are used in

CRYSTAL

CERAMIC RESONATOR

2MHz

400

5

4MHz

75

UNITS

Ω

2MHz - 4MHz

UNITS

Ω

R

C

R

C

R

(Typical)

10

40

SMAX

0

S

0

1

7

pF

0.008

0.012

15 - 30

15 - 25

10

pF

4.3

pF

1

15 - 40

15 - 30

10

pF

30

pF

OSC1

OSC2

P

OSC1

OSC2

P

pF

30

pF

MΩ

K

1 - 10

1250

MΩ

-

Q

30

40

Q

FIGURE 4A. CRYSTAL/CERAMIC RESONATOR PARAMETERS

L

C₁

R_S

MCU

OSC2

38

OSC1

39

OSC1

OSC2

38

R_P

39

C₀

C_OSC1

C_OSC2

38

39

FIGURE 4B. CRYSTAL OSCILLATOR CONNECTIONS

FIGURE 4C. EQUIVALENT CRYSTAL CIRCUIT

MCU

OSC1

39

OSC2

38

OSC1

39

OSC2

38

UNCONNECTED

EXTERNAL CLOCK

R

FIGURE 4D. RC OSCILLATOR CONNECTIONS

FIGURE 4E. EXTERNAL CLOCK SOURCE CONNECTIONS

FIGURE 4. OSCILLATOR CONNECTIONS

2-25

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

the serial peripheral interface (SPI). Two of these lines, serial data output/input (MOSI), system clock (SCK), and

PD0/RDI and PD1/TD0, are used in the serial communica- slave select (SS) respectively. Refer to Serial Communica-

tions interface (SCI). Refer to INPUT/OUTPUT PROGRAM- tions Interface and Serial Peripheral Interface for a more

MING for a detailed description of I/O programming.

INPUT/OUTPUT PROGRAMMING

Parallel Ports

detailed discussion.

DATA

DIR REG

BIT

Ports A, B, and C may be programmed as an input or an out-

put under software control. The direction of the pins is deter-

mined by the state of the corresponding bit in the port data

direction register (DDR). Each 8-bit port has an associated

8-bit data direction register. Any port A, port B, or port C pin

is conﬁgured as an output if its corresponding DDR bit is set

to a logic one. A pin is conﬁgured as an input if its corre-

sponding DDR bit is cleared to a logic zero. At power-on or

reset, all DDRs are cleared, which conﬁgure all port A, B,

and C pins as inputs. The data direction registers are capa-

ble of being written to or read by the processor. Refer to Fig-

ure 5 and Table 1. During the programmed output state, a

read of the data register actually reads the value of the out-

put data latch and not the I/O pin.

OUTPUT

I/O

LATCHED

OUTPUT

DATA BIT

INPUT REG BIT

INPUT I/O

FIGURE 5A.

7

6

5

4

3

2

1

0

TYPICAL

PORT DATA

DIRECTION

REGISTER

DDR 7 DDR 6 DDR 5 DDR 4 DDR 3 DDR 2 DDR 1 DDR 0

TYPICAL

PORT

REGISTER

TABLE 1. I/O PIN FUNCTIONS

(NOTE)

R/W

DDR

I/O PIN FUNCTION

P7

P6

P5

P4

P3

P2

P1

P0

0

The I/O pin is in input mode. Data is

written into the output data latch.

FIGURE 5B.

0

1

Data is written into the output data latch

and output to the I/O pin.

V_DD

PORT DATA

PORT DRR

1

0

1

The state of the I/O pin is read.

P (NOTE 1)

N (NOTE 1)

The I/O pin is in an output mode. The

output data latch is read.

PAD

NOTE: R/W is an internal signal.

INTERNAL LOGIC

Fixed Port

Port D is a 7-bit ﬁxed input port (PD0 - PD5, PD7) that con-

tinually monitors the external pins whenever the SPI or SCI

systems are disabled. During power-on reset or external

reset all seven bits become valid input ports because all

special function output drivers are disabled. For example,

with the serial peripheral interface (SPI) system disabled

(SPE = 0) PD2 through PD5 will read the state of the pin at

the time of the read operation. No data register is associated

with the port when it is used as an input.

NOTES:

1. Denotes devices have same physical size, and are enhancement

type.

2. IP = Input Protection

3. Latch-up protection not shown.

FIGURE 5C.

FIGURE 5. TYPICAL PARALLEL PORT I/O CIRCUITRY

NOTE: It is recommended that all unused inputs, except OSC2, and

I/O ports (conﬁgured as inputs) be tied to an appropriate logic level

MEMORY

(e.g. either V or V ).

DD

SS

As shown in Figure 6, the CDP68HC05C4, CDP68HCL05C4

and CDP68HSC05C4 MCUs are capable of addressing

Serial Port (SCI and SPI)

The serial communications interface (SCI) and serial periph- 8192 bytes of memory and I/O registers with its program

eral interface (SPI) use the port D pins for their functions. counter. The MCUs have implemented 4601 bytes of these

The SCI function requires two of the pins (PD0 - PD1) for its locations. The ﬁrst 256 bytes of memory (page zero)

receive data input (RDI) and transmit data output (TDO) include 25 bytes of I/O features such as data ports, the port

respectively, whereas the SPI function requires four of the DDRs, timer, serial peripheral interface (SPI), and serial

pins (PD2 - PD5) for its serial data input/output (MISO), communication interface (SCI); 48 bytes of user ROM, and

2-26

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

$0000

0000

PORT A DATA REGISTER

PORT B DATA REGISTER

$00

$01

$02

$03

$04

$05

$06

$07

$08

$09

$0A

$0B

$0C

$0D

$0E

$0F

$10

$11

$12

$13

$14

$15

$16

$17

$18

$19

$1A

$1B

$1C

$1D

$1E

$1F

PORTS

7 BYTES

I/O

32 BYTES

PORT C DATA REGISTER

PORT D FIXED INPUT REGISTER

PORT A DATA DIRECTION REGISTER

PORT B DATA DIRECTION REGISTER

PORT C DATA DIRECTION REGISTER

UNUSED

3 BYTES

$001F

$0020

0031

0032

USER

ROM

48 BYTES

SERIAL

PERIPHERAL

INTERFACE

3 BYTES

0079

0080

$004F

$0050

UNUSED

RAM

SERIAL PERIPHERAL CONTROL REGISTER

SERIAL PERIPHERAL STATUS REGISTER

SERIAL PERIPHERAL DATA I/O REGISTER

SERIAL COMMUNICATIONS BAUD RATE REGISTER

SERIAL COMMUNICATIONS CONTROL REGISTER 1

SERIAL COMMUNICATIONS CONTROL REGISTER 2

SERIAL COMMUNICATIONS STATUS REGISTER

SERIAL COMMUNICATIONS DATA REGISTER

TIMER CONTROL REGISTER

176 BYTES

SERIAL

COMMUNICATIONS

INTERFACE

$00BF

$00C0

0191

0192

5 BYTES

STACK

64 BYTES

TIMER

10 BYTES

$00FF

$0100

0255

0256

USER

ROM

4096 BYTES

UNUSED

4 BYTES

$10FF

$1100

4351

4352

0031

TIMER STATUS REGISTER

INPUT CAPTURE HIGH REGISTER

INPUT CAPTURE LOW REGISTER

OUTPUT COMPARE HIGH REGISTER

OUTPUT COMPARE LOW REGISTER

COUNTER HIGH REGISTER

UNUSED

3584 BYTES

$1EFF

$1F00

7935

7936

SELF CHECK

COUNTER LOW REGISTER

ALTERNATE COUNTER HIGH REGISTER

ALTERNATE COUNTER LOW REGISTER

UNUSED

$1FDF

$1FE0

256 BYTES

SELF CHECK

VECTORS

UNUSED

$1FEF

$1FF0

8175

8176

USER

VECTORS

16 BYTES

UNUSED

$1FFF

8191

FIGURE 6. ADDRESS MAP FOR CDP68HC05C4, CDP68HCL05C4 AND CDP68HSC05C4

176 bytes of RAM. The next 4096 bytes complete the user age. Figure

7

illustrates the memory map for

ROM. The self-check ROM (224 bytes) and self-check vec- CDP68HC05C8, CDP68HCL05C8 and CDP68HSC05C8

tors (16 bytes) are contained in memory locations $1F00 MCUs. It is similar to the memory map in Figure 6, except for

through $1FEF. The 16 highest address bytes contain the 3584 bytes of additional user ROM at memory locations

user deﬁned reset and the interrupt vectors. Seven bytes of $1100 through $1EFF.

the lowest 32 memory locations are unused and the 176

bytes of user RAM include up to 64 bytes for the stack.

CPU REGISTER

Since most programs use only a small part of the allocated

stack locations for interrupts and/or subroutine stacking pur-

poses, the unused bytes are usable for program data stor-

The CPU contains ﬁve registers, as shown in the program-

ming model of Figure 8. The interrupt stacking order is

shown in Figure 9.

2-27

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

$0000

0000

PORT A DATA REGISTER

PORT B DATA REGISTER

$00

$01

$02

$03

$04

$05

$06

$07

$08

$09

$0A

$0B

$0C

$0D

$0E

$0F

$10

$11

$12

$13

$14

$15

$16

$17

$18

$19

$1A

$1B

$1C

$1D

$1E

$1F

PORTS

7 BYTES

I/O

32 BYTES

PORT C DATA REGISTER

PORT D FIXED INPUT REGISTER

PORT A DATA DIRECTION REGISTER

PORT B DATA DIRECTION REGISTER

PORT C DATA DIRECTION REGISTER

UNUSED

3 BYTES

$001F

$0020

0031

0032

USER

ROM

48 BYTES

SERIAL PERIPHERAL

0079

0080

$004F

$0050

INTERFACE

3 BYTES

UNUSED

RAM

176 BYTES

SERIAL PERIPHERAL CONTROL REGISTER

SERIAL PERIPHERAL STATUS REGISTER

SERIAL PERIPHERAL DATA I/O REGISTER

SERIAL COMMUNICATIONS BAUD RATE REGISTER

SERIAL COMMUNICATIONS CONTROL REGISTER 1

SERIAL COMMUNICATIONS CONTROL REGISTER 2

SERIAL COMMUNICATIONS STATUS REGISTER

SERIAL COMMUNICATIONS DATA REGISTER

TIMER CONTROL REGISTER

TIMER STATUS REGISTER

SERIAL

COMMUNICATIONS

INTERFACE

5 BYTES

$00BF

$00C0

0191

0192

STACK

64 BYTES

TIMER

10 BYTES

$00FF

$0100

0255

0256

USER

ROM

7680 BYTES

UNUSED

4 BYTES

0031

INPUT CAPTURE HIGH REGISTER

INPUT CAPTURE LOW REGISTER

OUTPUT COMPARE HIGH REGISTER

OUTPUT COMPARE LOW REGISTER

COUNTER HIGH REGISTER

$1EFF

$1F00

7935

7936

SELF CHECK

COUNTER LOW REGISTER

ALTERNATE COUNTER HIGH REGISTER

ALTERNATE COUNTER LOW REGISTER

UNUSED

$1FDF

$1FE0

256 BYTES

SELF CHECK

VECTORS

UNUSED

$1FEF

$1FF0

8175

8176

USER

VECTORS

16 BYTES

UNUSED

$1FFF

8191

FIGURE 7. ADDRESS MAP FOR CDP68HC05C8, CDP68HCL05C8 AND CDP68HSC05C8

0

7

A

ACCUMULATOR

STACK

0

7

0

CONDITION CODE REG

ACCUMULATOR (A)

1

0

1

X

INDEX REGISTER

PROGRAM COUNTER

STACK POINTER

12

PC

INDEX REGISTER (X)

7

PROGRAM COUNTER HIGH

0

1

SP

PROGRAM COUNTER LOW

4

CC

N

H

I

Z

C

CONDITION CODE REG

UNSTACK

CARRY/BORROW

ZERO

NEGATIVE

INTERRUPT MASK

HALF CARRY

NOTE: Since the Stack Pointer decrements during pushes, the PCL

is stacked ﬁrst, followed by PCH, etc. Pulling from the stack is in the

reverse order.

FIGURE 8. PROGRAMMING MODEL

FIGURE 9. STACKING ORDER

2-28

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

Accumulator (A)

Zero (Z)

The accumulator is an 8-bit general purpose register used to When set, this bit indicates that the result of the last arith-

hold operands, results of the arithmetic calculations, and metic, logical, or data manipulation is zero.

data manipulations.

Carry/Borrow (C)

Index Register (X)

Indicates that a carry or borrow out of the arithmetic logic

The X register is an 8-bit register which is used during the unit (ALU) occurred during the last arithmetic operation. This

indexed modes of addressing. It provides an 8-bit value bit is also affected during bit test and branch instructions,

which is used to create an effective address. The index reg- shifts, and rotates.

ister is also used for data manipulations with the read-mod-

ify-write type of instructions and as a temporary storage

SELF-CHECK

register when not performing addressing operations.

The self-check capability of the CDP68HC05C4 MCU pro-

vides an internal check to determine if the device is functional.

Self-check is performed using the circuit shown in the sche-

Program Counter (PC)

The program counter is a 13-bit register that contains the matic diagram of Figure 10. As shown in the diagram, port C

address of the next instruction to be executed by the processor. pins PC0 - PC3 are monitored (light emitting diodes are

shown but other devices could be used) for the self-check

results. The self-check mode is entered by applying a 9V

Stack Pointer (SP)

input (through a 4.7kΩ resistor) to the IRQ pin (2) and 5V

input (through a 4.7kΩ resistor) to the TCAP pin (37) and then

depressing the reset switch to execute a reset. After reset, the

following seven tests are performed automatically:

The stack pointer is a 13-bit register containing the address of

the next free locations on the push-down/pop-up stack. When

accessing memory, the most signiﬁcant bits are permanently

conﬁgured to 0000011. These bits are appended to the six

least signiﬁcant register bits to produce an address within the

range of $00FF to $00CO. The stack area of RAM is used to

store the return address on subroutine calls and the machine

state during interrupts. During external or power-on reset, and

during a reset stack pointer (RSP) instruction, the stack

pointer is set to its upper limit ($00FF). Nested interrupt and/or

subroutines may use up to 64 (decimal) locations. When the

64 locations are exceeded, the stack pointer wraps around

and points to its upper limit ($00FF), thus, losing the previ-

ously stored information. A subroutine call occupies two RAM

bytes on the stack, while an interrupt uses ﬁve RAM bytes.

I/O - Functionally exercises ports A, B and C

RAM - Counter test for each RAM byte

Timer - Tracks counter register and checks OCF ﬂags

SCI - Transmission Test; checks for RDRF, TDRE,

TC, and FE ﬂags

ROM - Exclusive OR with odd ones parity result

SPI - Transmission test with check for SPIF,

WCOL, and MODF ﬂags

INTERRUPTS - Tests external, timer, SCI, and SPI interrupts

Condition Code Register (CC)

Self-check results (using the LEDs as monitors) are shown

in Table 2. The following subroutines are available to user

programs and do not require any external hardware.

The condition code register is a 5-bit register which indicates

the results of the instruction just executed as well as the

state of the processor. These bits can be individually tested

by a program and speciﬁed action taken as a result of their

state. Each bit is explained in the following paragraphs.

TABLE 2. SELF-CHECK RESULTS

PC3

1

PC2

0

PC1

0

PC0

1

REMARKS

Bad I/O

Half Carry Bit (H)

1

0

1

0

Bad RAM

Bad Timer

Bad SCI

Bad ROM

Bad SPI

The H bit is set to a one when a carry occurs between bits 3

and 4 of the ALU during an ADD or ADC instruction. The H

bit is useful in binary coded decimal subroutines.

1

0

1

0

1

0

1

Interrupt Mask Bit (I)

1

0

When the I bit is set, all interrupts are disabled. Clearing this

bit enables the interrupts. If an external interrupt occurs

while the I bit is set, the interrupt is latched and processed

after the I bit is next cleared; therefore, no interrupts are lost

because of the I bit being set. An internal interrupt can be

lost if it is cleared while the I bit is set (refer to Programmable

Timer, Serial Communications Interface, and Serial Periph-

eral Interface Sections for more information).

1

Bad Interrupts or IRQ Request

Good Device

Flashing

All Others

Bad Device, Bad Port C, etc.

NOTE: 0 indicates LED on; 1 indicates LED is off.

TIMER TEST SUBROUTINE

This subroutine returns with the Z bit cleared if any error is

detected; otherwise, the Z bit is set.

Negative (N)

When set, this bit indicates that the result of the last arith-

metic, logical, or data manipulation is negative (bit 7 in the

result is a logic one).

This subroutine is called at location $1F0E. The output com-

pare register is ﬁrst set to the current timer state. Because

the timer is free running and has only a divide-by-four pres-

2-29

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

RESET

+9V

RESET

1

4.7K

1.0µF

10K

IRQ

2

3

2N3904

V_DD

+5V

NC

+5V

40

39

20pF

OSC1

10K

TCAP

37

10M

4MHz

PA7

PA6

PA5

PA4

PA3

PA2

PA1

38

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

4

5

(SEE NOTE)

PD7

TCMP

+5V

4.7K

6

PD5/SS

PD4/SCK

PD3/MOSI

PD2/MISO

PD1/TDO

PD0/RDI

PC0

7

1M

8

10K

2N3904

9

10

PA0

11

4.7K

+5V

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

12

13

14

15

16

17

18

19

4.7K

PC1

10K

PC2

PC3

PC4

PC5

PC6

PC7

V_SS

20

FIGURE 10. SELF-CHECK CIRCUIT SCHEMATIC DIAGRAM

caler, each timer count cannot be tested. The test tracks the RESET Pin

counter until the timer wraps around, triggering the output

The RESET input pin is used to reset the MCU to provide an

orderly software startup procedure. When using the external

reset mode, the RESET pin must stay low for a minimum of

one and one half t_CYC. The RESET pin contains an internal

Schmitt Trigger as part of its input to improve noise immunity.

compare ﬂag in the timer status register. RAM locations

$0050 and $0051 are overwritten. Upon return to the user’s

program, X = 40. If the test passed, A = 0.

ROM CHECKSUM SUBROUTINE

This subroutine returns with the Z bit cleared if any error is Power-On Reset

detected; otherwise, the Z bit is set. This subroutine is called

The power-on reset occurs when a positive transition is

at location $1F93 with RAM location $0053 equal to $01 and

A = 0. A short routine is set up and executed in RAM to com-

pute a checksum of the entire ROM pattern. Upon return to

the user’s program, X = 0. If the test passed, A = 0. RAM

locations $0050 through $0053 are overwritten.

detected on V_DD. The power-on reset is used strictly for

power turn-on conditions and should not be used to detect

any drops in the power supply voltage. There is no provision

for a power-down reset. The power-on circuitry provides for

a 4064 t_CYCdelay from the time that the oscillator becomes

active. If the external RESET pin is low at the end of the

4064 t_CYCtime out, the processor remains in the reset condi-

tion until RESET goes high.

Resets, Interrupts, and Low Power Modes

RESETS

Table 3 shows the actions of the two resets on internal cir-

cuits, but not necessarily in order of occurrence (X indicates

that the condition occurs for the particular reset).

The MCU has two reset modes: an active low external reset

pin (RESET) and a power-on reset function; refer to Figure 11.

2-30

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

V_DD

OSC1

(NOTE 2)

4064

t_OXOVt_CYC

t_CYC

INTERNAL

PROCESSOR

CLOCK (NOTE 1)

INTERNAL

ADDRESS BUS

(NOTE 1)

NEW

PC

NEW

PC

1FFE

PCH

1FFF

PCL

1FFE

1FFF

INTERNAL

DATA BUS

(NOTE 3)

OP

CODE

NEW

PCH

NEW

PCL

OP

CODE

t_RL

RESET

(NOTE 3)

NOTES:

1. Internal signal and bus information is not available externally.

2. OSC1 is not meant to represent frequency. It is only meant to represent time.

3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.

FIGURE 11. POWER-ON RESET AND RESET

TABLE 3. RESET ACTION ON INTERNAL CIRCUIT

INTERRUPTS

POWER-

ON

RESET

Systems often require that normal processing be interrupted

so that some external event may be serviced. The

CDP68HC05C4 may be interrupted by one of ﬁve different

methods: either one of four maskable hardware interrupts

(IRQ, SPI, SCI, or Timer) and one non-maskable software

interrupt (SWI). Interrupts such as Timer, SPI, and SCI have

several ﬂags which will cause the interrupt. Generally, inter-

rupt ﬂags are located in read-only status registers, whereas

their equivalent enable bits are located in associated control

registers. The interrupt ﬂags and enable bits are never con-

tained in the same register. If the enable bit is a logic zero it

blocks the interrupt from occurring but does not inhibit the

ﬂag from being set. Reset clears all enable bits to preclude

interrupts during the reset procedure.

RESET

CONDITION

Timer Prescaler reset to zero state

Timer counter conﬁgured to $FFFC

Timer output compare (TCMP) bit reset to zero

X

All timer interrupt enable bits cleared (ICIE,

OCIE, and TOIE) to disable timer interrupts.

The OLVL timer bit is also cleared by reset.

All data direction registers cleared to zero

(input)

X

Conﬁgure stack pointer to $00FF

X

Force internal address bus to restart vector

(See Table 4)

The general sequence for clearing an interrupt is a software

sequence of ﬁrst accessing the status register while the

interrupt ﬂag is set, followed by a read or write of an associ-

ated register. When any of these interrupts occur, and if the

enable bit is a logic one, normal processing is suspended at

the end of the current instruction execution. Interrupts cause

the processor registers to be saved on the stack (see

Figure 9) and the interrupt mask (I bit) set to prevent addi-

tional interrupts. The appropriate interrupt vector then points

to the starting address of the interrupt service routine (refer

to Figure 6 for vector location). Upon completion of the inter-

rupt service routine, the RTI instruction (which is normally a

part of the service routine) causes the register contents to be

recovered from the stack followed by a return to normal pro-

cessing. The stack order is shown in Figure 9.

Set I bit in condition code register to a logic one

Clear STOP latch

X

X (Note)

Clear external interrupt latch

Clear WAIT latch

X

Disable SCI (serial control bits TE = 0 and

RE = 0). Other SCI bits cleared by reset

include: TIE, TCIE, RIE, ILIE, RWU, SBK,

RDRF, IDLE, OR, NF, and FE.

Disable SPI (serial output enable control bit

SPE = 0). Other SPI bits cleared by reset

include: SPIE, MSTR, SPIF WCOL, and

MODF.

X

Set serial status bits TDRE and TC

X

NOTE: The interrupt mask bit (I bit) will be cleared if and only if the

corresponding bit stored in the stack is zero.

Clear all serial interrupt enable bits (SPIE,

TIE and TCIE)

Place SPI system in slave mode (MSTR = 0)

X

A discussion of interrupts, plus a table listing vector

addresses for all interrupts including reset, in the MCU is

provided in Table 4.

Clear SCI prescaler rate control bits

SCP0 - SCP1

NOTE: Timeout still occurs.

2-31

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

TABLE 4. VECTOR ADDRESS FOR INTERRUPTS AND RESET

REGISTER

N/A

FLAG NAME

INTERRUPTS

CPU INTERRUPT

VECTOR ADDRESS

$1FFE - $1FFF

$1FFC - $1FFD

$1FFA - $1FFB

$1FF8 - $1FF9

N/A

Reset

RESET

SWI

N/A

Software

N/A

External Interrupt

IRQ

Timer Status

ICF

OCF

TOF

Input Capture

Timer

Output Compare

Timer Overﬂow

SCI Status

SPI Status

TDRE

TC

Transmit Buffer Empty

Transmit Complete

Receiver Buffer Ful

Idle Line Detect

Overrun

SCI

SPI

$1FF6 - $1FF7

$1FF4 - $1FF5

RDRF

IDLE

OR

SPIF

Transfer Complete

Mode Fault

MODF

Hardware Controlled Interrupt Sequence

External Interrupt

The following three functions (RESET, STOP, and WAIT) are If the interrupt mask (I bit) of the condition code register has

not in the strictest sense an interrupt; however, they are been cleared and the external interrupt pin (IRQ) has gone

acted upon in a similar manner. Flowcharts for hardware low, then the external interrupt is recognized. When the

interrupts are shown in Figure 12, and for STOP and WAIT interrupt is recognized, the current state of the CPU is

are provided in Figure 13. A discussion is provided below.

pushed onto the stack and I bit is set. This masks further

interrupts until the present one is serviced. The interrupt ser-

vice routine address is speciﬁed by the contents of memory

location $1FFA and $1FFB. Either a level-sensitive and neg-

ative edge-sensitive trigger, or a negative edge-sensitive

only trigger are available as a mask option. Figure 14 shows

both a functional and mode timing diagram for the interrupt

line. The timing diagram shows two different treatments of

the interrupt line (IRQ) to the processor. The ﬁrst method

shows single pulses on the interrupt line spaced far enough

apart to be serviced. The minimum time between pulses is a

function of the number of cycles required to execute the

interrupt service routine plus 21 cycles. Once a pulse

occurs, the next pulse should not occur until the MCU soft-

ware has exited the routine (an RTI occurs). The second

conﬁguration shows several interrupt lines “wire-ORed” to

form the interrupts at the processor. Thus, if after servicing

one interrupt the interrupt line remains low, then the next

interrupt is recognized.

(a) A low input on the RESET input pin causes the program

to vector to its starting address which is speciﬁed by the

contents of memory locations $1FFE and $1FFF. The

I bit in the condition code register is also set. Much of the

MCU is conﬁgured to a known state during this type of

reset as previously described in RESETS paragraph.

(b) STOP - The STOP instruction causes the oscillator to be

turned off and the processor to “sleep” until an external

interrupt (IRQ) or reset occurs.

(c) WAIT - The WAIT instruction causes all processor clocks

to stop, but leaves the Timer, SCI, and SPI clocks run-

ning. This “rest” state of the processor can be cleared by

reset, an external interrupt (IRQ), Timer interrupt, SPI

interrupt, or SCI interrupt.

Software Interrupt (SWI)

The software interrupt is an executable instruction. The

action of the SWI instruction is similar to the hardware inter-

rupts. The SWI is executed regardless of the state of the

interrupt mask (I bit) in the condition code register. The inter-

rupt service routine address is speciﬁed by the contents of

memory location $1FFC and $1FFD.

NOTE: The internal interrupt latch is cleared in the ﬁrst part of the

service routine; therefore, one (and only one) external interrupt pulse

could be latched during t

cleared.

and serviced as soon as the I bit is

ILIL

2-32

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

FROMRESET

IS

I BIT

SET?

Y

N

IRQ

EXTERNAL

INTERRUPT

CLEAR IRQ

REQUEST

LATCH

Y

N

STACK

PC, X, A, CC

TIMER

INTERNAL

INTERRUPT

N

SET

I BIT

SCI

EXTERNAL

INTERRUPT

Y

LOAD PC FROM

IRQ: $1FFA - $1FFB

TIMER: $1FF8 - $1FF8

SCI: $1FF6 - $1FF7

SPI: $1FF4 - $1FF5

N

SPI

INTERNAL

INTERRUPT

COMPLETE

INTERRUPT

N

ROUTINE AND

EXECUTE RTI

EXECUTE

INSTRUCTION

FETCH NEXT

INSTRUCTION

FIGURE 12. HARDWARE INTERRUPT FLOW DIAGRAM

STOP

WAIT

STOP OSCILLATOR

AND ALL CLOCKS

OSCILLATOR ACTIVE

TIMER, SCI, AND SPI

CLOCKS ACTIVE

CLEAR I BIT

PROCESSOR CLOCKS STOPPED

N

RESET

Y

RESET

N

EXTERNAL

INTERRUPT

IRQ

Y

EXTERNAL

INTERRUPT

IRQ

N

TIMER

INTERRUPT

Y

N

TURN ON OSCILLATOR

WAIT FOR TIME

DELAY TO STABILIZE

RESTART

PROCESSOR CLOCK

SCI

Y

INTERRUPT

(1) FETCH RESET VECTOR OR

(2) SERVICE INTERRUPT

A. STACK

(1) FETCH RESET VECTOR OR

(2) SERVICE INTERRUPT

A. STACK

N

SPI

B. SET I BIT

C. VECTOR TO INTERRUPT

ROUTINE

B. SET I BIT

C. VECTOR TO INTERRUPT

ROUTINE

INTERRUPT

Y

FIGURE 13. STOP/WAIT FLOW DIAGRAM

2-33

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

Serial Communications Interface (SCI) Interrupts

LEVEL-SENSITIVE TRIGGER

MASK OPTION

An interrupt in the serial communications interface (SCI)

occurs when one of the interrupt ﬂag bits in the serial

communications status register is set, provided the I bit in

the condition code register is clear and the enable bit in the

serial communications control register 2 (locations $0F) is

enabled. When the interrupt is recognized, the current state

of the machine is pushed onto the stack and the I bit in the

condition code register is set. This masks further interrupts

until the present one is serviced. The SCI interrupt causes

the program counter to vector to memory location $1FF6

and $1FF7 which contains the starting address of the

interrupt service routine. Software in the serial interrupt

service routine must determine the priority and cause of the

SCI interrupt by examining the interrupt ﬂags and the status

bits located in the serial communications status register

(location $10). The general sequence for clearing an

interrupt is a software sequence of accessing the serial

communications status register while the ﬂag is set followed

by a read or write of an associated register. Refer to Serial

Communications Interface for a description of the SCI

system and its interrupts.

V_DD

EXTERNAL

INTERRUPT

REQUEST

D

Q

C

I BIT (CC)

R

POWER-ON RESET

INTERRUPT

EXTERNAL RESET

EXTERNAL INTERRUPT

BEING SERVICED

(READ OF VECTORS)

FIGURE 14A. EXTERNAL INTERRUPT FUNCTION DIAGRAM

IRQ

t_ILIH

t_ILIL

IRQ1

t_ILIH

NORMALLY

USED WITH

WIRE - ORED

CONNECTION

IRQn

Serial Peripheral Interface (SPI) Interrupts

An interrupt in the serial peripheral interface (SPI) occurs

when one of the interrupt ﬂag bits in the serial peripheral sta-

tus register (location $0B) is set, provided the I bit in the con-

dition code register is clear and the enable bit in the serial

peripheral control register (location $0A) is enabled. When

the interrupt is recognized, the current state of the machine

is pushed onto the stack and the I bit in the condition code

register is set. This masks further interrupts until the present

one is serviced. The SPI interrupt causes the program

counter to vector to memory location $1FF4 and $1FF5

which contain the starting address of the interrupt service

routine. Software in the serial peripheral interrupt service

routine must determine the priority and cause of the SPI

interrupt by examining the interrupt ﬂag bits located in the

SPI status register. The general sequence for clearing an

interrupt is a software sequence of accessing the status reg-

ister while the ﬂag is set, followed by a read or write of an

associated register. Refer to Serial Peripheral Interface for

a description of the SPI system and its interrupts.

IRQ

(MCU)

NOTE:

Edge-Sensitive Trigger Condition - The minimum pulse width (t

is either 125ns (V

should be less than the number of t

the interrupt service routine plus 21 t

)

ILIH

= 5V) or 250ns (V

= 3V). The period t

DD

DD ILIL

cycles it takes to execute

cycles.

CYC

Level-Sensitive Trigger Condition - If after servicing an interrupt the

IRQ remains low, then the next interrupt is recognized.

FIGURE 14B. EXTERNAL INTERRUPT MODE DIAGRAM

FIGURE 14.

Timer Interrupt

There are three different timer interrupt ﬂags that will cause

a timer interrupt whenever they are set and enabled. These

three interrupt ﬂags are found in the three most signiﬁcant

bits of the timer status register (TSR, location $13) and all

three will vector to the same interrupt service routine

($1FF8 - $1FF9).

LOW POWER MODES

STOP Instruction

All interrupt ﬂags have corresponding enable bits (ICIE,

OCIE, and TOIE) in the timer control register (TCR, location

$12). Reset clears all enable bits, thus preventing an inter-

rupt from occurring during the reset time period. The actual

processor interrupt is generated only if the I bit in the condi-

tion code register is also cleared. When the interrupt is rec-

ognized, the current machine state is pushed onto the stack

and I bit is set. This masks further interrupts until the present

one is serviced. The interrupt service routine address is

speciﬁed by the contents of memory location $1FF8 and

$1FF9. The general sequence for clearing an interrupt is a

software sequence of accessing the status register while the

ﬂag is set, followed by a read or write of an associated regis-

ter. Refer to Programmable Timer for additional information

about the timer circuitry.

The STOP instruction places the MCU in its lowest power

consumption mode. In the STOP mode the internal oscillator

is turned off, causing all internal processing to be halted;

refer to Figure 13. During the STOP mode, the I bit in the

condition code register is cleared to enable external inter-

rupts. All other registers and memory remain unaltered and

all input/output lines remain unchanged. This continues until

an external interrupt (IRQ) or reset is sensed at which time

the internal oscillator is turned on. The external interrupt or

reset causes the program counter to vector to memory loca-

tion $1FFA and $IFFB or $1FFE and $1FFF which contains

the starting address of the interrupt or reset service routine

respectively.

2-34

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

WAIT Instruction

vary from several microseconds to many seconds. A block

diagram of the timer is shown in Figure 15 and timing dia-

grams are shown in Figure 16 through Figure 19.

The WAIT instruction places the MCU in a low power con-

sumption mode, but the WAIT mode consumes somewhat

more power than the STOP mode. In the WAIT mode, the Because the timer has a 16-bit architecture, each speciﬁc

internal clock remains active, and all CPU processing is functional segment (capability) is represented by two regis-

stopped; however, the programmable timer, serial peripheral ters. These registers contain the high and low byte of that

interface, and serial communications interface systems functional segment. Generally, accessing the low byte of a

remain active. Refer to Figure 13. During the WAIT mode, speciﬁc timer function allows full control of that function;

the I bit in the condition code register is cleared to enable all however, an access of the high byte inhibits that speciﬁc

interrupts. All other registers and memory remain unaltered timer function until the low byte is also accessed.

and all parallel input/output lines remain unchanged. This

continues until any interrupt or reset is sensed. At this time

nipulating both the high and low byte register of a speciﬁc timer function

NOTE: The I bit in the condition code register should be set while ma-

the program counter vectors to the memory location ($1FF4

through $1FFF) which contains the starting address of the

interrupt or reset service routine.

to ensure that an interrupt does not occur. This prevents interrupts from

occurring between the time that the high and low bytes are accessed.

The programmable timer capabilities are provided by using

the following ten addressable 8-bit registers (note the high

and low represent the signiﬁcance of the byte). A description

of each register is provided below.

DATA RETENTION MODE

The contents of RAM and CPU registers are retained at sup-

ply voltages as low as 2V. This is referred to as the DATA

RETENTION mode, where the data is held, but the device is

not guaranteed to operate.

Timer Control Register (TCR) locations $12,

Timer Status Register (TSR) location $13,

Input Capture High Register location $14,

Input Capture Low Register location $15,

Output Compare High Register location $16,

Output Compare Low Register location $17,

Counter High Register location $18,

Counter Low Register location $19,

Alternate Counter High Register location $1A, and

Alternate Counter Low Register location $1B.

Programmable Timer

INTRODUCTION

The programmable timer, which is preceded by a ﬁxed

divide-by-four prescaler, can be used for many purposes,

including input waveform measurements while simulta-

neously generating an output waveform. Pulse widths can

MCU INTERNAL BUS

INTERNAL

PROCESSOR

CLOCK

8-BIT

BUFFER

HIGH

BYTE BYTE

LOW

HIGH

BYTE

HIGH LOW

BYTE BYTE

LOW

BYTE

÷4

16 - BIT FREE

RUNNING

COUNTER

INPUT

CAPTURE

REGISTER

OUTPUT

COMPARE

REGISTER

$16

$17

$18

$19

$14

$15

COUNTER

ALTERNATE

REGISTER

$1A

$1B

OUTPUT

COMPARE

CIRCUIT

OVERFLOW

DETECT

CIRCUIT

EDGE

DETECT

CIRCUIT

D

Q

CLK

C

OUTPUT

LEVEL REG.

TIMER

STATUS

REG.

$13

ICF OCF TOF

ICIE OCIE TOIE IEDG OLVL

RESET

TIMER

CONTROL

REG.

OUTPUT EDGE

LEVEL INPUT

(TCMP (TCAP

PIN 35) PIN 37)

INTERRUPT

CIRCUIT

$12

FIGURE 15. PROGRAMMABLE TIMER BLOCK DIAGRAM

2-35

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

INTERNAL PROCESSOR CLOCK

(INTERNAL RESET)

T00

T01

INTERNAL TIMER CLOCKS

T10

T11

COUNTER (16 - BIT)

$FFFC

$FFFD

$FFFE

$FFFF

RESET (EXTERNAL OR END OF POR)

NOTE:

1. The Counter Register and the Timer Control Register are the only ones affected by RESET.

FIGURE 16. TIMER STATE DIAGRAM FOR RESET

INTERNAL PROCESSOR

CLOCK

T00

T01

INTERNAL TIMER

CLOCKS

T10

T11

COUNTER (16 - BIT)

INPUT EDGE

$FFEB

$FFEC

$FFED

$FFEE

$FFEF

(SEE NOTE)

INTERNAL CAPTURE LATCH

INPUT CAPTURE REGISTER

$????

$FFED

INPUT CAPTURE FLAG

NOTE:

1. If the input edge occurs in the shaded area from one timer state T10 to the next, the input capture ﬂag is set during the next T11.

FIGURE 17. TIMER STATE DIAGRAM FOR INPUT CAPTURE

2-36

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

INTERNAL PROCESSOR CLOCK

T00

T01

INTERNAL TIMER

T10

T11

COUNTER (16 - BIT)

COMPARE REGISTER

$FFEB

$FFEC

$FFED

$FFEE

$FFED

$FFEF

(NOTE 1)

CPU WRITES $FFED

(NOTE 2)

COMPARE REGISTER

LATCH

OUTPUT COMPARE

FLAG (OCF) AND

TCMP (PIN 35)

(NOTE 3)

NOTES:

1. The CPU write to the Compare Register may take place at any time, but a compare only occurs at timer state T01. Thus a 4 cycle differ-

ence may exist between the write to the Compare Register and the actual compare.

2. Internal compare takes place during timer state T01.

3. OCF is set at the timer state T11 which follows the comparison match ($FFED in this example).

FIGURE 18. TIMER STATE DIAGRAM FOR OUTPUT COMPARE

INTERNAL PROCESSOR CLOCK

T00

T01

INTERNAL TIMER

T10

T11

COUNTER (16 - BIT)

$FFFE

$FFFF

$0000

$0001

$0002

TIMER OVERFLOW

FLAG (TOF)

NOTE:

1. The TOF bit is set at timer state T11 (transition of the counter from $FFFF to $0000). It is cleared by a read of the Timer Status Register

during the internal processor clock high time followed by a read of the Counter Low Register.

FIGURE 19. TIMER STATE DIAGRAM FOR TIMER OVERFLOW

2-37

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

COUNTER

After a processor write cycle to the output compare register

containing the most signiﬁcant byte ($16), the output com-

pare function is inhibited until the least signiﬁcant byte ($17)

is also written. The user must write both bytes (locations) if

the most signiﬁcant byte is written ﬁrst. A write made only to

the least signiﬁcant byte ($17) will not inhibit the compare

function. The free running counter is updated every four

internal processor clock cycles due to the internal prescaler.

The minimum time required to update the output compare

register is a function of the software program rather than the

internal hardware.

The key element in the programmable timer is a 16-bit free

running counter, or counter register, preceded by a prescaler

which divides the internal processor clock by four. The pres-

caler gives the timer a resolution of 2.0µs if the internal pro-

cessor clock is 2.0MHz. The counter is clocked to increasing

values during the low portion of the internal processor clock.

Software can read the counter at any time without affecting

its value.

The double byte free running counter can be read from

either of two locations $18 - $19 (called counter register at

this location), or $1A - $1B (counter alternate register at this

location). If a read sequence containing only a read of the

least signiﬁcant byte of the free running counter or counter

alternate register ﬁrst addresses the most signiﬁcant byte

($18, $1A) it causes the least signiﬁcant byte ($19, $1B) to

be transferred to a buffer. This buffer value remains ﬁxed

after the ﬁrst most signiﬁcant byte “read” even if the user

reads the most signiﬁcant byte several times. This buffer is

accessed when reading the free running counter or counter

alternate register, if the most signiﬁcant byte is read, the

least signiﬁcant byte must also be read in order to complete

the sequence.

A processor write may be made to either byte of the output

compare register without affecting the other byte. The output

level (OLVL) bit is clocked to the output level register regard-

less of whether the output compare ﬂag (OCF) is set or clear.

Because neither the output compare ﬂag (OCF bit) or output

compare register is affected by reset, care must be exer-

cised when initializing the output compare function with soft-

ware. The following procedure is recommended:

1. Write the high byte of the output compare register to inhibit

further compares until the low byte is written.

2. Read the timer status register to arm the OCF if it is al-

ready set.

The free running counter is conﬁgured to $FFFC during

reset and is always a read-only register. During a power-on-

reset (POR), the counter is also conﬁgured to $FFFC and

begins running after the oscillator startup delay. Because the

free running counter is 16 bits preceded by a ﬁxed divide-by-

four prescaler, the value in the free running counter repeats

every 262,144 MPU internal processor clock cycles. When

the counter rolls over from $FFFF to $0000, the timer over-

ﬂow ﬂag (TOF) bit is set. An interrupt can also be enabled

when counter rollover occurs by setting its interrupt enable

bit (TOIE).

3. Write the output compare register low byte to enable the

output compare function with the ﬂag clear.

The advantage of this procedure is to prevent the OCF bit

from being set between the time it is read and the write to

the output compare register. A software example is shown

below.

B716

B613

BF17

STA

LDA

STX

OCMPHI;

TSTAT;

INHIBIT OUTPUT COMPARE

ARM OCF BIT IF SET

OCMPLO;

READY FOR NEXT COMPARE

INPUT CAPTURE REGISTER

OUTPUT COMPARE REGISTER

The two 8-bit registers which make up the 16-bit input cap-

ture register are read-only and are used to latch the value of

the free running counter after a deﬁned transition is sensed

by the corresponding input capture edge detector. The level

transition which triggers the counter transfer is deﬁned by

the corresponding input edge bit (IEDG). Reset does not

affect the contents of the input capture register.

The output compare register is a 16-bit register, which is

made up of two 8-bit registers at locations $16 (most signiﬁ-

cant byte) and $17 (least signiﬁcant byte). The output com-

pare register can be used for several purposes such as,

controlling an output waveform or indicating when a period

of time has elapsed. The output compare register is unique

in that all bits are readable and writable and are not altered

by the timer hardware. Reset does not affect the contents of

this register and if the compare function is not utilized, the

two bytes of the output compare register can be used as

storage locations. The contents of the output compare regis-

ter are compared with the contents of the free running

counter once during every four internal processor clocks. If a

match is found, the corresponding output compare ﬂag

(OCF) bit is set and the corresponding output level (OLVL)

bit is clocked (by the output compare circuit pulse) to an out-

put level register. The values in the output compare register

and the output level bit should be changed after each suc-

cessful comparison in order to control an output waveform or

establish a new elapsed timeout. An interrupt can also

accompany a successful output compare provided the corre-

sponding interrupt enable bit, OCIE, is set.

The result obtained by an input capture will be one more

than the value of the free running counter on the rising edge

of the internal processor clock preceding the external transi-

tion (refer to timing diagram shown in Figure 17). This delay

is required for internal synchronization. Resolution is

affected by the prescaler allowing the timer to only increment

every four internal processor clock cycles.

After a read of the most signiﬁcant byte of the input capture

register ($14), counter transfer is inhibited until the least sig-

niﬁcant byte ($15) of the input capture register is also read.

This characteristic forces the minimum pulse period attain-

able to be determined by the time used in the capture soft-

ware routine and its interaction with the main program. The

free running counter increments every four internal proces-

sor clock cycles due to the prescaler.

2-38

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

A read of the least signiﬁcant byte ($15) of the input capture 1. A proper transition has taken place at pin 37 with an ac-

register does not inhibit the free running counter transfer.

Again, minimum pulse periods are ones which allow soft-

ware to read the least signiﬁcant byte ($15) and perform

needed operations. There is no conﬂict between the read of

the input capture register and the free running counter trans-

fer since they occur on opposite edges of the internal pro-

cessor clock.

companying transfer of the free running counter contents

to the input capture register,

2. A match has been found between the free running counter

and the output compare register, and

3. A free running counter transition from $FFFF to $0000 has

been sensed (timer overﬂow).

The timer status register is illustrated below followed by a

deﬁnition of each bit. Refer to timing diagrams shown in Fig-

ures 16, 17, and 18 for timing relationship to the timer status

register bits.

TIMER CONTROL REGISTER (TCR)

The timer control register (TCR, location $12) is an 8-bit

read/write register which contains ﬁve control bits. Three of

these bits control interrupts associated with each of the three

ﬂag bits found in the timer status register (discussed below).

The other two bits control: 1) which edge is signiﬁcant to

the capture edge detector (i.e., negative or positive), and

2) the next value to be clocked to the output level register in

response to a successful output compare. The timer control

register and the free running counter are the only sections of

the timer affected by reset. The TCMP pin is forced low dur-

ing external reset and stays low until a valid compare

changes it to a high. The timer control register is illustrated

below followed be a deﬁnition of each bit.

7

6

5

4

0

3

0

2

0

1

0

ICF OCF TOF

$13

B7, ICF

The input capture ﬂag (ICF) is set when a proper

edge has been sensed by the input capture

edge detector. It is cleared by a processor

access of the timer status register (with ICF set)

followed by accessing the low byte ($15) of the

input capture register. Reset does not affect the

input compare ﬂag.

B6, OCF The output compare ﬂag (OCF) is set when the

output compare register contents match the

contents of the free running counter. The OCF is

cleared by accessing the timer status register

(with OCF set) and then accessing the low byte

($17) of the output compare register. Reset does

not affect the output compare ﬂag.

7

6

5

4

0

3

0

2

0

1

0

ICIE OCIE TOIE

IEDG OLVL $12

B7, ICIE

If the input capture interrupt enable (ICIE) bit is

set, a timer interrupt is enabled when the ICF

status ﬂag (in the timer status register) is set. If

the ICIE bit is clear, the interrupt is inhibited. The

ICIE bit is cleared by reset.

B5, TOF

The timer overﬂow ﬂag (TOF) bit is set by a tran-

sition of the free running counter from $FFFF to

$0000. It is cleared by accessing the timer status

register (with TOF set) followed by an access of

the free running counter least signiﬁcant byte

($19). Reset does not affect the TOF bit.

B6, OCIE If the output compare interrupt enable (OCIE) bit

is set, a timer interrupt is enabled whenever the

OCF status ﬂag is set. If the OCIE bit is clear,

the interrupt is inhibited. The OCIE bit is cleared

by reset.

Accessing the timer status register satisﬁes the ﬁrst condi-

tion required to clear any status bits which happen to be set

during the access. The only remaining step is to provide an

access of the register which is associated with the status bit.

Typically, this presents no problem for the input capture and

output compare functions.

B5, TOIE If the timer overﬂow interrupt enable (TOIE) bit is

set, a timer interrupt is enabled whenever the

TOF status ﬂag (in the timer status register) is

set. If the TOIE bit is clear, the interrupt is inhib-

ited. The TOIE bit is cleared by reset.

A problem can occur when using the timer overﬂow function

and reading the free running counter at random times to mea-

sure an elapsed time. Without incorporating the proper pre-

cautions into software, the timer overﬂow ﬂag could

unintentionally be cleared if: 1) the timer status register is

read or written when TOF is set, and 2) the least signiﬁcant

byte of the free running counter is read but not for the purpose

of servicing the ﬂag. The counter alternate register at address

$1A and $1B contains the same value as the free running

counter (at address $18 and $19); therefore, this alternate

register can be read at any time without affecting the timer

overﬂow ﬂag in the timer status register.

B1, IEDG The value of the input edge (IEDG) bit determines

which level transition on pin 37 will trigger a free

running counter transfer to the input capture

register. Reset does not affect the IEDG bit.

0 = negative edge

1 = positive edge

B0, OLVL The value of the output level (OLVL) bit is

clocked into the output level register by the next

successful output compare and will appear at

pin 35. This bit and the output level register are

cleared by reset.

0 = low output

During STOP and WAIT instructions, the programmable timer

functions as follows: during the wait mode, the timer continues

to operate normally and may generate an interrupt to trigger the

CPU out of the wait state; during the stop mode, the timer holds

at its current state, retaining all data, and resumes operation

from this point when an external interrupt is received.

1 = high output

TIMER STATUS REGISTER (TSR)

The timer status register (TSR) is an 8-bit register of which

the three most signiﬁcant bits contain read-only status infor-

mation. These three bits indicate the following:

2-39

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

4. The data is transmitted and received least-signiﬁcant-bit ﬁrst.

Serial Communications Interface (SCI)

5. A STOP bit (high in the tenth or eleventh bit position) indi-

cates the byte is complete.

INTRODUCTION

A full-duplex asynchronous serial communications interface

(SCI) is provided with a standard NRZ format and a variety

of baud rates. The SCI transmitter and receiver are function-

ally independent, but use the same data format and bit rate.

The serial data format is standard mark/space (NRZ) which

provides one start bit, eight or nine data bits, and one stop

bit. “Baud” and “bit rate” are used synonymously in the fol-

lowing description.

6. A break is deﬁned as the transmission or reception of a

low (logic zero) for some multiple of the data format.

CONTROL BIT ‘M’

SELECTS 8 OR 9

BIT DATA

0

1

2

3

4

5

6

7

8

0

†

IDLE LINE

SCI Two Wire System Features

S

T

A

R

T

S

T

O

P

S

T

A

R

T

• Standard NRZ (mark/space) format

• Advanced error detection method includes noise detection

for noise duration of up to 1/16 bit time.

†STOP bit is always high.

FIGURE 20. DATA FORMAT

• Full-duplex operation (simultaneous transmit and receive)

• Software programmable for one of 32 different baud rates

• Software selectable word length (eight or nine bit words)

• Separate transmitter and receiver enable bits.

• SCI may be interrupt driven

WAKE-UP FEATURE

In a typical multiprocessor conﬁguration, the software protocol

will usually identify the addressee(s) at the beginning of the

message. In order to permit uninterested MPUs to ignore the

remainder of the message, a wake-up feature is included

whereby all further SCI receiver ﬂag (and interrupt)

processing can be inhibited until its data line returns to the idle

state. An SCI receiver is re-enabled by an idle string of at

least ten (or eleven) consecutive ones. Software for the

transmitter must provide for the required idle string between

consecutive messages and prevent it from occurring within

messages.

• Four separate enable bits available for interrupt control

SCI Receiver Features

• Receiver wake-up function (idle or address bit)

• Idle line detect

• Framing error detect

• Noise detect

The user is allowed a second method of providing the wake-

up feature in lieu of the idle string discussed above. This

method allows the user to insert a logic one in the most sig-

niﬁcant bit of the transmit data word which needs to be

received by all “sleeping” processors.

• Overrun detect

• Receiver data register full ﬂag

SCI Transmitter Features

RECEIVE DATA IN

• Transmit data register empty ﬂag

• Transmit complete ﬂag

Receive data in is the serial data which is presented from the

input pin via the SCI to the internal data bus. While waiting

for a start bit, the receiver samples the input at a rate which

is 16 times higher than the set baud rate. This 16 times

higher-than-baud rate is referred to as the RT rate in Figures

21 and 22, and as the receiver clock in Figure 26. When the

input (idle) line is detected low, it is tested for three more

sample times (referred to as the start edge veriﬁcation sam-

ples in Figure 21). If at least two of these three veriﬁcation

samples detect a logic low, a valid start bit is assumed to

have been detected (by a logic low following the three start

qualiﬁers) as shown in Figure 21; however, if in two or more

of the veriﬁcation samples a logic high is detected, the line is

assumed to be idle. (A noise ﬂag is set if one of the three

veriﬁcation sample detects a logic high, thus a valid start bit

could be assumed and a noise ﬂag still set.) The receiver

clock generator is controlled by the baud rate register (see

Figures 25 and 26); however, the serial communications

interface is synchronized by the start bit (independent of the

transmitter).

• Break send

Any SCI two-wired system requires receive data in (RDI)

and transmit data out (TDO).

DATA FORMAT

Receive data in (RDI) or transmit data out (TDO) is the serial

data which is presented between the internal data bus and

the output pin (TDO), and between the input pin (RDI) and

the internal data bus. Data format is as shown for the NRZ in

Figure 20 and must meet the following criteria:

1. A high level indicates a logic one and a low level indicates

a logic zero.

2. The idle line is in a high (logic one) state prior to transmis-

sion/reception of a message.

3. A start bit (logic zero) is transmitted/received indicating the

start of a message.

2-40

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

16x INTERNAL SAMPLING CLOCK

1

R

T

2

R

T

3

R

T

4

R

T

5

R

T

6

R

T

7

R

T

8

R

T

RT CLOCK EDGES (FOR ALL THREE EXAMPLES)

RD11

START

1

0

START

START EDGE VERIFICATION SAMPLES

NOISE

QUALIFIERS

IDLE

RD12

RD13

START

0

1

0

1

0

IDLE

NOISE

START

0

1

0

1

0

FIGURE 21. EXAMPLES OF START BIT SAMPLING TECHNIQUE

Once a valid start bit is detected, the start bit, each data bit,

and the stop bit are sampled three times at RT intervals of

8RT, 9RT, and 10RT (1RT is the position where the bit is

expected to start as shown in Figure 22. The value of the bit

is determined by voting logic which takes the value of the

majority of samples (two or three out of three). A noise ﬂag is

set when all three samples on a valid start bit or a data bit or

the stop bit do not agree. (As discussed above, a noise ﬂag

is also set when the start bit veriﬁcation samples do not

agree).

EXPECTED

STOP

ARTIFICIAL

EDGE

DATA

RECEIVE

DATA IN

START BIT

DATA

DATA SAMPLES

FIGURE 23A. CASE 1, RECEIVE LINE LOW DURING ARTIFICIAL

EDGE

EXPECTED

START EDGE

DATA

STOP

RECEIVE

DATA IN

START BIT

PREVIOUS BIT

RDI

PRESENT BIT

SAMPLES

NEXT BIT

V

DATA

16

R

1

R

T

8

R

T

9

R

T

10

R

16

R

T

1

R

T

DATA SAMPLES

T

FIGURE 23B. CASE 2, RECEIVE LINE HIGH DURING EXPECTED

START EDGE

FIGURE 22. SAMPLING TECHNIQUE USED ON ALL BITS

FIGURE 23. SCI ARTIFICIAL START FOLLOWING A FRAMING

ERROR

START BIT DETECTION FOLLOWING A

FRAMING ERROR

If the receiver detects that a break (RDRF = 1, FE = 1,

receiver data register = $00) produced the framing error, the

start bit will not be artiﬁcially induced and the receiver must

actually receive a logic one bit before start. See Figure 24.

If there has been a framing error without detection of a break

(10 zeros for 8-bit format or 11 zeros for 9-bit format), the circuit

continues to operate as if there actually were a stop bit and the

start edge will be placed artiﬁcially. The last bit received in the

data shift register is inverted to a logic one, and the three logic

one start qualiﬁers (shown in Figure 21) are forced into the

sample shift register during the interval when detection of a

start bit is anticipated (see Figure 23); therefore the start bit will

be accepted no sooner than it is anticipated.

EXPECTED

STOP

DETECTED AS

VALID START EDGE

BREAK

START BIT

RECEIVE

DATA IN

START START EDGE

QUALI- VERIFICATION

DATA SAMPLES

FIER

SAMPLER

FIGURE 24. SCI START BIT FOLLOWING A BREAK

2-41

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

SCI INTERRUPT

INTERNAL BUS

$0F

SCCR2

TRANSMIT

DATA

REGISTER

RECEIVE

DATA

REGISTER

(SEE

NOTE)

(SEE

TIE

$11

NOTE)

TCIE

RIE

TDO

(PD1,

PIN 30)

ILIE

TE

TRANSMIT

DATA

SHIFT

RECEIVE

DATA

SHIFT

RE

SBK

RWU

REGISTER

RDI

(PD0,

PIN 29)

2

SCSR

$10

FE

NF

OR

IDLE RDRF TC

TDRE

WAKE

UP

UNIT

7

SBK

TE

TRANSMIT

CONTROL

FLAG

CONTROL

RECEIVE

CONTROL

INTERNAL

PROCESSOR

CLOCK

RATE GENERATOR

BAUD

RATE

REGISTER

$0D

-

SCP1

-

SCR2 SCR1 SCR0

SCP0

$0E

SCCR1

R8

T8

-

M

WAKE

-

NOTE: The Serial Communications Data Register (SCDAT) is controlled by the internal R/W signal. It is the transmit data register when writ-

ten and receive data register when read.

FIGURE 25. SERIAL COMMUNICATIONS INTERFACE BLOCK DIAGRAM

REGISTERS

SCI

TRANSMIT

CLOCK (Tx)

There are ﬁve different registers used in the serial communi-

cations interface (SCI) and the internal conﬁguration of

these registers is discussed in the following paragraphs. A

block diagram of the SCI system is shown in Figure 25.

÷16

OSCILLATOR

FREQUENCY

Serial Communications Data Register (SCDAT)

SCR0 - SCR2

SCI SELECT

RATE

SCR0 - SCR2

SCP0 - SCP1

PRESCALER

CONTROL

÷N

SCI

7

6

5

4

3

2

1

0

SCI SELECT

RECEIVE

÷2

RATE

CLOCK (RT)

CONTROL

Serial Communications Data Register

$11

÷M

FIGURE 26. RATE GENERATOR DIVISION

2-42

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

The serial communications data register performs two func-

receiver. If the WAKE bit is set to a logic one, the

system acknowledges an address bit (most sig-

niﬁcant bit). The address bit is dependent on

both the WAKE bit and the M bit level (table

shown below). (Additionally, the receiver does

not use the wake-up feature unless the RWU

control bit in serial communications control reg-

ister 2 is set as discussed below.) Reset does

not affect this bit.

tions in the serial communications interface; i.e. it acts as the

receive data register when it is read and as the transmit data

register when it is written. Figure 25 shows the register as two

separate registers, namely: the receive data register (RDR)

and the transmit data register (TDR). As shown in Figure 25,

the TDR (transmit data register) provides the parallel interface

from the internal data bus to the transmit shift register and the

receive data register (RDR) provides the interface from the

receive shift register to the internal data bus.

WAKE

M

METHOD OF RECEIVER “WAKE-UP”

When SCDAT is read, it becomes the receive data register

and contains the last byte of data received. The receive data

register, represented above, is a read-only register contain-

ing the last byte of data received from the shift register for

the internal data bus. The RDRF bit (receive data register

full bit in the serial communications status register) is set to

indicate that a byte has been transferred from the input

serial shift register to the serial communications data regis-

ter. The transfer is synchronized with the receiver bit rate

clock (from the receive control) as shown in Figure 25. All

data is received least-signiﬁcant-bit ﬁrst.

0

X

Detection of an idle line allows the next

data byte received to cause the receive

data register to ﬁll and produce an

RDRF ﬂag.

1

0

1

Detection of a received one in the

eighth data bit allows an RDRF ﬂag and

associated error ﬂags.

Detection of a received one in the ninth

data bit allows an RDRF ﬂag and asso-

ciated error ﬂags.

When SCDAT is written, it becomes the transmit data regis-

ter and contains the next byte of data to be transmitted. The

transmit data register, also represented above, is a write-

only register containing the next byte of data to be applied to

the transmit shift register from the internal data bus. As long

Serial Communications Control Register 2 (SCCR2)

7

6

5

4

3

2

1

0

TIE TCIE RIE

ILIE

TE

RE RWU SBK $0F

as the transmitter is enabled, data stored in the serial com- The serial communications control register 2 (SCCR2) pro-

munications data register is transferred to the transmit shift vides the control bits which: individually enable/disable the

register (after the current byte in the shift register has been transmitter or receiver, enable the system interrupts, and

transmitted). The transfer from the SCDAT to the transmit provide the wake-up enable bit and a “send break code” bit.

shift register is synchronized with the bit rate clock (from the Each of these bits is described below. (The individual ﬂags

transmit control) as shown in Figure 25. All data is transmit- are discussed in the Serial Communications Status Reg-

ted least-signiﬁcant-bit ﬁrst.

ister Section.)

Serial Communications Control Register 1 (SCCR1)

B7, TIE When the transmit interrupt enable bit is set, the

SCI interrupt occurs provided TDRE is set (see

Figure 25). When TIE is clear, the TDRE interrupt

is disabled. Reset clears the TIE bit.

7

6

5

-

4

3

2

-

1

-

0

-

R8

T8

M

WAKE

$0E

B6, TCIE When the transmission complete interrupt

enable bit is set, the SCI interrupt occurs pro-

vided TC is set (see Figure 25). When TCIE is

clear, the TC interrupt is disabled. Reset clears

the TCIE bit.

The serial communications control register 1 (SCCR1) pro-

vides the control bits which: 1) determine the word length

(either 8 or 9 bits), and 2) selects the method used for the

wake-up feature. Bits 6 and 7 provide a location for storing

the ninth bit for longer bytes.

B5, RIE

When the receive interrupt enable bit is set, the

SCI interrupt occurs provided OR is set or

RDRF is set (see Figure 25). When RIE is clear,

the OR and RDRF interrupts are disabled. Reset

clears the RIE bit.

B7, R8

B6, T8

B4, M

If the M bit is a one, then this bit provides a stor-

age location for the ninth bit in the receive data

byte. Reset does not affect this bit.

If the M bit is one, then this bit provides a stor-

age locations for the ninth bit in the transmit data

byte. Reset does not affect this bit.

B4, ILIE

B3, TE

When the idle line interrupt enable bit is set, the

SCI interrupt occurs provided IDLE is set (see

Figure 25). When ILIE is clear, the IDLE interrupt

is disabled. Reset clears the ILIE bit.

The option of the word length is selected by the

conﬁguration of this bit and is shown below.

Reset does not affect this bit. 0 = 1 start bit, 8

data bits, 1 stop bit 1 = 1 start bit, 9 data bits, 1

stop bit

When the transmit enable bit is set, the transmit

shift register output is applied to the TDO line.

Depending on the state of control bit M in serial

communications control register 1, a preamble

of 10(M = 0) or 11(M = 1) consecutive ones is

transmitted when software sets the TE bit from a

B3, WAKE This bit allows the user to select the method for

receiver “wake up”. If the WAKE bit is a logic

zero, an idle line condition will “wake up” the

2-43

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

cleared state. If a transmission is in progress, The serial communications status register (SCSR) provides

and TE is written to a zero, then the transmitter inputs to the interrupt logic circuits for generation of the SCI

will wait until after the present byte has been system interrupt. In addition, a noise ﬂag bit and a framing

transmitted before placing the TDO pin in the error bit are also contained in the SCSR.

idle high-impedance state. If the TE pin has

B7, TDRE The transmit data register empty bit is set to

been written to a zero and then set to a one

indicate that the contents of the serial communi-

before the current byte is transmitted, the trans-

cations data register have been transferred to

mitter will wait until that byte is transmitted and

the transmit serial shift register. If the TDRE bit

will then initiate transmission of a new preamble.

is clear, it indicates that the transfer has not yet

After the preamble is transmitted, and provided

occurred and a write to the serial communica-

the TDRE bit is set (no new data to transmit),

tions data register will overwrite the previous

the line remains idle (driven high while TE = 1);

value. The TDRE bit is cleared by accessing the

otherwise, normal transmission occurs. This

serial communications status register (with

function allows the user to “neatly” terminate a

TDRE set), followed by writing to the serial com-

transmission sequence. After loading the last

munication data register. Data can not be trans-

byte in the serial communications data register

mitted unless the serial communications status

and receiving the interrupt from TDRE, indicat-

register is accessed before writing to the serial

ing the data has been transferred into the shift

communications data register to clear the TDRE

register, the user should clear TE. The last byte

ﬂag bit. Reset sets the TDRE bit.

will then be transmitted and the line will go idle

(high impedance). Reset clears the TE bit.

B6, TC

The transmit complete bit is set at the end of a

data frame, preamble, or break condition if:

B2, RE

When the receive enable bit is set, the receiver

is enabled. When RE is clear, the receiver is dis-

abled and all of the status bit associated with the

receiver (RDRF, IDLE, OR, NF, and FE) are

inhibited. Reset clears the RE bit.

1. TE = 1, TDRE = 1, and no pending data, pre-

amble, or break is to be transmitted; or

2. TE = 0, and the data, preamble, or break (in the

transmit shift register) has been transmitted.

The TC bit is a status ﬂag which indicates that

one of the above conditions has occurred. The

TC bit is cleared by accessing the serial commu-

nications status register (with TC set), followed

by writing to the serial communications data reg-

ister. It does not inhibit the transmitter function in

any way. Reset sets the TC bit.

B1, RWU When the receiver wake-up bit is set, it enables

the “wake up” function. The type of “wake up”

mode for the receiver is determined by the

WAKE bit discussed above (in the SCCR1).

When the RWU bit is set, no status ﬂags will be

set. Flags which were set previously will not be

cleared when RWU is set. If the WAKE bit is

cleared, RWU is cleared after receiving 10(M = B5, RDRF When the receive data register full bit is set, it indi-

0) or 11(M = 1) consecutive ones. Under these

conditions, RWU cannot be set if the line is idle.

If the WAKE bit is set, RWU is cleared after

receiving an address bit. The RDRF ﬂag will

then be set and the address byte will be stored

in the receiver data register. Reset clears the

RWU bit.

cates that the receiver serial shift register is trans-

ferred to the serial communications data register. If

multiple errors are detected in any one received

word, the NF, FE, and RDRF bits will be affected

as appropriate during the same clock cycle. The

RDRF bit is cleared when the serial communica-

tions status register is accessed (with RDRF set)

followed by a read of the serial communications

data register. Reset clears the RDRF bit.

B0, SBK

When the send break bit is set the transmitter

sends zeros in some number equal to a multiple

of the data format bits. If the SBK bit is toggled

set and clear, the transmitter sends 10(M = 0) or

11(M = 1) zeros and then reverts to idle or send-

ing data. The actual number of zeros sent when

SBK is toggled depends on the data format set

by the M bit in the serial communications control

register 1; therefore, the break code will be syn-

chronous with respect to the data stream. At the

completion of the break code, the transmitter

sends at least one high bit to guarantee recogni-

tion of a valid start bit. Reset clears the SBK bit.

B4, IDLE When the idle line detect bit is set, it indicates

that a receiver idle line is detected (receipt of a

minimum number of ones to constitute the num-

ber of bits in the byte format). The minimum

number of ones needed will be 10(M = 0) or

11(M = 1). This allows a receiver that is not in

the wake-up mode to detect the end of a mes-

sage, detect the preamble of a new message, or

to resynchronize with the transmitter. The IDLE

bit is cleared by accessing the serial communi-

cations status register (with IDLE set) followed

by a read of the serial communications data reg-

ister. The IDLE bit will not be set again until after

an RDRF has been set; i.e., a new idle line

occurs. The IDLE bit is not set by an idle line

when the receiver “wakes up” from the wake-up

mode. Reset clears the IDLE bit.

Serial Communications Status Register (SCSR)

7

6

5

4

3

2

1

0

-

TDRE TC RDRF IDLE OR

NF

FE

$10

2-44

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

B3, OR

When the overrun error bit is set, it indicates that as a prescaler for the SCR0 - SCR2 bits. Together, these ﬁve

the next byte is ready to be transferred from the bits provide multiple, baud rate combinations for a given

receive shift register to the serial communications crystal frequency.

data register when it is already full (RDRF bit is

set). Data transfer is then inhibited until the RDRF

bit is cleared. Data in the serial communications

B5, SCP1, These two bits in the baud rate register are used

B4, SCP0 as a prescaler to increase the range of standard

baud rates controlled by the SCR0 - SCR2 bits.

data register is valid in this case, but additional

A table of the prescaler internal processor clock

data received during an overrun condition (includ-

division versus bit levels is provided below.

ing the byte causing the overrun) will be lost. The

Reset clears SCP1 - SCP0 bits (divide-by-one).

OR bit is cleared when the serial communications

status register is accessed (with OR set), fol-

lowed by a read of the serial communications

data register. Reset clears the OR bit.

INTERNAL PROCESSOR

SCP1

SCP0

CLOCK DIVIDE BY

0

1

0

1

0

1

3

B2, NF

The noise ﬂag bit is set if there is noise on a

“valid” start bit or if there is noise on any of the

data bits or if there is noise on the stop bit. It is

not set by noise on the idle line nor by invalid

(false) start bits. If there is noise, the NF bit is

not set until the RDRF ﬂag is set. Each data bit

is sampled three times as described above in

RECEIVE DATA IN and shown in Figure 22. The

NF bit represents the status of the byte in the

serial communications data register. For the

byte being received (shifted in) there will also be

a “working” noise ﬂag the value of which will be

transferred to the NF bit when the serial data is

loaded into the serial communications data reg-

ister. The NF bit does not generate an interrupt

because the RDRF bit gets set with NF and can

be used to generate the interrupt. The NF bit is

cleared when the serial communications status

register is accessed (with NF set), followed by a

read of the serial communications data register.

Reset clears the NF bit.

4

13

B2, SCR2, These three bits in the baud rate register are

B1, SCR1, used to select the baud rates of both the trans-

B0, SCR0 mitter and receiver. A table of baud rates versus

bit levels is shown below. Reset does not affect

the SCR2 - SCR0 bits.

PRESCALER OUTPUT

SCR2

SCR1

SCR0

DIVIDE BY

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

B1, FE

The framing error bit is set when the byte bound-

aries in the bit stream are not synchronized with

the receiver bit counter (generated by a “lost”

stop bit). The byte is transferred to the serial com-

munications data register and the RDRF bit is

set. The FE bit does not generate an interrupt

because the RDRF bit is set at the same time as

FE and can be used to generate the interrupt.

Note that if the byte received causes a framing

error and it will also cause an overrun if trans-

ferred to the serial communications data register,

then the overrun bit will be set, but not the fram-

ing error bit, and the byte will not be transferred to

the serial communications data register. The FE

bit is cleared when the serial communications

status register is accessed (with FE set) followed

by a read of the serial communications data reg-

ister. Reset clears the FE bit.

The diagram of Figure 26 and Tables 5 and 6 illustrate the

divided chain used to obtain the baud rate clock (transmit

clock). Note that there is a ﬁxed rate divide-by-16 between

the receive clock (RT) and the transmit clock (Tx). The

actual divider chain is controlled by the combined

SCP0 - SCP1 and SCR0 - SCR2 bits in the baud rate regis-

ter as illustrated. All divided frequencies shown in the ﬁrst

table represent the ﬁnal transmit clock (the actual baud rate)

resulting from the internal processor clock division shown in

the “divide-by” column only (prescaler division only). The

second table illustrates how the prescaler output can be fur-

ther divided by action of the SCI select bits (SCR0 - SCR2).

For example, assume that a 9600Hz baud rate is required

with a 2.4576MHz external crystal. In this case the prescaler

bits (SCP0 - SCP1) could be conﬁgured as a divide-by-one

or a divide-by-four. If a divide-by-four prescaler is used, then

the SCR0 - SCR2 bits must be conﬁgured as a divide-by-

two. This results in a divide-by-128 of the internal processor

clock to produce a 9600Hz baud rate clock. Using the same

crystal, the 9600 baud rate can be obtained with a prescaler

divide-by-one and the SCR0 - SCR2 bits conﬁgured for a

divide-by-eight.

Baud Rate Register

7

-

6

-

5

4

3

-

2

1

0

SCP1 SCP0

SCR2 SCR1 SCR0 $0D

The baud rate register provides the means for selecting dif-

ferent baud rates which may be used as the rate control for

the transmitter and receiver. The SCP0 - SCP1 bits function

NOTE: The crystal frequency is internally divided-by-two to generate

the internal processor clock.

2-45

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

TABLE 5. PRESCALER HIGHEST BAUD RATE FREQUENCY OUTPUTT

SCP BIT

(NOTE 1)

CRYSTAL FREQUENCY MHz

CLOCK

1

0

1

0

1

DIVIDED BY (NOTE 2) 8.0

4.194304

131.072kHz

43.691kHz

32.768kHz

10.082kHz

4.0

2.4576

2.0

1.8432

57.60kHz

19.20kHz

14.40kHz

4430Hz

0

1

3

250.000kHz

83.332kHz

62.500kHz

19.200kHz

125.000kHz

41.666kHz

31.250kHz

9600Hz

76.80kHz

25.60kHz

19.20kHz

5.907kHz

62.50kHz

20.833kHz

15.625kHz

4800Hz

0

1

4

13

NOTES:

1. The clock in the "CLOCK DIVIDED BY" column is the internal processor clock.

2. CDP68HSC05C4 and CDP68HSC05C8 types.

3. The divided frequencies shown in Table 5 represent baud rates which are the highest transmit baud rate (Tx) that can be obtained by a

specific crystal frequency and only using the prescaler division. Lower baud rates may be obtained by providing a further division using

the SCI rate select bits as shown below for some representative prescaler outputs.

TABLE 6. TRANSMIT BAUD RATE OUTPUT FOR A GIVEN PRESCALER OUTPUT

SCR BITS

REPRESENTATIVE HIGHEST PRESCALER BAUD RATE OUTPUT

(NOTE 1)

DIVIDE BY 250.000kHz 131.072kHz 32.768kHz

2

1

0

1

0

1

0

1

0

1

0

1

0

1

76.80kHz

38.40kHz

19.20kHz

9600Hz

4800Hz

2400Hz

1200Hz

600Hz

19.20kHz

9600Hz

4800Hz

2400Hz

1200Hz

600Hz

9600Hz

4800Hz

2400Hz

1200Hz

600Hz

300Hz

150Hz

75Hz

0

1

2

-

131.072kHz 32.768kHz

0

125.000kHz 65.536kHz 16.384kHz

0

4

62.500kHz 32.678kHz

31.250kHz 16.384kHz

8.192kHz

4.096kHz

2.048kHz

1.024kHz

512Hz

0

8

1

16

32

64

128

15.625kHz

7.813kHz

3.906kHz

1.953kHz

8.192kHz

4.096kHz

2.048kHz

1.024kHz

1

300Hz

256Hz

150Hz

NOTES:

1. CDP68HSC05C4 and CDP68HSC05C8 types.

2. Table 6 illustrates how the SCI select bits can be used to provide lower transmitter baud rates by further dividing the prescaler output

frequency. The five examples are only representative samples. In all cases, the baud rates shown are transmit baud rates (transmit clock)

and the receiver clock is 16 times higher in frequency than the actual baud rate.

Features

Serial Peripheral Interface (SPI)

• Full Duplex, Three-Wire Synchronous Transfers

INTRODUCTION AND FEATURES

• Master or Slave Operation

Introduction

• Master Bit Frequency

The serial peripheral interface (SPI) is an interface built into

- 1.05MHz Maximum (CDP68HC05C4, CDP68HC05C8,

and CDP68HCL05C4, CDP68HCL05C8)

the MCU which allows several MCUs, or one MCU plus

peripheral devices, to be interconnected within a single “black

box” or on the same printed circuit board. In a serial peripheral

interface (SPI), separate wires (signals) are required for data

and clock. In the SPI format, the clock is not included in the

data stream and must be furnished as a separate signal. An

SPI system may be conﬁgured as one containing one master

MCU and several slave MCUs, or in a system in which an

MCU is capable of being either a master or a slave.

- 2.0MHz Maximum (CDP68HSC05C4, CDP68HSC05C8)

• Slave Bit Frequency

- 2.1MHz Maximum (CDP68HC05C4, CDP68HC05C8,

and CDP68HCL05C4, CDP68HCL05C8)

- 4.0MHz Maximum (CDP68HSC05C4, CDP68HSC05C8)

• Four Programmable Master Bit Rates

• Programmable Clock Polarity and Phase

• End of Transmission Interrupt Flag

Figure 27 illustrates a typical multicomputer system conﬁgu-

ration. Figure 27 represents a system of ﬁve different MCUs

in which there are one master and four slave (0, 1, 2, 3). In

this system four basic line (signals) are required for the

MOSI (master out slave in), MISO (master in slave out),

SCK serial clock, and SS (slave select) lines.

• Write Collision Flag Protection

• Master-Master Mode Fault Protection Capability

2-46

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

CDP68HC05C4 SLAVE 0

MISO

MOSI

SCK

SS

MISO MOSI SCK SS

V_DD

CDP68HC05C8

MASTER

0

1

2

3

PORT

MISO MOSI SCK SS

CDP68HC05C4 SLAVE 3

MISO MOSI SCK SS

CDP68HC05C4 SLAVE 2

MISO MOSI SCK SS

CDP68HC05C4 SLAVE 1

FIGURE 27. MASTER-SLAVE SYSTEM CONFIGURATION (SINGLE MASTER, FOUR SLAVES)

SIGNAL DESCRIPTION

on this line; most signiﬁcant bit ﬁrst, least signiﬁcant bit last.

The MISO pin of a slave device is placed in the high-imped-

ance state if it is not selected by the master; i.e., its SS pin is

a logic one. The timing diagram of Figure 28 shows the rela-

tionship between data and clock (SCK). As shown in Figure

28, four possible timing relationships may be chosen by

using control bits CPOL and CPHA. The master device

always allows data to be applied on the MOSI line a half-

cycle before the clock edge (SCK) in order for the slave

device to latch the data.

The four basic signals (MOSI, MISO, SCK, SS) discussed

above are described in the following paragraphs. Each sig-

nal function is described for both the master and slave

mode.

Master Out Slave In (MOSI)

The MOSI pin is conﬁgured as a data output in a master

(mode) device and as a data input in a slave (mode) device.

In this manner data is transferred serially from a master to a

slave on this line; most signiﬁcant bit ﬁrst, least signiﬁcant bit

last. The timing diagrams of Figure 28 summarize the SPI

timing and show the relationship between data and clock

(SCK). As shown in Figure 28, four possible timing relation-

ships may be chosen by using control bits CPOL and CPHA.

The master device always allows data to be applied on the

MOSI line a half-cycle before the clock edge (SCK) in order

for the slave device to latch the data.

NOTE: The slave device(s) and a master device must be program-

med to similar timing modes for proper data transfer.

When the master device transmits data to a slave device via

the MOSI line, the slave device responds by sending data to

the master device via the MISO line. This implies full duplex

transmission with both data out and data in synchronized

with the same clock signal (one which is provided by the

master device). Thus, the byte transmitted is replaced by the

byte received and eliminates the need for separate transmit-

empty and receiver-full status bits. A single status bit (SPIF)

in the serial peripheral status register (SPSR, location $0B)

is used to signify that the I/O operation is complete.

NOTE: Both the slave device(s) and a master device must be pro-

grammed to similar timing modes for proper data transfer.

When the master device transmits data to a second (slave)

device via the MOSI line, the slave device responds by send-

ing data to the master device via the MISO line. This implies

full duplex transmission with both data out and data in syn-

chronized with the same clock signal (one which is provided

by the master device). Thus, the byte transmitted is replaced

by the byte received and eliminates the need for separate

transmit-empty and receiver-full status bits. A single status bit

(SPIF) is used to signify that the I/O operation is complete.

In the master device, the MSTR control bit in the serial

peripheral control register (SPCR, location $0A) is set to a

logic one (by the program) to allow the master device to

receive data on its MISO pin. In the slave device, its MISO

pin is enable by the logic level of the SS pin; i.e., if SS = 1

then the MISO pin is placed in the high-impedance state,

whereas, if SS = 0 the MISO pin is an output for the slave

device.

Conﬁguration of the MOSI pin is a function of the MSTR bit

in the serial peripheral control register (SPCR, location $0A).

When a device is operating as a master, the MOSI pin is an

output because the program in ﬁrmware sets the MSTR bit

to a logic one.

Serial Clock (SCK)

The serial clock is used to synchronize the movement of data

both in and out of the device through its MOSI and MISO pins.

The master and slave devices are capable of exchanging a

data byte of information during a sequence of eight clock

pulses. The SCK is generated by the master device, is an

input on all slave devices, and synchronizes master/slave

data transfers. The type of clock and its relationship to data

Master In Slave Out (MISO)

The MISO pin is conﬁgured as an input in a master (mode)

device and as an output in a slave (mode) device. In this

manner data is transferred serially from a slave to a master

2-47

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

SS

SCK

(CPOL = 0, CPHA = 0)

(CPOL = 0, CPHA = 1)

SCK

(CPOL = 1, CPHA = 0)

(CPOL = 1, CPHA = 1)

MISO/

MOSI

MSB

6

5

4

3

2

1

LSB

INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)

FIGURE 28. DATA CLOCK TIMING DIAGRAM

are controlled by the CPOL and CPHA bits in the Serial This ensures that there is only one master controlling the SS

Peripheral Control Register (SPCR, location $0A) discussed line for a particular system. When the SS line is detected

below. Refer to Figure 28 for timing.

low, it clears the MSTR control bit (serial peripheral control

register, location $0A). Also, control bit SPE in the serial

peripheral control register is cleared which causes the serial

peripheral interface (SPI) to be disabled. The MODF ﬂag bit

in the serial peripheral status register (location $0B) is also

set to indicate to the master device that another device is

attempting to become a master. Two devices attempting to

be outputs are normally the result of a software error; how-

ever, a system could be conﬁgured which would contain a

default master which would automatically “take-over” and

restart the system.

The master device generates the SCK through a circuit

driven by the internal processor clock. Two bits (SPR0 and

SPR1) in the SPCR of the master device select the clock

rate. The master device uses the SCK to latch incoming

slave device data on the MISO line and shifts out data to the

slave device on the MOSI line. Both master and slave

devices must be operated in the same timing mode as con-

trolled by the CPOL and CPHA bits in the SPCR. In slave

devices, SPR0, SPR1 have no effect on the operation of the

SPI. Timing is shown in Figure 28.

FUNCTIONAL DESCRIPTION

Slave Select (SS)

A block diagram of the serial peripheral interface (SPI) is

shown in Figure 29. In a master conﬁguration, the master

start logic receives an input from the CPU (in the form of a

write to the SPI rate generator) and originates the system

clock (SCK) based on the internal processor clock. This

clock is also used internally to control the state controller as

well as the 8-bit shift register. As a master device, data is

parallel loaded into the 8-bit shift register (from the internal

bus) during a write cycle, data is applied serially from a slave

device via the MISO pin to the 8-bit shift register. After the

8-bit shift register is loaded, its data is parallel transferred to

the read buffer and then is made available to the internal

data bus during a CPU read cycle.

The slave select (SS) pin is a ﬁxed input, which receives an

active low signal to enable slave device(s) to transfer data. A

high level SS signal forces the MISO line to the high-imped-

ance state. Also, SCK and MOSI are ignored by a slave

device when its SS signal is high. The SS signal must be

driven low prior to the ﬁrst SCK and must remain low

throughout a transfer. The SS input on a Master must be

held high at all times (see description of MODF under Serial

Peripheral Status Register for more details).

As shown in Figure 28, with CPHA = 0, the ﬁrst bit of data

must be applied to the MISO line prior to the ﬁrst transition of

the SCK. In this case, SS going low is used to provide the

ﬁrst clock edge of a transfer. A device is prevented from writ-

ing to its SPI data register while SS is low and CPHA = 0

(see description of WCOL under Serial Peripheral Status

Register for more details). These facts require that SS go

high between SPI data transfers whenever CPHA = 0.

In a slave conﬁguration, the slave start logic receives a logic

low (from a master device) at the SS pin and a system clock

input (from the same master device) at the SCK pin. Thus, the

slave is synchronized with the master. Data from the master is

received serially at the slave MOSI pin and loads the 8-bit

shift register. After the 8-bit shift register is loaded, its data is

parallel transferred to the read buffer and then is made avail-

able to the internal data bus during a CPU read cycle. During

a write cycle, data is parallel loaded into the 8-bit shift register

from the internal data bus and then shifted out serially to the

MISO pin for application to the master device.

When CPHA = 1, the SS of a slave can be held low through-

out a series of SPI transfers and in a single slave system

can even be permanently wired low.

When a device is a master, it constantly monitors its SS sig-

nal input for a logic low. The master device will become a

slave device any time its SS signal input is detected low.

2-48

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

SEE NOTE

INTERNAL

PROCESSOR

CLOCK

33

SCK

32

MOSI

31 MISO

READ

RATE

GENERATOR

MASTER

START LOGIC

8

INTERNAL

DATA BUS

(LOAD)

(FULL)

READ BUFFER

34

SS

SPIF

(END TX)

8

$0C

SLAVE

START LOGIC

8-BIT SHIFT

REGISTER

8

(SEE NOTE)

2

WRITE

CONTROL

BITS

SPCR

$0A

3

7

STATE

CONTROLLER

SPSR

$0B

FLAGS

NOTES:

The SS, SCK, MOSI and MISO are external pins which provide the following functions:

1. MOSI - Provides serial output to slave unit(s) when device is conﬁgured as a master. Receives serial input from master unit when device

is conﬁgured as a slave unit.

2. MISO - Receives serial input from slave unit(s) when device is configured as a master. Provides serial output to master when device is

configured as a slave unit.

3. SCK - Provides system clock when device is configured as a master unit. Receives system clock when device is configured as a slave unit.

4. SS - Provides a logic low to select device for a transfer with a master device.

FIGURE 29. SERIAL PRIPHERAL INTERFACE BLOCK DIAGRAM

Figure 30 illustrates the MOSI, MISO, and SCK master- Serial Peripheral Control Register (SPCR)

slave interconnections. Note that in Figure 30 the master SS

7

6

5

-

4

3

2

1

0

pin is tied to a logic high and the slave SS pin is a logic low.

Figure 27 provides a larger system connection for these

same pins. Note that in Figure 27, all SS pins are connected

to a port pin of a master/slave device. In this case any of the

devices can be a slave.

SPIE SPE

MSTR CPOL CPHA SPR1 SPR0 $0A

The serial peripheral control register bits are deﬁned as

follows:

B7, SPIE When the serial peripheral interrupt enable is

high, it allows the occurrence of a processor

interrupt, and forces the proper vector to be

loaded into the program counter if the serial

peripheral status register ﬂag bit (SPIF and/or

MODE) is set to a logic one. It does not inhibit

the setting of a status bit. The SPIE bit is cleared

by reset.

MASTER

SLAVE

MISO

MOSI

SCK

MISO

MOSI

SCK

8 - BIT SHIFT

REGISTER

8 - BIT SHIFT

REGISTER

SPI

CLOCK

GENERATOR

SS

+5V

SS

0V

B6, SPE

When the serial peripheral output enable control

bit is set, all output drive is applied to the

external pins and the system is enabled. When

the SPE bit is set, it enables the SPI system by

connecting it to the external pins thus allowing it

to interface with the external SPI bus. The pins

that are deﬁned as output depend on which

mode (master or slave) the device is in.

Because the SPE bit is cleared by reset, the SPI

system is not connected to the external pins

upon reset.

FIGURE 30. SERIAL PERIPHERAL INTERFACE MASTER-

SLAVE INTERCONNECTION

REGISTERS

There are three register in the serial parallel interface which

provide control, status, and data storage functions. These

registers which include the serial peripheral control register

(SPCR, location $0A), serial peripheral status register

(SPSR, location $0B), and serial peripheral data I/O register

(SPDR, location $0C) are described below.

2-49

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

B4, MSTR The master bit determines whether the device is

Serial Peripheral Status Register (SPSR)

a master or a slave. If the MSTR bit is a logic

zero it indicates a slave device and a logic one

denotes a master device. If the master mode is

selected, the function of the SCK pin changes

from an input to an output and the function of the

MISO and MOSI pins are reversed. This allows

the user to wire device pins MISO to MISO, and

MOSI to MOSI, and SCK to SCK without inci-

dent. The MSTR bit is cleared by reset; there-

fore, the device is always placed in the slave

mode during reset.

7

6

5

-

4

3

-

2

-

1

-

0

-

SPIF WCOL

MODF

$0B

The status ﬂags which generate a serial peripheral interface

(SPI) interrupt may be blocked by the SPIE control bit in the

serial peripheral control register. The WCOL bit does not

cause an interrupt. The serial peripheral status register bits

are deﬁned as follows:

B7, SPIF The serial peripheral data transfer ﬂag bit noti-

ﬁes the user that a data transfer between the

device and an external device has been com-

pleted. With the completion of the data transfer,

SPIF is set, and if SPIE is set, a serial peripheral

interrupt (SPI) is generated. During the clock

cycle that SPIF is being set, a copy of the

received data byte in the shift register is moved

to a buffer. When the data register is read, it is

the buffer that is read. During an overrun condi-

tion, when the master device has sent several

bytes of data and the slave device has not

responded to the ﬁrst SPIF, only the ﬁrst byte

sent is contained in the receiver buffer and all

other bytes are lost.

B3, CPOL The clock polarity bit controls the normal or

steady state value of the clock when data is not

being transferred. The CPOL bit affects both the

master and slave modes. It must be used in con-

junction with the clock phase control bit (CPHA)

to produce the wanted clock-data relationship

between a master and a slave device. When the

CPOL bit is a logic zero, it produces a steady

state low value at the SCK pin of the master

device. If the CPOL bit is a logic one, a high value

is produced at the SCK pin of the master device

when data is not being transferred. The CPOL bit

is not affected by reset. Refer to Figure 28.

The transfer of data is initiated by the master

device writing its serial peripheral data register.

B2, CPHA The clock phase bit controls the relationship

between the data on the MISO and MOSI pins

and the clock produced or received at the SCK

pin. This control has effect in both the master and

slave modes. It must be used in conjunction with

the clock polarity control bit (CPOL) to produce

the wanted clock-data relation. The CPHA bit in

general selects the clock edge which captures

data and allows it to change states. It has its

greatest impact on the ﬁrst bit transmitted (MSB)

in that it does or does not allow a clock transition

before the ﬁrst data capture edge. The CPHA bit

is not affected by reset. Refer to Figure 28.

Clearing the SPIF bit is accomplished by a soft-

ware sequence of accessing the serial periph-

eral status register while SPIF is set and

followed by a write to or a read of the serial

peripheral data register. While SPIF is set, all

writes to the serial peripheral data register are

inhibited until the serial peripheral status register

is read. This occurs in the master device. In the

slave device, SPIF can be cleared (using a simi-

lar sequence) during a second transmission;

however, it must be cleared before the second

SPIF in order to prevent an overrun condition.

The SPIF bit is cleared by reset.

B1, SPR1 These two serial peripheral rate bits select one

B0, SPR0 of four baud rates to used as SCK if the device

is a master; however they have no effect in the

slave mode. The slave device is capable of shift-

ing data in and out at a maximum rate which is

equal to the CPU clock. A rate table is given

below for the generation of the SCK from the

master. The SPR1 and SPR0 bits are not

affected by reset.

B6, WCOL The function of the write collision status bit is to

notify the user that an attempt was made to write

the serial peripheral data register while a data

transfer was taking place with an external

device. The transfer continues uninterrupted;

therefore, a write will be unsuccessful. A “read

collision” will never occur since the received

data byte is placed in a buffer in which access is

always synchronous with the MCU operation. If

a “write collision” occurs, WCOL is set but no

SPI interrupt is generated. The WCOL bit is a

status ﬂag only.

INTERNAL PROCESSOR

SPR1

SPR0

CLOCK DIVIDE BY

0

1

0

1

0

1

2

4

Clearing the WCOL bit is accomplished by a

software sequence of accessing the serial

peripheral status register while WCOL is set, fol-

lowed by 1) a read of the serial peripheral data

register prior to the SPIF bit being set, or 2) a

read or write of the serial peripheral data regis-

16

32

2-50

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

ter after the SPIF bit is set. A write to the serial

peripheral data register (SPDR) prior to the

SPIF bit being set, will result in generation of

another WCOL status ﬂag. Both the SPIF and

WCOL bits will be cleared in the same

sequence. If a second transfer has started while

trying to clear (the previously set) SPIF and

WCOL bits with a clearing sequence containing

a write to the serial peripheral data register, only

the SPIF bit will be cleared.

In this case it is assumed that the data byte writ-

ten (in the slave device serial peripheral inter-

face) is lost and the contents of the slave device

read buffer becomes the byte that is transferred.

Because the master device receives back the

last byte transmitted, the master device can

detect that a fatal WCOL occurred.

Since the slave device is operating asynchro-

nously with the master device, the WCOL bit

may be used as an indicator of a collision occur-

rence. This helps alleviate the user from a strict

real-time programming effort. The WCOL bit is

cleared by reset.

A collision of a write to the serial peripheral data

register while an external data transfer is taking

place can occur in both the master mode and

the slave mode, although with proper program-

ming the master device should have sufﬁcient

information to preclude this collision.

B4, MODF The function of the mode fault ﬂag is deﬁned for

the master mode (device). If the device is a

slave device the MODF bit will be prevented

from toggling from a logic zero to a logic one;

however, this does not prevent the device from

being in the slave mode with the MODF bit set.

The MODF bit is normally a logic zero and is set

only when the master device has its SS pin

pulled low. Toggling the MODF bit to a logic one

affects the internal serial peripheral interface

(SPI) system in the following ways:

Collision in the master device is deﬁned as a

write of the serial peripheral data register while

the internal rate clock (SCK) is in the process of

transfer. The signal on the SS pin is always high

on the master device.

A collision in a slave device is deﬁned in two

separate modes. One problem arises in a slave

device when the CPHA control bit is a logic zero.

When CPHA is a logic zero, data is latched with

the occurrence of the ﬁrst clock transition. The

slave device does not have any way of knowing

when that transition will occur; therefore, the

slave device collision occurs when it attempts to

write the serial peripheral data register after its

SS pin has been pulled low. The SS pin of the

slave device freezes the data in its serial periph-

eral data register and does not allow it to be

altered if the CPHA bit is a logic zero. The mas-

ter device must raise the SS pin of the slave

device high between each byte it transfers to the

slave device.

1. MODF is set and SPI interrupt is generated if

SPIE = 1.

2. The SPE bit is forced to a logic zero. This

blocks all output drive from the device, dis-

ables the SPI system.

3. The MSTR bit is forced to a logic zero, thus

forcing the device into the slave mode.

Clearing the MODF is accomplished by a soft-

ware sequence of accessing the serial periph-

eral status register while MODF is set followed

by a write to the serial peripheral control regis-

ter. Control bit SPE and MSTR may be restored

to their original set state during this cleared

sequence or after the MODF bit has been

cleared. Hardware does not allow the user to set

the SPE and MSTR bit while MODF is a logic

one unless it is during the proper clearing

sequence. The MODF ﬂag bit indicates that

there might have been a multi-master conﬂict for

system control and allows a proper exit from

system operation to a reset or default system

state. The MODF bit is cleared by reset.

The second collision mode is deﬁned for the

state of the CPHA control bit being a logic one.

With the CPHA bit set, the slave device will be

receiving a clock (SCK) edge prior to the latch of

the ﬁrst data transfer. This ﬁrst clock edge will

freeze the data in the slave device I/O register

and allow the MSB onto the external MISO pin

of the slave device. The SS pin low state

enables the slave device but the drive onto the

MISO pin does not take place until the ﬁrst data

transfer clock edge. The WCOL bit will only be

set if the I/O register is accessed while a transfer

is taking place. By deﬁnition of the second colli-

sion mode, a master device might hold a slave

device SS pin low during a transfer of several

bytes of data without a problem.

Serial Peripheral Data I/O Register (SPDR)

7

6

5

4

3

2

1

0

Serial Peripheral Data I/O Register

$0C

A special case of WCOL occurs in the slave The serial peripheral data I/O register is used to transmit and

device. This happens when the master device receive data on the serial bus. Only a write to this register

starts a transfer sequence (an edge on SCK for will initiate transmission/reception of another byte and this

CPHA = 1; or an active SS transition for CPHA = will only occur in the master device. A slave device writing to

0) at the same time the slave device CPU is writ- its data I/O register will not initiate a transmission. At the

ing to its serial peripheral interface data register. completion of transmitting a byte of data, the SPIF status bit

2-51

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

is set in both the master and slave devices. A write or read of will always receive the previous byte back from the slave

the serial peripheral data I/O register, after accessing the device if all MISO and MOSI lines are connected and the

serial peripheral status register with SPIF set, will clear SPIF. slave has not written its data I/O register. Other transmission

security methods might be deﬁned using ports for hand-

shake lines or data bytes with command ﬁelds.

During the clock cycle that the SPIF bit is being set, a copy

of the received data byte in the shift register is being moved

to a buffer. When the user reads the serial peripheral data

I/O register, the buffer is actually being read. During an over-

run condition, when the master device has sent several

bytes of data and the slave device has not internally

responded to clear the ﬁrst SPIF, only the ﬁrst byte is con-

tained in the receive buffer of the slave device; all others are

lost. The user may read the buffer at any time. The ﬁrst SPIF

must be cleared by the time a second transfer of data from

the shift register to the read buffer is initiated or an overrun

condition will exist.

A multi-master system may also be conﬁgured by the user.

An exchange of master control could be implemented using

a handshake method through the I/O ports or by an

exchange of code messages through the serial peripheral

interface system. The major device control that plays a part

in this system is the MSTR bit in the serial peripheral control

register and the MODF bit in the serial peripheral status

register.

Effects of STOP and WAIT Modes on the

Timer and Serial Systems

A write to the serial peripheral data I/O register is not buff-

ered and places data directly into the shift register for trans-

mission.

INTRODUCTION

The STOP and WAIT instructions have different effects on

the programmable timer, serial communications interface

(SCI), and serial peripheral interface (SPI) systems. These

different effects are discussed separately below.

The ability to access the serial peripheral data I/O register is

limited when a transmission is taking place. It is important to

read the discussion deﬁning the WCOL and SPIF status bit

to understand the limits on using the serial peripheral data

I/O register.

STOP MODE

SERIAL PERIPHERAL INTERFACE (SPI)

SYSTEM CONSIDERATIONS

When the processor executes the STOP instruction, the

internal oscillator is turned off. This halts all internal CPU

processing including the operation of the programmable

timer, serial communications interface, and serial peripheral

interface. The only way for the MCU to “wake up” from the

STOP mode is by receipt of an external interrupt (logic low

on IRQ pin) or by the detection of a reset (logic low on

RESET pin or a power-on reset). The effects of the STOP

mode on each of the MCU systems (Timer, SCI, and SPI)

are described separately.

There are two types of SPI systems; single master system

and multi-master systems. Figure 27 illustrates a single

master system and a discussion of both is provided below.

Figure 27 illustrates how a typical single master system may

be conﬁgured, using a CDP68HC05 family device as the

master and four CDP68HC05 family devices as slaves. As

shown, the MOSI, MISO, and SCK pins are all wired to

equivalent pins on each of the ﬁve devices. The master

device generates the SCK clock, the slave devices all

receive it. Since the CDP68HC05 master device is the bus

master, it internally controls the function of its MOSI and

MISO lines, thus writing data to the slave devices on the

MOSI and reading data from the slave devices on the MISO

lines. The master device selects the individual slave devices

by using four pins of a parallel port to control the four SS

pins of the slave devices. A slave device is selected when

the master device pulls its SS pin low. The SS pins are

pulled high during reset since the master device ports will be

forced to be inputs at that time, thus disabling the slave

devices. Note that the slave devices do not have to be

enabled in a mutually exclusive fashion except to prevent

bus contention on the MISO line. For example, three slave

devices, enabled for a transfer, are permissible if only one

has the capability of being read by the master. An example

of this is a write to several display drivers to clear a display

with a single I/O operation. To ensure that proper data trans-

mission is occurring between the master device and a slave

device, the master device may have the slave device

respond with a previously received data byte (this data byte

Timer During STOP Mode

When the MCU enters the STOP mode, the timer counter

stops counting (the internal processor is stopped) and

remains at that particular count value until the STOP mode is

exited by an interrupt (if exited by reset the counter is forced

to $FFFC). If the STOP mode is exited by an external low on

the IRQ pin, then the counter resumes from its stopped

value as if nothing had happened. Another feature of the

programmable timer, in the STOP mode, is that if at least

one valid input capture edge occurs at the TCAP pin, the

input capture detect circuitry is armed. This action does not

set any timer ﬂags or “wake up” the MCU, but when the

MCU does “wake up” there will be an active input capture

ﬂag (and data) from that ﬁrst valid edge which occurred dur-

ing the STOP mode. If the STOP mode is exited by an exter-

nal reset (logic low on RESET pin), then no such input

capture ﬂag or data action takes place even if there was a

valid input capture edge (at the TCAP pin) during the MCU

STOP mode.

SCI During STOP Mode

could be inverted or at least be a byte that is different from When the MCU enters the STOP mode, the baud rate gener-

the last one sent by the master device). The master device ator which drives the receiver and transmitter is shut down.

2-52

CDP68HC05C4, C8, CDP68HCL05C4, C8, CDP68HSC05C4, C8

This essentially stops all SCI activity. The receiver is unable results in an MCU “wake up”. Caution should be observed

to receive and transmitter is unable to transmit. If the STOP when operating the SPI (as a slave) during the STOP mode

instruction is executed during a transmitter transfer, that because none of the protection circuitry (write collision,

transfer is halted. When the STOP mode is exited, that par- mode fault, etc.) is active.

ticular transmission resumes (if the exit is the result of a low

It should also be noted that when the MCU enters the STOP

input to the IRQ pin). Since the previous transmission

mode all enabled output drivers (TDO, TCMP, MISO, MOSI,

resumes after an IRQ interrupt STOP mode exit, the user

and SCK ports) remain active and any sourcing currents

should ensure that the SCI transmitter is in the idle state

from these outputs will be part of the total supply current

when the STOP instruction is executed. If the receiver is

required by the device.

receiving data when the STOP instruction is executed,

received data sampling is stopped (baud rate generator

stops) and the rest of the data is lost. For the above reasons,

all SCI transactions should be in the idle state when the

STOP instruction is executed.

WAIT MODE

When the MCU enters the WAIT mode, the CPU clock is

halted. All CPU action is suspended; however, the timer,

SCI, and SPI systems remain active. In fact an interrupt from

the timer, SCI, or SPI (in addition to a logic low on the IRQ or

RESET pins) causes the processor to exit the WAIT mode.

Since the three systems mentioned above operate as they

do in the normal mode, only a general discussion of the

WAIT mode is provided below.

SPI During STOP Mode

When the MCU enters the STOP mode, the baud rate gener-

ator which drives the SPI shuts down. This essentially stops

all master mode SPI operation, thus the master SPI is unable

to transmit or receive any data. If the STOP instruction is exe-

cuted during an SPI transfer, that transfer is halted until the

MCU exits the STOP mode (provided it is an exit resulting

from a logic low on the IRQ pin). If the STOP mode is exited

by a reset, then the appropriate control/status bits are cleared

and the SPI is disabled. If the device is in the slave mode

when the STOP instruction is executed, the slave SPI will still

operate. It can still accept data and clock information in addi-

tion to transmitting its own data back to a master device.

The WAIT mode power consumption depends on how many

systems are active. The power consumption will be highest

when all the systems (timer, TCMP, SCI, and SPI) are active.

The power consumption will be the least when the SCI and

SPI systems are disabled (timer operation cannot be dis-

abled in the WAIT mode). If a non-reset exit from the WAIT

mode is performed (i.e., timer overﬂow interrupt exit), the

state of the remaining systems will be unchanged. If a reset

exit from the WAIT mode is performed all the systems revert

to the disabled reset state.

At the end of a possible transmission with a slave SPI in the

STOP mode, no ﬂags are set until a logic low IRQ input

2-53


型号：	CDP68HCL05C4D
厂家：	RENESAS TECHNOLOGY CORP
描述：	IC,MICROCONTROLLER,8-BIT,6805 CPU,CMOS,DIP,40PIN,CERAMIC 微控制器
文件：	总51页 (文件大小：338K)
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CDP68HCL05C4D [RENESAS]

相关型号：

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