EL2126CSZ-T13 [RENESAS]
OP-AMP, 2000uV OFFSET-MAX, 80MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, SOIC-8;
| 型号： | EL2126CSZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | OP-AMP, 2000uV OFFSET-MAX, 80MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, SOIC-8 放大器 光电二极管 |
| 文件： | 总19页 (文件大小：838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
EL2126
FN7046
Rev 4.00
May 2, 2007
Ultra-Low Noise, Low Power, Wideband Amplifier
The EL2126 is an ultra-low noise, wideband amplifier that
runs on half the supply current of competitive parts. It is
intended for use in systems such as ultrasound imaging
where a very small signal needs to be amplified by a large
amount without adding significant noise. Its low power
dissipation enables it to be packaged in the tiny SOT-23
package, which further helps systems where many input
channels create both space and power dissipation problems.
Features
• Voltage noise of only 1.3nV/Hz
• Current noise of only 1.2pA/Hz
• 200µV offset voltage
• 100MHz -3dB BW for A = 10
V
• Very low supply current - 4.7mA
• SOT-23 package
The EL2126 is stable for gains of 10 and greater and uses
traditional voltage feedback. This allows the use of reactive
elements in the feedback loop, a common requirement for
many filter topologies. It operates from ±2.5V to ±15V
supplies and is available in the 5 Ld SOT-23 and 8 Ld SO
packages.
• ±2.5V to ±15V operation
• Pb-free plus anneal available (RoHS compliant)
Applications
• Ultrasound input amplifiers
• Wideband instrumentation
• Communication equipment
• AGC and PLL active filters
• Wideband sensors
The EL2126 is fabricated in Elantec’s proprietary
complementary bipolar process, and is specified for
operation over the full -40°C to +85°C temperature range.
Pinouts
EL2126
(5 LD SOT-23)
TOP VIEW
OUT
VS-
IN+
1
2
3
5
4
VS+
IN-
+
-
EL2126
(8 LD SOIC)
TOP VIEW
NC
IN-
1
2
3
4
8
7
6
5
NC
VS+
OUT
NC
-
+
IN+
VS-
FN7046 Rev 4.00
May 2, 2007
Page 1 of 19
EL2126
Ordering Information
PART
NUMBER
PART
MARKING
TEMP RANGE
(°C)
TAPE AND REEL
PACKAGE
5 Ld SOT-23
PKG. DWG. #
MDP0038
EL2126CW-T7
EL2126CW-T7A
EL2126CS
G
G
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
7” (3k pcs)
7” (250 pcs)
5 Ld SOT-23
MDP0038
MDP0027
MDP0027
MDP0027
MDP0027
2126CS
2126CS
2126CS
2126CSZ
-
7”
13”
-
8 Ld SOIC (150 mil)
8 Ld SOIC (150 mil)
8 Ld SOIC (150 mil)
EL2126CS-T7
EL2126CS-T13
EL2126CSZ ( Note)
8 Ld SOIC (150 mil)
(Pb-free)
EL2126CSZ-T7 ( Note)
EL2126CSZ-T13 ( Note)
EL2126CWZ-T7 (Note)
EL2126CWZ-T7A (Note)
2126CSZ
2126CSZ
BAAH
-40 to +85
-40 to +85
-40 to +85
-40 to +85
7”
13”
7”
8 Ld SOIC (150 mil)
(Pb-free)
MDP0027
MDP0027
P5.064
8 Ld SOIC (150 mil)
(Pb-free)
5 Ld SOT-23 (SC74)
(1.65mm) (Green)
BAAH
7”
5 Ld SOT-23 (SC74)
(1.65mm) (Green)
P5.064
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN7046 Rev 4.00
May 2, 2007
Page 2 of 19
EL2126
Absolute Maximum Ratings
Thermal Information
V + to V -) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-60°C to +150°C
Maximum Die Junction Temperature . . . . . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
S
S
Any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . V + -0.3V to V - +0.3V
S
S
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, T = +25°C, R = 180, R = 20, R = 500 Unless Otherwise Specified.
S
S
A
F
G
L
Parameter
Description
Conditions
Min
Typ
0.2
17
Max
Unit
DC PERFORMANCE
V
Input Offset Voltage (SO8)
2
3
mV
mV
OS
Input Offset Voltage (SOT23-5)
T
Offset Voltage Temperature
Coefficient
µV/°C
CVOS
I
I
Input Bias Current
-10
-7
µA
µA
B
Input Bias Current Offset
0.06
0.013
0.6
OS
T
Input Bias Current Temperature
Coefficient
µA/°C
CIB
C
Input Capacitance
Open Loop Gain
2.2
87
pF
dB
dB
IN
A
V
= -2.5V to +2.5V
O
80
80
VOL
PSRR
Power Supply Rejection Ratio
(Note 1)
100
CMRR
CMIR
Common Mode Rejection Ratio
Common Mode Input Range
Positive Output Voltage Swing
Negative Output Voltage Swing
Positive Output Voltage Swing
Negative Output Voltage Swing
at CMIR
75
-4.6
3.8
106
dB
V
3.8
-3.9
-3.2
V
V
V
V
No load, R = 1k
3.8
-4
V
OUTH
OUTL
OUTH2
OUTL2
OUT
F
No load, R = 1k
V
F
R
R
= 100
= 100
3.2
80
3.45
-3.5
100
V
L
L
V
I
Output Short Circuit Current
(Note 2)
mA
I
Supply Current
4.7
5.5
mA
SY
AC PERFORMANCE - R = 20, C = 3pF
G
L
BW
-3dB Bandwidth, R = 500
100
17
MHz
MHz
MHz
dB
L
BW ±0.1dB
BW ±1dB
Peaking
SR
±0.1dB Bandwidth, R = 500
L
±1dB Bandwidth, R = 500
80
L
Peaking, R = 500
0.6
110
2.8
-7
L
Slew Rate
V
= 2V , measured at 20% to 80%
P-P
80
V/µs
%
OUT
OS
Overshoot, 4V
Wave
Output Square
Positive
P-P
Negative
%
t
Settling Time to 0.1% of ±1V Pulse
51
ns
S
FN7046 Rev 4.00
May 2, 2007
Page 3 of 19
EL2126
Electrical Specifications V + = +5V, V - = -5V, T = +25°C, R = 180, R = 20, R = 500 Unless Otherwise Specified.
S
S
A
F
G
L
Parameter
Description
Conditions
Min
Typ
1.3
1.2
-70
-70
Max
Unit
nV/Hz
pA/Hz
dBc
V
Voltage Noise Spectral Density
Current Noise Spectral Density
N
I
N
HD2
2nd Harmonic Distortion (Note 3)
3rd Harmonic Distortion (Note 3)
HD3
dBc
NOTES:
1. Measured by moving the supplies from ±4V to ±6V
2. Pulse test only and using a 10 load
3. Frequency = 1MHz, V
= 2V , into 500 and 5pF load
P-P
OUT
Electrical Specifications V + = +15V, V - = -15V, T = 25°C, R = 180, R = 20, R = 500 unless otherwise specified.
S
S
A
F
G
L
Parameter
Description
Conditions
Min
Typ
0.5
4.5
Max
Unit
DC PERFORMANCE
V
Input Offset Voltage (SO8)
3
3
mV
mV
OS
Input Offset Voltage (SOT23-5)
T
Offset Voltage Temperature
Coefficient
µV/°C
CVOS
I
I
Input Bias Current
-10
-7
µA
µA
B
Input Bias Current Offset
0.12
0.016
0.7
OS
T
Input Bias Current Temperature
Coefficient
µA/°C
CIB
C
Input Capacitance
Open Loop Gain
2.2
90
80
pF
dB
dB
IN
A
80
65
VOL
PSRR
Power Supply Rejection Ratio
(Note 4)
CMRR
CMIR
Common Mode Rejection Ratio
Common Mode Input Range
Positive Output Voltage Swing
Negative Output Voltage Swing
Positive Output Voltage Swing
Negative Output Voltage Swing
at CMIR
70
85
dB
V
-14.6
13.6
13.8
-13.7
-9.5
V
V
V
V
No load, R = 1k
13.7
-13.8
11.2
-10.3
220
V
OUTH
OUTL
OUTH2
OUTL2
OUT
F
No load, R = 1k
V
F
R
= 100, R = 1k
10.2
140
V
L
L
F
R
= 100, R = 1k
V
F
I
Output Short Circuit Current
(Note 5)
mA
I
Supply Current
5
6
mA
SY
AC PERFORMANCE - R = 20, C = 3pF
G
L
BW
-3dB Bandwidth, R = 500
135
26
MHz
MHz
MHz
dB
L
BW ±0.1dB
BW ±1dB
Peaking
SR
±0.1dB Bandwidth, R = 500
L
±1dB Bandwidth, R = 500
60
L
Peaking, R = 500
2.1
150
L
Slew Rate (±2.5V Square Wave,
Measured 25%-75%)
130
V/µS
OS
Overshoot, 4V
Wave
Output Square
Positive
1.6
-4.4
48
%
%
ns
P-P
Negative
T
Settling Time to 0.1% of ±1V Pulse
S
FN7046 Rev 4.00
May 2, 2007
Page 4 of 19
EL2126
Electrical Specifications V + = +15V, V - = -15V, T = 25°C, R = 180, R = 20, R = 500 unless otherwise specified. (Continued)
S
S
A
F
G
L
Parameter
Description
Conditions
Min
Typ
1.4
1.1
-72
-73
Max
Unit
nV/Hz
pA/Hz
dBc
V
Voltage Noise Spectral Density
Current Noise Spectral Density
N
I
N
HD2
2nd Harmonic Distortion (Note 6)
3rd Harmonic Distortion (Note 6)
HD3
dBc
NOTES:
4. Measured by moving the supplies from ±13.5V to ±16.5V
5. Pulse test only and using a 10 load
6. Frequency = 1MHz, V
= 2V , into 500 and 5pF load
P-P
OUT
Typical Performance Curves
10
10
V
= ±5V
= 10
= 5pF
= 500
V
= ±15V
= 10
= 5pF
= 500
S
S
R
= 1k
F
A
C
R
A
C
R
V
L
L
V
L
L
R
= 1k
F
6
2
6
2
R
R
= 500
= 180
R
= 500
F
F
F
-2
-2
R
= 180
F
R
= 100
F
-6
-6
R
= 100
F
-10
-10
1M
10M
FREQUENCY (Hz)
100M
1M
10M
FREQUENCY (Hz)
100M
FIGURE 1. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
FIGURE 2. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
8
8
V
= ±5V
= -10
= 5pF
= 500
R = 1k
F
V
= ±15V
= -10
= 5pF
= 500
S
S
R
= 500
R = 1k
F
F
A
C
R
A
C
R
V
L
L
V
L
L
R
= 500
4
0
4
0
F
R
= 350
F
R
= 350
F
R = 200
F
R
= 200
F
-4
-4
R
F
= 100
R
= 100
F
-8
-8
-12
1M
-12
1M
10M
FREQUENCY (Hz)
100M
10M
FREQUENCY (Hz)
100M
FIGURE 3. INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
FIGURE 4. INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
FN7046 Rev 4.00
May 2, 2007
Page 5 of 19
EL2126
Typical Performance Curves (Continued)
10
10
6
V
= ±5V
= 20
= 500
= 5pF
V
= ±15V
= 20
= 500
= 5pF
S
S
R
R
C
R
R
C
G
L
L
G
L
L
6
2
A
= 10
V
2
A
= 10
V
A
= 20
A
= 20
V
V
-2
-2
-6
-10
A
= 50
V
A
= 50
V
-6
-10
1M
10M
FREQUENCY (Hz)
100M
1M
10M
FREQUENCY (Hz)
100M
FIGURE 5. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS GAIN
FIGURE 6. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS GAIN
8
8
V
C
R
= ±5V
= 5pF
= 35
S
L
G
V
C
R
= ±15V
= 5pF
= 20
S
L
G
4
0
4
0
A
= -10
V
A
= -10
V
-4
-4
A
= -50
10M
V
A
= -50
V
A
= -20
A
= -20
V
V
-8
-8
-12
1M
-12
1M
100M
10M
FREQUENCY (Hz)
100M
FREQUENCY (Hz)
FIGURE 7. INVERTING FREQUENCY RESPONSE FOR
VARIOUS GAIN
FIGURE 8. INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
10
8
V
= ±15V
= 5pF
= 500
= 180
= 10
S
V
= ±5V
= 5pF
= 500
= 180
= 10
S
C
R
R
A
L
L
F
V
C
R
R
A
L
L
F
V
V
= 30mV
PP
6
2
O
4
0
V
= 500mV
O
PP
V
= 30mV
PP
O
V
= 500mV
PP
O
V
= 1V
PP
O
-2
-4
V
= 10V
O
PP
V
= 5V
PP
O
V
O
= 5V
-6
PP
V
= 2.5V
PP
-8
O
V
= 2.5V
PP
O
V
= 1V
PP
O
-10
-12
1M
1M
10M
FREQUENCY (Hz)
100M
10M
FREQUENCY (Hz)
100M
FIGURE 10. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
FIGURE 9. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
FN7046 Rev 4.00
May 2, 2007
Page 6 of 19
EL2126
Typical Performance Curves (Continued)
8
8
4
V
= ±5V
= 5pF
= 500
= 350
= 10
V
= ±15V
= 5pF
= 500
= 200
= 10
S
S
V
= 500mV
PP
V = 500mV
O
C
R
R
A
C
R
R
A
O
PP
V = 30mV
O
L
L
F
V
L
L
F
V
4
0
V
= 30mV
O
PP
PP
V
= 1V
O
PP
V
= 1V
PP
O
0
V
= 3.4V
V = 3.4V
O PP
O
PP
-4
-4
-8
-12
V
= 2.5V
V
= 2.5V
O
PP
O
PP
-8
-12
1M
10M
FREQUENCY (Hz)
100M
1M
10M
100M
FREQUENCY (Hz)
FIGURE 11. INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
FIGURE 12. INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
10
10
V
= ±15V
= 180
= 10
V
= ±5V
= 150
= 10
S
S
R
A
R
R
A
R
F
V
L
F
V
L
C
= 28pF
C = 11pF
L
L
6
2
6
2
C
= 28pF
L
= 500
= 500
C
= 16pF
L
C
= 11pF
C = 16pF
L
L
C
= 5pF
C
L
= 5pF
= 1pF
L
-2
-2
C
= 1.2pF
L
C
L
-6
-6
-10
-10
1M
10M
FREQUENCY (Hz)
100M
1M
10M
FREQUENCY (Hz)
100M
FIGURE 14. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
FIGURE 13. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
8
8
V
= ±5V
= 350
= 500
= -10
C
= 28pF
V
S
= ±15V
= 200
= 500
= -10
S
L
C
= 28pF
L
R
R
A
R
R
A
F
L
V
F
L
V
4
0
4
0
C
= 16pF
= 11pF
L
C
= 16pF
L
C
L
C = 11pF
L
-4
-4
C
= 5pF
L
C
= 5pF
L
C
= 1.2pF
L
C
= 1.2pF
L
-8
-8
-12
-12
1M
10M
FREQUENCY (Hz)
100M
1M
10M
FREQUENCY (Hz)
100M
FIGURE 15. INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
FIGURE 16. INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
FN7046 Rev 4.00
May 2, 2007
Page 7 of 19
EL2126
Typical Performance Curves (Continued)
100
80
60
40
20
0
250
GAIN
150
PHASE
50
0.6/DIV
-50
-150
-250
V
=±5V
S
0
10k
100k
1M
10M
100M
1G
0
1.5/DIV
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
FIGURE 17. OPEN LOOP GAIN AND OPEN LOOP PHASE
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
3.0
160
V
= ±5V
= 20
= 500
= 5pF
V
= ±5V
= 20
= 500
= 5pF
S
S
140
120
100
80
A = -10
V
R
R
C
R
R
C
G
L
L
G
L
L
2.5
2.0
1.5
1.0
0.5
0
A
= 10
V
A
= 10
V
A
= -20
V
60
40
A
= -20
= 50
V
A
= -10
8
V
A
= -50
V
20
A
V
0
0
2
4
6
10
12
14
16
0
2
4
6
8
10
12
14
16
SUPPLY VOLTAGE (V)
±V (V)
S
FIGURE 20. PEAKING vs Vs
FIGURE 19. BANDWIDTH vs Vs
R
R
= 180
= 20
V
V
= ±5V
F
G
S
O
= 2V
PP
0.5V/DIV
20mV/DIV
R
R
= 180
= 20
F
G
V
V
= ±5V
= 100mV
S
O
PP
10ns/DIV
10ns/DIV
FIGURE 22. SMALL SIGNAL STEP RESPONSE
FIGURE 21. LARGE SIGNAL STEP RESPONSE
FN7046 Rev 4.00
May 2, 2007
Page 8 of 19
EL2126
Typical Performance Curves (Continued)
-40
-30
-40
-50
-60
-70
-80
-90
-100
V
V
R
A
R
= ±5V
V
V
= ±5V
S
O
F
V
L
S
O
= 2V
= 2V
P-P
P-P
-50
-60
= 180
= 10
R
A
R
= 180
= 10
= 500
F
V
L
2nd HD
2nd HD
3rd HD
= 500
-70
-80
3rd HD
-90
-100
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
V
(V
)
V
(V )
OUT P-P
OUT P-P
FIGURE 23. 1MHz HARMONIC DISTORTION vs OUTPUT
SWING
FIGURE 24. 1MHz HARMONIC DISTORTION vs OUTPUT
SWING
-20
10
V
V
= ±5V
= 2V
S
O
-30
-40
-50
-60
-70
-80
-90
P-P
I
, V = ±5V
S
N
V
, V = ±15V
S
N
V
, V = ±5V
S
N
I
, V = ±15V
S
N
1
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 25. TOTAL HARMONIC DISTORTION vs FREQUENCY
FIGURE 26. NOISE vs FREQUENCY
16
12
8
70
60
50
40
30
20
10
0
V
R
= ±5V
= 500
S
L
A
= 10
V
4
A
= -10
V
0
-4
1M
10M
FREQUENCY (Hz)
100M
400M
0.1
1.0
10.0
ACCURACY (%)
FIGURE 28. GROUP DELAY vs FREQUENCY
FIGURE 27. SETTLING TIME vs ACCURACY
FN7046 Rev 4.00
May 2, 2007
Page 9 of 19
EL2126
Typical Performance Curves (Continued)
-10
-30
110
90
70
50
30
10
V
=±5V
S
PSRR-
-50
-70
PSRR+
-90
-110
10
100
1k
10k 100k 1M
FREQUENCY (Hz)
10M 100M
10k
100k
1M
10M
200M
FREQUENCY (Hz)
FIGURE 29. CMRR vs FREQUENCY
FIGURE 30. PSRR vs FREQUENCY
120
100
80
60
40
20
0
3.5
3
100
10
V
= ±5V
V
= ±5V
S
S
2.5
2
BANDWIDTH
1.5
1
1
PEAKING
0.5
0
0.1
0.01
-0.5
10k
100k
1M
10M
100M
-40
0
40
80
120
160
FREQUENCY (Hz)
TEMPERATURE (°C)
FIGURE 31. CLOSED LOOP OUTPUT IMPEDANCE vs
FREQUENCY
FIGURE 32. BANDWIDTH AND PEAKING vs TEMPERATURE
5.2
220
15V
-
SR
200
180
160
140
120
100
80
V
=±15V
S
5.1
5
15V
+
SR
V
=±5V
5V
-
S
SR
4.9
4.8
5V
+
SR
60
-1
-50
0
50
100
150
1
3
5
7
9
11
13
15
DIE TEMPERATURE (°C)
V
SWING (V
)
PP
OUT
FIGURE 34. SUPPLY CURRENT vs TEMPERATURE
FIGURE 33. SLEW RATE vs SWING
FN7046 Rev 4.00
May 2, 2007
Page 10 of 19
EL2126
Typical Performance Curves (Continued)
1
120
110
100
90
V
= ±5V
S
0
-1
-2
V
= ±5V
S
V
= ±15V
S
80
-50
-50
0
50
100
150
0
50
100
150
DIE TEMPERATURE (°C)
DIE TEMPERATURE (°C)
FIGURE 35. OFFSET VOLTAGE vs TEMPERATURE
FIGURE 36. CMRR vs TEMPERATURE
110
106
4.05
4
3.95
3.9
V
= ±5V
S
102
98
94
90
86
82
V
= ±5V
S
V
= ±15V
S
3.85
3.8
-50
0
50
100
150
-50
0
50
100
150
DIE TEMPERATURE (°C)
DIE TEMPERATURE (°C)
FIGURE 37. PSRR vs TEMPERATURE
FIGURE 38. POSITIVE OUTPUT SWING vs TEMPERATURE
13.85
-3.9
-3.95
-4
13.8
13.75
13.7
V
= ±15V
S
V
= ±5V
-4.05
-4.1
S
-4.15
-4.2
13.65
13.6
-4.25
-50
0
50
100
150
-50
0
50
100
150
DIE TEMPERATURE (°C)
DIE TEMPERATURE (°C)
FIGURE 39. POSITIVE OUTPUT SWING vs TEMPERATURE
FIGURE 40. NEGATIVE OUTPUT SWING vs TEMPERATURE
FN7046 Rev 4.00
May 2, 2007
Page 11 of 19
EL2126
Typical Performance Curves (Continued)
-13.76
102
100
98
V
= ±5V
S
-13.78
96
V
= ±15V
S
94
-13.8
92
90
-13.82
88
-50
-50
0
50
100
150
0
50
100
150
DIE TEMPERATURE (°C)
DIE TEMPERATURE (°C)
FIGURE 41. NEGATIVE OUTPUT SWING vs TEMPERATURE
FIGURE 42. SLEW RATE vs TEMPERATURE
155
150
3.52
3.5
V
= ±5V
S
V
= ±15V
S
145
140
135
3.48
3.46
3.44
V
= 2V
PP
O
-50
0
50
100
150
-50
0
50
100
150
DIE TEMPERATURE (°C)
DIE TEMPERATURE (°C)
FIGURE 43. SLEW RATE vs TEMPERATURE
FIGURE 44. POSITIVE LOADED OUTPUT SWING vs
TEMPERATURE
11.8
11.6
-3.35
-3.4
V
= ±15V
S
11.4
11.2
11
-3.45
-3.5
V
= ±5V
S
3.55
10.8
10.6
-3.6
-50
0
50
100
150
-50
0
50
100
150
DIE TEMPERATURE (°C)
DIE TEMPERATURE (°C)
FIGURE 45. POSITIVE LOADED OUTPUT SWING vs
TEMPERATURE
FIGURE 46. NEGATIVE LOADED OUTPUT SWING vs
TEMPERATURE
FN7046 Rev 4.00
May 2, 2007
Page 12 of 19
EL2126
Typical Performance Curves (Continued)
-9.4
-9.6
-9.8
V =±15V
S
-10
-10.2
-10.4
-10.6
-50
0
50
Die Temperature (°C)
100
150
FIGURE 47. NEGATIVE LOADED OUTPUT SWING vs TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1
1.8
1.6
1.4
1.2
1
781mW
488mW
1.136W
543mW
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT Temperature (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 48. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 49. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7046 Rev 4.00
May 2, 2007
Page 13 of 19
EL2126
Pin Descriptions
EL2126CW
EL2126CS
(5 Ld SOT-23)
( 8 Ld SOIC)
PIN NAME
PIN FUNCTION
EQUIVALENT CIRCUIT
1
6
VOUT
Output
V
+
S
V
OUT
Circuit 1
2
3
4
3
VS-
Supply
Input
VINA+
V
+
S
V
+
V -
IN
IN
V
-
S
Circuit 2
4
5
2
7
VINA-
VS+
Input
Reference Circuit 2
Supply
FN7046 Rev 4.00
May 2, 2007
Page 14 of 19
EL2126
Noise Calculations
Applications Information
The primary application for the EL2126 is to amplify very small
signals. To maintain the proper signal-to-noise ratio, it is
essential to minimize noise contribution from the amplifier.
Figure 51 shows all the noise sources for all the components
around the amplifier.
Product Description
The EL2126 is an ultra-low noise, wideband monolithic
operational amplifier built on Elantec's proprietary high speed
complementary bipolar process. It features 1.3nV/Hz input
voltage noise, 200µV typical offset voltage, and 73dB THD. It is
intended for use in systems such as ultrasound imaging where
very small signals are needed to be amplified. The EL2126
R
3
V
V
V
N
IN
R3
+
-
I
+
V
ON
N
also has excellent DC specifications: 200µV V , 22µA IB,
OS
0.4µA I , and 106dB CMRR. These specifications allow the
OS
EL2126 to be used in DC-sensitive applications such as
V
R1
R
1
difference amplifiers.
I
-
V
R2
N
Gain-Bandwidth Product
R
2
The EL2126 has a gain-bandwidth product of 650MHz at ±5V.
For gains less than 20, higher-order poles in the amplifier's
transfer function contribute to even higher closed-loop
bandwidths. For example, the EL2126 has a -3dB bandwidth of
100MHz at a gain of 10 and decreases to 33MHz at gain of 20.
It is important to note that the extra bandwidth at lower gain
does not come at the expenses of stability. Even though the
EL2126 is designed for gain 10. With external compensation,
the device can also operate at lower gain settings. The RC
network shown in Figure 50 reduces the feedback gain at high
frequency and thus maintains the amplifier stability. R values
must be less than RF divided by 9 and 1 divided by 2RC
must be less than 200MHz.
FIGURE 51.
V
is the amplifier input voltage noise
N
I + is the amplifier positive input current noise
N
I - is the amplifier negative input current noise
N
V
is the thermal noise associated with each resistor:
RX
(EQ. 1)
V
=
4kTRx
RX
where:
k is Boltzmann's constant = 1.380658 x 10
-23
R
F
R
T is temperature in degrees Kelvin (273 + °C)
-
V
OUT
C
+
The total noise due to the amplifier seen at the output of the
amplifier can be calculated by using the Equation 2.
V
IN
As the equation shows, to keep noise at a minimum, small
resistor values should be used. At higher amplifier gain
FIGURE 50.
configuration where R is reduced, the noise due to IN-, R ,
2
2
and R decreases and the noise caused by IN+, VN, and R
Choice of Feedback Resistor, RF
1
3
starts to dominate. Because noise is summed in a root-mean-
squares method, noise sources smaller than 25% of the
largest noise source can be ignored. This can greatly simplify
the formula and make noise calculation much easier to
calculate.
The feedback resistor forms a pole with the input capacitance.
As this pole becomes larger, phase margin is reduced. This
increases ringing in the time domain and peaking in the
frequency domain. Therefore, RF has some maximum value
which should not be exceeded for optimum performance. If a
large value of RF must be used, a small capacitor in the few pF
range in parallel with RF can help to reduce this ringing and
peaking at the expense of reducing the bandwidth. Frequency
response curves for various RF values are shown in the typical
performance curves section of this data sheet.
2
2
2
2
R
R
R
R
2
2
2
2
2
1
1
1
1
------
------
------
------
V
=
BW VN 1 +
+ IN- R + IN+ R 1 +
+ 4 K T R + 4 K T R
+ 4 K T R 1 +
ON
1
3
1
2
3
R
2
R
2
R
2
R
2
(EQ. 2)
FN7046 Rev 4.00
May 2, 2007
Page 15 of 19
EL2126
Output Drive Capability
Supply Voltage Range and Single Supply Operation
The EL2126 is designed to drive low impedance load. It can
The EL2126 has been designed to operate with supply voltage
range of ±2.5V to ±15V. With a single supply, the EL2126 will
operate from +5V to +30V. Pins 4 and 7 are the power supply
pins. The positive power supply is connected to pin 7. When
used in single supply mode, pin 4 is connected to ground.
When used in dual supply mode, the negative power supply is
connected to pin 4.
easily drive 6V
signal into a 100 load. This high output
P-P
drive capability makes the EL2126 an ideal choice for RF, IF,
and video applications. Furthermore, the EL2126 is
current-limited at the output, allowing it to withstand
momentary short to ground. However, the power dissipation
with output-shorted cannot exceed the power dissipation
capability of the package.
As the power supply voltage decreases from +30V to +5V, it
becomes necessary to pay special attention to the input
voltage range. The EL2126 has an input voltage range of 0.4V
from the negative supply to 1.2V from the positive supply. So,
for example, on a single +5V supply, the EL2126 has an input
voltage range which spans from 0.4V to 3.8V. The output range
of the EL2126 is also quite large, on a +5V supply, it swings
from 0.4V to 3.8V.
Driving Cables and Capacitive Loads
Although the EL2126 is designed to drive low impedance load,
capacitive loads will decreases the amplifier's phase margin.
As shown in the performance curves, capacitive load can result
in peaking, overshoot and possible oscillation. For optimum AC
performance, capacitive loads should be reduced as much as
possible or isolated with a series resistor between 5 to 20.
When driving coaxial cables, double termination is always
recommended for reflection-free performance. When properly
terminated, the capacitance of the coaxial cable will not add to
the capacitive load seen by the amplifier.
Power Supply Bypassing And Printed Circuit Board
Layout
As with any high frequency devices, good printed circuit board
layout is essential for optimum performance. Ground plane
construction is highly recommended. Lead lengths should be
kept as short as possible. The power supply pins must be
closely bypassed to reduce the risk of oscillation. The
combination of a 4.7µF tantalum capacitor in parallel with
0.1µF ceramic capacitor has been proven to work well when
placed at each supply pin. For single supply operation, where
pin 4 (V -) is connected to the ground plane, a single 4.7µF
S
tantalum capacitor in parallel with a 0.1µF ceramic capacitor
across pins 7 (V +) and pin 4 (V -) will suffice.
S
S
For good AC performance, parasitic capacitance should be
kept to a minimum. Ground plane construction again should be
used. Small chip resistors are recommended to minimize
series inductance. Use of sockets should be avoided since
they add parasitic inductance and capacitance which will result
in additional peaking and overshoot.
FN7046 Rev 4.00
May 2, 2007
Page 16 of 19
EL2126
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7046 Rev 4.00
May 2, 2007
Page 17 of 19
EL2126
Small Outline Transistor Plastic Packages (SOT23-5)
D
P5.064
VIEW C
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
INCHES MILLIMETERS
MIN
e1
SYMBOL
MAX
0.057
0.0059
0.051
0.020
0.018
0.009
0.008
0.118
0.118
0.067
MIN
0.90
0.00
0.90
0.30
0.30
0.08
0.08
2.80
2.60
1.50
MAX
1.45
0.15
1.30
0.50
0.45
0.22
0.20
3.00
3.00
1.70
NOTES
5
1
4
A
A1
A2
b
0.036
0.000
0.036
0.012
0.012
0.003
0.003
0.111
0.103
0.060
-
-
-
-
E
C
L
C
E1
L
2
3
b
b1
c
e
6
6
3
-
C
L
c1
D
0.20 (0.008) M
C
C
C
L
E
E1
e
3
-
SEATING
PLANE
0.0374 Ref
0.0748 Ref
0.014 0.022
0.95 Ref
1.90 Ref
0.35 0.55
A2
A1
A
e1
L
-
-C-
4
L1
L2
N
0.024 Ref.
0.010 Ref.
5
0.60 Ref.
0.25 Ref.
5
0.10 (0.004) C
5
b
WITH
R
0.004
-
0.10
-
PLATING
b1
R1
0.004
0.010
0.10
0.25
o
o
o
o
0
8
0
8
-
c
c1
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178AA.
4X 1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
GAUGE PLANE
SEATING
PLANE
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
L
C
L2
L1
4X 1
VIEW C
FN7046 Rev 4.00
May 2, 2007
Page 18 of 19
EL2126
SOT-23 Package Family
MDP0038
SOT-23 PACKAGE FAMILY
e1
D
A
MILLIMETERS
SOT23-5
6
4
N
SYMBOL
SOT23-6
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
6
TOLERANCE
MAX
A
A1
A2
b
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
5
±0.05
E1
E
±0.15
2
3
±0.05
0.15
2X
C
D
c
±0.06
1
2
3
0.20
2X
C
D
Basic
5
e
E
Basic
E1
e
Basic
0.20
C
A-B
D
M
B
b
NX
Basic
e1
L
Basic
±0.10
L1
N
Reference
Reference
Rev. F 2/07
0.15
2X
C
A-B
1
3
D
NOTES:
C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
A2
SEATING
PLANE
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
A1
0.10
NX
C
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
6. SOT23-5 version has no center lead (shown as a dashed line).
(L1)
H
A
GAUGE
PLANE
0.25
c
+3°
-0°
L
0°
© Copyright Intersil Americas LLC 2002-2007. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7046 Rev 4.00
May 2, 2007
Page 19 of 19
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