EL5174ISZ-T [RENESAS]
LINE DRIVER;
| 型号： | EL5174ISZ-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | LINE DRIVER 驱动 接口集成电路 |
| 文件： | 总14页 (文件大小：492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
550MHz Differential Twisted-Pair Drivers
EL5174, EL5374
Features
The EL5174 and EL5374 are single and triple high bandwidth
amplifiers with an output in differential form. They are
primarily targeted for applications such as driving twisted-pair
lines in component video applications. The inputs can be in
either single-ended or differential form but the outputs are
always in differential form.
• Fully differential inputs, outputs, and feedback
• Differential input range ±2.3V
• 550MHz 3dB bandwidth
• 1100V/µs slew rate
• Low distortion at 5MHz
On the EL5174 and EL5374, two feedback inputs provide the
user with the ability to set the gain of each device (stable at
minimum gain of one). For a fixed gain of two, please see the
EL5173, EL5373 data sheet (FN7312).
• Single 5V or dual ±5V supplies
• 60mA maximum output current
• Low power - 12.5mA per channel
• Pb-free (RoHS compliant)
The output common mode level for each channel is set by the
associated REF pin, which has a -3dB bandwidth of over
110MHz. Generally, these pins are grounded but can be tied to
any voltage reference.
Applications
• Twisted-pair driver
All outputs are short circuit protected to withstand temporary
overload condition.
• Differential line driver
• VGA over twisted-pair
The EL5174 is available in a 8 Ld SOIC package and the EL5374 is
available in a 28 Ld QSOP package. All are specified for operation
over the full -40°C to +85°C temperature range.
• ADSL/HDSL driver
• Single-ended to differential amplification
• Transmission of analog signals in a noisy environment
Pinouts
EL5174
(8 LD SOIC)
TOP VIEW
EL5374
(28 LD QSOP)
TOP VIEW
FBP
IN+
1
2
3
4
8
7
6
5
OUT+
VS-
NC
INP1
INN1
1
2
3
28 OUT1
27 FBP1
26 FBN1
25 OUT1B
24 VSP
+
-
+
-
REF
FBN
VS+
OUT-
REF1 4
NC
INP2
INN2
REF2
NC
5
6
7
8
9
23 VSN
22 OUT2
21 FBP2
20 FBN2
19 OUT2B
18 OUT3
17 FBP3
16 FBN3
15 OUT3B
+
-
INP3 10
INN3 11
REF3 12
NC 13
+
-
EN 14
August 28, 2012
FN7313.8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2003-2005, 2007, 2010, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
EL5174, EL5374
Pin Descriptions
EL5174
EL5374
PIN NAME
PIN FUNCTION
Feedback from non-inverting output
Non-inverting input
1
2
3
4
5
6
7
8
FBP
IN+
REF
Inverting inputs, note that on EL5174, this pin is also the REF pin
Feedback from inverting output
Inverting output
FBN
OUT-
VS+
Positive supply
VS-
Negative supply
OUT+
Non-inverting output
17, 21, 27
2, 6, 10
3, 7, 11
16, 20, 26
15, 19, 25
24
FBP3, FBP2, FBP1
INP1, INP2, INP3
INN1, INN2, INN3
FBN3, FBN2, FBN1
OUT3B, OUT2B, OUT1B
VSP
Feedback from non-inverting outputs
Non-inverting inputs
Inverting inputs, note that on EL5174, this pin is also the REF pin
Feedback from inverting outputs
Inverting outputs
Positive supply
23
VSN
Negative supply
18, 22, 28
1, 5, 9, 13
4, 8, 12
14
OUT3, OUT2, OUT1
NC
Non-inverting outputs
No connect; grounded for best crosstalk performance
Reference inputs, sets common-mode output voltage
ENABLE
REF1, REF2, REF3
EN
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
EL5174ISZ
5174ISZ
EL5374IUZ
-40 to +85
-40 to +85
8 Ld SOIC
28 Ld QSOP
M8.15E
M28.15
EL5374IUZ
NOTE:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for EL5174, EL5374. For more information on MSL please see tech brief
TB363.
FN7313.8
August 28, 2012
2
EL5174, EL5374
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage (V + to V -) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Supply Voltage Rate-of-rise (dV/dT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Thermal Resistance (Typical, Note 4)
θ
(°C/W)
S
S
JA
120.40
77.61
8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 Ld QSOP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage (IN+, IN- to V +, V -) . . . . . . . . . . . . . V - - 0.3V to V + + 0.3V
S
S
S
S
Differential Input Voltage (IN+ to IN-). . . . . . . . . . . . . . . . . . . . . . . . . . ±4.8V
Maximum Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, T = +25°C, V = 0V, R = 1kΩ, R = 0, R = OPEN, C = 2.7pF, unless otherwise
S
S
A
IN
LD
F
G
LD
specified.
MIN
MAX
PARAMETER
AC PERFORMANCE
DESCRIPTION
CONDITIONS
(Note 5)
TYP
(Note 5)
UNIT
BW
-3dB Bandwidth
A = 1, C = 2.7pF
LD
550
130
20
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
V
A = 2, R = 500, C = 2.7pF
LD
V
F
A = 10, R = 500, C = 2.7pF
LD
V
F
BW
SR
±0.1dB Bandwidth
Slew Rate (EL5174)
Slew Rate (EL5374)
A = 1, C = 2.7pF
120
1100
850
10
V
LD
V
V
V
= 3V , 20% to 80%
800
600
OUT
OUT
OUT
P-P
= 3V , 20% to 80%
P-P
t
t
Settling Time to 0.1%
= 2V
P-P
STL
Output Overdrive Recovery Time
Gain Bandwidth Product
20
ns
OVR
GBWP
200
110
134
70
MHz
MHz
V/µs
V/µs
nV/√Hz
pA/√Hz
dBc
V
V
V
V
BW (-3dB)
SR+
V
V
V
-3dB Bandwidth
Slew Rate - Rise
Slew Rate - Fall
A = 1, C = 2.7pF
REF
REF
REF
N
REF
REF
REF
V
LD
V
= 2V , 20% to 80%
OUT
OUT
P-P
SR-
V
= 2V , 20% to 80%
P-P
Input Voltage Noise
at 10kHz
at 10kHz
21
I
Input Current Noise
2.7
N
HD2
Second Harmonic Distortion
V
V
V
V
= 2V , 5MHz
P-P
-95
OUT
OUT
OUT
OUT
= 2V , 20MHz
P-P
-94
dBc
HD3
Third Harmonic Distortion
= 2V , 5MHz
P-P
-88
dBc
= 2V , 20MHz
P-P
-87
dBc
dG
Differential Gain at 3.58MHz
Differential Phase at 3.58MHz
R
R
= 300Ω, A = 2
0.06
0.13
90
%
LD
LD
V
dθ
= 300Ω, A = 2
°
V
e
Channel Separation - for EL5374 only
INPUT CHARACTERISTICS
Input Referred Offset Voltage
at f = 1MHz
dB
S
V
(EL5174)
(EL5374)
±1.4
±2.2
-14
±25
±25
-7
mV
mV
µA
µA
kΩ
OS
I
I
Input Bias Current (V +, V -)
-30
0.5
IN
IN
IN
Input Bias Current (V
)
2.3
4
REF
REF
R
Differential Input Resistance
150
IN
FN7313.8
August 28, 2012
3
EL5174, EL5374
Electrical Specifications V + = +5V, V - = -5V, T = +25°C, V = 0V, R = 1kΩ, R = 0, R = OPEN, C = 2.7pF, unless otherwise
S
S
A
IN
LD
F
G
LD
specified. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 5)
TYP
1
(Note 5)
UNIT
pF
V
C
Differential Input Capacitance
Differential Mode Input Range
IN
DMIR
CMIR+
CMIR-
±2.1
3.4
±2.3
3.4
±2.5
Common Mode Positive Input Range at V +, V
IN
-
V
IN
Common Mode Negative Input Range at V +, V
IN
-
-4.3
3.7
V
IN
V
V
V
+
-
Positive Reference Input Voltage Range (EL5374)
Negative Reference Input Voltage Range (EL5374)
Output Offset Relative to V (EL5374)
V
V
+ = V - = 0V
IN
V
REFIN
REFIN
REFOS
IN
+ = V - = 0V
IN
-3.3
±50
78
-3
V
IN
±100
mV
dB
V
REF
CMRR
Gain
Input Common Mode Rejection Ratio (EL5374)
Gain Accuracy
V
V
V
= ±2.5V
65
IN
IN
IN
= 1V (EL5174)
= 1V (EL5374)
0.980
0.978
0.995
0.993
1.010
1.008
V
OUTPUT CHARACTERISTICS
V
Output Voltage Swing
R
R
R
= 500Ω to GND (EL5174)
= 500Ω to GND (EL5374)
±3.4
±3.8
±60
130
V
V
OUT
L
L
L
±3.6
±50
I
(Max)
Maximum Output Current
Output Impedance
= 10Ω, V + = ±3.2V
IN
±100
mA
mΩ
OUT
R
OUT
SUPPLY
V
Supply Operating Range
V + to V -
4.75
10
11
14
10
V
SUPPLY
S
S
I
I
I
Power Supply Current - Per Channel
Positive Power Supply Current - Disabled (EL5374)
Negative Power Supply Current - Disabled (EL5374)
Power Supply Rejection Ratio
12.5
1.7
mA
µA
µA
dB
S(ON)
+
-
EN pin tied to 4.8V
S(OFF)
-200
60
-120
75
S(OFF)
PSRR
ENABLE (EL5374 ONLY)
V from ±4.5V to ±5.5V
S
t
t
Enable Time
130
1.2
ns
µs
V
EN
DS
Disable Time
V
V
EN Pin Voltage for Power-Up
EN Pin Voltage for Shut-Down
EN Pin Input Current High
EN Pin Input Current Low
V + -1.5
S
IH
V + -0.5
S
V
IL
I
I
At V = 5V
EN
123
-8
150
µA
µA
IH-EN
IL-EN
At V = 0V
EN
-10
NOTE:
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN7313.8
August 28, 2012
4
Connection Diagrams
R
F1
C
L1
5pF
-5V
0Ω
OUT
FBP
INP
1
2
3
OUT 8
VSN 7
IN+
R
LD
1kΩ
R
G
REF
REF
VSP 6
R
R
S1
50Ω
S1
50Ω
OUTB
4 FBN
OUTB 5
C
R
L2
5pF
F2
+5V
0Ω
FIGURE 1. EL5174
+5V
R
1
2
NC
OUT1 28
FBP1 27
FBN1 26
OUT1B 25
VSP 24
R
F
INP1
INN1
REF1
INP1
INN1
REF1
NC
0Ω
R
LD1
1kΩ
G
R
F
3
0Ω
4
5
INP2
INN2
REF2
6
INP2
INN2
REF2
NC
VSN 23
7
OUT2 22
R
F
R
LD2
1kΩ
FBP2
FBN2
OUT2B
OUT3
FBP3
8
21
20
19
18
17
16
0Ω
R
G
R
F
9
INP3
INN3
REF3
0Ω
INP3
INN3
REF3
NC
10
11
12
13
R
F
0Ω
R
G
R
LD3
1kΩ
R
R
R
R
R
R
R
50Ω
R
R
R
F
SP1
50Ω
SN1
50Ω
SR1
50Ω
SP2
50Ω
SN2
50Ω
SR2
50Ω
SP3
SN3
50Ω
SR3
50Ω
FBN3
0Ω
14 EN
OUT3B 15
C
C
C
C
C
C
L1
5pF
L1B
5pF
L2
5pF
L2B
5pF
L3
5pF
L3B
5pF
-5V
ENABLE
FIGURE 2. EL5374
EL5174, EL5374
Typical Performance Curves
A
= 1, R = 1kΩ, C = 2.7pF
LD LD
R
= 1kΩ, C = 2.7pF
LD
V
LD
4
3
4
3
2
2
V
= 200mV
OP-P
1
1
A
= 1
V
0
0
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
A
= 2
V
V
= 1V
OP-P
A
= 5
V
A
= 10
V
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE
FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS GAIN
A
= 1, C = 2.7pF
LD
A
= 1, R = 1kΩ
V
V
LD
10
4
3
C
= 50pF
LD
8
6
C
= 23pF
LD
2
C
= 34pF
LD
R
= 1kΩ
LD
4
1
2
0
0
-1
-2
-3
-4
-5
-6
R
= 500Ω
C
= 9pF
LD
LD
-2
-4
-6
-8
-10
C
= 2.7pF
LD
R
= 200Ω
LD
1M
10M
100M
1G
1M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE vs C
FIGURE 6. FREQUENCY RESPONSE vs R
LD
LD
A
= 2, C = 2.7pF, R = 750Ω
LD
A
= 2, R = 1kΩ, C = 2.7pF
LD LD
V
F
V
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
R
= 1kΩ
F
R
= 1kΩ
LD
R
= 500Ω
R
= 500Ω
F
LD
R
= 200Ω
F
R
= 200Ω
LD
1M
10M
FREQUENCY (Hz)
100M
400M
1M
10M
FREQUENCY (Hz)
100M
400M
FIGURE 7. FREQUENCY RESPONSE
FIGURE 8. FREQUENCY RESPONSE vs R
LD
FN7313.8
August 28, 2012
6
EL5174, EL5374
Typical Performance Curves (Continued)
5
4
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
3
2
1
PSRR-
0
-1
-2
-3
-4
-5
PSRR+
10M
100k
1M
10M
100M
1M
FREQUENCY (Hz)
10k
100k
100M
FREQUENCY (Hz)
FIGURE 9. FREQUENCY RESPONSE - V
FIGURE 10. PSRR vs FREQUENCY
REF
1k
100
80
60
40
20
0
100
10
1
E
N
I
N
-20
10k
FREQUENCY (Hz)
10
100
1k
100k
1M
10M
1M
10M
1k
10k
100k
100M
1G
FREQUENCY (Hz)
FIGURE 12. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 11. CMRR vs FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100
10
CH1 <=> CH2, CH2 <=> CH3
1.0
0.1
CH1 <=> CH3
10M
100k
1M
100M
1G
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. CHANNEL ISOLATION (EL5374 ONLY)
FIGURE 14. OUTPUT IMPEDANCE vs FREQUENCY
FN7313.8
August 28, 2012
7
EL5174, EL5374
Typical Performance Curves (Continued)
V
= ±5V, A = 2, R = 1kΩ
LD
V
= ±5V, A = 1, R = 1kΩ
LD
S
V
S
V
-40
-50
-40
-50
-60
-70
-80
-90
HD3 (f = 5MHz)
-60
HD3 (f = 20MHz)
HD3 (f = 20MHz)
-70
-80
-90
HD2 (f = 5MHz)
HD2 (f = 20MHz)
4.5
5.0
HD2 (f = 5MHz)
-100
-100
1
2
3
4
5
6
7
8
9
10
1.0
1.5
2.0
2.5
V
3.0
3.5
(V)
4.0
V
(V)
OP-P, DM
OP-P, DM
FIGURE 15. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE
FIGURE 16. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE
V
= ±5V, A = 1, V
= 1V
OP-P, DM
S
V
V
= ±5V, A = 2, V
V
= 2V
S
OP-P, DM
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
HD3 (f = 20MHz)
HD3 (f = 5MHz)
HD2 (f =
20MHz)
HD2 (f = 5MHz)
200 300 400 500 600 700 800 900 1000
(Ω)
100 200 300 400 500 600 700 800 900 1000
(Ω)
R
R
LD
LD
FIGURE 17. HARMONIC DISTORTION vs R
FIGURE 18. HARMONIC DISTORTION vs R
LD
LD
V
V
= ±5V, R = 1kΩ, V
= 1V for A = 1,
OP-P, DM V
S
LD
= 2V for A = 2
OP-P, DM
V
-40
-50
HD3 (A = 2)
V
-60
-70
50mV/DIV
-80
-90
-100
0
10
20
30
40
50
60
10ns/DIV
FREQUENCY (MHz)
FIGURE 19. HARMONIC DISTORTION vs FREQUENCY
FIGURE 20. SMALL SIGNAL TRANSIENT RESPONSE
FN7313.8
August 28, 2012
8
EL5174, EL5374
Typical Performance Curves (Continued)
M = 400ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
CH1
CH2
0.5V/DIV
10ns/DIV
400ns/DIV
FIGURE 22. ENABLED RESPONSE
FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
M = 400ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
1.2
1.010W
1.0
0.8
0.6
0.4
0.2
0
QSOP28
= +99°C/W
θ
JA
625mW
CH1
SO8
= +160°C/W
θ
CH2
JA
0
25
50
75 85 100
125
150
400ns/DIV
AMBIENT TEMPERATURE (°C)
FIGURE 23. DISABLED RESPONSE
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.266W
QSOP28
θ
= +79°C/W
JA
909mW
SO8
= +110°C/W
θ
JA
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FN7313.8
August 28, 2012
9
EL5174, EL5374
Simplified Schematic
V +
S
R
R
3
4
R
R
2
1
R
R
7
8
IN+
IN-
FBP
FBN
V
B1
B2
OUT+
R
R
CD
CD
REF
10
R
R
9
V
OUT-
C
C
C
C
R
R
6
5
V -
S
differential mode signal. For the true balance differential
outputs, the REF pin must be tied to the same bias level as the
Description of Operation and
Application Information
Product Description
The EL5174 and EL5374 are wide bandwidth, low power and
single/differential ended to differential output amplifiers. The
EL5174 is a single channel differential amplifier. Since the I -
pin and REF pin are tied together internally, the EL5174 can be
used as a single-ended to differential converter. The EL5374 is
a triple channel differential amplifier. The EL5374 has a
I + pin. For a ±5V supply, just tie the REF pin to GND if the I +
N
N
pin is biased at 0V with a 50Ω or 75Ω termination resistor. For
a single supply application, if the I + is biased to half of the
N
rail, the REF pin should be biased to half of the rail also.
The gain setting for EL5174 is expressed in Equation 1:
N
R
+ R
⎛
⎞
⎟
⎠
F1
F2
----------------------------
V
= V + × 1 +
⎜
ODM
IN
R
G
⎝
(EQ. 1)
2R
⎛
⎞
⎟
⎠
separate I - pin and REF pin for each channel. It can be used
F
N
----------
V
V
= V + = 1 +
⎜
ODM
OCM
IN
R
G
as single/differential ended to differential converter. The
EL5174 and EL5374 are internally compensated for closed
loop gain of +1 of greater. Connected in a gain of 1 and driving
a 1kΩ differential load, the EL5174 and EL5374 have a -3dB
bandwidth of 550MHz. Driving a 200Ω differential load at gain
of 2, the bandwidth is about 130MHz. The EL5374 is available
with a power-down feature to reduce the power while the
amplifier is disabled.
⎝
= V
= 0V
REF
Where:
V
= 0V
REF
= R = R
F
R
F1
F2
The EL5374 has a separate I - pin and REF pin. It can be used
N
Input, Output and Supply Voltage Range
as a single/differential ended to differential converter. The
voltage applied at REF pin can set the output common mode
voltage and the gain is one.
The EL5174 and EL5374 have been designed to operate with a
single supply voltage of 5V to 10V or split supplies with its total
voltage from 5V to 10V. The amplifiers have an input common
mode voltage range from -4.3V to 3.4V for ±5V supply. The
differential mode input range (DMIR) between the two inputs
is from -2.3V to +2.3V. The input voltage range at the REF pin is
from -3.3V to 3.7V. If the input common mode or differential
mode signal is outside the above-specified ranges, it will cause
the output signal to become distorted.
The gain setting for EL5374 is expressed in Equation 2:
R
+ R
⎛
⎞
⎟
⎠
F1
F2
----------------------------
V
= (V + – V -) × 1 +
⎜
ODM
IN
IN
R
G
⎝
(EQ. 2)
2R
⎛
⎞
⎟
⎠
F
----------
V
V
= (V + – V -) × 1 +
⎜
ODM
OCM
IN
IN
R
G
⎝
The output of the EL5174 and EL5374 can swing from -3.8V to
+3.8V at 1kΩ differential load at ±5V supply. As the load
resistance becomes lower, the output swing is reduced.
= V
REF
Where:
= R = R
F
R
F1
F2
Differential and Common Mode Gain
Settings
For EL5174, since the I - pin and REF pin are bound together
N
as the REF pin in an 8 Ld package, the signal at the REF pin is
part of the common mode signal and also part of the
FN7313.8
August 28, 2012
10
EL5174, EL5374
resistor. Again, a small series resistor at the output can help to
reduce peaking.
R
F1
Disable/Power-Down (for EL5374 only)
FBP
The EL5374 can be disabled and its outputs placed in a high
impedance state. The turn-off time is about 1.2µs and the
turn-on time is about 130ns. When disabled, the amplifier's
V
+
V
V
+
-
IN
O
O
I +
N
R
G
V
-
IN
I -
N
supply current is reduced to 1.7µA for I + and 120µA for I -
S
S
V
REF
FBN
REF
typically, thereby effectively eliminating the power
consumption. The amplifier's power-down can be controlled by
standard CMOS signal levels at the EN pin. The applied logic
R
F2
signal is relative to the V + pin. Letting the EN pin float or
S
FIGURE 26.
applying a signal that is less than 1.5V below V + will enable
S
the amplifier. The amplifier will be disabled when the signal at
Choice of Feedback Resistor and Gain
Bandwidth Product
For applications that require a gain of +1, no feedback resistor
is required. Just short the OUT+ pin to FBP pin and OUT- pin to
FBN pin. For gains greater than +1, the feedback resistor
forms a pole with the parasitic capacitance at the inverting
input. As this pole becomes smaller, the amplifier's phase
margin is reduced. This causes ringing in the time domain and
the EN pin is above V + - 0.5V.
S
Output Drive Capability
The EL5174 and EL5374 have internal short circuit protection. Its
typical short circuit current is ±60mA. If the output is shorted
indefinitely, the power dissipation could easily increase such that
the part will be destroyed. Maximum reliability is maintained if
the output current never exceeds ±60mA. This limit is set by the
design of the internal metal interconnections.
peaking in the frequency domain. Therefore, R has some
F
maximum value that should not be exceeded for optimum
performance. If a large value of R must be used, a small
capacitor in the few Pico farad range in parallel with R can
F
Power Dissipation
F
With the high output drive capability of the EL5174 and EL5374,
it is possible to exceed the +135°C absolute maximum junction
temperature under certain load current conditions. Therefore, it
is important to calculate the maximum junction temperature for
the application to determine if the load conditions or package
types need to be modified for the amplifier to remain in the safe
operating area.
help to reduce the ringing and peaking at the expense of
reducing the bandwidth.
The bandwidth of the EL5174 and EL5374 depends on the load
and the feedback network. R and R appear in parallel with
F
G
the load for gains other than +1. As this combination gets
smaller, the bandwidth falls off. Consequently, R also has a
F
minimum value that should not be exceeded for optimum
The maximum power dissipation allowed in a package is
determined according to Equation 4:
bandwidth performance. For gain of +1, R = 0 is optimum. For
F
the gains other than +1, optimum response is obtained with R
between 500Ω to 1kΩ.
F
T
– T
AMAX
JMAX
(EQ. 4)
--------------------------------------------
PD
=
MAX
Θ
JA
The EL5174 and EL5374 have a gain bandwidth product of
Where:
200MHz for R = 1kΩ. For gains ≥5, its bandwidth can be
LD
predicted by Equation 3:
T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
(EQ. 3)
Gain × BW = 200MHz
T
AMAX
Driving Capacitive Loads and Cables
θ
= Thermal resistance of the package
JA
The EL5174 and EL5374 can drive a 23pF differential
The maximum power dissipation actually produced by an IC is
the total quiescent supply current times the total power supply
voltage, plus the power in the IC due to the load, or as
expressed in Equation 5:
capacitor in parallel with 1kΩ differential load with less than
5dB of peaking at gain of +1. If less peaking is desired in
applications, a small series resistor (usually between 5Ω to
50Ω) can be placed in series with each output to eliminate
most peaking. However, this will reduce the gain slightly. If the
ΔV
⎛
⎞
⎟
⎠
O
(EQ. 5)
-----------
LD
PD = i × V
× I
+ (V
– ΔV ) ×
⎜
STOT
SMAX
STOT
O
R
⎝
gain setting is greater than 1, the gain resistor R can then be
G
chosen to make up for any gain loss, which may be created by
the additional series resistor at the output.
Where:
V
= Total supply voltage = V + - V -
S S
STOT
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
I
= Maximum quiescent supply current per channel
SMAX
ΔV = Maximum differential output voltage of the
application
O
R
= Differential load resistance
LD
FN7313.8
August 28, 2012
11
EL5174, EL5374
I
= Load current
For good AC performance, parasitic capacitance should be
LOAD
i = Number of channels
By setting the two PD
kept to a minimum. Use of wire-wound resistors should be
avoided because of their additional series inductance. Use of
sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the inverting
input pin. Strip line design techniques are recommended for
the signal traces.
equations equal to each other, we
MAX
can solve the output current and R to avoid the device
overheat.
LD
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit board
layout is necessary for optimum performance. Lead lengths
should be as short as possible. The power supply pin must be well
bypassed to reduce the risk of oscillation. For normal single
Typical Applications
As the signal is transmitted through a cable, the high frequency
signal will be attenuated. One way to compensate this loss is to
boost the high frequency gain at the receiver side.
supply operation, where the V - pin is connected to the ground
S
plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF
ceramic capacitor from V + to GND will suffice. This same
S
capacitor combination should be placed at each supply pin to
ground if split supplies are to be used. In this case, the V - pin
S
becomes the negative supply rail.
R
F
FBP
IN+
IN-
50
50
TWISTED PAIR
IN+
R
R
G
T
EL5174/
EL5374
EL5175/
EL5375
V
O
REF
IN-
Z
= 100Ω
O
FBN
REF
R
F
R
FR
R
GR
FIGURE 27. TWISTED PAIR CABLE RECEIVER
R
F
GAIN
(dB)
FBP
I +
V
V
+
-
O
N
R
T
R
R
G
GC
75
I -
N
C
REF
FBN
L
O
f
f
H
FREQUENCY
R
L
F
2R
1
F
------------------------
≅
f
f
----------
DC Gain = 1 +
L
2πR
C
C
R
G
G
1
2R
----------------------------
≅
F
H
2πR
C
C
--------------------------
G
(HF)Gain = 1 +
GC
||
R
R
GC
FIGURE 28. TRANSMIT EQUALIZER
FN7313.8
August 28, 2012
12
EL5174, EL5374
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN7313.8
August 28, 2012
13
EL5174, EL5374
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
N
M28.15
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
INDEX
AREA
0.25(0.010)
M
B M
H
E
GAUGE
PLANE
INCHES
MIN
MILLIMETERS
-B-
SYMBOL
MAX
0.069
0.010
0.061
0.012
0.010
0.394
0.157
MIN
1.35
0.10
-
MAX
1.75
0.25
1.54
0.30
0.25
10.00
3.98
NOTES
A
A1
A2
B
0.053
0.004
-
-
1
2
3
-
L
0.25
0.010
SEATING PLANE
A
-
-A-
0.008
0.007
0.386
0.150
0.20
0.18
9.81
3.81
9
D
h x 45°
C
-
-C-
D
E
3
α
4
A2
e
A1
C
e
0.025 BSC
0.635 BSC
-
B
0.10(0.004)
H
0.228
0.0099
0.016
0.244
0.0196
0.050
5.80
0.26
0.41
6.19
0.49
1.27
-
0.17(0.007) M
C
A M B S
h
5
L
6
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
N
α
28
28
7
0°
8°
0°
8°
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Rev. 1 6/04
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimen-
sion at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
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without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
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FN7313.8
August 28, 2012
14
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