EL5421TIYZ [RENESAS]
12MHz Rail-to-Rail Input-Output Buffer; MSOP10; Temp Range: -40° to 85°C;
| 型号： | EL5421TIYZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 12MHz Rail-to-Rail Input-Output Buffer; MSOP10; Temp Range: -40° to 85°C 放大器 光电二极管 |
| 文件： | 总13页 (文件大小：673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
EL5421T
12MHz Rail-to-Rail Input-Output Buffer
FN6922
Rev 0.00
September 25, 2009
The EL5421T is a high voltage rail-to-rail input-output buffer
with low power consumption. The EL5421T contains four
buffers. Each buffer exhibits beyond the rail input capability,
rail-to-rail output capability and is unity gain stable.
Features
• 12MHz -3dB bandwidth
• 4 Unity Gain Buffers
The maximum operating voltage range is from 4.5V to 19V. It
can be configured for single or dual supply operation, and
typically consumes only 500µA per buffer. The EL5421T has
an output short circuit capability of ±200mA and a
• 4.5V to 19V Maximum Supply Voltage Range
• 12V/µs Slew Rate
• 500µA Supply Current (per buffer)
• ±70mA Continuous Output Current
• ±200mA Output Short Circuit Current
• Unity-gain Stable
continuous output current capability of ±70mA.
The EL5421T features a slew rate of 12V/µs. Also, the
device provides common mode input capability beyond the
supply rails, rail-to-rail output capability, and a bandwidth of
12MHz (-3dB). This enables the buffers to offer maximum
dynamic range at any supply voltage. These features make
the EL5421T an ideal buffer solution for use in TFT-LCD
• Beyond the Rails Input Capability
• Rail-to-rail Output Swing
• Built-in Thermal Protection
panels as a V
or static gamma buffer, and in high speed
COM
filtering and signal conditioning applications. Other
applications include battery power and portable devices,
especially where low power consumption is important.
• -40°C to +85°C Ambient Temperature Range
• Pb-free (RoHS compliant)
The EL5421T is available in a space saving 10 Ld MSOP
package and operates over an ambient temperature range
of -40°C to +85°C.
Applications
• TFT-LCD Panels
• V
COM
Buffers
Ordering Information
• Electronics Notebooks
• Electronics Games
PART
NUMBER
(Note)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
• Personal Communication Devices
• Personal Digital Assistants (PDA)
• Portable Instrumentation
• Wireless LANs
EL5421TIYZ*
BBBLA
10 Ld MSOP
M10.118A
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• Office Automation
• Active Filters
• ADC/DAC Buffers
Pinout
EL5421T
(10 LD MSOP)
TOP VIEW
VOUTA
VINA
1
2
3
4
5
10 VOUTD
9
8
7
6
VIND
VS-
VS+
VINB
VINC
VOUTC
VOUTB
FN6922 Rev 0.00
Page 1 of 13
September 25, 2009
EL5421T
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . +19.8V
Thermal Resistance Junction-to-Ambient (Typical)
10 Ld MSOP (Note 1). . . . . . . . . . . . . . . . . . . . . . . .
JA
(°C/W)
160
S
S
Input Voltage Range (V ) . . . . . . . . . . . .(V -)-0.5V to (V +)+0.5V
INx
S
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . ±70mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3000V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . .See Figure 27 and 28
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications V + = +5V, V - = -5V, R = 10k to 0V, T = +25°C unless otherwise specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
13
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
V
= 0V
= 0V
3
4
2
1
2
mV
µV/°C
nA
OS
CM
CM
TCV
Average Offset Voltage Drift (Note 2)
Input Bias Current
OS
I
50
B
R
Input Impedance
G
IN
IN
C
Input Capacitance
pF
A
Voltage Gain
-4.5V V
OUTx
4.5V
0.992
4.85
1.008
-4.85
V/V
V
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -5mA
-4.94
4.94
V
V
OL
L
I = +5mA
OH
L
I
V
= 0V, Source: V
short to V -,
±200
mA
SC
CM
Sink: V
OUTx
short to V +
S
OUTx
S
I
Output Current
±70
mA
OUT
POWER SUPPLY PERFORMANCE
(V +) - (V -)
Supply Voltage Range
4.5
60
19
V
S
S
I
Supply Current (Per Buffer)
Power Supply Rejection Ratio
V
= 0V, No load
500
75
750
µA
dB
S
CM
PSRR
Supply is moved from ±2.25V to ±9.5V
DYNAMIC PERFORMANCE
SR Slew Rate (Note 3)
-4.0V V
OUTx
4.0V, 20% to 80%
= 2V step,
12
V/µs
ns
t
Settling to +0.1% (Note 4)
A
= +1, V
500
S
V
OUTx
R = 10k, C = 8pF
L
L
BW
CS
-3dB Bandwidth
R = 10k, C = 8pF
12
75
MHz
dB
L
L
Channel Separation
f = 5MHz
Electrical Specifications V + = +5V, V - = 0V, R = 10k to 2.5V, T = +25°C unless otherwise specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
13
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
V
= 2.5V
= 2.5V
3
4
2
mV
µV/°C
nA
OS
CM
CM
TCV
Average Offset Voltage Drift (Note 2)
Input Bias Current
OS
I
50
B
FN6922 Rev 0.00
Page 2 of 13
September 25, 2009
EL5421T
Electrical Specifications V + = +5V, V - = 0V, R = 10k to 2.5V, T = +25°C unless otherwise specified. (Continued)
S
S
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
0.992
4.85
TYP
1
MAX
UNIT
GW
pF
R
Input Impedance
IN
C
Input Capacitance
Voltage Gain
2
IN
A
0.5 V
4.5V
OUTx
1.008
150
V/V
V
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -2.5mA
30
mV
V
OL
L
I = +2.5mA
4.97
±125
OH
L
I
V
= 0V, Source: V
short to V -,
mA
SC
CM
Sink: V
OUTx
short to V +
S
OUTx
S
I
Output Current
±70
mA
OUT
POWER SUPPLY PERFORMANCE
(V +) - (V -)
Supply Voltage Range
4.5
60
19
V
S
S
I
Supply Current (Per Buffer)
Power Supply Rejection Ratio
V
= 2.5V, No load
500
75
750
µA
dB
S
CM
PSRR
Supply is moved from 4.5V to 19V
DYNAMIC PERFORMANCE
SR Slew Rate (Note 3)
1V V
4V, 20% to 80%
12
V/µs
ns
OUTx
t
Settling to +0.1% (Note 4)
A
= +1, V
= 2V step,
500
S
V
OUTx
R = 10k, C = 8pF
L
L
BW
CS
-3dB Bandwidth
R = 10k, C = 8pF
12
75
MHz
dB
L
L
Channel Separation
f = 5MHz
Electrical Specifications V + = +18V, V - = 0V, R = 10k to 9V, T = +25°C unless otherwise specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
15
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
= 9V
= 9V
4
5
2
1
2
mV
µV/°C
nA
OS
CM
CM
TCV
Average Offset Voltage Drift (Note 2)
Input Bias Current
OS
I
V
50
B
R
C
Input Impedance
G
IN
IN
Input Capacitance
pF
A
Voltage Gain
0.5 V
17.5V
OUTx
0.992
17.85
1.008
150
V/V
V
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -9mA
100
17.90
±200
mV
V
OL
L
I = +9mA
OH
L
I
V
= 9V, Source: V
short to V -,
mA
SC
CM
Sink: V
OUTx
short to V +
S
OUTx
S
I
Output Current
±70
mA
OUT
POWER SUPPLY PERFORMANCE
(V +) - (V -)
Supply Voltage Range
4.5
60
19
V
S
S
I
Supply Current (Per Buffer)
Power Supply Rejection Ratio
V
= 9V, No load
550
75
750
µA
dB
S
CM
PSRR
Supply is moved from 4.5V to 19V
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 3)
1V V
14V, 20% to 80%
12
V/µs
OUTx
FN6922 Rev 0.00
Page 3 of 13
September 25, 2009
EL5421T
Electrical Specifications V + = +18V, V - = 0V, R = 10k to 9V, T = +25°C unless otherwise specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
t
Settling to +0.1% (Note 4)
A
= +1, V = 2V step,
OUTx
500
ns
S
V
R = 10k, C = 8pF
L
L
BW
-3dB Bandwidth
R = 10k, C = 8pF
12
75
MHz
dB
L
L
CS
Channel Separation
f = 5MHz
NOTES:
2. Measured over -40°C to +85°C ambient operating temperature range. See the typical TCV
“Typical Performance Curves” on page 5
production distribution shown in the
OS
3. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges of the output signal.
4. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output level settles within
a ±0.1% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*0.1%]
FN6922 Rev 0.00
Page 4 of 13
September 25, 2009
EL5421T
Typical Performance Curves
28
24
20
16
12
8
2200
VS = ±5V
TA = +25°C
TYPICAL
PRODUCTION
DISTRIBUTION
TYPICAL
PRODUCTION
DISTRIBUTION
V
= ±5V
2000
S
-40°C TO +85°C
1800
1600
1400
1200
1000
800
600
400
200
0
4
0
1
3
5
7
9
11
13
15
-8 -7 -6 -5 -4 -3 -2 -1
0 1 2 3 4 5 6 7 8
INPUT OFFSET VOLTAGE DRIFT (|µV|/°C)
INPUT OFFSET VOLTAGE (mV)
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
2
1
10
V
= ±5V
S
V
= ±5V
S
5
0
0
-1
-2
-5
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
-4.91
4.95
V
OUT
= ±5V
S
V
= ±5V
= 5mA
S
I
= -5mA
I
OUT
-4.92
-4.93
-4.94
-4.95
-4.96
4.93
4.91
4.89
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
FIGURE 5. OUTPUT HIGH VOLTGE vs TEMPERATURE
FN6922 Rev 0.00
Page 5 of 13
September 25, 2009
EL5421T
Typical Performance Curves (Continued)
1.0018
14
13
12
11
VS = ±5V
RL = 10k
VS = ±5V
RL = 10k
1.0016
1.0014
1.0012
1.0010
1.0008
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 8. SLEW RATE vs TEMPERATURE
FIGURE 7. VOLTAGE GAIN vs TEMPERATURE
550
525
500
475
450
650
600
550
500
450
400
350
T
= +25°C
A
V
= ±5V
S
NO LOAD
INPUTS AT GND
2
4
6
8
10
-50
0
50
TEMPERATURE (°C)
100
150
SUPPLY VOLTAGE (±V)
FIGURE 10. SUPPLY CURRENT PER CHANNEL vs SUPPLY
VOLTAGE
FIGURE 9. SUPPLY CURRENT PER CHANNEL vs
TEMPERATURE
20
5
T
A
R
C
= +25°C
= 1
= 10k
= 8pF
A
V
L
L
10k
16
12
8
0
1k
560
-5
150
V
V
C
= ±5V
= 1
= 8pF
S
-10
-15
A
L
4
100k
1M
10M
100M
2
4
6
8
10
SUPPLY VOLTAGE (±V)
FREQUENCY (Hz)
FIGURE 11. SLEW RATE vs SUPPLY VOLTAGE
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS R
L
FN6922 Rev 0.00
September 25, 2009
Page 6 of 13
EL5421T
Typical Performance Curves (Continued)
20
200
160
120
80
V
= ±5V
= 1
= OPEN
100pF
S
A
V
10
R
V
L
= +13dBm
OUTx
0
-10
-20
-30
50pF
8pF
1000pF
1M
V
= ±5V
= 1
= 10k
S
40
A
V
R
L
0
100k
10M
100M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
FIGURE 14. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS C
L
0
12
10
8
V
A
= ±5V
= +25°C
S
-10
-20
-30
-40
-50
-60
-70
-80
T
6
V
= ±5V
= +25°C
= 1
= 10k
= 8pF
S
T
A
4
2
0
A
V
PSRR+
PSRR-
R
C
L
L
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. MAXIMUM OUTPUT SWING vs FREQUENCY
FIGURE 16. PSRR vs FREQUENCY
1000
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
V
= ±5V
T
A
= +25°C
S
R
= 10k
= 1
L
A
V
V
= 1.4V
IN
RMS
100
10
1
100
1k
10k
100k
1M
10M
100M
100
1k
10k
FREQUENCY (Hz)
100k
FREQUENCY (Hz)
FIGURE 18. TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY
FIGURE 17. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
FN6922 Rev 0.00
Page 7 of 13
September 25, 2009
EL5421T
Typical Performance Curves (Continued)
-60
100
80
60
40
20
0
MEASURED CH A TO D, OR B TO C
OTHER COMBINATIONS YIELD
IMPROVED REJECTION
-70
V
= ±5V
= 1
S
-80
-90
A
V
V
= 0dBm
INx
V
= ±5V
= +25°C
= 1
S
T
A
A
V
R
= 10k
L
V
= ±50mV
INx
-100
10
100
LOAD CAPACITANCE (pF)
1000
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 20. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
FIGURE 19. CHANNEL SEPARATION vs FREQUENCY
RESPONSE
V
T
A
= ±5V
= +25°C
= 1
V
S
A
5
V
T
= ±5V
= +25°C
= 1
= 10k
= 8pF
S
A
4
3
R = 10k
C
L
L
A
=8pF
V
R
C
0.1%
0.1%
L
L
2
1
0
-1
-2
-3
-4
-5
6V STEP
1µs/DIV
100
200
300
400
500
600
700
SETTLING TIME (ns)
FIGURE 22. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 21. STEP SIZE vs SETTLING TIME
V
= ±5V
= +25°C
= 1
S
T
A
A
V
R = 10k
L
L
C
=8pF
200ns/DIV
100mV STEP
FIGURE 23. SMALL SIGNAL TRANSIENT RESPONSE
FN6922 Rev 0.00
Page 8 of 13
September 25, 2009
EL5421T
Typical Performance Curves (Continued)
EL5421T
(10LD MSOP shown)
1
2
10
VOUTA
VOUTD
VOUTA
VOUTD
VIND+
RLA
RLD
CLA
CLD
9
VINA
Vs+
VIND
Vs-
VINA+
49.9
49.9
8
3
4
VS+
VS-
+
+
4.7µF
4.7µF
0.1µF
0.1µF
7
6
VINB+
VINB
VINC
VINC+
49.9
49.9
5
VOUTB
VOUTC
VOUTB
VOUTC
RLB
RLC
CLB
CLC
FIGURE 24. BASIC TEST CIRCUIT
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
EQUIVALENT CIRCUIT
1
2
VOUTA
VINA
Buffer A Output
Buffer A Input
(Reference Circuit 1)
(Reference Circuit 2)
3
VS+
Positive Power Supply
Buffer B Input
4
VINB
(Reference Circuit 2)
(Reference Circuit 1)
(Reference Circuit 1)
(Reference Circuit 2)
5
VOUTB
VOUTC
VINC
Buffer B Output
Buffer C Output
Buffer C Input
6
7
8
VS-
Negative Power Supply
Buffer D Input
9
VIND
(Reference Circuit 1)
(Reference Circuit 2)
10
VOUTD
Buffer D Output
V
S+
V
V
S+
V
OUTx
V
INx
S-
GND
V
S-
CIRCUIT 1
CIRCUIT 2
FN6922 Rev 0.00
Page 9 of 13
September 25, 2009
EL5421T
Applications Information
V
= ±2.5V, T = +25°C, V
= 6V
R = 10kto GND
L
S
A
INx
P-P,
Product Description
The EL5421T is a high voltage rail-to-rail input-output buffer
with low power consumption. The EL5421T contains four
buffers. Each buffer exhibits beyond the rail input capability,
rail-to-rail output capability and is unity gain stable.
OUTPUT
The EL5421T features a slew rate of 12V/µs. Also, the
device provides common mode input capability beyond the
supply rails, rail-to-rail output capability, and a bandwidth of
12MHz (-3dB). This enables the buffers to offer maximum
dynamic range at any supply voltage.
INPUT
100µs/DIV
Operating Voltage, Input and Output Capability
FIGURE 25. OPERATION WITH BEYOND-THE-RAILS INPUT
The EL5421T can operate on a single supply or dual supply
configuration. The EL5421T operating voltage ranges from a
minimum of 4.5V to a maximum of 19V. This range allows for
a standard 5V (or ±2.5V) supply voltage to dip to -10%, or a
standard 18V (or ±9V) to rise by +5.5% without affecting
performance or reliability.
V
= ±5V, T = +25°C, V
= 10V R = 10kto GND
P-P, L
S
A
INx
The input common-mode voltage range of the EL5421T
extends 500mV beyond the supply rails. Also, the EL5421T
is immune to phase reversal. However, if the common mode
input voltage exceeds the supply voltage by more than 0.5V,
electrostatic protection diodes in the input stage of the
device begin to conduct. Even though phase reversal will not
occur, to maintain optimal reliability it is suggested to avoid
input overvoltage conditions. Figure 25 shows the input
voltage driven 500mV beyond the supply rails and the device
output swinging between the supply rails.
100µs/DIV
FIGURE 26. OPERATION WITH RAIL-TO-RAIL INPUT AND
Output Current
The EL5421T is capable of output short circuit currents of
200mA (source and sink), and the device has built-in
protection circuitry which limits the short circuit current to
±200mA (typical).
The EL5421T output typically swings to within 50mV of
positive and negative supply rails with load currents of
±5mA. Decreasing load currents will extend the output
voltage range even closer to the supply rails. Figure 26
shows the input and output waveforms for the device in a
unity-gain configuration. Operation is from ±5V supply with a
To maintain maximum reliability the continuous output
current should never exceed ±70mA. This ±70mA limit is
determined by the characteristics of the internal metal
interconnects. Also, see “Power Dissipation” on page 11 for
detailed information on ensuring proper device operation
and reliability for temperature and load conditions.
10k load connected to GND. The input is a 10V
P-P
sinusoid and the output voltage is approximately 9.9V
.
P-P
Refer to the “Electrical Specifications” Table beginning on
page 2 for specific device parameters. Parameter variations
with operating voltage, loading and/or temperature are
shown in the “Typical Performance Curves” on page 5.
Unused Buffers
It is recommended that any unused buffers have their inputs
tied to the ground plane.
Driving Capacitive Loads
As load capacitance increases, the -3dB bandwidth will
decrease and peaking can occur. Depending on the
application, it may be necessary to reduce peaking and to
improve device stability. To improve device stability a
snubber circuit or a series resistor may be added to the
output of the EL5421T.
A snubber is a shunt load consisting of a resistor in series
with a capacitor. An optimized snubber can improve the
FN6922 Rev 0.00
Page 10 of 13
September 25, 2009
EL5421T
phase margin and the stability of the EL5421T. The advantage
of a snubber circuit is that it does not draw any DC load current
or reduce the gain.
Where:
• i = 1 to 4
(1, 2, 3, 4 corresponds to Channel A, B, C, D respectively)
• V = Total supply voltage (V + - V -)
Another method to reduce peaking is to add a series output
resistor (typically between 1 to 10). Depending on the
capacitive loading, a small value resistor may be the most
appropriate choice to minimize any reduction in gain.
S
S
S
• V + = Positive supply voltage
S
• V - = Negative supply voltage
S
Power Dissipation
• I
= Maximum supply current per buffer
= EL5421T quiescent current ÷ 4)
SMAX
With the high-output drive capability of the EL5421T buffers, it
is possible to exceed the +150°C absolute maximum junction
temperature under certain load current conditions. It is
important to calculate the maximum power dissipation of the
EL5421T in the application. Proper load conditions will ensure
that the EL5421T junction temperature stays within a safe
operating region.
(I
SMAX
• V
= Output voltage
= Load current
OUT
• I
LOAD
Device overheating can be avoided by calculating the minimum
resistive load condition, R , resulting in the highest power
LOAD
dissipation. To find R
to each other and solve for V
package power dissipation curves, Figures 27 and 28, for further
information.
set the two P
equations equal
LOAD
DMAX
. Reference the
The maximum power dissipation allowed in a package is
determined according to Equation 1:
/I
OUT LOAD
T
– T
AMAX
JMAX
(EQ. 1)
--------------------------------------------
P
=
DMAX
JA
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
8
where:
• T
7
625mW
MSOP10
6
= Maximum junction temperature
= Maximum ambient temperature
= +200°C/W
JMAX
AMAX
JA
5
4
3
2
1
0
• T
• = Thermal resistance of the package
JA
• P
DMAX
= Maximum power dissipation allowed
The total power dissipation produced by an IC is the total
quiescent supply current times the total power supply voltage,
plus the power dissipation in the IC due to the loads, or:
85
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
(EQ. 2)
P
= iV I
+ V + – V
i I
i
LOAD
DMAX
S
SMAX
S
OUT
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
when sourcing, and:
1.0
0.9
(EQ. 3)
781mW
P
= iV I
+ V
i – V - I
i
LOAD
DMAX
S
SMAX
OUT
S
0.8
MSOP10
JA
= +160°C/W
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
when sinking.
85
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6922 Rev 0.00
Page 11 of 13
September 25, 2009
EL5421T
performance. Ground plane construction is highly
recommended, trace lengths should be as short as possible
and the power supply pins must be well bypassed to reduce
any risk of oscillation.
Thermal Shutdown
The EL5421T has a built-in thermal protection which
ensures safe operation and prevents internal damage to the
device due to overheating. When the die temperature
reaches +165°C (typical) the device automatically shuts OFF
the outputs by putting them in a high impedance state. When
the die cools by +15°C (typical) the device automatically
turns ON the outputs by putting them in a low impedance or
(normal) operating state.
For normal single supply operation (the V - pin is connected
S
to ground) a 4.7µF capacitor should be placed from V + to
S
ground, then a parallel 0.1µF capacitor should be connected
as close to the device as possible. One 4.7µF capacitor may
be used for multiple devices. For dual supply operation the
same capacitor combination should be placed at each
supply pin to ground.
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5421T can provide gain at high frequency, so good
printed circuit board layout is necessary for optimum
Revision History
DATE
REVISION
CHANGE
9/10/09
FN6922.0
Issued File Number FN6922. Initial release of Datasheet with file number FN6922 making this
a Rev 0.
© Copyright Intersil Americas LLC 2009 All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6922 Rev 0.00
Page 12 of 13
September 25, 2009
EL5421T
Package Outline Drawing
M10.118A (JEDEC MO-187-BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
A
3.0 ± 0.1
DETAIL "X"
0.25 CAB
10
1.10 Max
0.18 ± 0.05
SIDE VIEW 2
B
PIN# 1 ID
1
2
0.95 BSC
0.5 BSC
TOP VIEW
Gauge
Plane
0.86 ± 0.09
0.25
H
C
3°±3°
SEATING PLANE
0.55 ± 0.15
DETAIL "X"
0.10 ± 0.05
0.10 C
0.23 +0.07/ -0.08
0.08 CAB
SIDE VIEW 1
5.80
4.40
3.00
NOTES:
1. Dimensions are in millimeters.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
0.50
4. Plastic interlead protrusions of 0.25mm max per side are not
included.
0.30
1.40
5. Dimensions “D” and “E1” are measured at Datum Plane “H”.
6. This replaces existing drawing # MDP0043 MSOP10L.
TYPICAL RECOMMENDED LAND PATTERN
FN6922 Rev 0.00
September 25, 2009
Page 13 of 13
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