EL5424CL-T13 [RENESAS]
13 BUFFER AMPLIFIER, PQCC32, 0.90 MM HEIGHT, EXPOSED PAD, PLASTIC, MO-220, LPP-32;
| 型号： | EL5424CL-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 13 BUFFER AMPLIFIER, PQCC32, 0.90 MM HEIGHT, EXPOSED PAD, PLASTIC, MO-220, LPP-32 放大器 |
| 文件： | 总12页 (文件大小：632K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5224, EL5324, EL5424
®
Data Sheet
November 7, 2002
FN7004
12MHz Rail-to-Rail Buffers + 100mA V
Amplifier
Features
COM
• 8, 10, and 12 channel versions
• 12MHz -3dB buffer bandwidth
The EL5224, EL5324, and EL5424
feature 8, 10, and 12 low power
• 150mA V
buffer
• Supply voltage from 4.5V to 18V
buffers, respectively, and one high
power output amplifier. They are designed primarily for
buffering column driver reference voltages in TFT-LCD
COM
• Low supply current - 6mA total (8-channel version)
• Rail-to-rail input/output swing (buffers only)
• LPP package - just 0.9mm high
applications as well as generation of the V
supply. Each
COM
low power buffer features a -3dB bandwidth of 12MHz and
features rail-to-rail input/output capability. The high power
buffer can drive 100mA and swings to within 2V of each rail.
Applications
The 8-channel EL5224 is available in 24-pin LPP and 24-pin
HTSSOP packages, the 10-channel EL5324 is available in
32-pin LPP and 28-pin HTSSOP packages, and the 12-
channel EL5434 is available in the 32-pin LPP package.
They are specified for operation over the full -40°C to +85°C
temperature range.
• TFT-LCD column driver buffering and V
• Electronics notebooks
• Computer monitors
supply
COM
• Electronics games
Ordering Information
• Touch-screen displays
• Portable instrumentation
TAPE &
REEL
PART NUMBER
EL5224CL-T7
EL5224CL-T13
EL5224CRE
PACKAGE
24-Pin LPP
PKG. NO.
MDP0046
MDP0046
MDP0048
MDP0048
MDP0046
MDP0046
MDP0048
MDP0048
MDP0046
MDP0046
7”
24-Pin LPP
13”
-
24-Pin HTSSOP
EL5224CRE-T13 24-Pin HTSSOP
13”
7”
EL5324CL-T7
EL5324CL-T13
EL5324CRE
32-Pin LPP
32-Pin LPP
13”
-
28-Pin HTSSOP
EL5324CRE-T13 28-Pin HTSSOP
13”
7”
EL5424CL-T7
EL5424CL-T13
32-Pin LPP
32-Pin LPP
13”
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL5224, EL5324, EL5424
Pinouts
EL5224
(24-PIN HTSSOP)
TOP VIEW
EL5324
(28-PIN HTSSOP)
TOP VIEW
VIN1
VIN2
VIN3
VIN4
VS+
1
2
3
4
5
6
7
8
9
24 VOUT1
VIN1
VIN2
VIN3
VIN4
VIN5
VS+
1
2
3
4
5
6
7
8
9
28 VOUT1
23 VOUT2
22 VOUT3
21 VOUT4
20 VS-
27 VOUT2
26 VOUT3
25 VOUT4
24 VOUT5
23 VS-
VIN5
VIN6
VIN7
VIN8
19 VOUT5
18 VOUT6
17 VOUT7
16 VOUT8
15 VSA-
Thermal
Pad
VIN6
VIN7
VIN8
22 VOUT6
21 VOUT7
20 VOUT8
19 VOUT9
18 VOUT1
17 VSA-
Thermal
Pad
VSA+ 10
VINA+ 11
NC 12
VIN9 10
VIN10 11
VSA+ 12
VINA+ 13
NC 14
14 VINA-
13 VOUTA
16 VINA-
15 VOUTA
EL5324 & EL5424
(32-PIN LPP)
TOP VIEW
EL5224
(24-PIN LPP)
TOP VIEW
VIN3
VIN4
VIN5
VS+
1
2
3
4
5
6
7
8
9
25 VOUT3
24 VOUT4
23 VOUT5
22 VS-
VIN3
1
2
3
4
5
6
7
19 VOUT3
VIN4
VS+
18 VOUT4
17 VS-
VIN5
VIN6
VIN7
VIN8
Thermal Pad
16 VOUT5
15 VOUT6
14 VOUT7
13 VOUT8
VIN6
VIN7
VIN8
VIN9
VIN10
Thermal Pad
21 VOUT6
20 VOUT7
19 VOUT8
18 VOUT9
17 VOUT10
*Not available in EL5324
2
EL5224, EL5324, EL5424
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . .+18V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
S
S
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . V - -0.5V, V +0.5V
S
S
Maximum Continuous Output Current (V
Maximum Continuous Output Current (V
) . . . . . . . . . . 30mA
OUT0-9
) . . . . . . . . . . . 150mA
OUTA
ESD Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications V + = +15V, V - = 0, R = 10kΩ, R = R = 20kΩ, C = 10pF to 0V, Gain of V
= -1, and T = 25°C unless
A
S
S
L
F
G
L
COM
otherwise specified.
DESCRIPTION
INPUT CHARACTERISTICS (REFERENCE BUFFERS)
PARAMETER
CONDITIONS
MIN
TYP
MAX
14
UNIT
V
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Impedance
V
= 0V
2
5
mV
µV/°C
nA
OS
CM
(Note 1)
= 0V
TCV
OS
I
V
2
50
B
CM
R
C
1
GΩ
IN
IN
V
Input Capacitance
Voltage Gain
1.35
pF
A
1V ≤ V
≤ 14V
0.992
1.008
4
V/V
OUT
INPUT CHARACTERISTICS (V
BUFFER)
COM
V
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Impedance
V
= 7.5V
1
3
mV
µV/°C
nA
OS
CM
TCV
(Note 1)
OS
I
V
V
= 7.5V
2
100
B
CM
R
1
GΩ
pF
IN
IN
C
Input Capacitance
Load Regulation
1.35
V
= 6V, -100mA < I < 100mA
-20
+20
150
mV
REG
COM
L
OUTPUT CHARACTERISTICS (REFERENCE BUFFERS)
V
V
Output Swing Low
Output Swing High
Short Circuit Current
I = 7.5mA
50
mV
V
OL
L
I = 7.5mA
L
14.85
120
14.95
140
OH
I
mA
SC
OUTPUT CHARACTERISTICS (V
BUFFER)
COM
V
V
Output Swing Low
50Ω to 7.5V
50Ω to 7.5V
1
1.5
V
V
OL
Output Swing High
Short Circuit Current
13.5
14
OH
I
160
mA
SC
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
Reference buffer V from 4.5V to 15.5V
55
60
5
80
100
6.8
7.8
8.8
dB
dB
S
V
buffer, V from 4.5V to 15.5V
S
COM
I
Total Supply Current
EL5224 (no load)
EL5324 (no load)
EL5424 (no load)
8
mA
mA
mA
S
6
9.5
11
7
DYNAMIC PERFORMANCE (BUFFER AMPLIFIERS)
SR
Slew Rate (Note 2)
-4V ≤ V
≤ 4V, 20% to 80%
7
15
V/µs
OUT
3
EL5224, EL5324, EL5424
Electrical Specifications V + = +15V, V - = 0, R = 10kΩ, R = R = 20kΩ, C = 10pF to 0V, Gain of V
= -1, and T = 25°C unless
A
S
S
L
F
G
L
COM
otherwise specified. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
(A = +1), V = 2V step
MIN
TYP
250
12
MAX
UNIT
ns
t
Settling to +0.1% (A = +1)
V
S
V
O
BW
-3dB Bandwidth
R
R
R
= 10kΩ, C = 10pF
MHz
MHz
°
L
L
L
L
GBWP
PM
Gain-Bandwidth Product
Phase Margin
= 10kΩ, C = 10pF
8
L
= 10kΩ, C = 10pF
50
L
CS
Channel Separation
f = 5MHz
75
dB
NOTES:
1. Measured over operating temperature range
2. Slew rate is measured on rising and falling edges
Pin Descriptions
24-PIN HTSSOP
24-PIN LPP
32-PIN LPP
28-PIN HTSSOP
PIN NAME
VIN1
PIN FUNCTION
1
2
23
24
1
31
1
Input
Input
Input
Input
Power
Input
Input
Input
Input
Power
32
2
VIN2
3
1
3
VIN3
4
2
2
4
VIN4
5
3
4
6
VS+
6
4
3
5
VIN5
7
5
5
7
VIN6
8
6
6
8
VIN7
9
7
7
9
VIN8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
8
11
12
13
14
15
16
17
20
21
22
24
23
25
26
27
28
10
11
VSA+
VINA+
NC
9
12
Positive input of V
Not connected
COM
22
10
11
12
13
14
15
16
17
18
19
20
21
29
13
VOUTA
VINA-
VSA-
Output of V
COM
14
Negative input of V
Power
COM
15
19
VOUT8
VOUT7
VOUT6
VOUT5
VS-
Output
Output
Output
Output
Power
20
21
23
22
24
VOUT4
VOUT3
VOUT2
VOUT1
VIN9
Output
Output
Output
Output
Input
25
26
27
8
9
VIN10
VIN11
VOUT11
VOUT10
Input
10 (Note 1)
16 (Note 1)
17
Input
Output
Output
18
4
EL5224, EL5324, EL5424
Pin Descriptions (Continued)
24-PIN HTSSOP
24-PIN LPP
32-PIN LPP
28-PIN HTSSOP
PIN NAME
PIN FUNCTION
18
19
VOUT9
VOUT0
VIN0
Output
Output
Input
28 (Note1)
30 (Note 1)
NOTE:
1. Not available in EL5324L
5
EL5224, EL5324, EL5424
Typical Performance Curves
Frequency Response for Various R (Buffer)
Frequency Response for Various C (Buffer)
L
L
20
10
20
10
V
=±7.5V
V =±7.5V
S
L
S
1000pF
C =10pF
R =10kΩ
L
10kΩ
100pF
1kΩ
0
0
12pF
47pF
-10
-20
-30
-10
-20
-30
150Ω
562Ω
100k
1M
10M
100M
100k
1M
10M
100M
100M
1k
Frequency (Hz)
Frequency (Hz)
PSRR vs Frequency (Buffer)
PSRR+
Output Impedance vs Frequency (Buffer)
100
80
60
40
20
0
600
480
360
240
120
0
V
=±7.5V
V
T
=±7.5V
=25°C
S
S
A
PSRR-
1k
10k
100k
1M
10M
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Input Noise Special Density vs Frequency (Buffer)
Overshoot vs Load Capacitance (Buffer)
80
70
60
50
40
30
20
10
0
V
=±7.5V
S
100
10
1
R =10kΩ
V
L
IN
=100mV
10k
100k
1M
10M
100M
10
100
Frequency (Hz)
Capacitance (pF)
Settling Time vs Step Size (Buffer)
Total Harmonic Distortion + Noise vs Frequency
(Buffer)
10
8
0.018
0.016
0.014
0.012
0.01
V
=±7.5V
V =±5V
S
S
R =10kΩ
C =12pF
R =10kΩ
L
L
L
V =2V
IN P-P
6
4
2
0
-2
-4
-6
-8
-10
0.008
0.006
200 250 300 350 400 450 500 550 600 650
1k
10k
100k
Settling Time (ns)
Frequency (Hz)
6
EL5224, EL5324, EL5424
Typical Performance Curves (Continued)
Output Swing vs Frequency (Buffer)
Frequency Response (V
)
COM
12
10
8
4
2
A =5
V
A =1
V
0
6
-2
-4
-6
4
2
V
=±5V
V =±7.5V
S
L
S
R =10kΩ
C =1µF
L
0
10k
100k
1M
10M
100
1k
10k
Frequency (Hz)
100k
1M
Frequency (Hz)
Transient Load Regulation - Sourcing (Buffer)
Transient Load Regulation - Sinking (Buffer)
0mA
5mA
5mA/div
5mA
0mA
5mA/div
R
=0Ω
S
R
=10Ω
S
C =200pF
L
C =1nF
L
0V
500mV/div
0V
500mV/div
R
=10Ω
S
C =4.7nF
L
R
=0Ω
R =10Ω
S
L
S
R
=10Ω
C =200pF
C =4.7nF
S
L
M=1µs/div
M=1µs/div
C =1nF
L
V
V
=±7.5V
V
V
=±7.5V
S
S
=0V
=0V
IN
IN
Transient Load Regulation - Sourcing (V
COM
)
Transient Load Regulation - Sinking (V
)
COM
0mA
100mA/div
100mA
0mA
-100mA
100mA/div
20mV/div
0V
0V
20mV/div
C =1µF
L
C =1µF
L
M=4µs/div
M=4µs/div
V
V
=±7.5V
V
V
=±7.5V
S
S
=0V
=0V
IN
IN
Small Signal Transient Response (Buffer)
Large Signal Transient Response (Buffer)
V
=±7.5V
V =±7.5V
S
S
R =10kΩ
C =12pF
L
L
50mV/div
1V/div
200ns/div
1µs/div
7
EL5224, EL5324, EL5424
Typical Performance Curves (Continued)
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-7 High Effective Thermal Conductivity (4-layer) Test
Board, LPP exposed diepad soldered to PCB per JESD51-5
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-3 and SEMI G42-88 (Single Layer) Test Board
3
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.857W
758mW
714mW
2.5 2.703W
LPP32
=35°C/W
LPP32
2
θ
JA
θ
=132°C/W
JA
LPP24
=140°C/W
1.5
LPP24
=37°C/W
θ
JA
θ
JA
1
0.5
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
Ambient Temperature (°C)
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-7 High Effective Thermal Conductivity Test Board
HTSSOP Exposed Diepad Soldered to PCB per JESD51-5
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
3.5
3
1
3.333W
909mW
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.030W
833mW
2.5
2
HTSSOP28
HTSSOP28
θ
=110°C/W
JA
θ
=30°C/W
JA
HTSSOP24
1.5
1
HTSSOP24
=120°C/W
θ
=33°C/W
JA
θ
JA
0.5
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
Ambient Temperature (°C)
GND. The input is a 10V
P-P
sinusoid. The output voltage is
Applications Information
approximately 9.985V
.
P-P
Product Description
The EL5224, EL5324, and EL5424 unity gain buffers and
100mA V amplifier are fabricated using a high voltage
CMOS process. The buffers exhibit rail-to-rail input and
output capability and has low power consumption (600µA
per buffer). When driving a load of 10kΩ and 12pF, the
buffers have a -3dB bandwidth of 12MHz and exhibits
COM
5V
10µs
V
T
V
=±5V
=25°C
S
A
=10V
IN
P-P
18V/µs slew rate. The V
amplifier exhibits rail-to-rail
COM
input. The output can be driving to within 2V of each supply
rail. With a 1µF capacitance load, the GBWP is about 1MHz.
5V
The EL5224, EL5324, and EL5424 are specified with a
single nominal supply voltage from 5V to 16.5V or a split
supply with its total range from 5V to 16.5V. Correct
operation is guaranteed for a supply range of 4.5V to 16.5V.
FIGURE 1. OPERATIONWITH RAIL-TO-RAIL INPUT
AND OUTPUT
SHORT-CIRCUIT CURRENT LIMIT
The Use of the Buffers
The buffers will limit the short circuit current to ±120mA if the
output is directly shorted to the positive or the negative
supply. If an output is shorted indefinitely, the power
dissipation could easily increase such that the device may be
damaged. Maximum reliability is maintained if the output
continuous current never exceeds ±30mA. This limit is set by
the design of the internal metal interconnects.
The output swings of the buffers typically extend to within
100mV of positive and negative supply rails with load
currents of 5mA. Decreasing load currents will extend the
output voltage range even closer to the supply rails. Figure 1
shows the input and output waveforms for the device.
Operation is from ±5V supply with a 10kΩ load connected to
8
EL5224, EL5324, EL5424
OUTPUT PHASE REVERSAL
designed to be dominated by the load capacitance, thus for
very short duration pulses (< 1µs) the output capacitor
supplies the current. For longer pulses the V amplifier
The buffers are immune to phase reversal as long as the
COM
input voltage is limited from V - -0.5V to V + +0.5V. Figure 2
S
S
supplies the current. By virtue of its high transconductance
which progressively increases as more current is drawn, it
can maintain regulation within 5mV as currents up to 100mA
are drawn, while consuming only 2mA of quiescent current.
shows a photo of the output of the device with the input
voltage driven beyond the supply rails. Although the device's
output will not change phase, the input's overvoltage should
be avoided. If an input voltage exceeds supply voltage by
more than 0.6V, electrostatic protection diodes placed in the
input stage of the device begin to conduct and overvoltage
damage could occur.
V
BOOST
R
R
1
2
IPCOM
INCOM
V
V
COM
DDCOM
+
1V
10µs
V
COM
-
V
SSCOM
1µF
ceramic
low ESR
FIGURE 3. V
USED AS A VOLTAGE BUFFER
COM
Alternatively, the back plate potential can be generated by a
DAC and the V amplifier used to buffer the DAC voltage,
V
T
V
=±2.5V
=25°C
=6V
S
A
IN
1V
COM
P-P
with gain if necessary. This is shown in Figure 4. In this case,
the effective transconductance of the feedback is reduced,
thus the amplifier will be more stable, but regulation will be
degraded by the feedback factor.
FIGURE 2. OPERATION WITH BEYOND-THE-
RAILS INPUT
UNUSED BUFFERS
It is recommended that any unused buffers have their inputs
tied to the ground plane.
V
BOOST
DRIVING CAPACITIVE LOADS
From
DAC
+
-
V
COM
The buffers can drive a wide range of capacitive loads. As
load capacitance increases, however, the -3dB bandwidth of
the device will decrease and the peaking increase. The
buffers drive 10pF loads in parallel with 10kΩ with just 1.5dB
of peaking, and 100pF with 6.4dB of peaking. If less peaking
is desired in these applications, a small series resistor
(usually between 5Ω and 50Ω) can be placed in series with
the output. However, this will obviously reduce the gain
slightly. Another method of reducing peaking is to add a
snubber circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values of
150Ω and 10nF are typical. The advantage of a snubber is
that it does not draw any DC load current or reduce the gain.
R
R
1µF
1
ceramic
low ESR
2
FIGURE 4. V
USED AS A BUFFER WITH GAIN
COM
CHOICE OF OUTPUT CAPACITOR
A 1µF ceramic capacitor with low ESR is recommended for
this amplifier. (For example, GRM42_ 6X7R105K16). This
capacitor determines the stability of the amplifier. Reducing
it will make the amplifier less stable, and should be avoided.
With a 1µF capacitor, the unity gain bandwidth of the
amplifier is close to 1MHz when reasonable currents are
being drawn. (For lower load currents, the gain and hence
bandwidth progressively decreases.) This means the active
trans-conductance is:
The Use of V
Amplifier
COM
amplifier is designed to control the voltage on the
The V
COM
back plate of an LCD display. This plate is capacitively
coupled to the pixel drive voltage which alternately cycles
positive and negative at the line rate for the display. Thus the
amplifier must be capable of sourcing and sinking capacitive
pulses of current, which can occasionally be quite large (a
few 100mA for typical applications).
2π × 1µF × 1MHz = 6.28S
This high transconductance indicates why it is important to
have a low ESR capacitor.
A simple use of the V
amplifier is as a voltage follower,
COM
If:
as illustrated in Figure 3. Here, a voltage, corresponding to
the mid-DAC potential, is generated by a resistive divider
and buffered by the amplifier. The amplifier's stability is
ESR × 6.28 > 1
9
EL5224, EL5324, EL5424
then the capacitor will not force the gain to roll off below
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
unity, and subsequent poles can affect stability. The
recommended capacitor has an ESR of 10mΩ, but to this
must be added the resistance of the board trace between the
capacitor and the sense connection - therefore this should
be kept short, as illustrated in Figure 1, by the diagonal line
to the capacitor. Also ground resistance between the
P
= Σi × [V × I
+ (V + - V
i) × I
i] +
LOAD
DMAX
S
SMAX
S
OUT
[V
× I
+ (V + - V
) × I
]
LA
SA
SAA
SA
OUTA
capacitor and the base of R must be kept to a minimum.
when sourcing, and:
2
These constraints should be considered when laying out the
PCB.
P
= Σi × [V × I
+ (V
i - V -) × I
i] +
LOAD
DMAX
S
SMAX
OUT
S
[V
× I
+ (V + - V
) × I
]
SA
SAA
SA
OUTA
LA
If the capacitor is increased above 1µF, stability is generally
improved and short pulses of current will cause a smaller
when sinking.
where:
“perturbation” on the V
voltage. The speed of response
COM
of the amplifier is however degraded as its bandwidth is
decreased. At capacitor values around 10µF, a subtle
interaction with internal DC gain boost circuitry will decrease
the phase margin and may give rise to some overshoot in the
response. The amplifier will remain stable though.
• i = 1 to total number of buffers
• V = Total supply voltage of buffer
S
• V = Total supply voltage of V
SA COM
RESPONSE TO HIGH CURRENT SPIKES
• I
= Maximum quiescent current per channel
SMAX
The V
COM
amplifier's output current is limited to 150mA.
• I = Maximum quiescent current of V
SA COM
This limit level, which is roughly the same for sourcing and
sinking, is included to maintain reliable operation of the part.
It does not necessarily prevent a large temperature rise if the
current is maintained. (In this case the whole chip may be
shut down by the thermal trip to protect functionality.) If the
display occasionally demands current pulses higher than this
limit, the reservoir capacitor will provide the excess and the
amplifier will top the reservoir capacitor back up once the
pulse has stopped. This will happen on the µs time scale in
practical systems and for pulses 2 or 3 times the current
• V
• V
• I
i = Maximum output voltage of the application
OUT
= Maximum output voltage of V
OUTA
COM
i = Load current of buffer
LOAD
• I = Load current of V
LA COM
If we set the two P
can solve for the R
package power dissipation curves provide a convenient way
to see if the device will overheat. The maximum safe power
dissipation can be found graphically, based on the package
type and the ambient temperature. By using the previous
equations equal to each other, we
's to avoid device overheat. The
DMAX
LOAD
limit, the V
voltage will have settled again before the
COM
next line is processed.
Power Dissipation
equation, it is a simple matter to see if P
device's power derating curves.
exceeds the
DMAX
With the high-output drive capability of the EL5224, EL5324,
and EL5424 buffer, it is possible to exceed the 125°C
“absolute-maximum junction temperature” under certain load
current conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if load conditions need to be modified for the
buffer to remain in the safe operating area.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit board
layout is necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be
as short as possible, and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
The maximum power dissipation allowed in a package is
determined according to:
supply operation, where the V - and V - pins are
S
SA
connected to ground, two 0.1µF ceramic capacitors should
T
- T
AMAX
JMAX
P
= --------------------------------------------
be placed from V + and V + pins to ground. A 4.7µF
DMAX
S
SA
Θ
JA
tantalum capacitor should then be connected from V + and
S
V
+ pins to ground. One 4.7µF capacitor may be used for
SA
where:
• T
multiple devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are to be
used. Internally, V + and V + are shorted together and V -
and V - are shorted together. To avoid high current density,
the V + pin and V + pin must be shorted in the PCB
SA
= Maximum junction temperature
= Maximum ambient temperature
JMAX
S
SA
S
• T
AMAX
SA
• θ = Thermal resistance of the package
JA
S
layout. Also, the V - pin and V - pin must be shorted in the
• P
DMAX
= Maximum power dissipation in the package
S
SA
PCB layout.
10
EL5224, EL5324, EL5424
Important Note: The metal plane used for heat sinking of
the device is electrically connected to the negative
supply potential (V - and V -). If V - and V - are tied
to ground, the thermal pad can be connected to ground.
Otherwise, the thermal pad must be isolated from any
other power planes.
S
SA SA
S
Package Outline Drawing (HTSSOP)
Package Outline Drawing (LPP)
NOTE: The package drawings shown here may not be the latest versions. For the latest revisions, please refer to the Intersil
website at: http://www.intersil.com/design/packages/elantec
11
EL5224, EL5324, EL5424EL5224, EL5324, EL5424
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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