EL5525IRE-T7 [RENESAS]
SPECIALTY ANALOG CIRCUIT, PDSO38, MO-153, TSSOP-38;
| 型号： | EL5525IRE-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SPECIALTY ANALOG CIRCUIT, PDSO38, MO-153, TSSOP-38 光电二极管 |
| 文件： | 总10页 (文件大小：722K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
EL5525
FN7393
Rev 2.00
September 21, 2010
18-Channel TFT-LCD Reference Voltage Generator
The EL5525 is designed to produce the reference voltages
required in TFT-LCD applications. Each output is
programmed to the required voltage with 10 bits of
resolution. Reference pins determine the high and low
voltages of the output range, which are capable of swinging
to either supply rail. Programming of each output is
performed using the serial interface. A serial out pin enables
daisy chaining of multiple devices.
Features
• 18-channel Reference Outputs
• Accuracy of ±0.1%
• Supply Voltage of 4.5V to 16.5V
• Digital Supply 3.3V to 5V
• Low Supply Current of 15mA
• Rail-to-Rail Capability
A number of the EL5525 can be stacked for applications
requiring more than 18 outputs. The reference inputs can be
tied to the rails, enabling each part to output the full voltage
range, or alternatively, they can be connected to external
resistors to split the output range and enable finer
resolutions of the outputs.
• Internal Thermal Protection
• Pb-Free Available (RoHS Compliant)
Applications
• TFT-LCD Drive Circuits
• Reference Voltage Generators
The EL5525 has 18 outputs and comes in a 38-pin HTSSOP
package. It is specified for operation over the full -40°C to
+85°C temperature range.
Pinout
Ordering Information
EL5525
(38-PIN HTSSOP)
TOP VIEW
PART
NUMBER
(Note)
TEMP
RANGE
(°C)
PKG.
DWG.
NUMBER
PART
MARKING
PACKAGE
(Pb-free)
ENA
SDI
1
2
3
4
5
6
7
8
9
38 OUTA
37 OUTB
36 OUTC
35 GND
EL5525IREZ*
5525IREZ -40 to +85 38-Pin HTSSOP MDP0048
EL5525IREZ-T7* 5525IREZ -40 to +85 38-Pin HTSSOP MDP0048
EL5525IREZ-T13* 5525IREZ -40 to +85 38-Pin HTSSOP MDP0048
SCLK
SDO
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant
and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
EXT_OSC
VS
34 OUTD
33 OUTE
32 OUTF
31 OUTG
30 OUTH
29 OUTI
28 GND
VSD
NC
NC
THERMAL
PAD
OSC_SELECT 10
VS 11
REFH 12
REFL 13
GND 14
27 OUTJ
26 OUTK
25 OUTL
24 GND
CAP 15
VS 16
23 OUTM
22 OUTN
21 OUTO
20 OUTP
NC 17
OUTR 18
OUTQ 19
FN7393 Rev 2.00
Page 1 of 10
September 21, 2010
EL5525
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Between V and GND . . . . . . . . . . . . . . . .4.5V(min) to 18V(max)
S
Between V
and GND . . . . . . . . . . . 3V(min) to V and +7(max)
S
SD
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications
V
= 15V, V = 5V, V
SD
= 13V, V
= 2V, R = 1.5k and C = 200pF to 0V, T = +25°C, unless
S
REFH
REFL
L
L
A
otherwise specified.
PARAMETER
SUPPLY
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
I
I
Supply Current
No load
15
18
mA
mA
S
Digital Supply Current
0.17
0.35
SD
ANALOG
V
V
Output Swing Low
Sinking 5mA (V
= 15V, V
= 0)
50
14.95
140
60
150
mV
V
OL
REFH
REFL
= 15V, V = 0)
REFL
Output Swing High
Sourcing 5mA (V
14.85
100
45
OH
REFH
I
Short Circuit Current
R
= 10
L
mA
SC
PSRR
Power Supply Rejection Ratio
Program to Out Delay
Accuracy Referred to the Ideal Value
Channel to Channel Mismatch
Droop Voltage
V + is moved from 14V to 16V
S
dB
t
4
ms
D
V
Code = 512
Code = 512
20
mV
AC
V
2
mV
MIS
V
1
2
mV/ms
k
DROOP
R
Input Resistance @ V
Load Regulation
Band Gap
, V
REFH REFL
34
INH
REG
I
= 5mA step
0.5
1.3
1.5
1.6
mV/mA
V
OUT
BG
1.1
2
DIGITAL
V
V
Logic 1 Input Voltage
Logic 0 Input Voltage
Clock Frequency
Setup Time
V
V
IH
1
5
IL
F
MHz
ns
CLK
t
t
t
t
t
20
20
20
20
10
1
S
Hold Time
ns
H
Load to Clock Time
Clock to Load Line
ns
LC
CE
DCO
ns
Clock to Out Delay Time
Input Resistance
Negative edge of SCLK
ns
R
S
G
µs
SDIN
DIN
T
Minimum Pulse Width for EXT_OSC
Signal
5
PULSE
Duty Cycle
F_OSC
INL
Duty Cycle for EXT_OSC Signal
Internal Refresh Oscillator Frequency
Integral Nonlinearity Error
50
21
%
OSC_Select = 0
kHz
LSB
LSB
1.3
0.5
DNL
Differential Nonlinearity Error
FN7393 Rev 2.00
Page 2 of 10
September 21, 2010
EL5525
Pin Descriptions
PIN NUMBER
PIN NAME
ENA
PIN TYPE
Logic Input
Logic Input
Logic Input
Logic Output
Input/Output
Power
PIN DESCRIPTION
Chip select, low enables data input to logic
1
2
SDI
Serial data input
3
SCLK
SDO
Serial data clock
4
Serial data output
5
EXT_OSC
VS
Oscillator pin for synchronizing
Positive supply voltage for analog circuits (4.5V to 16.5V)
Positive power supply for digital circuites (3.3V to 5V)
Not connected
6, 11, 16
7
VSD
Power
8, 9, 17
NC
10
OSC_SELECT
REFH
REFL
Oscillator select, “0” = internal, “1” = external
High reference voltage
12
Analog Input
Analog Input
Power
13
Low reference voltage
14, 24, 28, 35
GND
Ground
15
18
19
20
21
22
23
25
26
27
29
30
31
32
33
34
36
37
38
CAP
Analog
Decoupling capacitor for internal reference
Channel R output voltage
Channel Q output voltage
Channel P output voltage
Channel O output voltage
Channel N output voltage
Channel M output voltage
Channel L output voltage
Channel K output voltage
Channel J output voltage
Channel I output voltage
Channel H output voltage
Channel G output voltage
Channel F output voltage
Channel E output voltage
Channel D output voltage
Channel C output voltage
Channel B output voltage
Channel A output voltage
OUTR
OUTQ
OUTP
OUTO
OUTN
OUTM
OUTL
OUTK
OUTJ
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
OUTI
OUTH
OUTG
OUTF
OUTE
OUTD
OUTC
OUTB
OUTA
FN7393 Rev 2.00
Page 3 of 10
September 21, 2010
EL5525
Typical Performance Curves
REFH = 13V, REFL = 2V
0.3
0.2
0.1
0
1.5
1
0.5
0
-0.1
-0.2
-0.5
-1
V
V
= 15V
V
V
= 13V
= 2V
S
REFH
REFL
= 5V
SD
-0.3
10
0
200
400
600
800
1000
1200
210
410
610
810
1010
CODE
INPUT CODE
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. INTEGRAL NONLINEARITY ERROR
V
= V
REFH
= 15V
V
= V = 15V
REFH
S
S
0mA
5mA
5mA/DIV
5mA
0mA
5mA/DIV
C = 4.7nF
C =1nF
L
S
L
R
= 20
R = 20
S
5V
200mV/DIV
200mV/DIV
C
R
= 1nF
= 20
C = 4.7nF
L
S
L
S
R = 20
C
= 180pF
C = 180pF
L
L
M = 400ns/DIV
M = 400ns/DIV
FIGURE 4. TRANSIENT LOAD REGULATION (SINKING)
FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING)
SCLK
SCLK
SDA
ENA
SDA
ENA
OUTA
OUTA
M = 200µs/DIV
M = 200µs/DIV
FIGURE 6. SMALL SIGNAL RESPONSE (FALLING FROM
200mV TO 100mV)
FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V
TO 8V)
FN7393 Rev 2.00
Page 4 of 10
September 21, 2010
EL5525
together, connect the SDO pin to the SDI pin on the next
chip. While the ENA is held low, the 16m-bit data is loaded to
the SDI input of the first chip. The first 16-bit data will go to
the last chip and the last 16-bit data will go to the first chip.
While the ENA is held high, all addressed outputs will be
updated simultaneously.
General Description
The EL5525 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5525,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5525. As all of the output
buffers are identical, it is also possible to use the EL5525 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
The Serial Timing Diagram and parameters table show the
timing requirements for three-wire signals.
The serial data has a minimum length of 16 bits, the MSB
(most significant bit) is the first bit in the signal. The bits are
allocated to the following functions (also refer to Table 1).
• Bit 15 is always set to a zero
• Bits 14 through 10 select the channel to be written to, these
are binary coded with channel A = 0, and channel R = 17
• The 10-bit data is on bits 9 through 0. Some examples of
data words are shown in Table 3.
Digital Interface
The EL5525 uses a simple 3-wire SPI compliant digital
interface to program the outputs. The EL5525 can support
the clock rate up to 5MHz.
TABLE 1. CONTROL BITS LOGIC TABLE
BIT
B15
B14
B13
B12
B11
B10
B9
NAME
Test
A4
DESCRIPTION
Always 0
Serial Interface
Channel Address
The EL5525 is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The MSB
(bit 15) is loaded first and the LSB (bit 0) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
A3
Channel Address
A2
Channel Address
A1
Channel Address
A0
Channel Address
Data
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
B8
Data
B7
Data
B6
Data
B5
Data
To facilitate the system designs that use multiple EL5525
chips, a buffered serial output of the shift register (SDO pin)
is available. Data appears on the SDO pin at the 16th falling
SCLK edge after being applied to the SDI pin.
B4
Data
B3
Data
B2
Data
B1
Data
To control the multiple EL5525 chips from a single three-wire
serial port, just connect the ENA pins and the SCLK pins
B0
Data
Serial Timing Diagram
ENA
t
r
t
HE
t
t
T
f
t
t
SE
SE
HE
SCLK
t
t
t
w
SD
HD
B15
B14
B13
B12-B2
B1
B0
SDI
t
MSB
LOAD MSB FIRST, LSB LAST
LSB
FN7393 Rev 2.00
September 21, 2010
Page 5 of 10
EL5525
TABLE 2. SERIAL TIMING PARAMETERS
PARAMETER
RECOMMENDED OPERATING RANGE
DESCRIPTION
T
200ns
0.05 * T
10ns
Clock Period
t /t
r f
Clock Rise/Fall Time
ENA Hold Time
t
HE
t
10ns
ENA Setup Time
Data Hold Time
SE
t
10ns
HD
t
10ns
Data Setup Time
Clock Pulse Width
SD
t
0.50 * T
W
TABLE 3. SERIAL PROGRAMMING EXAMPLES
Data
Control
Channel Address
A3 A2
C1
0
A4
0
A1 A0 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0
Condition
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
1
1
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
1
1
1
Channel A, Value = 0
Channel A, Value = 1023
Channel A, Value = 512
Channel C, Value = 513
Channel H, Value = 31
Channel R, Value = 31
0
0
0
0
0
0
0
0
0
1
For transient load application, the external clock Mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
Analog Section
Transfer Function
The transfer function is: shown in Equaion 1:
data
(EQ. 1)
------------
V
= V
+
V
- V
REFL
OUTIDEAL
REFL
REFH
1024
where data is the decimal value of the 10-bit data binary
input code.
After power on, the chip will start with the internal oscillator
mode. At this time, the EXT_OSC pin will be in a high
impedance condition to prevent contention. By setting pin 10
to high, the chip is on external clock mode. Setting pin 10 to
low, the chip is on internal clock mode.
The output voltages from the EL5525 will be derived from
the reference voltages present at the V
pins. The impedance between those two pins is about 32k.
and V
REFL
REFH
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
EL5525. GND < V
REFH
V and GND V
REFL
V .
REFH
S
Clock Oscillator
The EL5525 requires an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling OSC
clock edges. The output refreshed switches open at the rising
edges of the OSC clock. The driving load shouldn’t be changed
at the rising edges of the OSC clock. Otherwise, it will generate
a voltage error at the outputs. This clock may be input or output
via the clock pin labeled EXT_OSC. The internal clock is
provided by an internal oscillator running at approximately
21kHz and can be output to the EXT_OSC pin. In a 2 chip
system, if the driving loads are stable, one chip may be
programmed to use the internal oscillator; then the OSC pin will
output the clock from the internal oscillator. The second chip
may have the OSC pin connected to this clock source.
FN7393 Rev 2.00
Page 6 of 10
September 21, 2010
EL5525
Block Diagram
REFH
OUTA
OUTB
OUTC
OUTD
OUTE
OUTP
OUTQ
18
VOLTAGE
SOURCES
CHANNEL
REGISTERS
OUTR
REFL
CAP
SDO
SDI
SCLK
ENA
CONTROL IF
OSC_SELECT
EXT_OSC
Channel Outputs
Output Stage and the Use of External
Oscillator
Each of the channel outputs has a rail-to-rail buffer. This
enables all channels to have the capability to drive to within
50mV of the power rails, (see Table Electrical Specifications
on page 2 for details).
CH
S
1
1.3V
+
-
+
-
When driving large capacitive loads, a series resistor should
be placed in series with the output. (Usually between 5 and
50).
V
OUT
1.3V
S
2
V
+
-
IN
Each of the channels is updated on a continuous cycle, the
time for the new data to appear at a specific output will
depend on the exact timing relationship of the incoming data
to this cycle.
OSC
FIGURE 7. SIMPLIFIED OUTPUT SAMPLE AND HOLD AMP
STAGE FOR ONE CHANNEL
The best-case scenario is when the data has just been
captured and then passed on to the output stage
immediately; this can be as short as 48µs. In the worst-case
scenario, this will be 860µs for EL5525, when the data has
just missed the cycle at f_OSC = 21kHz.
The output voltage is generated from the DAC, which is V
in Figure 7. The refreshed switches are controlled by the
internal or external oscillator signal. When the OSC clock
IN
signal is low, switches S and S are closed. The output
1
2
When a large change in output voltage is required, the
change will occur in 2V steps, thus the requisite number of
timing cycles will be added to the overall update time. This
means that a large change of 16V can take between 6.8ms
and 7.2ms depending on the absolute timing relative to the
update cycle.
V
= V and at the same time the sample and hold cap
OUT
IN
CH is being charged. When the OSC clock signal is high, the
refreshed switches S and S are opened and the output
1
2
voltage is maintained by CH. This refreshed process will
repeat every 18 clock cycles for each channel. The time
FN7393 Rev 2.00
Page 7 of 10
September 21, 2010
EL5525
takes to update the output depends on the timing at the V
and the state of the switches. It can take 1 to 18 clock cycles
to update each output.
Ch1 --- Output1
Ch3 --- Output2
Ch2 --- EXT_OSC
IN
For the sample and hold capacitor CH to maintain the
correct output voltage, the driving load shouldn’t be changed
at the rising edge of the OSC signal. Since at the rising edge
of the OSC clock, the refreshed switches are being opened,
if the load changes at that time, it will generate an error
output voltage. For a fixed load condition, the internal
oscillator can be used.
At the falling edge of the OSC, output 1 is being refreshed,
and one clock cycle later, output 2 is being refreshed. The
spike you see here is the response of the output amplifier
when the refreshed switches are closed. When driving a big
capacitor load, there will be ringing at the spikes because
the phase margin of the amplifier is decreased.
For the transient load condition, the external OSC mode
should be used to avoid the conflict between the rising edge
of the OSC signal and the changing load. So a timing delay
circuit will be needed to delay the OSC signal and avoid the
rising edge of the OSC signal and changing the load at the
same time.
The speed of the external OSC signal shouldn’t be greater
than 70kHz because for the worst condition, it will take at
least 4µs to charge the sample and hold capacitor CH. The
pulse width has to be at least 4µs long. From our lab test, the
duty cycle of the OSC signal must be greater than 30%.
POWER DISSIPATION
With the 30mA maximum continues output drive capability
for each channel, it is possible to exceed the +125°C
absolute maximum junction temperature. Therefore, it is
important to calculate the maximum junction temperature for
the application to determine if load conditions need to be
modified for the part to remain in the safe operation.
The maximum power dissipation allowed in a package is
determined according to: Equation 2:
T
- T
AMAX
JMAX
(EQ. 2)
--------------------------------------------
P
=
DMAX
JA
where:
FIGURE 8. TRANSIENT LOAD RESPONSE
Channel 3 --- sinking and sourcing 5mA current
Channel 2 --- EXT_OSC signal
• T
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
• = Thermal resistance of the package
JA
Channel 1 --- V
OUT
• P
DMAX
= Maximum power dissipation in the package
In Figure Table 8 on page 8, the OSC signal is synchronized
to the load signal. The rising edge of the OSC signal is then
delayed by some amount of time and gives enough time for
CH to be charged to a new voltage before the switches are
opened.
The maximum power dissipation actually produced by the IC
is the total quiescent supply current times the total power
supply voltage and plus the power in the IC due to the loads.
(EQ. 3)
P
= V I + V - V
i I
i
LOAD
DMAX
S
S
S
OUT
when sourcing, and:
(EQ. 4)
P
= V I + V
i I
i
LOAD
DMAX
S
S
OUT
when sinking.
Where:
• i = 18
• V = Supply voltage
S
• I = Quiescent current
S
FIGURE 9. CHANNEL TO CHANNEL REFRESH
• V
i = Output voltage of the i channel
OUT
• I
i = Load current of the i channel
LOAD
FN7393 Rev 2.00
Page 8 of 10
September 21, 2010
EL5525
By setting the two P
equations equal to each other, we
POWER SUPPLY BYPASSING AND PRINTED CIRCUIT
BOARD LAYOUT
DMAX
s to avoid the device overheat. The
can solve for the R
LOAD
package power dissipation curves provide a convenient way
to see if the device will overheat.
Good printed circuit board layout is necessary for optimum
performance. A low impedance and clean analog ground
plane should be used for the EL5525. The traces from the
two ground pins to the ground plane must be very short. The
thermal pad of the EL5525 should be connected to the
analog ground plane. Lead length should be as short as
possible and all power supply pins must be well bypassed. A
THERMAL SHUTDOWN
The EL5525 has an internal thermal shutdown circuitry that
prevents overheating of the part. When the junction
temperature goes up to about +150°C, the part will be
disabled. When the junction temperature drops down to
about +120°C, the part will be enabled. With this feature, any
short circuit at the outputs will enable the thermal shutdown
circuitry to disable the part.
0.1µF ceramic capacitor must be place very close to the V ,
S
V
, V
, and CAP pins. A 4.7µF local bypass
REFH REFL
tantalum capacitor should be placed to the V , V
, and
REFH
S
V
pins.
REFL
Application Drawing
HIGH REFERENCE
VOLTAGE
COLUMN
(SOURCE)
DRIVER
+10V
REFH
VS
OUTA
0.1µF
OUTB
OUTC
OUTD
OUTE
OUTF
+12V
+5V
0.1µF
LCD PANEL
VSD
MICROCONTROLLER
0.1µF
SDI
SCK
ENA
SDO
OSC
LCD
TIMING
CONTROLLER
HORIZONTAL RATE
CAP
5V
0.1µF
OSC_SET
OUTQ
+1V
REFL
GND
0.1µF
OUTR
EL5525
© Copyright Intersil Americas LLC 2004-2010. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7393 Rev 2.00
Page 9 of 10
September 21, 2010
EL5525
HTSSOP (Heat-Sink TSSOP) Family
MDP0048
0.25 M C A B
HTSSOP (HEAT-SINK TSSOP) FAMILY
D
A
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD TOLERANCE
A
A1
A2
b
1.20
1.20
1.20
1.20
1.20
Max
PIN #1 I.D.
E
0.075 0.075 0.075 0.075 0.075
±0.075
E1
0.90
0.25
0.15
5.00
3.2
0.90
0.25
0.15
6.50
4.2
0.90
0.25
0.15
7.80
4.3
0.90
0.25
0.15
9.70
5.0
0.90
0.22
0.15
9.70
7.25
6.40
4.40
3.0
+0.15/-0.10
+0.05/-0.06
+0.05/-0.06
±0.10
0.20 C B A
c
2X
1
(N/2)
N/2 LEAD TIPS
TOP VIEW
B
D
D1
E
Reference
Basic
6.40
4.40
3.0
6.40
4.40
3.0
6.40
4.40
3.0
6.40
4.40
3.0
D1
EXPOSED
THERMAL PAD
E1
E2
e
±0.10
Reference
Basic
0.65
0.60
1.00
14
0.65
0.60
1.00
20
0.65
0.60
1.00
24
0.65
0.60
1.00
28
0.50
0.60
1.00
38
E2
L
±0.15
L1
N
Reference
Reference
Rev. 3 2/07
BOTTOM VIEW
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.05
H
e
C
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEATING
PLANE
3. Dimensions “D” and “E1” are measured at Datum Plane H.
0.10 M C A B
b
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.10 C
N LEADS
SIDE VIEW
SEE DETAIL “X”
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
FN7393 Rev 2.00
Page 10 of 10
September 21, 2010
相关型号：
©2020 ICPDF网 联系我们和版权申明