EL7642AILTZ-T13 [RENESAS]
TFT-LCD DC/DC with Integrated Amplifiers;
| 型号： | EL7642AILTZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | TFT-LCD DC/DC with Integrated Amplifiers CD 开关 |
| 文件： | 总19页 (文件大小：899K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
EL7640A, EL7641A, EL7642A
TFT-LCD DC/DC with Integrated Amplifiers
FN6270
Rev 0.00
May 15, 2006
The EL7640A, EL7641A, and EL7642A integrate a high
performance boost regulator with 2 LDO controllers for V
Features
ON
• Current mode boost regulator
- Fast transient response
- 1% accurate output voltage
- 18V/3A integrated FET
- >90% efficiency
and V
, a V -slice circuit with adjustable delay and
OFF ON
either one (EL7640A), three (EL7641A), or five amplifiers
(EL7642A) for V and V applications.
COM
GAMMA
The boost converter in the EL7640A, EL7641A, and
EL7642A is a current mode PWM type integrating an 18V
NHchannel MOSFET. Operating at 1.2MHz, this boost can
operate in either P-mode for superior transient response, or
in PI-mode for tighter output regulation.
• 2.6V to 5.5V V supply
IN
• 2 LDO controllers for V
- 2% output regulation
and V
OFF
ON
Using external low-cost transistors, the LDO controllers
- V -slice circuit
ON
provide tight regulation for V , V
start-up sequence control and fault protection.
, as well as providing
ON OFF
• High speed amplifiers
- 150mA short-circuit output current
- 12V/s slew rate
The amplifiers are ideal for V and V
COM
GAMMA
applications, with 150mA peak output current drive, 12MHz
bandwidth, and 12V/s slew rate. All inputs and outputs are
rail-to-rail.
- 12MHz -3dB bandwidth
- Rail-to-rail inputs and outputs
• Built-in power sequencing
• Internal soft-start
Available in the 32 Ld thin QFN (5mm x 5mm) Pb-free
packages, the EL7640A, EL7641A, and EL7642A are specified
for operation over the -40°C to +85°C temperature range.
• Multiple overload protection
• Thermal shutdown
Ordering Information
• 32 Ld 5x5 thin QFN package
• Pb-free plus anneal available (RoHS compliant)
PART NUMBER
(Note)
PART
MARKING REEL
TAPE & PACKAGE
PKG.
DWG. #
(Pb-Free)
EL7640AILTZ
7640AILTZ
7640AILTZ
-
7”
13”
-
32 Ld 5x5
Thin QFN
MDP0051
MDP0051
MDP0051
MDP0051
MDP0051
MDP0051
MDP0051
MDP0051
MDP0051
Applications
• TFT-LCD panels
• LCD monitors
• Notebooks
EL7640AILTZ-T7
32 Ld 5x5
Thin QFN
EL7640AILTZ-T13 7640AILTZ
32 Ld 5x5
Thin QFN
EL7641AILTZ
7641AILTZ
7641AILTZ
32 Ld 5x5
Thin QFN
• LCD-TVs
EL7641AILTZ-T7
7”
13”
-
32 Ld 5x5
Thin QFN
EL7641AILTZ-T13 7641AILTZ
32 Ld 5x5
Thin QFN
EL7642AILTZ
7642AILTZ
7642AILTZ
32 Ld 5x5
Thin QFN
EL7642AILTZ-T7
7”
13”
32 Ld 5x5
Thin QFN
EL7642AILTZ-T13 7642AILTZ
32 Ld 5x5
Thin QFN
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements
of IPC/JEDEC J STD-020.
FN6270 Rev 0.00
May 15, 2006
Page 1 of 19
EL7640A, EL7641A, EL7642A
Pinouts
EL7640A
(32 LD QFN)
TOP VIEW
EL7641A
(32 LD QFN)
TOP VIEW
SRC
REF
1
2
3
4
5
6
7
8
24 COMP
23 FB
22 IN
SRC
REF
1
2
3
4
5
6
7
8
24 COMP
23 FB
AGND
PGND
OUT1
NEG1
POS1
NC
AGND
PGND
OUT1
NEG1
POS1
OUT2
22 IN
21 LX
20 NC
19 NC
18 IC
21 LX
THERMAL
PAD
THERMAL
PAD
20 NC
19 NC
18 IC
17 NC
17 OUT3
NC = NOT INTERNALLY CONNECTED
IC = INTERNALLY CONNECTED
NC = NOT INTERNALLY CONNECTED
IC = INTERNALLY CONNECTED
EL7642A
(32 LD QFN)
TOP VIEW
SRC
1
2
3
4
5
6
7
8
24 COMP
23 FB
REF
AGND
PGND
OUT1
NEG1
POS1
OUT2
22 IN
21 LX
THERMAL
PAD
20 OUT5
19 NEG5
18 POS5
17 OUT4
FN6270 Rev 0.00
May 15, 2006
Page 2 of 19
EL7640A, EL7641A, EL7642A
Absolute Maximum Ratings (T = 25°C)
A
IN, CTL to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
COM, DRN to AGND . . . . . . . . . . . . . . . . . . . . -0.3V to V
+0.3V
SRC
COMP, FB, FBP, FBN, DEL, REF to AGND. . . . . -0.3V to V +0.3V
LX Maximum Continuous RMS Output Current. . . . . . . . . . . . . 1.6A
OUT1, OUT2, OUT3, OUT4, OUT5
IN
PGND, BGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +24V
SUP to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +18V
DRVP, SRC to AGND . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +36V
POS1, NEG1, OUT1, POS2, NEG2, OUT2, POS3, OUT3,
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . ±75mA
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Continuous Junction Temperature . . . . . . . . . . . . +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
POS4, NEG4, OUT4, POS5, OUT5 to AGND . .-0.3V to V
+0.3V
SUP
DRVN to AGND . . . . . . . . . . . . . . . . . . . . . . . V -20V to V +0.3V
IN IN
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications
V
= 3V, V
BOOST
= V
= 12V, V
= 20V, Over temperature from -40°C to 85°C.
SRC
IN
SUP
Unless Otherwise Specified.
PARAMETER
SUPPLY
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
Input Supply Range
2.6
2.4
2.2
5.5
2.6
2.4
2.5
10
V
V
IN
Undervoltage Lockout Threshold
Undervoltage Lockout Threshold
Quiescent Current
V
V
rising
falling
2.5
2.3
LOR
LOF
IN
IN
V
I
I
LX not switching
LX switching
mA
mA
ms
V
S
Quiescent Current - Switching
Fault Delay Time
5
SS
T
C
= 100nF
23
FD
DEL
= 25°C
A
V
Reference Voltage
T
1.19
1.215
1.215
140
1.235
1.238
REF
1.187
V
SHUTDN
Thermal Shutdown Temperature
°C
MAIN BOOST REGULATOR
V
Output Voltage Range
(Note 1)
V
+
18
V
BOOST
IN
15%
1050
82
F
Oscillator Frequency
Maximum Duty Cycle
Boost Feedback Voltage
1200
85
1350
kHz
%
V
OSC
D
CM
V
T
= 25°C
1.192
1.188
0.85
1.205
1.205
0.925
0.1
1.218
1.222
1.020
FBB
A
V
V
FB Fault Trip Level
Load Regulation
Falling edge
50mA < I
V
FTB
V
I
/
/
< 250mA
LOAD
%
BOOST
BOOST
V
V
Line Regulation
V
V
= 2.6V to 5.5V
0.08
%/V
BOOST
IN
IN
I
Input Bias Current
FB Transconductance
LX On Resistance
LX Leakage Current
LX Current Limit
= 1.35V
500
40
nA
µA/V
m
µA
FB
FB
gmV
dI = ±2.5µA at COMP, FB = COMP
160
160
0.02
3.0
7
R
LX
ON
I
I
t
LX
LEAK
V
= 1.35V, V = 13V
LX
FB
LX
Duty cycle = 65% (Note 1)
= 100nF
A
LIM
B
Soft-Start Period
C
ms
SS
DEL
FN6270 Rev 0.00
May 15, 2006
Page 3 of 19
EL7640A, EL7641A, EL7642A
Electrical Specifications
V
= 3V, V
BOOST
= V
= 12V, V
= 20V, Over temperature from -40°C to 85°C.
SRC
IN
SUP
Unless Otherwise Specified. (Continued)
PARAMETER
DESCRIPTION CONDITIONS
MIN
TYP
MAX
UNIT
OPERATIONAL AMPLIFIERS
V
Supply Operating Range
4.5
18
800
12
V
SUP
I
Supply Current per Amplifier
Offset Voltage
600
3
µA
mV
nA
V
SUP
V
OS
I
Input Bias Current
-50
0
+50
B
CMIR
Common Mode Input Range
Common Mode Rejection Ratio
Open Loop Gain
V
SUP
CMRR
60
90
dB
dB
mV
A
V
110
OL
Output Voltage High
I
I
= 100µA
= 5mA
V
V
OH
OUT
OUT
SUP
-15
SUP
-2
V
V
mV
SUP
-250
SUP
-150
V
Output Voltage Low
I
I
= -100µA
= -5mA
2
30
mV
mV
OL
OUT
OUT
100
150
150
I
I
Short-Circuit Current
Continuous Output Current
Power Supply Rejection Ratio
-3dB Bandwidth
100
±50
60
mA
SC
CONT
mA
PSRR
BW
100
12
8
dB
MHz
MHz
V/µs
-3dB
GBWP
Gain Bandwidth Product
Slew Rate
SR
12
POSITIVE LDO
V
Positive Feedback Voltage
I
I
= 100µA, T = 25°C
A
1.176
1.176
0.82
-50
1.2
1.2
0.9
1.224
1.229
0.98
50
V
V
FBP
FTP
DRVP
DRVP
= 100µA
falling
V
V
Fault Trip Level
V
V
V
V
FBP
FBP
I
Positive LDO Input Bias Current
FBP Load Regulation
= 1.4V
nA
%
BP
FBP
V
I
/
= 25V, I
= 0 to 20µA
0.5
POS
POS
DRVP
DRVP
I
I
t
Sink Current
V
V
= 1.1V, V
= 1.4V, V
= 100nF
= 10V
= 30V
2
4
0.1
7
mA
µA
ms
DRVP
FBP
DRVP
DRVP
P
DRVP Off Leakage Current
Soft-Start Period
10
LEAK
FBP
P
C
DEL
SS
NEGATIVE LDO
V
FBN Regulation Voltage
I
I
= 0.2mA, T = 25°C
A
0.173
0.171
380
0.203
0.203
430
0.233
0.235
480
V
V
FBN
DRVN
DRVN
= 0.2mA
rising
V
V
Fault Trip Level
V
V
V
V
V
mV
nA
%
FTN
FBN
FBN
I
Negative LDO Input Bias Current
FBN Load Regulation
Source Current
= 250mV
-50
50
BN
FBN
= -6V, I
= 2µA to 20µA
DRVN
0.5
4
DRVN
I
I
t
= 500mV, V
= -6V
= 30V
DRVP
2
mA
µA
ms
DRVN
FBN
FBP
DRVN
N
DRVN Off Leakage Current
Soft-start Period
= 1.35V, V
= 100nF
0.1
7
10
LEAK
N
C
DEL
SS
FN6270 Rev 0.00
May 15, 2006
Page 4 of 19
EL7640A, EL7641A, EL7642A
Electrical Specifications
V
= 3V, V
BOOST
= V
= 12V, V
= 20V, Over temperature from -40°C to 85°C.
SRC
IN
SUP
Unless Otherwise Specified. (Continued)
PARAMETER
DESCRIPTION CONDITIONS
MIN
TYP
MAX
UNIT
V
-SLICE CIRCUIT
ON
LO
V
V
CTL Input Low Voltage
V
V
= 2.6V to 5.5V
0.4V
1
V
V
IN
IN
IN
CTL Input High Voltage
= 2.6V to 5.5V
0.6V
-1
HI
IN
I
CTL
CTL Input Leakage Current
CTL to OUT Rising Prop Delay
CTL = AGND or IN
µA
ns
LEAK
t rise
1k from DRN to 8V, V
no load on OUT, measured from V
to OUT = 20%
= 0V to 3V step,
100
100
D
CTL
= 1.5V
CTL
t fall
CTL to OUT Falling Prop Delay
1k from DRN to 8V, V
CTL
= 3V to 0V step,
ns
D
no load on OUT, measured from V
= 1.5V
CTL
to OUT = 80%
V
SRC Input Voltage Range
SRC Input Current
30
V
µA
µA
SRC
ISRC
Start-up sequence not completed
Start-up sequence completed
Start-up sequence completed
Start-up sequence completed
Start-up sequence not completed
150
150
5
250
250
10
R
R
R
SRC
DRN
COM
SRC On Resistance
ON
ON
ON
DRN On Resistance
30
60
COM to GND On Resistance
350
1000
1800
SEQUENCING
t
t
t
t
Turn On Delay
C
C
C
C
= 100nF (See Figure 23)
= 100nF (See Figure 23)
= 100nF (See Figure 23)
= 100nF (See Figure 23)
10
10
ms
ms
ms
ms
nF
ON
DEL
DEL
DEL
DEL
Delay Between V
Delay Between V
and V
DEL1
DEL2
DEL3
BOOST
ON
OFF
and V
10
OFF
Delay From V
ON
to V -slice Enabled
ON
10
C
Delay Capacitor
22
100
DEL
NOTE:
1. Guaranteed by design.
FN6270 Rev 0.00
May 15, 2006
Page 5 of 19
EL7640A, EL7641A, EL7642A
Pin Descriptions
PIN NAME
EL7642A
EL7641A
EL7640A
PIN FUNCTION
Upper reference voltage for switch output
Internal reference bypass terminal
SRC
1
1
2
1
2
REF
2
AGND
PGND
OUT1
NEG1
POS1
OUT2
NEG2
POS2
BGND
POS3
NEG3
OUT3
SUP
3
3
3
Analog ground for boost converter and control circuitry
Power ground for boost switch
4
4
4
5
5
5
Operational amplifier 1 output
6
6
6
Operational amplifier 1 inverting input
Operational amplifier 1 non-inverting input
Operational amplifier 2 output
7
7
7
8
8
-
9
9
-
Operational amplifier 2 inverting input
Operational amplifier 2 non-inverting input
Operational amplifier ground
10
11
12
-
10
11
15
16
17
14
-
-
11
-
Operational amplifier 3 non-inverting input
Operational amplifier 3 inverting input
Operational amplifier 3 output
-
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-
14
-
Amplifier positive supply rail. Bypass to BGND with 0.1µF capacitor
Operational amplifier 4 non-inverting input
Operational amplifier 4 inverting input
Operational amplifier 4 output
POS4
NEG4
OUT4
POS5
NEG5
OUT5
LX
-
-
-
-
-
-
Operational amplifier 5 non-inverting input
Operational amplifier 5 inverting input
Operational amplifier 5 output
-
-
-
-
21
22
23
24
25
26
27
28
29
30
31
32
21
22
23
24
25
26
27
28
29
30
31
32
Main boost regulator switch connection
Main supply input; bypass to AGND with 1µF capacitor
Main boost feedback voltage connection
Error amplifier compensation pin
IN
FB
COMP
FBP
Positive LDO feedback connection
DRVP
FBN
Positive LDO transistor drive
Negative LDO feedback connection
Negative LDO transistor driver
DRVN
DEL
Connection for switch delay timing capacitor
Input control for switch output
CTL
DRN
Lower reference voltage for switch output
COM
Switch output; when CTL = 1, COM is connected to SRC through a 15
resistor; when CTL = 0, COM is connected to DRN through a 30 resistor
FN6270 Rev 0.00
May 15, 2006
Page 6 of 19
EL7640A, EL7641A, EL7642A
Typical Performance Curves
94
92
90
88
86
84
82
80
78
100
90
80
V
=5V
IN
70
60
50
40
30
20
10
0
V
=3V
IN
V
=5V
IN
V
=3V
IN
0
200
400
600
800
1000 1200
0
200
400
600
800
1000 1200
LOAD CURRENT (mA)
LOAD CURRENT (mA)
FIGURE 1. BOOST EFFICIENCY AT V
= 12V (PI MODE)
FIGURE 2. BOOST EFFICIENCY AT V
= 12V (P MODE)
OUT
OUT
0
0
-2
-0.1
V
=3V
IN
V
=5.0V
IN
-4
-6
-0.2
-0.3
-0.4
-0.5
-0.6
-8
V
=3.3V
IN
V
=5V
IN
-10
-12
-14
0
200
400
600
800
1000 1200
0
200
400
600
800
1000 1200
LOAD CURRENT (mA)
LOAD CURRENT (mA)
FIGURE 3. BOOST LOAD REGULATION vs LOAD CURRENT
(PI MODE)
FIGURE 4. BOOST LOAD REGULATION vs LOAD CURRENT
(P MODE)
0.12
0.1
3.5
3
2.5
2
0.08
0.06
0.04
0.02
0
1.5
1
0.5
0
3
3.5
4
4.5
5
5.5
6
3
3.5
4
4.5
5
5.5
6
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 5. BOOST LINE REGULATION vs INPUT VOLTAGE
(PI MODE)
FIGURE 6. BOOST LINE REGULATION vs INPUT VOLTAGE
(P MODE)
FN6270 Rev 0.00
May 15, 2006
Page 7 of 19
EL7640A, EL7641A, EL7642A
EL7640A, EL7641A, EL7642A
Typical Performance Curves (Continued)
0
-0.05
-0.1
V
=20V
ON
BOOST OUTPUT
VOLTAGE
(AC COUPLING)
BOOST OUTPUT
CURRENT
-0.15
-0.2
V
=12V
BOOST
C
=30µF
OUT
-0.25
5
10
15
20
25
30
V
LOAD CURRENT (mA)
ON
FIGURE 7. BOOST PULSE LOAD TRANSIENT RESPONSE
FIGURE 8. V LOAD REGULATION
ON
0
0
-0.1
V
=-8V
OFF
-0.02
-0.04
-0.06
-0.08
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
V
=20V
ON
-0.1
I
=20mA
LOAD
-0.12
20
21
22
23
24
25
26
5
10
15
20
25
30
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
FIGURE 9. V
LINE REGULATION
FIGURE 10. V
LOAD REGULATION
OFF
ON
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
V
CDEL
V
BOOST
V
OFF
V
ON
V
=-8V
=50mA
OFF
I
LOAD
-15
-14
-13
-12
-11
-10
INPUT VOLTAGE (V)
TIME (20ms/DIV)
FIGURE 11. V
LINE REGULATION
FIGURE 12. START-UP SEQUENCE
OFF
FN6270 Rev 0.00
May 15, 2006
Page 8 of 19
EL7640A, EL7641A, EL7642A
Typical Performance Curves (Continued)
INPUT VOLTAGE
INPUT
V
BOOST
V
OUTPUT
OFF
V
ON
TIME (50µs/DIV)
TIME (20ms/DIV)
FIGURE 13. START-UP SEQUENCE
FIGURE 14. OP AMP RAIL-TO-RAIL INPUT/OUTPUT
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD -
QFN EXPOSED DIEPAD SOLDERED TO
PCB PER JESD51-5
JEDEC JESD51-3 AND SEMI G42-88
(SINGLE LAYER) TEST BOARD
0.8
3
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.857W
2.5
2
758mW
QFN32
=125°C/W
QFN32
=35°C/W
JA
JA
1.5
1
0.5
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 15. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 16. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
TABLE 1. RECOMMENDED COMPONENTS
Applications Information
The EL7640A, EL7641A, EL7642A provide a highly integrated
multiple output power solution for TFT-LCD applications. The
system consists of one high efficiency boost converter and two
DESIGNATION
DESCRIPTION
C , C , C
10µF, 16V X5R ceramic capacitor (1210)
TDK C3216X5R0J106K
1
2
3
low cost linear-regulator controllers (V
and V
) with
ON
OFF
D
1A 20V low leakage schottky rectifier
(CASE 457-04)
ON SEMI MBRM120ET3
1
multiple protection functions. The block diagram of the whole
part is shown in Figure 17. Table 1 lists the recommended
components.
D
, D , D
200mA 30V schottky barrier diode (SOT-23)
Fairchild BAT54S
11 12 21
The EL7640A, EL7641A, EL7642A integrate an N-channel
MOSFET in boost converter to minimize the external
L
6.8µH 1.3A Inductor
1
component counts and cost. The V , V
linear-regulators
are independently regulated by using external resistors. To
TDK SLF6025T-6R8M1R3-PF
ON OFF
Q
200mA 40V PNP amplifier (SOT-23)
Fairchild MMBT3906
11
21
achieve higher voltage than V
charge pumps may be used.
, one or multiple stage
BOOST
Q
200mA 40V NPN amplifier (SOT-23)
Fairchild MMBT3904
FN6270 Rev 0.00
May 15, 2006
Page 9 of 19
EL7640A, EL7641A, EL7642A
V
REF
REFERENCE
GENERATOR
OSCILLATOR
SLOPE COMP OSC
COMPENSATION
LX
PWM
LOGIC
CONTROLLER
BUFFER
VOLTAGE
AMPLIFIER
FBB
GM
AMPLIFIER
C
INT
CURRENT
PGND
AMPLIFIER
UVLO
COMPARATOR
CURRENT REF
CURRENT
LIMIT COMPARATOR
SS
+
SHUTDOWN
& START-UP
CONTROL
V
DRVP
FBP
REF
-
BUFFER
THERMAL
SHUTDOWN
UVLO
COMPARATOR
SS
+
DRVN
FBN
0.2V
-
BUFFER
0.4V
UVLO
COMPARATOR
FIGURE 17. BLOCK DIAGRAM
Figure 18 shows the block diagram of the boost controller.
It uses a summing amplifier architecture consisting of GM
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor current
cycle by cycle and terminates the PWM cycle if the current limit
is reached.
Boost Converter
The main boost converter is a current mode PWM converter
operating at a fixed frequency. The 1.2MHz switching
frequency enables the use of low profile inductor and
multilayer ceramic capacitors, which results in a compact, low
cost power system for LCD panel design.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current drawn
by the resistor network should be limited to maintain the overall
converter efficiency. The maximum value of the resistor
network is limited by the feedback input bias current and the
potential for noise being coupled into the feedback pin. A
resistor network in the order of 60k is recommended. The
boost converter output voltage is determined by the following
equation:
The boost converter can operate in continuous or
discontinuous inductor current mode. The EL7640A, EL7641A,
EL7642A are designed for continuous current mode, but they
can also operate in discontinuous current mode at light load. In
continuous current mode, current flows continuously in the
inductor during the entire switching cycle in steady state
operation. The voltage conversion ratio in continuous current
mode is given by:
V
1
BOOST
-----------------------
-------------
=
R
+ R
2
R
1
1
V
1 – D
--------------------
IN
V
=
V
BOOST
REF
Where D is the duty cycle of switching MOSFET.
FN6270 Rev 0.00
May 15, 2006
Page 10 of 19
EL7640A, EL7641A, EL7642A
The current through MOSFET is limited to 3A peak. This
restricts the maximum output current based on the following
equation:
Where I is peak to peak inductor ripple current, and is set
by:
L
V
D
f
S
IN
--------- ----
I
=
I
V
L
L
L
IN
--------
---------
I
=
I
–
LMT
OMAX
2
V
O
where f is the switching frequency.
S
SHUTDOWN
& START-UP
CONTROL
CLOCK
SLOPE
COMPENSATION
I
I
FB
CURRENT
AMPLIFIER
PWM
LX
REF
LOGIC
BUFFER
I
FB
FBB
GM
AMPLIFIER
I
REF
VOLTAGE
AMPLIFIER
REFERENCE
GENERATOR
PGND
COMP
FIGURE 18. THE BLOCK DIAGRAM OF THE BOOST CONTROLLER
FN6270 Rev 0.00
May 15, 2006
Page 11 of 19
EL7640A, EL7641A, EL7642A
capacitance drop as the voltage across them increases. C
in the
The following table gives typical values (margins are
OUT
equation above assumes the effective value of the capacitor at a
particular voltage and not the manufacturer’s stated value, measured at
zero volts.
considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, f and
S
I
:
LMT
TABLE 2.
L (µH)
Compensation
V
(V)
V
(V)
f
(MHz)
1.2
I
(mA)
IN
O
S
OMAX
The EL7640A, EL7641A, EL7642A can operate in either P
mode or PI mode. Connecting COMP pin directly to V will
3.3
3.3
3.3
5
9
6.8
6.8
6.8
6.8
6.8
6.8
898
IN
enable P mode; For better load regulation, use PI mode with a
2.2nF capacitor and a 180 resistor in series between COMP
pin and ground. To improve the transient response, either the
resistor value can be increased or the capacitor value can be
reduced, but too high resistor value or too low capacitor value
will reduce loop stability.
12
15
9
1.2
622
458
1360
944
694
1.2
1.2
5
12
15
1.2
5
1.2
Boost Feedback Resistors
As the boost output voltage, V
, is reduced below 12V
BOOST
Input Capacitor
The input capacitor is used to supply the current to the
converter. It is recommended that C be larger than 10F. The
the effective voltage feedback in the IC increases the ratio of
voltage to current feedback at the summing comparator
because R2 decreases relative to R1. To maintain stable
operation over the complete current range of the IC, the
voltage feedback to the FBB pin should be reduced
IN
reflected ripple voltage will be smaller with larger C . The
IN
voltage rating of input capacitor should be larger than
maximum input voltage.
proportionally, as V
is reduced, by means of a series
BOOST
Boost Inductor
resistor-capacitor network (R7 and C7) in parallel with R1, with
a pole frequency (fp) set to approximately 10kHz. for C2
effective = 10µF and 4kHz for C2 (effective) = 30µF.
The boost inductor is a critical part which influences the output
voltage ripple, transient response, and efficiency. Value of
3.3H to 10H inductor is recommended in applications to fit
the internal slope compensation. The inductor must be able to
handle the following average and peak current:
R7 = ((1/0.1 x R2) – 1/R1)^-1
C7 = 1/(2 x 3.142 x fp x R7)
I
Linear-Regulator Controllers (V
and V )
OFF
L
ON
--------
I
= I
+
LPK
LAVG
2
The EL7640A, EL7641A, EL7642A include 2 independent
linear-regulator controllers, in which there is one positive
I
O
-------------
I
=
LAVG
output voltage (V ), and one negative voltage (V
). The
1 – D
ON
OFF
V
and V
linear-regulator controller function diagram,
OFF
ON
application circuit and waveforms are shown in Figure 19 and
Figure 20 respectively.
Rectifier Diode
A high-speed diode is desired due to the high switching
frequency. Schottky diodes are recommended because of their
fast recovery time and low forward voltage. The rectifier diode
must meet the output current and peak inductor current
requirements.
V
BOOST
LX
0.1µF
LDO_ON
0.9V
Output Capacitor
PG_LDOP
CP (TO 36V)
0.1µF
+
-
36V
ESD
CLAMP
The output capacitor supplies the load directly and reduces the
ripple voltage at the output. Output ripple voltage consists of
two components: the voltage drop due to the inductor ripple
current flowing through the ESR of output capacitor, and the
charging and discharging of the output capacitor.
R
BP
700
DRVP
FBP
V
(TO 35V)
ON
R
P1
P2
C
ON
R
20k
V
– V
I
O
1
f
S
O
IN
+
-
----------------------- --------------- ----
V
= I
ESR +
LPK
RIPPLE
V
C
O
OUT
GMP
For low ESR ceramic capacitors, the output ripple is dominated
by the charging and discharging of the output capacitor. The
voltage rating of the output capacitor should be greater than
the maximum output voltage.
1: Np
FIGURE 19. V
FUNCTIONAL BLOCK DIAGRAM
ON
NOTE: Capacitors have a voltage coefficient that makes their effective
FN6270 Rev 0.00
May 15, 2006
Page 12 of 19
EL7640A, EL7641A, EL7642A
Set-up Output Voltage
Refer to Typical Application Diagram, the output voltages of
LX
V
, V
and V
are determined by the following
LOGIC
ON OFF
equations:
0.1µF
R
12
---------
V
= V
REF
1 +
ON
R
11
CP (TO -26V)
0.1µF
R
LDO_OFF
22
V
REF
---------
V
= V
+
V
– V
REF
OFF
REFN
REFN
R
PG_LDON
-
21
+
0.4V
R
N2
20k
Where V
= 1.2V, V
= 0.2V.
REFN
REF
FBN
High Charge Pump Output Voltage (>36V)
Applications
1: Nn
R
N1
V
(TO -20V)
OFF
In the applications where the charge pump output voltage is
over 36V, an external NPN transistor needs to be inserted in
between the DRVP pin and the base of pass transistor Q3 as
shown in Figure 21, or the linear regulator can control only one
stage charge pump and regulate the final charge pump output
as shown in Figure 22.
-
+
DRVN
C
OFF
GMN
R
BN
700
36V
ESD
CLAMP
FIGURE 20. V
FUNCTIONAL BLOCK DIAGRAM
OFF
V
IN
CHARGE PUMP
OUTPUT
OR V
BOOST
The V
ON
power supply is used to power the positive supply of
the row driver in the LCD panel. The DC/DC consists of an
external diode-capacitor charge pump powered from the
inductor (LX) of the boost converter, followed by a low dropout
linear regulator (LDO_ON). The LDO_ON regulator uses an
external PNP transistor as the pass element. The onboard
LDO controller is a wide band (>10MHz) transconductance
amplifier capable of 5mA output current, which is sufficient for
up to 50mA or more output current under the low dropout
700
Q11
DRVP
NPN
CASCODE
TRANSISTOR
V
ON
EL764X
FBP
condition (forced beta of 10). Typical V
voltage supported by
ON
EL7640A, EL7641A and EL7642A ranges from +15V to +36V.
A fault comparator is also included for monitoring the output
voltage. The under-voltage threshold is set at 25% below the
1.2V reference.
FIGURE 21. CASCODE NPN TRANSISTOR CONFIGURATION
FOR HIGH CHARGE PUMP OUTPUT VOLTAGE
(>36V)
The V
OFF
power supply is used to power the negative supply
of the row driver in the LCD panel. The DC/DC consists of an
external diode-capacitor charge pump powered from the
inductor (LX) of the boost converter, followed by a low dropout
linear regulator (LDO_OFF). The LDO_OFF regulator uses an
external NPN transistor as the pass element. The onboard
LDO controller is a wide band (>10MHz) transconductance
amplifier capable of 5mA output current, which is sufficient for
up to 50mA or more output current under the low dropout
condition (forced beta of 10). Typical V
voltage supported
OFF
by EL7640A, EL7641A and EL7642A ranges from -5V to -25V.
A fault comparator is also included for monitoring the output
voltage. The under-voltage threshold is set at 200mV above
the 0.2V reference level.
FN6270 Rev 0.00
May 15, 2006
Page 13 of 19
EL7640A, EL7641A, EL7642A
LX
0.1µF
V
BOOST
0.1µF
700
0.1µF 0.1µF
DRVP
Q11
V
ON
(>36V)
0.47µF
0.1µF
EL7642A
0.22µF
FBP
FIGURE 22. THE LINEAR REGULATOR CONTROLS ONE STAGE OF CHARGE PUMP
Calculation of the Linear Regulator Base-emitter
Resistors (RBP and RBN)
Charge Pump
To generate an output voltage higher than V
, single or
BOOST
For the pass transistor of the linear regulator, low frequency
gain (Hfe) and unity gain frequency (fT) are usually specified in
the datasheet. The pass transistor adds a pole to the loop
transfer function at fp = fT/Hfe. Therefore, in order to maintain
phase margin at low frequency, the best choice for a pass
device is often a high frequency low gain switching transistor.
Further improvement can be obtained by adding a base-
multiple stages of charge pumps are needed. The number of
stage is determined by the input and output voltage. For
positive charge pump stages:
V
+ V
– V
CE INPUT
OUT
V
-------------------------------------------------------------
N
POSITIVE
– 2 V
INPUT
F
where V is the dropout voltage of the pass component of the
CE
linear regulator. It ranges from 0.3V to 1V depending on the
transistor selected. V is the forward-voltage of the charge-
emitter resistor R (R , R , R
in the Functional Block
BE BP BL BN
Diagram), which increases the pole frequency to: fp = fT*(1+
Hfe *re/R )/Hfe, where re = KT/qIc. So choose the lowest
F
BE
pump rectifier diode.
value R in the design as long as there is still enough base
BE
current (I ) to support the maximum output current (I ).
The number of negative charge-pump stages is given by:
B
C
V
+ V
CE
We will take as an example the V
Fairchild MMBT3906 PNP transistor is used as the external
pass transistor, Q11 in the application diagram, then for a
linear regulator. If a
OUTPUT
ON
------------------------------------------------
N
NEGATIVE
V
– 2 V
INPUT
F
maximum V
operating requirement of 50mA the data sheet
To achieve high efficiency and low material cost, the lowest
number of charge-pump stages, which can meet the above
requirements, is always preferred.
ON
indicates Hfe_min = 60. The base-emitter saturation voltage is:
Vbe_max = 0.7V.
For the EL7640A, EL7641A and EL7642A, the minimum drive
current is:
I_DRVP_min = 2mA
Charge Pump Output Capacitors
Ceramic capacitor with low ESR is recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be chosen
by the following equation:
The minimum base-emitter resistor, RBP, can now be
calculated as:
I
RBP_min = VBE_max/(I_DRVP_min - Ic/Hfe_min) =
0.7V/(2mA - 50mA/60) = 600
OUT
------------------------------------------------------
C
OUT
2 V
f
OSC
RIPPLE
This is the minimum value that can be used – so, we now
choose a convenient value greater than this minimum value;
say 700. Larger values may be used to reduce quiescent
current, however, regulation may be adversely affected by
where f
is the switching frequency.
OSC
Discontinuous/Continuous Boost Operation and its
Effect on the Charge Pumps
supply noise if R is made too high in value.
BP
The EL7640A, EL7641A and EL7642A V
and V
OFF
ON
architecture uses LX switching edges to drive diode charge
pumps from which LDO regulators generate the V and
ON
FN6270 Rev 0.00
May 15, 2006
Page 14 of 19
EL7640A, EL7641A, EL7642A
supplies. It can be appreciated that should a regular
supply of LX switching edges be interrupted, for example
during discontinuous operation at light boost load currents,
V
Start-up Sequence
Figure 23 shows a detailed start-up sequence waveform. For a
successful power-up, there should be 6 peaks at V
When a fault is detected, the device will latch off until either EN
is toggled or the input supply is recycled.
OFF
.
CDEL
then this may affect the performance of V
and V
ON
OFF
regulation – depending on their exact loading conditions at the
time.
When the input voltage is higher than 2.4V, an internal current
To optimize V /V
regulation, the boundary of
discontinuous/continuous operation of the boost converter can
ON OFF
source starts to charge C
. During the initial slow ramp,
CDEL
the device checks whether there is a fault condition. If no fault
is found during the initial ramp, C is discharged after the
be adjusted, by suitable choice of inductor given V , V
switching frequency and the V
continuous operation.
,
IN OUT
CDEL
turns on at the peak of the first ramp.
current loading, to be in
BOOST
first peak. V
REF
Initially the boost is not enabled so V
rises to V -
IN
BOOST
through the output diode. Hence, there is a step at
The following equation gives the boundary between
discontinuous and continuous boost operation. For continuous
operation (LX switching every clock cycle) we require that:
V
V
DIODE
during this part of the start-up sequence.
BOOST
V
soft-starts at the beginning of the third ramp, and is
BOOST
I(V
_load) > D*(1-D)*V /(2*L*F
IN
)
BOOST
OSC
checked at the end of this ramp. The soft-start ramp depends
on the value of the C capacitor. For C of 100nF, the
where the duty cycle, D = (V
BOOST
– V )/V
DEL DEL
IN BOOST
soft-start time is ~7ms.
For example, with V = 5V, F
= 1.2MHz and V
=
IN OSC BOOST
V
turns on at the start of the fourth peak.
12V we find continuous operation of the boost converter can
be guaranteed for:
OFF
V
V
is enabled at the beginning of the sixth ramp. V
are checked at end of this ramp.
and
OFF
ON
ON
L = 10µH and I(V
) > 51mA
BOOST
L = 6.8µH and I(V
L = 3.3µH and I(V
) > 74mA
) > 153mA
BOOST
BOOST
FN6270 Rev 0.00
May 15, 2006
Page 15 of 19
EL7640A, EL7641A, EL7642A
V
CDEL
IN
V
REF
V
BOOST
t
ON
t
DEL1
V
OFF
t
DEL2
V
ON
V
CIRCUIT
ON SLICE
t
DEL3
START-UP SEQUENCE
TIMED BY C
NORMAL
OPERATION
FAULT
PRESENT
NOTE: Not to scale
DEL
FIGURE 23. START-UP SEQUENCE
be at least 1/5 of the value of C
(see above). Note that with
Component Selection for Start-up Sequencing and
Fault Protection
REF
100nF on C
the fault time-out will be typically 23ms and the
DEL
use of a larger/smaller value will vary this time proportionally
(e.g. 1µF will give a fault time-out period of typically 230ms).
The C
capacitor is typically set at 220nF and is required to
REF
stabilize the V
output. The range of C
is from 22nF to
REF
REF
1µF and should not be more than five times the capacitor on
to ensure correct start-up operation.
Fault Sequencing
C
DEL
The EL7640A, EL7641A and EL7642A have an advanced fault
detection system which protects the IC from both adjacent pin
shorts during operation and shorts on the output supplies. A
high quality layout/design of the PCB, in respect of grounding
The C
capacitor is typically 100nF and has a usable range
DEL
from 22nF minimum to several microfarads – only limited by
the leakage in the capacitor reaching µA levels. C
should
DEL
FN6270 Rev 0.00
May 15, 2006
Page 16 of 19
EL7640A, EL7641A, EL7642A
quality and decoupling is necessary to avoid falsely triggering
the fault detection scheme – especially during start-up. The
user is directed to the layout guidelines and component
selection sections to avoid problems during initial evaluation
and prototype PCB generation.
–3dB bandwidth of the device will decrease and the peaking
will increase. The amplifiers drive 10pF loads in parallel with
10k with just 1.5dB of peaking, and 100pF with 6.4dB of
peaking. If less peaking is desired in these applications, a
small series resistor (usually between 5 and 50) can be
placed in series with the output. However, this will obviously
reduce the gain. Another method of reducing peaking is to add
a “snubber” circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values of
150 and 10nF are typical. The advantage of a snubber is that
it does not draw any DC load current and reduce the gain.
V
-Slice Circuit
ON
The V -slice Circuit functions as a three way multiplexer,
ON
switching the voltage on COM between ground, DRN and SRC,
under control of the start-up sequence and the CTL pin.
During the start-up sequence, COM is held at ground via an
NDMOS FET, with ~1k impedance. Once the start-up
sequence has completed, CTL is enabled and acts as a
multiplexer control such that if CTL is low, COM connects to
DRN through a 5internal MOSFET, and if CTL is high, COM
connects to SRC via a 30MOSFET.
Over-Temperature Protection
An internal temperature sensor continuously monitors the die
temperature. In the event that the die temperature exceeds the
thermal trip point, the device will be latched off until either the
input supply voltage or enable is cycled.
The slew rate of start-up of the switch control circuit is mainly
restricted by the load capacitance at COM pin as in the
following equation:
Layout Recommendation
The device’s performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially at
high switching frequency.
V
V
t
g
-------
------------------------------------
i
=
R R C
L
L
Where V is the supply voltage applied to the switch control
g
There are some general guidelines for layout:
circuit, R is the resistance between COM and DRN or SRC
i
including the internal MOSFET r
, the trace resistance
DS(ON)
and the resistor inserted, R is the load resistance of the switch
1. Place the external power components (the input capacitors,
output capacitors, boost inductor and output diodes, etc.) in
close proximity to the device. Traces to these components
should be kept as short and wide as possible to minimize
parasitic inductance and resistance.
L
control circuit, and C is the load capacitance of the switch
L
control circuit.
In the Typical Application Circuit, R , R and C give the bias
to DRN based on the following equation:
8
9
8
2. Place V
and V
bypass capacitors close to the pins.
DD
REF
3. Reduce the loop with large AC amplitudes and fast slew
rate.
V
R + A
R
ON
9
VDD 8
------------------------------------------------------------
=
V
DRN
R
+ R
9
8
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
and R can be adjusted to adjust the slew rate.
10
Op Amps
5. The power ground (PGND) and signal ground (SGND) pins
should be connected at only one point.
The EL7640A, EL7641A and EL7642A have 1, 3 and 5
amplifiers respectively. The op amps are typically used to drive
6. The exposed die plate, on the underneath of the package,
should be soldered to an equivalent area of metal on the
PCB. This contact area should have multiple via
connections to the back of the PCB as well as connections
to intermediate PCB layers, if available, to maximize
thermal dissipation away from the IC.
the TFT-LCD backplane (V
) or the gamma-correction
COM
divider string. They feature rail-to-rail input and output
capability, they are unity gain stable, and have low power
consumption (typical 600A per amplifier). The EL7640A,
EL7641A and EL7642A have a –3dB bandwidth of 12MHz
while maintaining a 10V/s slew rate.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die plate
should be maximized and spread out as far as possible
from the IC. The bottom and top PCB areas especially
should be maximized to allow thermal dissipation to the
surrounding air.
Short Circuit Current Limit
The EL7640A, EL7641A and EL7642A will limit the short circuit
current to ±180mA if the output is directly shorted to the
positive or the negative supply. If an output is shorted for a long
time, the junction temperature will trigger the Over
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for feedback resistor networks (R1, R11, R41)
Temperature Protection limit and hence the part will shut down.
Driving Capacitive Loads
EL7640A, EL7641A and EL7642A can drive a wide range of
capacitive loads. As load capacitance increases, however, the
FN6270 Rev 0.00
May 15, 2006
Page 17 of 19
EL7640A, EL7641A, EL7642A
and the V
capacitor, C22, the C
DELAY
capacitor C7 and
A demo board is available to illustrate the proper layout
implementation.
REF
the integrator capacitor C23.
9. Minimize feedback input track lengths to avoid switching
noise pick-up.
Typical Application Circuit
D11
0.1µF
V
CP
D21
D12
0.1µF
0.1µF
0.1µF
V
CN
A
(9V)
V
VDD
IN
(2.6V-5.5V)
D1
L1
6.8µH
10µF
C1
10
10µFx2
LX
C2
64.9k
IN
R2
R1
FB
470nF
BOOST
10.2k
R OPEN
7
PGND
C
OPEN
7
180 COMP
2.2nF
700
GND
V
V
CP
CN
V
700
DRVN
DRVP
NEG
REG
POS
REG
0.1µF
0.1µF
Q21
Q11
V
ON
(24.5V)
82k
R12
R11
R22
NEG
182k
FBN
REF
FBP
(-8V)
470nF
10k
9.76k
470nF
R21
REF
SRC
0.1µF
CTL
DEL
TO GATE
DRIVER IC
CONTROL
COM
SW
INPUT
R
8
CTL
68k
R
R
9
1k
10
1k
100nF
DRN
A
VDD
C
8
0.1µF
OUT3
POS3
-
+
V
V
GAMMA
OP3
GAMMA SET
A
VDD
V
MAIN
NEG4
OUT4
POS4
NEG5
OUT5
POS5
V
V
V
V
COM FB4
COM FB3
COM3
-
+
-
+
V
COM4
OP4
OP2
OP5
OP1
V
COM SET4
COM SET3
NEG2
OUT2
POS2
NEG1
OUT1
POS1
V
V
V
V
COM FB2
COM FB1
COM1
-
+
-
+
V
COM2
COM SET2
V
COM SET1
AGND
FN6270 Rev 0.00
May 15, 2006
Page 18 of 19
EL7640A, EL7641A, EL7642A
QFN Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
© Copyright Intersil Americas LLC 2006. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6270 Rev 0.00
May 15, 2006
Page 19 of 19
相关型号：
EL7642BILTZ-T13
SWITCHING REGULATOR, 1350kHz SWITCHING FREQ-MAX, QCC32, 5 X 5 MM, ROHS COMPLIANT, MO-220, TQFN-32
RENESAS
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