F0453CEVB [RENESAS]
Dual Path RF Switch with LNA and DVGA 3300MHz to 4000MHz;
| 型号： | F0453CEVB |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual Path RF Switch with LNA and DVGA 3300MHz to 4000MHz |
| 文件： | 总30页 (文件大小：1798K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Path RF Switch with LNA
and DVGA 3300MHz to 4000MHz
F0453C
Datasheet
Description
Features
The F0453C is an integrated dual-path RF front-end consisting of
an RF switch and two gain stages with 6dB gain control used in
the analog front-end receiver of an Active Antenna System (AAS).
The F0453C supports frequencies from 3300MHz to 4000MHz.
.
Gain at 3500MHz
• 35dB typical in High Gain Mode
• 29dB typical in Low Gain Mode
1.35dB NF at 3500MHz
+23dBm OIP3 at 3500MHz
OP1dB at 3500MHz
.
.
.
The F0453C provides 35dB gain with +23dBm OIP3, +15dBm
output P1dB, and 1.35dB noise figure at 3500MHz. Gain is
reduced 6dB in a single step with a maximum gain settling time of
31ns. The device uses a single 3.3V supply and 130mA of IDD.
• +15dBm in High Gain Mode
• +14dBm in Low Gain Mode
The F0453C is offered in a 6 × 6 × 0.75 mm, 32-LGA package
with 50Ω input and output amplifier impedances for ease of
integration into the signal path.
. 50Ω single-ended input / output amplifier impedances
.
.
.
.
.
IDD = 130mA
Independent Standby Mode for power savings
Supply voltage: +3.15V to +3.45V
6 × 6 mm, 32-pin LGA package
Competitive Advantage
-40°C to +105°C exposed pad operating temperature range
.
.
.
.
High integration
Low noise and high linearity
On-chip matching and bias
Extremely low current consumption
Block Diagram
Typical Applications
.
.
.
.
Multi-mode, Multi-carrier receivers
AAS Rx Front-End
4.5G (LTE Advanced)
SW1_IN
5G NR band n48, n77, and n78
STBY1
ATT1_CTRL
SW1_CTRL
SW2_CTRL
ATT2_CTRL
STBY2
SW2_IN
© 2020 Renesas Electronics Corporation
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F0453C Datasheet
Contents
Pin Assignments....................................................................................................................................................................................................4
Pin Descriptions.....................................................................................................................................................................................................5
Absolute Maximum Ratings...................................................................................................................................................................................6
Recommended Operating Conditions ...................................................................................................................................................................7
Electrical Characteristics: General ........................................................................................................................................................................8
Electrical Characteristics: 3300MHz [1]...............................................................................................................................................................10
Electrical Characteristics: 3300MHz [2]...............................................................................................................................................................11
Electrical Characteristics: 3400MHz–3600MHz [1]..............................................................................................................................................12
Electrical Characteristics: 3400MHz–3600MHz [2]..............................................................................................................................................13
Electrical Characteristics: 3600MHz–3800MHz [1]..............................................................................................................................................14
Electrical Characteristics: 3600MHz–3800MHz [2]..............................................................................................................................................15
Electrical Characteristics: 3800MHz–4000MHz [1]..............................................................................................................................................16
Electrical Characteristics: 3800MHz–4000MHz [2]..............................................................................................................................................17
Thermal Characteristics.......................................................................................................................................................................................18
Typical Operating Conditions ..............................................................................................................................................................................18
Programming.......................................................................................................................................................................................................18
Typical Performance Characteristics...................................................................................................................................................................19
Evaluation Kit Picture ..........................................................................................................................................................................................23
Evaluation Kit Circuit ...........................................................................................................................................................................................24
Application Information........................................................................................................................................................................................26
Power Supplies...........................................................................................................................................................................................26
Control Pin Interface...................................................................................................................................................................................26
Marking Diagram .................................................................................................................................................................................................27
Package Outline Drawings ..................................................................................................................................................................................27
Ordering Information............................................................................................................................................................................................27
Revision History...................................................................................................................................................................................................27
List of Figures
Figure 1. Pin Assignments for 6 × 6 × 0.75 mm 32-pin LGA – Top View ...........................................................................................................4
Figure 2. Rx Mode Gain (High Gain) ................................................................................................................................................................19
Figure 3. Rx Mode Gain (Low Gain).................................................................................................................................................................19
Figure 4. Rx Mode Reverse Isolation (High Gain)............................................................................................................................................19
Figure 5. Rx Mode Reverse Isolation (Low Gain).............................................................................................................................................19
Figure 6. Rx Mode Input Return Loss (High Gain)............................................................................................................................................19
Figure 7. Rx Mode Input Return Loss (Low Gain) ............................................................................................................................................19
Figure 8. Rx Mode Output Return Loss (High Gain).........................................................................................................................................20
Figure 9. Rx Mode Output Return Loss (Low Gain)..........................................................................................................................................20
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F0453C Datasheet
Figure 10. Rx Mode OP1dB (High Gain) ............................................................................................................................................................20
Figure 11. Rx Mode OP1dB (Low Gain).............................................................................................................................................................20
Figure 12. Rx Mode OIP3 (High Gain)................................................................................................................................................................20
Figure 13. Rx Mode OIP3 (Low Gain) ................................................................................................................................................................20
Figure 14. Rx Mode Noise Figure (High Gain) ...................................................................................................................................................21
Figure 15. Rx Mode Noise Figure (Low Gain) ....................................................................................................................................................21
Figure 16. Tx Mode RF Switch Isolation.............................................................................................................................................................21
Figure 17. Rx Mode Channel Isolation ...............................................................................................................................................................21
Figure 18. Stability K-factor ................................................................................................................................................................................21
Figure 19. Gain Settling Time.............................................................................................................................................................................22
Figure 20. Gain Step Phase Settling Time .........................................................................................................................................................22
Figure 21. Power OFF Switching Time...............................................................................................................................................................22
Figure 22. Power ON Switching Time.................................................................................................................................................................22
Figure 23. Power OFF to Standby Mode............................................................................................................................................................22
Figure 24. Power ON from Standby Mode..........................................................................................................................................................22
Figure 25. Evaluation Kit: Top View....................................................................................................................................................................23
Figure 26. Evaluation Kit: Bottom View ..............................................................................................................................................................23
Figure 27. Electrical Schematic ..........................................................................................................................................................................24
Figure 28. Control Pin Interface Schematic........................................................................................................................................................26
List of Tables
Table 1. Pin Descriptions...................................................................................................................................................................................5
Table 2. Absolute Maximum Ratings.................................................................................................................................................................6
Table 3. Recommended Operating Conditions .................................................................................................................................................7
Table 4. Electrical Characteristics: General ......................................................................................................................................................8
Table 5. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance..........................................................................................10
Table 6. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance........................................................11
Table 7. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance..........................................................................................12
Table 8. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance........................................................13
Table 9. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance..........................................................................................14
Table 10. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance........................................................15
Table 11. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance..........................................................................................16
Table 12. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance........................................................17
Table 13. Thermal Characteristics.....................................................................................................................................................................18
Table 14. Gain Step Truth Table .......................................................................................................................................................................18
Table 15. Standby and RF Switch Truth Table..................................................................................................................................................18
Table 16. Bill of Materials (BOM).......................................................................................................................................................................25
© 2020 Renesas Electronics Corporation
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F0453C Datasheet
Pin Assignments
Figure 1. Pin Assignments for 6 × 6 × 0.75 mm 32-pin LGA – Top View
ATT1_CTRL
1
GND
SW1_IN
GND
NC
24
23
22
21
20
19
18
17
STBY1
2
SW1_CTRL
GND
3
4
5
6
7
8
GND
NC
SW2_CTRL
STBY2
GND
SW2_IN
GND
ATT2_CTRL
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F0453C Datasheet
Pin Descriptions
Table 1.
Pin Descriptions
Number
Name
Description
1-bit 6dB gain control for path 1. (Low/open = no attenuation; High = 6dB attenuation). A 500kΩ pull-down
resistor is connected between this input and GND.
1
2
ATT1_CTRL
STBY1
Standby (Low/open = path 1 power ON; High = path 1 power OFF). A 500kΩ pull-down resistor is connected
between this input and GND.
RF SWITCH 1 control (Low/open = select main RX PATH 1; High = termination). SW1_CTRL also puts path 1
into Standby Mode for minimum current consumption. A 500kΩ pull-down resistor is connected between this
input and GND.
3
SW1_CTRL
GND
4, 5, 9, 11,
13, 15, 17,
19, 22, 24,
Ground these pins.
26, 28, 30, 32
Power supply. Bypass to GND with capacitors shown in the F0453C Application Circuit as close as possible to
pin.
12, 14, 27, 29
VDD
SW2_CTRL
STBY2
RF SWITCH 2 control (Low/open = select main RX PATH 2; High = termination). SW2_CTRL also puts path 2
into Standby Mode for minimum current consumption. A 500kΩ pull-down resistor is connected between this
input and GND.
6
7
Standby (Low/open = path 2 power ON; High = path 2 power OFF). A 500kΩ pull-down resistor is connected
between this input and GND.
1-bit 6dB gain control for path 2. (Low/open = no attenuation; High = 6dB attenuation). A 500kΩ pull-down
resistor connects between this input and GND.
8
ATT2_CTRL
RX2_OUT
SW2_OUT
10
16
RF output path 2 matched to 50Ω. Use external DC block as close to the pin as possible.
RF2 switch output matched to 50Ω. Use external 50Ω terminating resistor with proper power rating as required
for the application.
18
23
SW2_IN
SW1_IN
RF2 switch input matched to 50Ω. Use external DC block as close to the pin as possible.
RF1 switch input matched to 50Ω. Use external DC block as close to the pin as possible.
RF1 switch output matched to 50Ω. Use external 50Ω terminating resistor with proper power rating as required
for the application.
25
31
SW1_OUT
RX1_OUT
NC
RF output path 1 matched to 50Ω. Use external DC block as close to the pin as possible.
These pins can be left unconnected, or be connected to ground (recommended). Use a via as close to the pin
as possible if grounded.
20, 21
Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground
vias to provide heat transfer out of the device into the PCB ground planes. These multiple via grounds are also
required to achieve the noted RF performance.
— EPAD
© 2020 Renesas Electronics Corporation
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F0453C Datasheet
Absolute Maximum Ratings
Stresses beyond those listed below may cause permanent damage to the device. Functional operation of the device at these or any other
conditions beyond those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Table 2.
Absolute Maximum Ratings
Parameter
Symbol
VDD
Minimum
-0.3
Maximum
+3.6
Units
VDD to GND
V
V
STBY1, STBY2, ATT1_CTRL, ATT2_CTRL, SW1_CTRL, SW2_CTRL to GND
VCTRL
-0.3
VDD + 0.25
SW1_IN, SW2_IN, RX1_OUT, RX2_OUT, SW1_OUT, SW2_OUT to GND
Externally Applied DC Voltage
VSW
-50
50
mV
Tx Mode CW Average Input Power +7.5dB PAR at SW1_IN, SW2_IN ports,
10s, 89% Duty Cycle
PABS_TX
+31
+33 [b]
dBm
50Ω, TEPAD = 105°C [a], VDD = +3.3V
Rx Mode Average Input Power +7.5dB PAR at SW1_IN, SW2_IN ports,
1 hour single event, 50% Duty Cycle
PABS_RX
+8
dBm
50Ω, TEPAD = 105°C [a], VDD = +3.3V
Storage Temperature Range
TST
-65
+150
+260
°C
°C
Lead Temperature (soldering, 10s)
TLEAD
Electrostatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
1500
VESDHBM
V
V
(Class 1C)
Electrostatic Discharge – CDM
(JEDEC JS-002-2014)
500
VESDCDM
(Class C2a)
ALL pins except pins 16, 18, 23, 25
Electrostatic Discharge – CDM
(JEDEC JS-002-2014)
Pins 16, 18, 23, 25
125
VESDCDM
V
(Class C0b)
[a] TEPAD = Temperature of the exposed paddle.
[b] RF input exposures greater than +31dBm and up to +33dBm for multiple extended periods will affect device reliability and lifetime if the maximum
recommended input junction temperature is exceeded.
© 2020 Renesas Electronics Corporation
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F0453C Datasheet
Recommended Operating Conditions
Table 3.
Recommended Operating Conditions
Parameter
Symbol
VDD
Condition
Minimum
3.15
Typical
Maximum
Units
V
Power Supply Voltage
3.3
3.45
+105
4000
Operating Temperature Range
RF Frequency Range
TEPAD
fRF
Exposed Paddle
-40
°C
3300
MHz
Tx Mode CW Average Input Power,
+7.5dB PAR, Full Life Time [a]
PMAX_TX
89% Duty Cycle
89% Duty Cycle
+30 [b]
-25
dBm
dBm
50Ω, VDD = +3.3V
Rx Mode CW Average Input Power,
+7.5dB PAR, Full Life Time [a]
PMAX_RX
50Ω, VDD = +3.3V
Port Impedance (SW1_IN, SW2_IN,
RX1_OUT, RX2_OUT)
ZRF
TJ
50
Ω
Junction Temperature
+125
°C
[a] Assumes device environmental temperature cycling within the specified exposed pad operating temperature range of -40°C and 105°C and a
maximum junction temperature of 125°C.
[b] Operation beyond the maximum recommended operating input power level should be limited and have reduced exposed pad temperatures to
maintain device reliability per foundry guidelines. Electrical characteristics and lifetime are not guaranteed for RF input power levels beyond what
is specified in this table.
© 2020 Renesas Electronics Corporation
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F0453C Datasheet
Electrical Characteristics: General
Table 4.
Electrical Characteristics: General
See the F0453C Application Circuit. Specifications apply when operated as an Rx RF amplifier with VDD = +3.3V, TEPAD = +25°C, STBY = LOW,
RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Lower of
(VDD, 3.3)
Logic Input High Threshold
VIH
1.17 [a]
V
Logic Input Low Threshold
Logic Current
VIL
-0.3
0.63
10
V
IIH, IIL
For each control pin
2 paths in Rx Mode
-10
µA
130
70
180
1 path in Rx Mode
1 path in Tx Mode
100
1 path in Rx Mode
DC Current
IDD
67
5
mA
1 path in Standby Mode
1 path in Tx Mode
1 path in Standby Mode
2 paths in Standby Mode
5
6
Gain Step
GSTEP
dB
dB
Relative to maximum gain,
over-voltage, and temperature
Gain Step Absolute Error
Relative Phase Gain Step
Gain Step Settling Time [b]
GSTEP_ERR
GSTEP_PH
GSTEP_SET
±0.5
27
deg
ns
50% control logic to RF output
within ±0.1dB of final value
21
31
30
50% control logic to RF output
within ±1 degree of final value
Gain Step Phase Settling Time [b]
Power ON Switching Time [b]
GSTEP_PHSET
19
ns
To Rx Mode from Tx Mode
50% control logic to RF output
settled to within ±0.1dB of final
value
SWON
1
µs
To Tx Mode from Rx Mode
50% control logic to RF input
settled within ±0.1dB of final
value
Power OFF Switching Time [b]
SWOFF
0.5
µs
© 2020 Renesas Electronics Corporation
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F0453C Datasheet
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
To Rx Mode from Standby
Mode
Power ON from Standby Mode [b]
SWON_STANDBY
1
1
µs
50% STBY to RF output settled
within ±0.1dB of final value
To Standby Mode from Rx
Mode
Power OFF to Standby Mode [b]
SWOFF_STANDBY
µs
50% STBY to gain below
-25dB from max gain
[a] Items in the Minimum/Maximum columns in bold italics are guaranteed by test. Items in the Minimum/Maximum columns NOT in bold italics are
guaranteed by design characterization.
[b] fRF = 3500MHz. Assumes the control signal is clean and no external RC circuitry is required on the pin. Adding RC circuitry increases switching
time.
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Electrical Characteristics: 3300MHz [1]
Table 5.
Electrical Characteristics: RX Path in Rx Mode Cascaded Performance
See the F0453C Application Circuit. Specifications apply when operated as an Rx RF amplifier with VDD = +3.3V, fRF = 3300MHz, TEPAD = +25°C,
STBY = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Measured at SW1_IN, SW2_IN
High Gain Mode
8 [a]
Measured at SW1_IN, SW2_IN
Low Gain Mode
Input Return Loss
RLIN
dB
6
Measured at SW1_IN, SW2_IN
TX mode [b] [c]
11
Measured at RX1_OUT,
RX2_OUT,
Output Return Loss
Reverse Isolation
RLOUT
5
dB
dB
High/Low Gain Modes
RX1_OUT to SW1_IN, or
RX2_OUT to SW2_IN
ISOREV
55
65
GHG
GHG_TEMP
GLG
High Gain Mode
TEPAD = -40 to 105°C
Low Gain Mode
32
31
34.5
37
38
Gain
dB
dB
Gain Attenuated
29
Measured at antenna port
ideally matched to LNA
1.2
1.4
1.9
Noise Figure
NF
dB
TEPAD = 105°C
Low Gain Mode
1.2
[a] Items in Minimum/Maximum columns in bold italics are guaranteed by test. Items in Minimum/Maximum columns NOT in bold italics are
guaranteed by design characterization.
[b] Specification reflects use of an external termination resistor at SW1_OUT, SW2_OUT with a RL > 22dB.
[c] Performance can be further improved with tuning at the SW1_OUT and SW2_OUT ports.
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Electrical Characteristics: 3300MHz [2]
Table 6.
Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance
See the F0453C Application Circuit. Specifications apply when operated as an Rx RF amplifier with VDD = +3.3V, fRF = 3300MHz, TEPAD = +25°C,
STBY = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Pout = 0dBm/tone
Minimum
Typical
Maximum
Units
OIP31
23
5MHz tone separation
Pout = 0dBm/tone
OIP32
OIP33
5MHz tone separation
TEPAD = -40 to 105°C
20
Pout = 0dBm/tone
5MHz tone separation
Low Gain Mode
Output Third-Order Intercept Point
dBm
22
Pout = 0dBm/tone
5MHz tone separation
Low Gain Mode
OIP34
18
TEPAD = -40 to 105°C
OP1dB1
OP1dB2
OP1dB3
OP1dB4
High Gain Mode [b]
15
14
High Gain Mode
G-24
G-18
TEPAD = -40 to 105°C
Output 1dB Compression
dBm
Low Gain Mode
Low Gain Mode
TEPAD = -40 to 105°C
RFISO1 = �ꢀꢁ1_ꢂꢃꢄ
ꢅ
ꢀꢁ2_ꢂꢃꢄ
ꢆꢇ
with -60 ≤ SW1_IN ≤ -30dBm
Channel Isolation
ISOCH
55
59
65
69
dB
dB
RFISO2 = �ꢀꢁ2_ꢂꢃꢄ
ꢅ
ꢀꢁ1_ꢂꢃꢄ
ꢆꢇ
with -60 ≤ SW2_IN ≤ -30dBm
Tx Mode
RF Switch Isolation
ISOSW
Measured at SW_IN to
RX_OUT of the same channel
[a] Items in Minimum/Maximum columns in bold italics are guaranteed by test. Items in Minimum/Maximum columns NOT in bold italics are
guaranteed by design characterization.
[b] In the OP1dB calculation formula, “G” denotes the gain of each part instance at the frequency of interest and appropriate High / Low gain state.
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Electrical Characteristics: 3400MHz–3600MHz [1]
Table 7.
Electrical Characteristics: RX Path in Rx Mode Cascaded Performance
See the F0453C Application Circuit. Specifications apply when operated as an Rx RF amplifier with VDD = +3.3V, fRF = 3500MHz, TEPAD = +25°C,
STBY = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Measured at SW1_IN, SW2_IN
High Gain Mode,
13 [a]
fRF = 3400MHz to 3600MHz
Measured at SW1_IN, SW2_IN
Low Gain Mode,
Input Return Loss
RLIN
dB
12
12
fRF = 3400MHz to 3600MHz
Measured at SW1_IN, SW2_IN
TX mode [b] [c]
Measured at RX1_OUT,
RX2_OUT,
Output Return Loss
RLOUT
6
dB
dB
High/Low Gain Modes,
fRF = 3400MHz to 3600MHz
Reverse Isolation, RX1_OUT to
SW1_IN, or RX2_OUT to SW2_IN
ISOREV
fRF = 3400MHz to 3600MHz
54
64
35
GHG
GHG_TEMP
GLG
High Gain Mode
TEPAD = -40 to 105°C
Low Gain Mode
32
31
37
38
Gain
dB
dB
Gain Attenuated
25.5
29
31.5
f
RF = 3400MHz to 3600MHz
(Difference between maximum
and minimum gain in each
100MHz subrange within the
specified frequency range)
Gain Ripple
Noise Figure
GRIPPLE
±0.2
dB
dB
Measured at antenna port
ideally matched to LNA
1.35
1.35
1.55
2.1
NF
TEPAD = 105°C
Low Gain Mode
[a] Items in Minimum/Maximum columns in bold italics are guaranteed by test. Items in Minimum/Maximum columns NOT in bold italics are
guaranteed by design characterization.
[b] Specification reflects use of an external termination resistor at SW1_OUT, SW2_OUT with a RL > 22dB.
[c] Performance can be further improved with tuning at the SW1_OUT and SW2_OUT ports.
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Electrical Characteristics: 3400MHz–3600MHz [2]
Table 8.
Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance
See the F0453C Application Circuit. Specifications apply when operated as an Rx RF amplifier with VDD = +3.3V, fRF = 3500MHz, TEPAD = +25°C,
STBY = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Pout = 0dBm/tone
Minimum
Typical
Maximum
Units
OIP31
23
5MHz tone separation
Pout = 0dBm/tone
OIP32
OIP33
5MHz tone separation
TEPAD = -40 to 105°C
20
Pout = 0dBm/tone
5MHz tone separation
Low Gain Mode
Output Third-Order Intercept Point
dBm
23
Pout = 0dBm/tone
5MHz tone separation
Low Gain Mode
OIP34
18
TEPAD = -40 to 105°C
OP1dB1
OP1dB2
OP1dB3
OP1dB4
High Gain Mode [b]
15
14
High Gain Mode
G-24
G-18
TEPAD = -40 to 105°C
Output 1dB Compression
dBm
Low Gain Mode
Low Gain Mode
TEPAD = -40 to 105°C
RFISO1 = �ꢀꢁ1_ꢂꢃꢄ
ꢅ
ꢀꢁ2_ꢂꢃꢄ
ꢆꢇ
with -60 ≤ SW1_IN ≤ -30dBm
Channel Isolation
ISOCH
55
59
65
69
dB
dB
RFISO2 = �ꢀꢁ2_ꢂꢃꢄ
ꢅ
ꢀꢁ1_ꢂꢃꢄ
ꢆꢇ
with -60 ≤ SW2_IN ≤ -30dBm
Tx Mode
RF Switch Isolation
ISOSW
Measured at SW_IN to
RX_OUT of the same channel
[a] Items in Minimum/Maximum columns in bold italics are guaranteed by test. Items in Minimum/Maximum columns NOT in bold italics are
guaranteed by design characterization.
[b] In the OP1dB calculation formula, “G” denotes the gain of each part instance at the frequency of interest and appropriate High / Low gain state.
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Electrical Characteristics: 3600MHz–3800MHz [1]
Table 9.
Electrical Characteristics: RX Path in Rx Mode Cascaded Performance
See the F0453C Application Circuit. Specifications apply when operated as an Rx RF amplifier with VDD = +3.3V, fRF = 3700MHz, TEPAD = +25°C,
STBY = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Measured at SW1_IN, SW2_IN
High Gain Mode,
13 [a]
fRF = 3600MHz to 3800MHz
Measured at SW1_IN, SW2_IN
Low Gain Mode,
Input Return Loss
RLIN
dB
16
12
fRF = 3600MHz to 3800MHz
Measured at SW1_IN, SW2_IN
[b] [c]
TX mode
Measured at RX1_OUT,
RX2_OUT,
Output Return Loss
RLOUT
7
dB
High/Low Gain Modes,
fRF = 3600MHz to 3800MHz
Reverse Isolation, S12
Gain
ISOREV
GHG
fRF = 3600MHz to 3800MHz
High Gain Mode
53
32
30
25
63
34
dB
dB
dB
37
38
GHG_TEMP
GLG
TEPAD = -40 to 105°C
Low Gain Mode
Gain Attenuated
29
31.5
f
RF = 3600MHz to 3800MHz
(Difference between maximum
and minimum gain in each
100MHz subrange within the
specified frequency range)
Gain Ripple
Noise Figure
GRIPPLE
±0.4
dB
dB
Measured at antenna port
ideally matched to LNA
1.4
1.4
1.6
NF
TEPAD = 105°C
Low Gain Mode
2.25
[a] Items in Minimum/Maximum columns in bold italics are guaranteed by test. Items in Minimum/Maximum columns NOT in bold italics are
guaranteed by design characterization.
[b] Specification reflects use of an external termination resistor at SW1_OUT, SW2_OUT with a RL > 22dB.
[c] Performance can be further improved with tuning at the SW1_OUT and SW2_OUT ports.
© 2020 Renesas Electronics Corporation
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F0453C Datasheet
Electrical Characteristics: 3600MHz–3800MHz [2]
Table 10. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance
See the F0453C Application Circuit. Specifications apply when operated as an Rx RF amplifier with VDD = +3.3V, fRF = 3700MHz, TEPAD = +25°C,
STBY = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Pout = 0dBm/tone
Minimum
Typical
Maximum
Units
OIP31
23
5MHz tone separation
Pout = 0dBm/tone
OIP32
OIP33
5MHz tone separation
TEPAD = -40°C to 105°C
20
Pout = 0dBm/tone
5MHz tone separation
Low Gain Mode
Output Third-Order Intercept Point
dBm
23
Pout = 0dBm/tone
5MHz tone separation
Low Gain Mode
OIP34
18
TEPAD = -40°C to 105°C
OP1dB1
OP1dB2
OP1dB3
OP1dB4
High Gain Mode [b]
15
14
High Gain Mode
G-24
G-18
TEPAD = -40°C to 105°C
Output 1dB Compression
dBm
Low Gain Mode
Low Gain Mode
TEPAD = -40°C to 105°C
RFISO1 = �ꢀꢁ1_ꢂꢃꢄ
ꢅ
ꢀꢁ2_ꢂꢃꢄ
ꢆꢇ
with -60 ≤ SW1_IN ≤ -30dBm
Channel Isolation
ISOCH
55
55
65
65
dB
dB
RFISO2 = �ꢀꢁ2_ꢂꢃꢄ
ꢅ
ꢀꢁ1_ꢂꢃꢄ
ꢆꢇ
with -60 ≤ SW2_IN ≤ -30dBm
Tx Mode
RF Switch Isolation
ISOSW
Measured at SW_IN to
RX_OUT of the same channel
[a] Items in Minimum/Maximum columns in bold italics are guaranteed by test. Items in Minimum/Maximum columns NOT in bold italics are
guaranteed by design characterization.
[b] In the OP1dB calculation formula, “G” denotes the gain of each part instance at the frequency of interest and appropriate High / Low gain state.
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Electrical Characteristics: 3800MHz–4000MHz [1]
Table 11. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance
See the F0453C Application Circuit. Specifications apply when operated as an Rx RF amplifier with VDD = +3.3V, fRF = 3900MHz, TEPAD = +25°C,
STBY = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Measured at SW1_IN, SW2_IN
High Gain Mode,
9 [a]
fRF = 3800MHz to 4000MHz
Measured at SW1_IN, SW2_IN
Low Gain Mode,
Input Return Loss
RLIN
dB
9
fRF = 3800MHz to 4000MHz
Measured at SW1_IN, SW2_IN
TX mode
11
[b] [c]
Measured at RX1_OUT,
RX2_OUT,
Output Return Loss
RLOUT
6
dB
High/Low Gain Modes,
fRF = 3800MHz to 4000MHz
Reverse Isolation, S12
Gain
ISOREV
GHG
fRF = 3800MHz to 4000MHz
High Gain Mode
52
30
28
62
33
dB
dB
dB
35
38
GHG_TEMP
GLG
TEPAD = -40 to 105°C
Low Gain Mode
Gain Attenuated
27.5
±0.5
f
RF = 3800MHz to 4000MHz
(Difference between maximum
and minimum gain in each
100MHz subrange within the
specified frequency range)
Gain Ripple
Noise Figure
GRIPPLE
dB
dB
Measured at antenna port
ideally matched to LNA
1.5
1.5
2
NF
TEPAD = 105°C
Low Gain Mode
2.5
[a] Items in Minimum/Maximum columns in bold italics are guaranteed by test. Items in Minimum/Maximum columns NOT in bold italics are
guaranteed by design characterization.
[b] Specification reflects use of an external termination resistor at SW1_OUT, SW2_OUT with a RL > 22dB.
[c] Performance can be further improved with tuning at the SW1_OUT and SW2_OUT ports.
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Electrical Characteristics: 3800MHz–4000MHz [2]
Table 12. Electrical Characteristics: RX Path in Rx Mode Cascaded Performance and TX Performance
See the F0453C Application Circuit. Specifications apply when operated as an Rx RF amplifier with VDD = +3.3V, fRF = 3900MHz, TEPAD = +25°C,
STBY = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Pout = 0dBm/tone
Minimum
Typical
Maximum
Units
OIP31
22
5MHz tone separation
Pout = 0dBm/tone
OIP32
OIP33
5MHz tone separation
TEPAD = -40°C to 105°C
18
Pout = 0dBm/tone
5MHz tone separation
Low Gain Mode
Output Third-Order Intercept Point
dBm
22
Pout = 0dBm/tone
5MHz tone separation
Low Gain Mode
OIP34
17
TEPAD = -40°C to 105°C
OP1dB1
OP1dB2
OP1dB3
OP1dB4
High Gain Mode [b]
13
12
High Gain Mode
G-24
G-18
TEPAD = -40°C to 105°C
Output 1dB Compression
dBm
Low Gain Mode
Low Gain Mode
TEPAD = -40°C to 105°C
RFISO1 = �ꢀꢁ1_ꢂꢃꢄ
ꢅ
ꢀꢁ2_ꢂꢃꢄ
ꢆꢇ
with -60 ≤ SW1_IN ≤ -30dBm
Channel Isolation
ISOCH
50
53
60
63
dB
dB
RFISO2 = �ꢀꢁ2_ꢂꢃꢄ
ꢅ
ꢀꢁ1_ꢂꢃꢄ
ꢆꢇ
with -60 ≤ SW2_IN ≤ -30dBm
Tx Mode
RF Switch Isolation
ISOSW
Measured at SW_IN to
RX_OUT of the same channel
[a] Items in Minimum/Maximum columns in bold italics are guaranteed by test. Items in Minimum/Maximum columns NOT in bold italics are
guaranteed by design characterization.
[b] In the OP1dB calculation formula, “G” denotes the gain of each part instance at the frequency of interest and appropriate High / Low gain state.
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Thermal Characteristics
Table 13. Thermal Characteristics
Parameter
Symbol
Value
Units
Junction-to-Ambient Thermal Resistance
θJA
31.2
°C/W
Junction-to-Case Thermal Resistance
(Case is defined as the exposed paddle)
θJC_BOT
3.4
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL3
Typical Operating Conditions
Unless otherwise noted:
.
.
.
.
.
.
VDD = +3.3V
TEPAD = 25°C
ZL = ZS = 50Ω single-ended with matching networks
STBY = Low or open
SW_CTRL = Low or open
Gain Setting = High Gain Mode
.
PIN ≤ -30dBm
.
.
All temperatures are referenced to the exposed paddle
Evaluation Kit traces and connector losses are de-embedded
Programming
Table 14. Gain Step Truth Table
ATT1_CTRL, ATT2_CTRL
Attenuation Setting
Low or NC
High
0dB
6dB
Table 15. Standby and RF Switch Truth Table
In TX Mode, the amplifiers are OFF, but the bias will remain ON for fast turn-on recovery time.
STBY
Low or NC
Low or NC
High
SW_CTRL
Low or NC
MODE
RX
Amplifier State
ON
OFF
OFF
High
TX
High or Low or NC
STANDBY
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Typical Performance Characteristics
Figure 2. Rx Mode Gain (High Gain)
Figure 3. Rx Mode Gain (Low Gain)
Figure 4. Rx Mode Reverse Isolation
(High Gain)
Figure 5. Rx Mode Reverse Isolation
(Low Gain)
Figure 6. Rx Mode Input Return Loss
(High Gain)
Figure 7. Rx Mode Input Return Loss
(Low Gain)
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Figure 8. Rx Mode Output Return Loss
(High Gain)
Figure 9. Rx Mode Output Return Loss
(Low Gain)
Figure 10. Rx Mode OP1dB (High Gain)
Figure 11. Rx Mode OP1dB (Low Gain)
Figure 12. Rx Mode OIP3 (High Gain)
Figure 13. Rx Mode OIP3 (Low Gain)
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Figure 14. Rx Mode Noise Figure (High Gain)
Figure 15. Rx Mode Noise Figure (Low Gain)
Figure 16. Tx Mode RF Switch Isolation
Figure 17. Rx Mode Channel Isolation
Figure 18. Stability K-factor
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Figure 19. Gain Settling Time
Figure 20. Gain Step Phase Settling Time
Figure 21. Power OFF Switching Time
Figure 22. Power ON Switching Time
Figure 23. Power OFF to Standby Mode
Figure 24. Power ON from Standby Mode
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Evaluation Kit Picture
Figure 25. Evaluation Kit: Top View
Figure 26. Evaluation Kit: Bottom View
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Evaluation Kit Circuit
Figure 27. Electrical Schematic
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Table 16. Bill of Materials (BOM)
Part Reference
C2,C3,C4,C5
C7,C9,C11,C13
C8,C10,C12,C14
C17,C18,C19,C20
C15
Qty
DNI
DNI
4
Description
Manufacturer Part #
GRM1555C1H101J
GRM155R71H103J
GRM155R61A105KE15D
GJM1555C1H8R0B
GRM188R71H103K
ERJ-2GE0R00X
Manufacturer
MURATA
100pF ±5%, 50V, C0G Ceramic Capacitor (0402)
10nF ±5%, 50V, X7R Ceramic Capacitor (0402)
1µF ±10% 10V Ceramic Capacitor X5R 0402
8pF ±0.1pF 50V Ceramic Capacitor C0G,NP0 (0402)
10nF ±5%, 50V, X7R Ceramic Capacitor (0603)
0Ω Resistors (0402)
MURATA
MURATA
4
MURATA
1
MURATA
R1,R2,R3,R4,R5,R6
R7
6
PANASONIC
PANASONIC
PANASONIC
1
1kΩ ±1%, 1/10W, Resistor (0402)
ERJ-2RKF1001X
R8
1
1.3kΩ ±1%, 1/10W, Resistor (0402)
ERJ-2RKF1301X
J1,J2,J3,J4,J5,J6,
J10,J11
Cinch
Connectivity
8
1
1
SMA Edge Mount
142-0761-881
10-89-7100
J12
J9
CONN HEADER VERT 2X5 POS GOLD
3M
Emerson
Johnson
Edge Launch SMA(0.375 inch pitch ground, tab) (50Ohm)
142-0701-851
SW1
U1
1
1
1
8-pin DIP Switch (3 POS)
Dual Path RF +LNA+DVGA 5x5 QFN
Printed Circuit Board
KAT1108E
IDE-Switch
Renesas
F0452C/F0453C LEG32K
F0452C/F0453C Stripline Rev. B
PCB
Keystone
Electronics
TEST POINT
DNI
BLACK/GND TP1
5001
5000
Keystone
Electronics
TEST POINT
C1,C6,C16
DNI
3
RED/VCC TP2
DNI
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Application Information
Power Supplies
A common VDD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to
minimize noise and fast transients. Supply noise can degrade the noise figure, and fast transients can trigger ESD clamps and cause them to
fail. Supply voltage change or transients should have a slew rate smaller than 1V / 20µs. In addition, all control pins should remain at
0V (±0.3V) while the supply voltage ramps up or while it returns to zero.
Control Pin Interface
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of each control pin is recommended. This applies to control pins 1, 2, 3, 6, 7, and 8 displayed in Figure 28.
Figure 28. Control Pin Interface Schematic
5 kΩ
ATT1_CTRL
2 pF
5 kΩ
STBY1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
2 pF
5 kΩ
SW1_CTRL
2 pF
5 kΩ
SW2_CTRL
2 pF
5 kΩ
STBY2
2 pF
5 kΩ
ATT2_CTRL
2 pF
© 2020 Renesas Electronics Corporation
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May 1, 2020
F0453C Datasheet
Marking Diagram
.
.
Lines 1 and 2 indicate the part number
IDTF04
53CLEGK
#YYWW$
Line 3 indicates the following:
• “#” denotes stepping
• “YY” is the last two digits of the year; “WW” is the work week number when the part
was assembled.
• “$” denotes the mark code.
LOT
.
Line 4 is the lot number
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/document/psc/32-fclga-package-outline-drawing-600-x-600-x-075-mm-body-460-x-460-mm-epad-05mm-pitch-lfg32p1
Ordering Information
Orderable Part Number
Package
MSL Rating
MSL3
Shipping Packaging
Temperature
-40° to +105°C
-40° to +105°C
F0453CLFGK
6 × 6 × 0.75 mm 32-pin LGA
6 × 6 × 0.75 mm 32-pin LGA
Tray
Reel
F0453CLFGK8
F0453CEVB
MSL3
Evaluation Board
Revision History
Revision Date
Description of Change
May 1, 2020
Added Application Information section.
Initial release.
February 26, 2020
© 2020 Renesas Electronics Corporation
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May 1, 2020
32-FCLGA, Package Outline Drawing
6.00 x 6.00 x 0.75 mm Body, 4.60 x 4.60 mm Epad, 0.5mm Pitch
LFG32P1, PSC-4813-01, Rev 00, Page 1
32-FCLGA, Package Outline Drawing
6.00 x 6.00 x 0.75 mm Body, 4.60 x 4.60 mm Epad, 0.5mm Pitch
LFG32P1, PSC-4813-01, Rev 00, Page 2
Package Revision History
Description
Date Created Rev No.
July 18, 2019 Rev 00 Initial Release
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