F1240NBGI [RENESAS]
Dual Channel IF Digital Variable Gain Amplifier 10MHz to 500MHz;
| 型号： | F1240NBGI |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual Channel IF Digital Variable Gain Amplifier 10MHz to 500MHz 电信 电信集成电路 |
| 文件： | 总35页 (文件大小：15956K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Channel IF Digital Variable Gain Amplifier
10MHz to 500MHz
F1240
Datasheet
Description
Features
The F1240 is a dual channel IF variable gain amplifier for diversity
basestation receivers. Each channel has 31.5dB of total
attenuation and a 0.5dB attenuation step. The device offers
significantly better noise and distortion performance than currently
available devices. It is packaged in a compact 5mm x 5mm QFN
with 200Ω differential input and output impedances for ease of
integration into the receiver lineup.
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Ideal for systems with high SNR requirements
20dB typical Maximum Gain
31.5dB gain control range
6 bit control via serial or parallel control
0.5dB Gain Steps
Excellent Noise Figure : 4.0dB
NF degrades just 1.3dB @ 10dB below Max Gain
Competitive Advantage
. 200Ω Differential Matched Input
. 200Ω Differential Matched Output
The F1240 IF VGA improves system signal-to-noise (SNR),
especially at lower gain settings. With IDT’s proprietary FlatNoiseTM
technology both OIP3 and noise figure are kept virtually flat while
gain is backed off, enhancing SNR significantly under high level
interferer conditions, and greatly benefiting 2G/3G/4G Multi-Carrier
IF sampling receivers.
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No termination resistors required
10MHz – 500MHz frequency range
Ultra-Linear: OIP3 +47dBm typical
Excellent 2nd Harmonic Rejection
External current setting resistors
Very fast settling < 15ns
The fast settling time, less than 15ns, gain step of 0.5dB coupled
with the excellent differential linearity allow for signal to noise ratio
(SNR) to be maximized further by targeting the minimum necessary
gain in small, accurate increments.
Individual Power Down Modes
Extremely Low Power: 80mA / Chan
The matched output does not require a terminating resistor, thus
the gain and distortion performance are preserved when driving
bandpass anti-alias filters.
.
5 × 5 32-QFN package
Block Diagram
Figure 1. Block Diagram
See the Applications Information section for more details and
benefits of the F1240 in IF sampling receivers.
Typical Applications
IN_A+
IN_A-
OUT_A+
OUT_A-
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.
Base Station 2G, 3G, 4G, TDD radio cards
Repeaters and E911 systems
Digital Pre-Distortion
Parallel [12]
CLK
VCC
FlatNoiseTM
STBY_A
Point to Point Infrastructure
Public Safety Infrastructure
Logic
Decoder
Bias
Control
DATA
CSb
STBY_B
ISET [2]
VMODE
OUT_B+
OUT_B-
IN_B+
IN_B-
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September 11, 2018
Pin Assignments
Figure 2. Pin Assignments for 5 x 5 x 0.75 mm QFN Package – Top View
GA3 / DATA
1
OUT_A+
24
23
22
21
20
19
18
17
EPAD
GA4 / CLK
GA5
2
3
4
5
6
7
8
OUT_A-
STBY_A
GND
VMODE
NC
GND
GB5
STBY_B
OUT_B-
OUT_B+
GB4
GB3
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September 11, 2018
Pin Descriptions
Table 1.
Pin Descriptions
Number
Name
Description
1
2
3
GA3 / DATA 4dB Attenuation control bit for Channel A (Parallel Mode) or DATA (Serial Mode).
GA4 / CLK 8dB Attenuation control bit for Channel A (Parallel Mode) or CLK (Serial Mode).
GA5
16dB Attenuation control bit for Channel A.
For the parallel mode set for logic HIGH or float (internal pullup resistor)
Set for logic Low for the serial mode.
4
VMODE
5, 13, 20,
21, 28
GND
Internally grounded. This pin must be grounded with a via as close to the pin as possible.
6
GB5
GB4
16dB Attenuation control bit for Channel B.
7
8dB Attenuation control bit for Channel B.
8
GB3
4dB Attenuation control bit for Channel B.
9
GB2
2dB Attenuation control bit for Channel B.
10
11
12
14
15
16
GB1
1dB Attenuation control bit for Channel B.
IN_B+
IN_B-
VCC
Channel B Differential Input +. Pin is AC coupled.
Channel B Differential Input -. Pin is AC coupled.
Power supply input. Bypass to ground with capacitors as close as possible to pin.
Channel B ICC set: Use the recommended value from the BOM section.
0.5dB Attenuation control bit for Channel B.
ISET_B
GB0
Channel B Differential Output+. Pull up to VCC through an inductor. An external series capacitor is
required.
17
18
OUT_B+
OUT_B-
Channel B Differential Output-. Pull up to VCC through an inductor. An external series capacitor is
required.
19
22
STBY_B
STBY_A
Pull low to Power Down Channel B. Float or Pull HIGH to enable Channel B.
Pull low to Power Down Channel A. Float or Pull HIGH to enable Channel A.
Channel A Differential Output -. Pull up to VCC through an inductor. An external series capacitor is
required.
23
24
OUT_A-
OUT_A+
Channel A Differential Output +. Pull up to VCC through an inductor. An external series capacitor is
required.
25
26
27
29
30
31
32
GA0
ISET_A
VCC
0.5dB Attenuation control bit for Channel A.
Channel A ICC set: Use the recommended value from the BOM section.
Connect this pin to the 5V DC Power Bus. Bypass capacitor is required.
Channel A Differential Input -. Pin is AC coupled.
IN_A-
IN_A+
GA1
Channel B Differential Input +. Pin is AC coupled.
1dB Attenuation control bit for Channel A.
GA2 / CSb 2dB Attenuation control bit for Channel A (Parallel Mode) or Chip Select, CSb (Serial Mode).
Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board
– EPAD
(PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground
planes. These multiple ground vias are also required to achieve the specified RF performance.
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September 11, 2018
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.
Functional operation of the F1240 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 2.
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Power Supply
VCC
VLOGIC
VRFIN
VRFOUT
PMAX
-0.3
-0.3
+5.5
VCC + 0.25
+2.2
V
V
GA[5-0], GB[5-0], DATA, CSb, CLK, VMODE, STBY_A, STBY_B
IN_A+, IN_A-, IN_B+, IN_B-
-0.3
V
OUT_A+, OUT_A-, OUT_B+, OUT_B-
Maximum RF Input Power (IN_A+, IN_A-, IN_B+, IN_B-) at maximum gain
Continuous Power Dissipation
+2.56
VCC + 0.25
+15
V
dBm
W
PDISS
TJMAX
TSTOR
TLEAD
1.5
Junction Temperature
+150
°C
°C
°C
Storage Temperature Range
-65
+150
Lead Temperature (soldering, 10s)
+260
Electrostatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
500
(Class 1B)
VESDHBM
VESDCDM
V
V
Electrostatic Discharge – CDM
(JEDEC 22-C101F)
1000
(Class C3)
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September 11, 2018
Recommended Operating Conditions
Table 3.
Recommended Operating Conditions
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Power supply voltage
VCC
+4.75
-40
+5.25
+100
V
Operating Temperature Range
TEPAD
Exposed paddle
°C
Low Distortion Range
Maximum Gain Setting
OIP3 > 40 dBm,
50
10
400
560
POUT = +3dBm/Tone
RF Frequency Range
fRF
MHz
Operating Range
Gain > 17dB
L1=L2=L3=L4=1500nH
ZIN_A
ZIN_B
,
Input Port Impedance
Output Port Impedance
Differential
Differential
200
200
Ω
Ω
ZOUT_A
ZOUT_B
,
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September 11, 2018
Electrical Characteristics
See the F1240 Typical Application Circuit. Specifications apply when operated at VCC = +5.0V, fRF = 200MHz, TEPAD = +25°C, Parallel Mode
(VMODE is logic HIGH), STBY_A=STBY_B=is logic HIGH, ZS = ZL = 200Ω differential, maximum gain setting, tone spacing = 0.8MHz,
POUT = +3dBm/tone, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Table 4.
Electrical Characteristics
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Logic Input High Threshold
Logic Input Low Threshold
VIH
VIL
2.0 [a]
0.0
V
V
0.8
+2
+1
GA[5-0], GB[5-0]
-2
Logic Current
IIH, IIL
ICC
µA
VMODE, STBY_A, STBY_B
-10
STBY_A=STBY_B set for
logic HIGH
160
2.3
176
5
DC Current
mA
STBY_A=STBY_B set for
logic LOW
ISTBY
LSB
Minimum Gain Step
Attenuation Range
0.5
dB
dB
31.5
Gain Setting = 20dB, or
Attenuator Setting = 0dB
Maximum Gain
GMAX
20
dB
18
Gain Setting = -11.5dB, or
Attenuator Setting = 31.5dB
Minimum Gain
Return Loss
GMIN
RL
-11.5
dB
dB
-9
15
7
fRF=200MHz
fRF=350MHz
fRF=450MHz
fRF=200MHz
fRF=350MHz
fRF=450MHz
Relative Phase Between the
Minimum and Maximum Attenuation
Φ∆
14
20
3
deg
Relative Phase over any 8 dB
Attenuation Range
Φ∆8
5
deg
dB
8
Step Error
DNL
0.08
Over 50MHz to 300MHz and
temperature
±(0.3+5%ATT) Typical
±(0.5+5%ATT) Typical
Absolute Attenuation Error
(Attenuation = 20 – Gain State)
INL
dB
Over 300MHz to 500MHz and
temperature
Frequency with a 1 dB gain
reduction compared to gain at
100MHz at the maximum gain
setting
1dB Gain Rolloff
Channel Isolation
BW
350
MHz
dBc
OUT_B referenced to OUT_A
with power applied at IN_A at
maximum gain setting
ISOL
60
69
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in
these columns that are not shown in bold italics are guaranteed by design characterization.
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September 11, 2018
Electrical Characteristics
See the F1240 Typical Application Circuit. Specifications apply when operated at VCC = +5.0V, fRF = 200MHz, TEPAD = +25°C, Parallel Mode
(VMODE is logic HIGH), STBY_A=STBY_B=is logic HIGH, ZS = ZL = 200Ω differential, maximum gain setting, tone spacing = 0.8MHz,
POUT = +3dBm/tone, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Table 5.
Electrical Characteristics
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Gain Setting = 20.0dB, or
Attenuator Setting = 0dB
OIP320A
42
46.5
Gain Setting = 20.0dB, or
Attenuator Setting = 0dB
Tone Spacing= 20MHz
OIP320B
OIP310
45
44.5
41
Gain Setting = 10dB, or
Attenuator Setting = 10dB
42
Output Third Order Intercept Point
dBm
Gain Setting = 20dB, or
Attenuator Setting = 0dB
fRF = 350MHz
OIP320C
Gain Setting = 20dB, or
Attenuator Setting = 0dB
fRF = 450MHz
OIP320D
OIP2
H2
41
76
Gain Setting = 10dB, or
Attenuator Setting = 10dB
f1 = 190MHz, f2 = 210MHz,
fM = f2 - f1
Output Second Order Intercept
Point
dBm
Gain Setting = 10dB, or
Attenuator Setting = 10dB
Output Power = + 3dBm
Second Harmonic
-90
dBc
Maximum spurious level on any RF
port
SPURMAX No RF Power applied
Gain Setting = 20dB, or
-135
4.5
dBm
4.0
5.3
Attenuator Setting = 0dB
Noise Figure
NF
dB
Gain Setting = 10.0dB, or
5.8
Attenuator Setting = 10.0dB
Gain Setting = 20dB, or
OP1dB
Output 1dB Compression
19.7
dBm
16
Attenuator Setting = 0dB
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in
these columns that are not shown in bold italics are guaranteed by design characterization.
7
September 11, 2018
Electrical Characteristics
See the F1240 Typical Application Circuit. Specifications apply when operated at VCC = +5.0V, fRF = 200MHz, TEPAD = +25°C, Parallel Mode
(VMODE is logic HIGH), STBY_A=STBY_B=is logic HIGH, ZS = ZL = 200Ω differential, maximum gain setting, tone spacing = 0.8MHz,
POUT = +3dBm/tone, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Table 6.
Electrical Characteristics
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
50% control signal to 30dBc of
initial output power. STBY is
switched from logic HIGH to
Logic LOW.
tOFF
100
Amplifier Switching Time [b]
ns
50% control signal to 0.5dBc
of final output power. STBY is
switched from logic LOW to
Logic HIGH.
tON
200
Any two Adjacent 1dB Steps
and settled to within +/-0.1dB
of the final power level
Settling Time [b]
Maximum Glitch
t1dB
12
ns
Only 1 transition has a glitch
greater than 0.4dB (8.5dB to
8.0dB)
0.4
1.5
dB
CSb must be pulled low this
minimum interval BEFORE the next
rising clock edge
Clock to CSb Setup
Clock Pulse Width
tEN
tW
ns
ns
8
Minimum clock interval from rising
to falling edge
20
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in
these columns that are not shown in bold italics are guaranteed by design characterization.
[b] Speeds are measured after SPI programming is completed (data latched with CSb = HIGH).
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September 11, 2018
Thermal Characteristics
Table 7.
Package Thermal Characteristics
Parameter
Symbol
Value
Units
Junction to Ambient Thermal Resistance.
θJA
40
°C/W
Junction to Case Thermal Resistance.
(Case is defined as the exposed paddle)
θJC-BOT
3
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL 1
Typical Operating Conditions (TOC)
Unless otherwise noted, for the TOC graphs on the following pages, the following conditions apply:
.
.
.
.
.
.
.
.
.
.
.
Vcc = 5.0V
ZL = ZS = 100Ω Single Ended or 200Ω Differential
f
RF = 200MHz
EPAD = +25°C
T
STBY = HIGH
Pout = 3dBm/Tone
0.8MHz or 20MHzTone Spacing
Gain setting = Maximum Gain
All temperatures are referenced to the exposed paddle
Linear parameters have the Evaluation Kit traces and connector losses de-embedded.
Non-linear parameters (IP3, P1dB, NF, switching) are measured using the single ended evaluation board with scalar correction.
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September 11, 2018
Typical Performance Characteristics
Figure 3. Gain versus Frequency [All States]
Figure 4. Gain versus Gain Setting
25
20
15
10
5
25
20
15
10
5
50.0 MHz
100.0 MHz
150.0 MHz
200.0 MHz
250.0 MHz
300.0 MHz
350.0 MHz
400.0 MHz
450.0 MHz
500.0 MHz
0
0
-5
-5
-10
-15
-10
-15
106
107
108
109
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Frequency (Hz)
Gain Setting (dB)
Figure 5. Input Return Loss versus Frequency
[All States]
Figure 6. Input Return Loss versus Gain
Setting
0
0
50.0 MHz
100.0 MHz
150.0 MHz
200.0 MHz
-5
-5
250.0 MHz
300.0 MHz
350.0 MHz
400.0 MHz
450.0 MHz
500.0 MHz
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
106
107
108
109
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Frequency (Hz)
Gain Setting (dB)
Figure 7. Output Return Loss versus
Frequency [All States]
Figure 8. Output Return Loss versus Gain
Setting
5
0
0
-5
-5
-10
-15
-20
-10
-15
-20
-25
-30
-35
-40
50.0 MHz
-25
100.0 MHz
150.0 MHz
200.0 MHz
250.0 MHz
300.0 MHz
350.0 MHz
400.0 MHz
450.0 MHz
500.0 MHz
-30
-35
-40
106
107
108
109
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Frequency (Hz)
Gain Setting (dB)
10
September 11, 2018
Typical Performance Characteristics
Figure 9. Relative Insertion Phase versus
Frequency [All States]
Figure 10. Relative Insertion Phase versus Gain
Setting
30
25
20
15
10
5
30
50.0 MHz
100.0 MHz
150.0 MHz
200.0 MHz
250.0 MHz
300.0 MHz
350.0 MHz
400.0 MHz
450.0 MHz
25
20
500.0 MHz
15
10
5
0
0
-5
-5
-10
-10
106
107
108
109
109
109
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Frequency (Hz)
Gain Setting (dB)
Figure 11. Relative Insertion Phase over any
8dB Range versus Frequency
Figure 12. Relative Insertion Phase over any
8dB Range versus Gain Setting
20
18
16
14
12
10
8
20
50.0 MHz
100.0 MHz
150.0 MHz
200.0 MHz
250.0 MHz
300.0 MHz
350.0 MHz
400.0 MHz
450.0 MHz
18
16
14
500.0 MHz
12
10
8
6
6
4
4
2
2
0
0
106
107
108
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Frequency (Hz)
Gain Setting (dB)
Figure 13. Maximum Gain versus Frequency
22.0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
4.75V / -40C
4.75V / +25C
4.75V / +105C
5.00V / -40C
5.00V / +25C
5.00V / +105C
5.25V / -40C
5.25V / +25C
5.25V / +105C
17.5
17.0
106
107
108
Frequency (Hz)
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September 11, 2018
Typical Performance Characteristics
Figure 14. Reverse Isolation versus Frequency
[All States]
Figure 15. Reverse Isolation versus Gain
Setting
0
0
-5
50.0 MHz
100.0 MHz
150.0 MHz
200.0 MHz
250.0 MHz
300.0 MHz
350.0 MHz
400.0 MHz
450.0 MHz
500.0 MHz
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
106
107
108
109
109
109
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Frequency (Hz)
Gain Setting (dB)
Figure 16. Worse Case Gain Accuracy versus
Frequency
Figure 17. Gain Accuracy versus Gain Setting
2.0
2.0
1.5
1.0
0.5
0.0
-40 C / Min
+25 C / Min
+105 C / Min
-40 C / Max
+25 C / Max
+105 C / Max
1.5
1.0
0.5
0.0
50.0 MHz
-0.5
-1.0
-1.5
-2.0
-0.5
100.0 MHz
150.0 MHz
200.0 MHz
250.0 MHz
300.0 MHz
350.0 MHz
400.0 MHz
450.0 MHz
500.0 MHz
-1.0
-1.5
-2.0
106
107
108
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Frequency (Hz)
Gain Setting (dB)
Figure 18. Worse Case Step Error versus
Frequency
Figure 19. Step Error versus Gain Setting
0.5
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-40 C / Min
+25 C / Min
+105 C / Min
-40 C / Max
+25 C / Max
+105 C / Max
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
50.0 MHz
100.0 MHz
150.0 MHz
200.0 MHz
250.0 MHz
300.0 MHz
350.0 MHz
400.0 MHz
450.0 MHz
500.0 MHz
-0.2
-0.3
-0.4
-0.5
106
107
108
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Frequency (Hz)
Gain Setting (dB)
12
September 11, 2018
Typical Performance Characteristics
Figure 20. Output IP3 versus Frequency
[Maximum Gain]
Figure 21. Second Harmonic versus Frequency
[Maximum Gain]
55
50
45
40
35
0
-10
-20
-30
-40
-50
-60
-70
30
-80
-40 C
-40 C
25
+25 C
+25 C
-90
+105 C
+105 C
20
-100
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Frequency (MHz)
Frequency (MHz)
Figure 22. Output P1B Compression versus
Frequency [Maximum Gain]
Figure 23. Noise Figure versus Frequency
[Maximum Gain]
22
21
20
19
18
17
10
9
8
7
6
5
4
3
16
2
-40 C
-40 C
+25 C
+105 C
15
+25 C
1
0
+105 C
14
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Frequency (MHz)
Frequency (MHz)
13
September 11, 2018
Typical Performance Characteristics
Figure 24.Output IP3 versus Gain State
[200MHz]
Figure 25.Output P1dB versus Gain State
[200MHz]
55
22
-40 C
+25 C
21
20
19
18
17
+105 C
50
45
40
35
30
25
20
16
-40 C
+25 C
15
+105 C
14
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Gain Setting (dB)
Gain Setting (dB)
Figure 26.Output IP3versus Gain State
[350MHz]
Figure 27.Output P1dB versus Gain State
[350MHz]
55
22
-40 C
+25 C
21
20
19
18
17
+105 C
50
45
40
35
30
25
20
16
-40 C
15
+25 C
+105 C
14
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Gain Setting (dB)
Gain State (dB)
Figure 28.Output IP3 versus Gain State
[450MHz]
Figure 29.Output P1dB versus Gain State
[450MHz]
55
22
-40 C
+25 C
21
20
19
18
17
+105 C
50
45
40
35
30
25
20
16
-40 C
15
+25 C
+105 C
14
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Gain Setting (dB)
Gain State (dB)
14
September 11, 2018
Typical Performance Characteristics
Figure 30. 2nd Harmonic versus Gain State
Figure 31. Noise Figure versus Gain State
[200MHz]
[200MHz]
0
30
28
26
24
22
20
18
16
14
12
10
8
-40 C
-40 C
+25 C
+25 C
-10
+105 C
+105 C
-20
-30
-40
-50
-60
-70
-80
-90
-100
6
4
2
0
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Gain Setting (dB)
Gain State (dB)
Figure 32. 2nd Harmonic versus Gain State
Figure 33. Noise Figure versus Gain State
[350MHz]
[350MHz]
55
30
-40 C
-40 C
28
26
24
22
20
18
16
14
12
10
8
+25 C
+25 C
+105 C
+105 C
50
45
40
35
30
25
20
6
4
2
0
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Gain Setting (dB)
Gain State (dB)
Figure 34. 2nd Harmonic versus Gain State
Figure 35. Noise Figure versus Gain State
[450MHz]
[450MHz]
55
30
-40 C
-40 C
28
26
24
22
20
18
16
14
12
10
8
+25 C
+25 C
+105 C
+105 C
50
45
40
35
30
25
20
6
4
2
0
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12 14 16 18 20
Gain Setting (dB)
Gain State (dB)
15
September 11, 2018
Typical Performance Characteristics
Figure 36. Channel Isolation versus Frequency
[Maximum Gain]
Figure 37. Current versus Power Supply
0
162
161
160
159
158
157
156
155
154
153
152
-10
-20
CH A to CH B
-30
CH B to CH A
-40
-50
-60
-70
-80
-40 C
+25 C
+105 C
-90
-100
1.E+06
1.E+07
1.E+08
1.E+09
4.7
4.8
4.9
5.0
5.1
5.2
5.3
400
90
Frequency (Hz)
Voltage (Volts)
Figure 38. Typical Standby OFF to ON
Switching
Figure 39. Typical Standby ON to OFF
Switching
15
15
10
10
5
5
0
0
-5
-5
Serial
Serial
Parallel
-10
-15
-20
-25
-30
-35
-10
-15
-20
-25
-30
-35
Parallel
-50
0
50
100
150
200
250
300
350
400
-50
0
50
100
150
200
250
300
350
Time (ns)
Time (ns)
Figure 40. Typical Switching Characteristics
Figure 41. Worse Case Switching
Characteristics (8.5 to 8.0 dB)
-1.4
0.4
+8.5 dB to +8.0 dB
+8.0 dB to +8.5 dB
+8.5 dB CW
+8.0 dB CW
+8.0 dB to +7.5 dB
+7.5 dB to +8.0 dB
+8.0 dB CW
+7.5 dB CW
-1.5
-1.6
-1.7
-1.8
-1.9
-2.0
-2.1
-2.2
-2.3
-2.4
-2.5
-2.6
-2.7
-2.8
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-2.0
-2.2
-2.4
1.5 dB
-10
0
10
20
30
40
50
60
70
80
90
-10
0
10
20
30
40
50
60
70
80
Time (ns)
Time (ns)
16
September 11, 2018
Programming
F1240 can be programmed using either the parallel or serial interface which is selectable via VMODE (pin 4). The serial mode is selected by
setting VMODE to a logic LOW and the parallel mode by floating VMODE or by setting VMODE to a logic HIGH.
Serial Mode
F1240 Serial Mode is selected by setting VMODE to a logic LOW. The serial interface is a 16 bit shift register made up of two words. The first
word is the address or channel word, which uses only 1 of 8 bits to select the channel that will be programmed. The second 8 bit word is the
Gain (or attenuation) word, which uses 6 bits to control the DSA state and one bit to enable or disable the channel.
When serial programming is used, all of the other parallel control input pins (3, 6-10, 25, 31, 32) can be left floating.
Table 8.
8-Bit SPI Address (Channel) Word Sequence
Data Bit
Symbol
A7
A6
A5
A4
A3
A2
A1
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
A0
Channel Selection
Table 9.
Truth Table for Address (Channel) Control Word
A7
(MSB)
A0
(LSB)
A6
A5
A4
A3
A2
A1
Program Channel
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
A
B
Table 10. 8-Bit SPI Gain (Attenuation) Word Sequence
Data Bit
Symbol
Enable Bit
D7
D6
D5
D4
D3
D2
D1
D0
Attenuation 16 dB Control Bit
Attenuation 8 dB Control Bit
Attenuation 4 dB Control Bit
Attenuation 2 dB Control Bit
Attenuation 1 dB Control Bit
Attenuation 0.5 dB Control Bit
Not Used
17
September 11, 2018
Table 11. Truth Table for Serial Gain (Attenuation) Control Word
D7
(MSB)
D0
(LSB)
Gain Setting
Target (dB)
Attenuation
D6
D5
D4
D3
D2
D1
(dB)
E
E
E
E
E
E
E
E
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
20
19.5
19
0
0.5
1
18
2
16
4
12
8
4
16
31.5
-11.5
[a] To enable the specified channel set E to a logic HIGH. To disable (or set for standby) the specific
channel set E for logic LOW. For this bit to work properly the standby pins (19, 22) must be floating
or set to logic HIGH.
In the Serial Mode, the F1240 is programmed via the serial port on the rising edge of Chip Select bar (CSb). It is required that CSb be kept logic
LOW until all data bits are clocked into the shift registers. The F1240 will change attenuation state after the data word is latched into the active
register. Refer to Figure 42.
Figure 42. Serial Register Timing Diagram
18
September 11, 2018
Table 12. SPI Timing Diagram Values for the Serial Mode
Parameter
Symbol
Test Condition
Minimum
Typical
Maximum
50
Units
CLK Frequency
fC
tCH
tCL
tS
tP
tH
tCLS
tLS
tL
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK HIGH Duration Time
CLK LOW Duration Time
DATA to CLK Setup Time
CLK Period [b]
CLK to Data Hold Time
Final CLK Rising Edge to LE Rising Edge
LE to CLK Setup Time
LE Trigger Pulse Width
LE Trigger to CLK Setup Time [c]
[a] (tCH + tCL) ≥ 1/fC.
20
20
10
40
10
10
10
10
10
tLC
[b] Once all desired data has been clocked in, CSb must transition from LOW to HIGH after the minimum setup time tLC and
before any further CLK signals.
Serial Mode Enable Functions and Standby Pins
There are two pins, STBY_A (pin 22) and STBY_B (pin 19) which can be used in the serial or parallel mode for fast switching of the two
channels. These pins float HIGH and should be left disconnected or set for logic HIGH for serial operation.
Using the Serial Mode for Standby
.
.
Each channel must be programmed separately using the Enable bit (Bit 7) of the Data word.
The gain setting is determined by the gain bits (D6-D1) are set for during the channel programming.
Parallel Control Mode
Parallel Mode is selected when VMODE (Pin 4) is floating or set to a logic HIGH. In this mode, the device will immediately react to any voltage
changes on the parallel control pins (1-3, 5-10, 16, 25, 31, 32). Use the Parallel Mode for the fastest settling time. This also allows both channels
to be programmed simultaneously.
The truth table for the Parallel Mode is identical for bits D6 to D0 as shown in the Serial Mode truth table; see Table 11.
Using the Standby Pins for Standby
.
.
Both channels can be switch at the same time by setting the standby pins simultaneously
The gain setting is determined by the gain bits (D6-D1) set during the last serial programming or by the existing parallel pins setting.
Default Startup Condition
When the device is first powered up, it will default to the maximum gain (minimum attenuation) of 20 dB (0 dB) and both channels will be enabled
independent of the VMODE and parallel pin [D6:D0] conditions.
19
September 11, 2018
Typical Application Circuit
Figure 43 is a typical minimum circuit design needed for the F1240.
Figure 43. Electrical Schematic
C12
C10
R34
U1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
B1_3-SD
B1_4-SCK
B1_5
OUT_A+
OUT_A-
L1
L2
GA3/DATA
GA4/CLK
GA5
OUT_A+
OUT_A-
STBY_A
GND21
GND20
STBY_B
OUT_B-
OUT_B+
VCC_IF1
C1
C4
P_EN
R37
Vmode
NC
R38
B2_5
B2_4
B2_3
GB5
OUT_B-
OUT_B+
L4
L3
GB4
VCC_IF2
C5
C7
GB3
VCC
C16
R36
C17
C18
20
September 11, 2018
Evaluation Kit Picture
Figure 44. Top View
Figure 45. Bottom View
21
September 11, 2018
Evaluation Kit / Applications Circuit
Figure 46 shows the electrical schematic for the evaluation board used for customer evaluation.
Figure 46. Electrical Schematic
J1
T1
C2
C12
C10
R34
U1
J4
T5
L1
L2
3
2
1
4
J6
SEC
PRI
PD
C1
C3
1
3
5
7
9
11
13
2
4
6
8
10
12
14
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
B1_0
B1_2-CS
B1_4-SCK
B1_1
B1_3-SD
B1_5
B1_3-SD
B1_4-SCK
B1_5
OUT_A+
OUT_A-
GA3/DATA
GA4/CLK
GA5
OUT_A+
OUT_A-
STBY_A
GND21
GND20
STBY_B
OUT_B-
OUT_B+
VCC_IF1
CT
B2_4
B2_2
B2_0
B2_5
B2_3
B2_1
6
4
6
J7
SD
1
2
3
4
P_EN
R37
C4
C5
Vmode
NC
R38
T6
L4
L3
B2_5
B2_4
B2_3
3
2
1
GB5
SEC
CT
PRI
PD
C8
OUT_B-
OUT_B+
GB4
VCC_IF2
J5
GB3
SD
C7
C16
VCC
R36
J8
C17
JP1
C18
R39
R40
R41
R42
C6
TP1
TP2
TP3
TP4
T3
J3
22
September 11, 2018
Table 13. Bill of Material (BOM)
Part Reference
QTY
Description
Manufacturer Part #
Manufacturer
C1, C5, C10, C16
C2, C3, C6 C,8
C4, C7, C12, C17
C18
4
4
4
1
1000pF ±5%, 50V, C0G Ceramic Capacitor (0402)
10nF ±5%, 50V, X7R Ceramic Capacitor (0402)
100nF ±10%, 16V, X7R Ceramic Capacitor (0402)
10uF ±20%, 6.3V, X5R Ceramic Capacitor (0603)
GRM1555C1H102J
GRM155R71H103J
GRM155R71C104K
GRM188R60J106M
MURATA
MURATA
MURATA
MURATA
R37, R39, R40, R41,
R42
5
0Ω Resistors (0402)
ERJ-2GE0R00X
PANASONIC
R34, R36
2
1
1
1
5
3.83kΩ ±1%, 1/10W, Resistor (0402)
CONN HEADER VERT SGL 2 X 1 POS GOLD
CONN HEADER VERT DBL 2 X 2 POS GOLD
CONN HEADER VERT DBL 7 X 2 POS GOLD
Edge Launch SMA (0.250 inch pitch ground, round)
ERJ-2RKF3831X
961102-6404-AR
90131-0762
PANASONIC
JP1
3M
Molex
J7
J6
N2514-6002-RB
142-0711-821
3M
J1, J3, J4, J5, J8
Emerson Johnson
390nH ±5%, 0.290A, Ferrite Ceramic Chip Inductor
(0805)
L1, L2, L3, L4
4
0805CS-391XJL
CoilCraft
T1, T3, T5, T6
U1
4
1
1
3MHz - 800MHz 50Ω, RF Transformer (4:1)
TC4-1WG2+
F1240
Mini Circuits
IDT
VGA
Printed Circuit Board
F1240 EVKIT REV 01
IDT
23
September 11, 2018
Evaluation Kit Operation
Power Supply Setup
Set up a power supply in the voltage range of 4.75V to 5.25V with the power supply output disabled. The voltage can be applied via one of the
following connections (see Figure 47).
.
.
Directly to J8 connector
JP1 header connection (note the polarity of the GND pin on this connector)
Figure 47. Power Supply Connections
VCC
GND
Logic Control Setup
The Evaluation Board has the ability to control the F1240 in the Parallel or Serial Mode. The logic voltages can be applied through the J4
connector (see Figure 48). For both the parallel and serial mode see Table 14 for the connections.
Figure 48. Logic Connections
Pin 1
Pin 3
Pin 14
24
September 11, 2018
Logic Control
Table 14. Parallel and Serial Logic Pins
J6 Pin
Parallel Function
Serial Function
F1240 Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GA0
GA1
GA2
GA3
GA4
GA5
GND
VMODE
GB4
GB5
GB2
GB3
GB0
GB1
Not used
Not used
CSb
DATA
CLK
Not used
GND
VMODE
Not used
Not used
Not used
Not used
Not used
Not used
25
31
32
1
2
3
4
7
6
9
8
16
10
Standby Pins
The evaluation board allows for setting the standby pins on connector J5. By default the standby pins are logic HIGH which allows the device
to be enable. By setting the pin to logic LOW (ground) the device will not draw very little current.
Figure 49. Standby Pins
STBY_A STBY_B
GND
Power-On Procedure
1. Set up the voltage supplies and Evaluation Board as described in the “Power Supply Setup” section and the “Logic Control Setup” section
above.
2. Enable the VCC supply. The F1240 should default to the maximum gain state.
3. Enable the proper gain (attenuation) setting according to Table 7-10 for Serial Mode or Table 11 for the Parallel Mode.
Power-Off Procedure
1. Set the logic control pins to a logic LOW.
2. Disable the VCC supply.
25
September 11, 2018
Application Information
The F1240 has been optimized for use in high performance IF sub-sampling applications. High absolute attenuator accuracy and low switching
time make the F1240 ideal for these very demanding applications.
Power Supplies
A common VCC power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to
minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail.
Supply voltage change or transients should have a slew rate smaller than 1V/20µS. In addition, all control pins should remain at 0V (+/-0.3V)
while the supply voltage ramps or while it returns to zero.
Digital Pin Voltage and Resistance Values
Table 15 provides open-circuit DC voltage referenced to ground and resistance values for each of the control pins listed.
Table 15. Digital Pin Voltages and Resistance
Open Circuit
DC Voltage
Pin
Name
Internal Connection
1 - 3, 6 - 10, 16,
25, 31, 32
Gain Control Bits
0V
> 10MΩ
4
VMODE
VCC
VCC
1.8MΩ
.80MΩ
19, 22
STBY_B, STB_A
Control Pin Interface
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of each control pin is recommended. This applies to control pins 1 - 4, 6 - 10, 16, 19, 22, 25, 31, and 32 as shown below.
Figure 50. Signal Integrity Schematic
5 kΩ
GA1
5 kΩ
2 pF
5 kΩ
GA0
GA2 / CSb
2 pF
2 pF
5 kΩ
GA3 / DATA
2 pF
5 kΩ
GA4 / CLK
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
2 pF
EPAD
5 kΩ
GA5
5 kΩ
2 pF
STBY_A
2 pF
5 kΩ
VMODE
2 pF
5 kΩ
5 kΩ
GB5
STBY_B
2 pF
2 pF
5 kΩ
GB4
2 pF
5 kΩ
GB3
2 pF
5 kΩ
5 kΩ
5 kΩ
GB2
GB1
GB0
2 pF
2 pF
2 pF
26
September 11, 2018
Matched Output
Unlike competing devices the F1240 features a matched 200Ω differential output. All of the datasheet parameters are specified as such. For
instance, the Gain of 20dB is a true Transducer Power gain (Power delivered to the matched load minus Power available from the source). This
is in contrast to competing devices that usually have a high or low impedance output and must be terminated with resistors to operate properly.
In IF sampling applications, the IF VGA usually drives a bandpass anti-alias filter which precedes the ADC. These filters typically need to ‘see’
matched terminations. Only the F1240’s performance is preserved in this environment. See directly below for a comparison to popular VGA
styles.
Figure 51. VGA Output Amplifier - Voltage Mode Schematic
Example 1: ‘Voltage Mode’ VGA
50 Ω Bandpass Anti-Alias Filter
25 Ω
2 Ω
50 Ω
50 Ω
In
200 Ω
Out
+
VS
-
25 Ω
Termination Resistors:
Ensure BPF is terminated properly with 50 Ω
Total load = 100 Ω …..Available Power = V2S / 100
Must Adjust Datasheet Values:
Gain with 100 Ω load = 22 dB
True Gain in-system = 19 dB
Half the Power is dissipated in the terminating resistors:
(0.5VS)2 / 50
The other half of the power is delivered to the input of the BPF
Output IP3 with 100 Ω load = +44 dBm
True OIP3 in-system = +41 dBm
Effectively, the Gain drops by 3 dB
Figure 52. VGA Output Amplifier - Current Mode Schematic
Example 2: ‘Current Mode’ VGA
300 Ω Bandpass Anti-alias Filter
300 Ω
300 Ω
300 Ω
IS
In
150 Ω
Out
5 kΩ
Termination Resistor:
Ensures BPF is terminated properly with 300 Ω.
Must Adjust Datasheet Values:
Total load = 150 Ω ...Available Power = I2 X 150
S
Half the Power is dissipated in the terminating resistor:
(0.5IS)2 X 300
Gain with 150 Ω load = 19 dB
True Gain in-system = 16 dB
The other half of the power is delivered to the BPF
Again effectively, the Gain drops by 3 dB
Output IP3 with 150 Ω load = +46 dBm
True OIP3 in-system = +43 dBm
27
September 11, 2018
Figure 53. VGA Output Amplifier - Matched Output Schematic
IDT: ‘Matched’ VGA
200
Ω Bandpass Anti-Alias Filter
0
+
200 Ω
In
200 Ω
200 Ω
VS
-
Out
200 Ω
0
Termination Resistors NOT NEEDED:
VGA itself terminates BPF with proper Z = 200 Ω
NO NEED to Adjust Datasheet Values:
Total external load = 200 Ω
Gain with 200 Ω load = 20 dB
True Gain in-system = 20 dB
Available Power = V2S / 200
ALL of the power is delivered to the input of the BPF
Effectively, the Gain is unchanged!
Output IP3 with 200 ohm load = +49 dBm
True IP3O in-system = +49 dBm
Noise Contour
The remarkable FlatNoiseTM feature of the device (see first four graphs on page 10) has great benefits when implemented in wideband multi-
carrier systems. For the first 13 dB of attenuation range, the device has only 2.3dB degradation in noise figure. This is in stark contrast to
standard VGAs like the voltage or current mode devices described earlier. These devices have a linear dB-for-dB degradation in Noise Figure
with increasing attenuation.
Refer to the figure below. It depicts the F1240 driving a matched Anti-Alias Filter which is followed by an ADC with a differential resistive 200
ohm termination. Note that at each point in the system the matching is preserved.
Figure 54. VGA Output Amplifier – Anti-Alias Filter Schematic
ZDIF F = 200 ohm
ZDIF F = 200 ohm
200 MHz Discrete Anti-Alias Filter
CB
V_IN+
L3
C2
VGA_OUT+
100
100
L1
5V
L2
CB
CB
VCML
Unbuffered
L5
C4
F1240/1
VGA_OUT-
C1
Pipeline ADC
C3
V_IN-
L4
CB
ZDIF F = 200 ohm
Loss = 2 dB
Z
DIF F = 200 ohm
28
September 11, 2018
A discrete realization of a 3rd order Anti-Alias filter is shown below. Sampling occurs in Nyquist Zone3 for a 60 MHz multi-carrier signal. Noise
just 20 MHz above and below the signal band edges will alias from either Zone4 or Zone2 and show up as added noise in the desired band at
the digital output of the ADC.
Figure 55. VGA Output Amplifier – Anti-Alias Filter Schematic
10
Chebyshev Discrete LC
filter 3rd order
Zone2 Alias
noise rejection
only ~ 6 dB
0
-10
Multi-Carrier
BW = 170 to 230
30 dB filtering for
H2 and IM2
-20
-30
-40
Zone4 Alias noise
rejection only ~ 3 dB
-50
-60
-70
-80
-90
-100
Sample Rate ~ 160 MHz
Digital
Downconversion BW
-110
-120
3rd Nyquist Zone =
3
1st Nyquist Zone =
0 to f SAMP
2nd Nyquist Zone =
4th Nyquist Zone =
3
½
½
f SAMP to f SAMP
f SAMP to
/ 2 f SAMP
/
2 f SAMP to 2f SAMP
-130
0
40
80
120
160
200
240
280
320
360
400
440
Frequency (MHz)
The result is that the F1240 with its unique noise contour will improve SNR significantly in this multi-carrier instance. Note in the graph below:
SNR improves over 2dB at high attenuation settings which potentially allows for the use of a lower cost 12-bit ADC in the Rx path.
Figure 56. VGA Output Amplifier – Anti-Alias Filter Schematic
13.0
Standard VGA w/14 bit ADC
Up to 2.1 dB advantage
in SNR!
11.0
F1240/1 w/14 bit ADC
F1240/1 w/12 bit ADC
Enables use of low cost
12-bit ADC with no loss
of performance
9.0
7.0
5.0
3.0
1.0
SNR @ 200 MHz
SNR @ 200 MHz
with 165 fsec clock
with 165 fsec clock
jitter = 69.3 dB
jitter = 67.7 dB
0
4
8
12
16
20
24
VGA Attenuation below Max Gain (dB)
Current Setting Resistors
The F1240 already offers the best IM3 distortion performance over the widest power range when driving a matched load with 160mA total
current for both channel. The user has the option to reduce the current even further at the expense of Output IP3.
29
September 11, 2018
Settling Time
The F1240 has been optimized to settle quickly and smoothly without any glitching when changing gain between ANY adjacent steps. Glitching
is defined as the power increase over the maximum power from either of the two states being switched. Most states show no glitching at all. A
few states have less than 0.4dB. Only one state was found with a 1.5 dB glitch. See Figure 40 and Figure 41 glitch Even for 1 dB steps that
involve MSB transitions, the settling time is less than 15 ns.
Gain Control Software
To control the F1240, IDT can supply a total solution, F1240EVS, to test the device. The software can be downloaded from RF Digital Control
Software Installer, and the user manual from AN-896 RF Products EVS Digital Control Software Guide.
Operation into a 100Ω Load
The F1240 can be dropped directly into a 100Ω termination environment without any topology changes, so no board redesign is necessary.
The example schematic below is for a 153MHz IF center frequency. Simply replace the pullup inductors already on the board with 91nH and
replace the series AC coupling capacitors already on the board with 18pF. The F1240 in this case will then drive a 100Ω filter with approximately
16dB return loss. See schematic and measured results when matched to 100Ω below.
Figure 57. 153MHz Output Filter to ADC Schematic
AC coupling
Capacitor
ZDIFF = 100 ohm
ZDIFF = 100 ohm
153 MHz +/- 20MHz AAF
18 pF
CB
CB
Pins 24, 23
V_IN+
VGA_OUT+
91 nH
50
50
CB
VCML
Unbuffered
Pipeline ADC
F1240/1
5V
91 nH
VGA_OUT-
V_IN-
Pins 18, 17
CB
18 pF
Pullup Inductors:
Coilcraft 0805CS
ZDIFF = 100 ohm
ZDIFF = 100 ohm
AC coupling
Capacitor
Figure 58. Measure Performance for 153MHz
Output Filter vs Frequency
Figure 59. Measure OIP3 Performance for
153MHz Output Filter vs Gain Setting
25
20
15
55
174 MHz
50
45
40
10
S21
S22
5
134 MHz
154 MHz
35
30
25
20
15
0
-5
-10
-15
-20
-25
-2
0
2
4
6
8
10
12
14
16
18
20
1.0E+08
1.2E+08
1.4E+08
1.6E+08
1.8E+08
2.0E+08
Gain Setting (dB)
Frequency (Hz)
30
September 11, 2018
Figure 60. Measured Harmonic Performance for
153MHz Output Filter vs Gain Setting
Figure 61. Measure Error Performance for
153MHz Output Filter vs Gain Setting
-50
-55
-60
-65
0.6
0.4
154 MHz Gain Step Error
0.2
-70
174 MHz
154 MHz
-75
0.0
-80
-85
-90
-0.2
-0.4
-0.6
154 MHz Absolute Gain Error
-95
134 MHz
-100
-2
0
2
4
6
8
10
12
14
16
18
20
-4
-2
0
2
4
6
8
10
12
14
16
18
20
Gain Setting (dB)
Gain Setting (dB)
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/document/psc/nbnbg32-package-outline-50-x-50-mm-body-epad-330mm-sq-050-mm-pitch-qfn
Ordering Information
Orderable Part Number
Package
MSL Rating
Shipping Packaging
Temperature
F1240NBGI
F1240NBGI8
F1240EVBI
F1240EVS
5 × 5 × 0.75 mm 32-QFN
5 × 5 × 0.75 mm 32-QFN
1
1
Tray
Reel
-40° to +100°C
-40° to +100°C
Evaluation Board
Evaluation Solution
Marking Diagram
.
.
Lines 1 and 2 are the part number.
Line 3 indicates the following:
.
.
“#” denotes stepping.
“YY” is the last two digits of the year; “WW” is the work week number when the part
was assembled.
.
“$” denotes the mark code.
.
Line 4 is the assembly lot number.
31
September 11, 2018
Revision History
Revision Date
Description of Change
•
•
•
•
Added spurs specification
Linked the package outline drawings
Updated the marking diagram
Updated the document formatting
September 11, 2018
Added power supply and control pin paragraphs in Application section. Corrected Absolute Maximum Rating
section. Corrected pin table. Addition of “Revision History” table. Addition of contacts and disclaimer table.
Revision of package drawing and addition of land pattern.
February 9, 2018
March 31, 2012
Minor edits.
Initial release.
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