F1471EVB-2P6 [RENESAS]
0.5W High Linearity RF Amplifier 400MHz to 4200MHz;
| 型号： | F1471EVB-2P6 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 0.5W High Linearity RF Amplifier 400MHz to 4200MHz |
| 文件： | 总23页 (文件大小：1560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
F1471
0.5W High Linearity RF Amplifier 400MHz to 4200MHz
The F1471 is a high linearity RF Driver Amplifier
designed to operate within the 400MHz to 4200MHz
frequency band. Using a single 5V power supply
and only 130mA of ICQ, the F1471 provides 15dB of
gain and 3.8dB of noise figure, and 29dBm OP1dB
at 3600MHz.
Features
• RF range: 400MHz to 4200MHz
• 15dB typical gain at 3600MHz
• 3.8dB NF at 3600MHz
• +29dBm output P1dB at 3600MHz
• 5V power supply
The F1471 is packaged in a 3 × 3 mm, 16-VFQFPN
package, with matched 50Ω input and output
impedances for ease of integration into the signal
path.
• Adjustable DC bias
• Bias control compatible for 3.3V and 5V VREF
operation allowing power-down mode for power
savings
Competitive Advantage
• 50Ω single-ended input and output impedances
• Internal DC overvoltage protection
• Internal RF overdrive protection
• On-chip ESD protection
• Excellent linearity maintained over large
bandwidths
• OIP3 linearity configurable with bias current
adjustments
• Exceptional OP1dB performance maintained at
low bias currents
• Operating temperature (TEP) range: -40°C to
+115°C
• Robust ESD Performance
o 1.5kV HBM ESD rating
o 1kV CDM ESD rating
• 3 × 3 mm, 16-VFQFPN package
Applications
• 4G/5G cellular base stations
• Multi-mode, multi-carrier transmitters
• Active antenna systems
• General purpose wireless
• Includes on-chip DC overvoltage and RF
overdrive protection
RFOUT
RFIN
Bias
Figure 1. Block Diagram
Rev.1.0
Page 1
Oct.16.20
F1471 Datasheet
Contents
1. Pin Information............................................................................................................................................... 4
Pin Configuration ................................................................................................................................... 4
Pin Descriptions..................................................................................................................................... 4
2. Specifications................................................................................................................................................. 5
Absolute Maximum Ratings................................................................................................................... 5
Recommended Operating Conditions ................................................................................................... 5
Electrical Characteristics ....................................................................................................................... 6
2.3.1.
2.3.2.
2.3.3.
2.3.4.
General.................................................................................................................................... 6
2300MHz to 2900MHz ............................................................................................................ 6
3300MHz to 3900MHz ............................................................................................................ 7
3800MHz to 4200MHz ............................................................................................................ 8
Thermal Characteristics......................................................................................................................... 8
3. Typical Operating Conditions (TOC) ........................................................................................................... 9
4. Typical Performance Characteristics ........................................................................................................ 10
2300MHz – 2900MHz.......................................................................................................................... 10
3300MHz – 3900MHz.......................................................................................................................... 11
3800MHz – 4200MHz.......................................................................................................................... 12
5. Programming................................................................................................................................................ 14
6. Applications Information ............................................................................................................................ 14
Power Supplies.................................................................................................................................... 14
7. Evaluation Kit Information.......................................................................................................................... 14
Evaluation Kit Circuit ........................................................................................................................... 15
Bill of Materials .................................................................................................................................... 16
Evaluation Kit Operation...................................................................................................................... 19
7.3.1.
7.3.2.
7.3.3.
7.3.4.
Power Supply Setup.............................................................................................................. 19
Shunt Jumper Setup ............................................................................................................. 19
Power-On Procedure ............................................................................................................ 19
Power-Off Procedure ............................................................................................................ 19
8. Package Outline Drawings.......................................................................................................................... 20
9. Ordering Information................................................................................................................................... 20
10. Marking Diagram.......................................................................................................................................... 20
11. Revision History .......................................................................................................................................... 20
Figures
Figure 1. Block Diagram ...........................................................................................................................................1
Figure 2. Gain .........................................................................................................................................................10
Figure 3. Reverse Isolation.....................................................................................................................................10
Figure 4. Input Return Loss ....................................................................................................................................10
Figure 5. Output Return Loss .................................................................................................................................10
Figure 6. OIP3 ........................................................................................................................................................10
Rev.1.0
Page 2
Oct.16.20
F1471 Datasheet
Figure 7. OIP3 vs Tone Power (2.6GHz)................................................................................................................10
Figure 8. OP1dB (2.6GHz) .....................................................................................................................................11
Figure 9. Noise Figure ............................................................................................................................................11
Figure 10. Gain .......................................................................................................................................................11
Figure 11. Reverse Isolation...................................................................................................................................11
Figure 12. Input Return Loss ..................................................................................................................................11
Figure 13. Output Return Loss ...............................................................................................................................11
Figure 14. OIP3 ......................................................................................................................................................12
Figure 15. OIP3 vs Tone Power (3.6GHz)..............................................................................................................12
Figure 16. OP1dB (3.6GHz) ...................................................................................................................................12
Figure 17. Noise Figure ..........................................................................................................................................12
Figure 18. Gain .......................................................................................................................................................12
Figure 19. Reverse Isolation...................................................................................................................................12
Figure 20. Input Return Loss ..................................................................................................................................13
Figure 21. Output Return Loss ...............................................................................................................................13
Figure 22. OIP3 ......................................................................................................................................................13
Figure 23. OIP3 vs Tone Power (4GHz).................................................................................................................13
Figure 24. OP1dB (4GHz) ......................................................................................................................................13
Figure 25. Noise Figure ..........................................................................................................................................13
Figure 26. Evaluation Kit Photo ..............................................................................................................................14
Figure 27. Electrical Schematic for the Evaluation Kit............................................................................................15
Tables
Table 1. STBY Truth Table.....................................................................................................................................14
Table 2. Evaluation Kit Bill of Material (BOM) – 2300MHz to 2900MHz Tune.......................................................16
Table 3. Evaluation Kit Bill of Material (BOM) – 3300MHz to 3900MHz Tune.......................................................17
Table 4. Evaluation Kit Bill of Material (BOM) – 3800MHz to 4200MHz Tune.......................................................18
Rev.1.0
Page 3
Oct.16.20
F1471 Datasheet
1. Pin Information
Pin Configuration
16 Ld 3 x 3 mm VFQFPN Package
Top View
NC
1
12
NC
2
3
11
10
RFIN
RFIN
RFOUT
RFOUT
4
9
NC
NC
Pin Descriptions
Number
Name
Description
No internal connection. Renesas highly recommends connecting these pins to a ground via, which is
located as close to the pin as possible.
1, 4, 5, 6, 7, 8,
9, 12, 13, 16
NC
RF input internally matched to 50Ω. Must use an external DC block.
2, 3
RFIN
RF output. Pull up to VCC through inductor. Must use an external DC block.
10, 11
RFOUT
Connect pin directly to VCC. Renesas recommends placing a 1000pF decoupling capacitor as close to this
pin as possible.
14
15
VCC
Reference current and STBY pin. Connect an external resistor (reference BOM) to VREF to set the
quiescent current of the device. Setting VREF < 2V disables the amplifier.
I_REF
Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board
(PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground
planes. These multiple ground vias are also required to achieve the specified RF performance.
EPAD
Rev.1.0
Page 4
Oct.16.20
F1471 Datasheet
2. Specifications
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause
permanent damage to the device. Functional operation of the F1471 at absolute maximum ratings is not implied.
Exposure to absolute maximum rating conditions may affect device reliability.
Parameter
Symbol
Minimum
Maximum
8.0
Units
VCC to GND
VREF to GND
VCC
0
0
V
V
V
V
[b]
VREF
5.5
RFIN Externally Applied DC Voltage
RFOUT Externally Applied DC Voltage
VRFIN
8.0
VRFOUT
8.0
Maximum CW input power applied for 24 hours
f = 2.6GHz, TEP = +115°C, input/output VSWR < 2:1 based on 50Ω system [a]
PMAXIN
18
dBm
Junction Temperature
TJMAX
TSTOR
+175
+150
+260
1500
1000
°C
°C
°C
V
Storage Temperature Range
-65
Lead Temperature (soldering, 10s)
TLEAD
Electrostatic Discharge – HBM (JEDEC/ESDA JS-001-2012)
Electrostatic Discharge – CDM (JEDEC 22-C101F)
VESDHBM
VESDCDM
V
[a] Exposure to these maximum RF levels can result in significantly higher ICC current draw due to overdriving the amplifier stages.
[b]
V
REF conditions apply when VCC is applied
Recommended Operating Conditions
Typical
Maximum
Units
Parameter
Symbol
Condition
Minimum
Power Supply Voltage
Reference Voltage
VCC
4.75
5.25
V
[a]
Powered On
Powered Off
3.3 or 5
1.8
VREF
V
0
2
Operating Temperature Range
RF Frequency Range
TEPAD
fRF
ZRFI
ZRFO
Exposed Paddle
-40
400
+115
4200
°C
MHz
Ω
RFIN Port Impedance
Single-ended
Single-ended
50
50
RFOUT Port Impedance
[a] Refer to R5 value in the BOM.
Ω
Rev.1.0
Page 5
Oct.16.20
F1471 Datasheet
Electrical Characteristics
See the Electrical Schematic. Specifications apply when operated as a TX amplifier with tuning optimized for
desired band of interest, VCC = +5.0V, VREF = +3.3V, TEPAD = +25°C, RBSET = 174Ω, (R5 in the electrical
schematic), ZS = ZL = 50Ω, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise
stated.
2.3.1.
General
Parameter
Symbol
ICQ
Condition
Minimum
Typical
130
2
Maximum
Units
mA
Quiescent Current [b]
160 [a]
IREF
mA
Reference Bias Current [b]
V
REF < 2V
IREF_STBY
500
µA
50% STBY control to within
0.5dB of the on-state final gain
value
TON
200
200
ns
ns
Standby Switching Time
50% STBY control to
ICC < 10mA
TOFF
2.3.2.
2300MHz to 2900MHz
See the Electrical Schematic. Specifications apply when operated as a TX amplifier with tuning optimized for the
2300MHz to 2900MHz band, fRF = 2600MHz, VCC = +5.0V, VREF = +3.3V, TEPAD = +25°C, RBSET = 174Ω, (R5 in
the electrical schematic), ZS = ZL = 50Ω, Evaluation Board (EVKit) traces and connectors are de-embedded,
unless otherwise stated.
Parameter
Symbol
G
Condition
Minimum
Typical
Maximum
Units
dB
Gain
16
1
Gain Flatness
f
RF = 2300MHz to 2900MHz
GFLAT
dB
TEPAD = -40°C to +115°C,
referenced to TEPAD = 25°C
Gain Variation Over Temp
GTEMP
+0.5/-1
dB
STBY Mode Gain
RF Input Return Loss
RF Output Return Loss
Reverse Isolation
Noise Figure
VREF < 2V
GSTBY
RLRFIN
RLRFOUT
ISOREV
NF
-16
12
12
27
4
dB
dB
dB
dB
dB
P
OUT = +18dBm/tone
Output Third Order Intercept Point
Output 1dB Compression Point
OIP3
38
dBm
dBm
1MHz tone separation
OP1dB
28.5
Pout = +18dBm,
LTE 20MHz, 9dB PAR
ACLR
ACLR
-48
dBc
Rev.1.0
Page 6
Oct.16.20
F1471 Datasheet
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
K-Factor [b]
TEPAD = -40°C to +115°C
VCC = 4.75V to 5.25V
Up to 20GHz
Stability
K
1
[a] Specifications in the minimum/maximum columns that are shown in bold italics are confirmed by test. Specifications in these columns
that are not shown in bold italics are confirmed by design characterization.
[b] K-Factor calculated taking the matching circuit into consideration, no de-embedding applied.
2.3.3.
3300MHz to 3900MHz
See the Electrical Schematic. Specifications apply when operated as a TX amplifier with tuning optimized for the
3300MHz to 3900MHz band, fRF = 3600MHz, VCC = +5.0V, VREF = +3.3V, TEPAD = +25°C, RBSET = 174Ω, (R5 in
the electrical schematic), ZS = ZL = 50Ω, Evaluation Board (EVKit) traces and connectors are de-embedded,
unless otherwise stated.
Parameter
Symbol
G
Condition
Minimum
Typical
Maximum
Units
dB
13[a]
15
1
Gain
Gain Flatness
fRF = 3300MHz to 3900MHz
GFLAT
dB
TEPAD = -40°C to +115°C,
referenced to TEPAD = 25°C
Gain Variation Over Temp
GTEMP
+0.5/-1
dB
STBY Mode Gain
RF Input Return Loss
RF Output Return Loss
Reverse Isolation
Noise Figure
VREF < 2V
GSTBY
RLRFIN
RLRFOUT
ISOREV
NF
-14
14
dB
dB
dB
dB
dB
12
25
3.8
POUT = +18dBm/tone
1MHz tone separation
38
dBm
dBm
POUT = +18dBm/tone
1MHz tone separation
VCC = 4.75V to 5.25V
TEPAD = -40°C to +115°C
Output Third Order Intercept Point
OIP3
32
29
dBm
Output 1dB Compression Point
OP1dB
VCC = 4.75V to 5.25V
TEPAD = -40°C to +115°C
26
dBm
dBc
Pout = +18dBm,
LTE 20MHz, 9dB PAR
ACLR
ACLR
K
-47
K-Factor [b]
TEPAD = -40°C to +115°C
VCC = 4.75V to 5.25V
Up to 20GHz
Stability
1
[a] Specifications in the minimum/maximum columns that are shown in bold italics are confirmed by test. Specifications in these columns
that are not shown in bold italics are confirmed by design characterization.
[b] K-Factor calculated taking the matching circuit into consideration, no de-embedding applied.
Rev.1.0
Page 7
Oct.16.20
F1471 Datasheet
2.3.4.
3800MHz to 4200MHz
See the Electrical Schematic. Specifications apply when operated as a TX amplifier with tuning optimized for the
3800MHz to 4200MHz band, fRF = 4000MHz, VCC = +5.0V, VREF = +3.3V, TEPAD = +25°C, RBSET = 174Ω, (R5 in
the electrical schematic), ZS = ZL = 50Ω, Evaluation Board (EVKit) traces and connectors are de-embedded,
unless otherwise stated.
Parameter
Symbol
G
Condition
Minimum
Typical
14
Maximum
Units
dB
Gain
Gain Flatness
fRF = 3800MHz to 4200MHz
GFLAT
1.2
dB
TEPAD = -40°C to +115°C,
referenced to TEPAD = 25°C
Gain Variation Over Temp
GTEMP
+0.5/-1
dB
STBY Mode Gain
RF Input Return Loss
RF Output Return Loss
Reverse Isolation
Noise Figure
VREF < 2V
GSTBY
RLRFIN
RLRFOUT
ISOREV
NF
-13
15
9
dB
dB
dB
dB
dB
25
3.8
POUT = +18dBm/tone
1MHz tone separation
Output Third Order Intercept Point
Output 1dB Compression Point
ACLR
OIP3
OP1dB
ACLR
37
28.5
-44
dBm
dBm
dBc
Pout = +18dBm,
LTE 20MHz, 9dB PAR
K-Factor [b]
TEPAD = -40°C to +115°C
VCC = 4.75V to 5.25V
Up to 20GHz
Stability
K
1
[a] Specifications in the minimum/maximum columns that are shown in bold italics are confirmed by test. Specifications in these columns
that are not shown in bold italics are confirmed by design characterization.
[b] K-Factor calculated taking the matching circuit into consideration, no de-embedding applied.
Thermal Characteristics
Units
Parameter
Junction to Ambient Thermal Resistance.
Symbol
θJA
Value
48.6
°C/W
°C/W
Junction to Case Thermal Resistance. (Case is defined as the exposed paddle)
Moisture Sensitivity Rating (Per J-STD-020)
θJC-BOT
4.3
MSL 1
Rev.1.0
Page 8
Oct.16.20
F1471 Datasheet
3. Typical Operating Conditions (TOC)
Unless otherwise noted, the following conditions apply for the TOC graphs on the following pages:
• Vcc = 5.0V
• ZL = ZS = 50Ω Single-ended
• fRF = 2600MHz (set 1)
• fRF = 3600MHz (set 2)
• fRF = 4000MHz (set 3)
• TEP = +25°C
• VREF = 3.3V
• 1MHz Tone Spacing
• All temperatures are referenced to the exposed paddle.
• ACLR measurements used with LTE signal, 20MHz, PAR = 9dB at 0.01% probability.
• Evaluation Kit traces and connector losses are de-embedded
Rev.1.0
Page 9
Oct.16.20
F1471 Datasheet
4. Typical Performance Characteristics
2300MHz – 2900MHz
Figure 2. Gain
Figure 4. Input Return Loss
Figure 6. OIP3
Figure 3. Reverse Isolation
Figure 5. Output Return Loss
Figure 7. OIP3 vs Tone Power (2.6GHz)
Rev.1.0
Page 10
Oct.16.20
F1471 Datasheet
Figure 8. OP1dB (2.6GHz)
Figure 9. Noise Figure
3300MHz – 3900MHz
Figure 10. Gain
Figure 11. Reverse Isolation
Figure 12. Input Return Loss
Figure 13. Output Return Loss
Rev.1.0
Oct.16.20
Page 11
F1471 Datasheet
Figure 14. OIP3
Figure 15. OIP3 vs Tone Power (3.6GHz)
Figure 16. OP1dB (3.6GHz)
Figure 17. Noise Figure
3800MHz – 4200MHz
Figure 18. Gain
Figure 19. Reverse Isolation
Rev.1.0
Page 12
Oct.16.20
F1471 Datasheet
Figure 20. Input Return Loss
Figure 21. Output Return Loss
Figure 23. OIP3 vs Tone Power (4GHz)
Figure 25. Noise Figure
Figure 22. OIP3
Figure 24. OP1dB (4GHz)
Rev.1.0
Page 13
Oct.16.20
F1471 Datasheet
5. Programming
The F1471 includes a STBY feature as defined in the following table.
Table 1. STBY Truth Table
VREF Voltage
VREF = 5V
State
Condition
Full operation
Full operation
Amplifier OFF
RBSET = See R5 in band specific BOM
RBSET = See R5 in band specific BOM
RBSET = See R5 in band specific BOM
VREF = 3.3V
VREF < 2V
6. Applications Information
The F1471 has been optimized for use in high performance RF applications from 400MHz to 4200MHz.
Power Supplies
Use a common VCC power supply for all power supply pins. To minimize noise and fast transients, de-coupling
capacitors to all supply pins. Supply noise can degrade noise figure and fast transients can trigger ESD clamps
causing them to fail. Supply voltage changes or transients should have a slew rate smaller than 1V/20µs. In
addition, keep all control pins at 0V (±0.3V) while the supply voltage ramps or while it returns to zero.
7. Evaluation Kit Information
Figure 26. Evaluation Kit Photo
Note: See the Evaluation Kit Operation section for proper setup and configuration
Rev.1.0
Page 14
Oct.16.20
F1471 Datasheet
Evaluation Kit Circuit
Figure 27. Electrical Schematic for the Evaluation Kit
Rev.1.0
Page 15
Oct.16.20
F1471 Datasheet
Bill of Materials
Table 2. Evaluation Kit Bill of Material (BOM) – 2300MHz to 2900MHz Tune
Part Reference
Qty
Description
Manufacturer Part #
Manufacturer
4.7nH ±0.1nH, 160mA, film Inductor (0402)
C4
1
LQP15MN4N7B02
Murata
3.1pF ±0.05pF, 50V, C0G Ceramic Capacitor (0402)
1000pF ±5%, 50V, C0G Ceramic Capacitor (0402)
47uF ±20%, 10V, C0G Ceramic Capacitor (0805)
100nF ±10%, 50V, C0G Ceramic Capacitor (0402)
0.9pF ±0.05pF, 50V, C0G Ceramic Capacitor (0402)
1.3pF ±0.05pF, 50V, C0G Ceramic Capacitor (0402)
1.2pF ±0.05pF, 50V, C0G Ceramic Capacitor (0402)
3.9nH ±2%, 250MHz, Ceramic Chip Inductor (0603)
1.2nH ±0.05nH, Inductor (0402)
C5
1
5
2
1
1
1
1
1
1
1
GJM1555C1H3R1WB01
GRM1555C1H102JA01
GRM21BR61A476ME15
GRM1555C81H104KE14
GRM1555C1HR90W
GJM1555C1H1R3WB01
GRM1555C1H1R20WA01
0603CS-3N9XGE
Murata
Murata
C3, C6, C7, C8, C11
C1, C12
C9
Murata
Murata
C10
C18
L1
Murata
Murata
Murata
L2
Coilcraft
Murata
L3
LQP15MN1N2W
5.1Ω ±1% 0.063W, 1/16W Resistor (0402)
R4
CRCW04025R10FKED
Vishay Dale
Vref at 3.3V: 174Ω ±0.5%, 0.063W, 1/16W Resistor
(0402)
TNPW0402174RDEED
Vishay Dale
R5
1
1
Vref at 5V: 2.5kΩ ±0.1%, 0.063W, 1/16W Resistor
(0402)
TNPW04022K52BEED
CRCW04020000Z0ED
Vishay Dale
Vishay Dale
0Ω Jumper 0.063W, 1/16W Chip Resistor (0402)
DNP
R6
R7
Edge Launch SMA (0.375-inch pitch ground, tab, 50Ω)
CONN HEADER VERT DBL 5x2 POS GOLD
CONN HEADER VERT SGL 2x1 POS GOLD
F1471_Evkit_Solder_Rev.03
J2, J3, J4, J8
J6
4
1
1
1
1
142-0701-851
961210-6404-AR
961102-6404-AR
Emerson Johnson
3M
J7
3M
EVB
Renesas
Renesas
F1471YAA
Module
Rev.1.0
Page 16
Oct.16.20
F1471 Datasheet
Table 3. Evaluation Kit Bill of Material (BOM) – 3300MHz to 3900MHz Tune
Part Reference
Qty
Description
Manufacturer Part #
Manufacturer
5.6nH ±0.1nH, 160mA, film Inductor (0402)
C4
1
LQP15MN5N6B02
Murata
1.3pF ±0.05pF, 50V, C0G Ceramic Capacitor (0402)
1000pF ±5%, 50V, C0G Ceramic Capacitor (0402)
47µF ±20%, 10V, C0G Ceramic Capacitor (0805)
100nF ±10%, 50V, C0G Ceramic Capacitor (0402)
DNI
C5
1
5
2
1
1
1
1
1
2
1
GJM1555C1H1R3WB01
GRM1555C1H102JA01
GRM21BR61A476ME15
GRM1555C81H104KE14
Murata
Murata
Murata
Murata
C3, C6, C7, C8, C11
C1, C12
C9
C10
C18
L1
1.2pF ±0.05pF, 50V, C0G Ceramic Capacitor (0402)
0.5pF ±0.05pF, 50V, C0G Ceramic Capacitor (0402)
3.3nH ±2%, 250 MHz, Ceramic Chip Inductor (0603)
0Ω Jumper 0.063W, 1/16W Chip Resistor (0402)
1Ω ±1% 0.063W, 1/16W Resistor (0402)
GJM1555C1H1R2WB01
GRM1555C1HR50WA01
0603CS-3N3XGE
Murata
Murata
L2
Coilcraft
L3, R6
R4
CRCW04020000Z0ED
CRCW04021R00FKED
Vishay Dale
Vishay Dale
Vref at 3.3V: 174Ω ±0.5%, 0.063W, 1/16W Resistor
(0402)
TNPW0402174RDEED
TNPW04022K52BEED
Vishay Dale
Vishay Dale
R5
1
Vref at 5V: 2.5kΩ ±0.1%, 0.063W, 1/16W Resistor
(0402)
DNP
R7
J2, J3, J4, J8
J6
Edge Launch SMA (0.375 inch pitch ground, tab, 50 Ω)
CONN HEADER VERT DBL 5x2 POS GOLD
CONN HEADER VERT SGL 2x1 POS GOLD
F1471_Evkit_Solder_Rev.03
F1471YAA
4
1
1
1
1
142-0701-851
961210-6404-AR
961102-6404-AR
Emerson Johnson
3M
J7
3M
EVB
Renesas
Renesas
Module
Rev.1.0
Page 17
Oct.16.20
F1471 Datasheet
Table 4. Evaluation Kit Bill of Material (BOM) – 3800MHz to 4200MHz Tune
Part Reference
Qty
1
Description
Manufacturer Part #
LQP15MN5N1B02
Manufacturer
Murata
5.1nH ±0.1nH, 160mA, film Inductor (0402)
1.2pF ±0.05pF, 50V, C0G Ceramic Capacitor (0402)
1000pF ±5%, 50V, C0G Ceramic Capacitor (0402)
47uF ±20%, 10V, C0G Ceramic Capacitor (0805)
100nF ±10%, 50V, C0G Ceramic Capacitor (0402)
DNI
C4
C5
1
GJM1555C1H1R2WB01
GRM1555C1H102JA01
GRM21BR61A476ME15
GRM1555C81H104KE14
Murata
C3, C6, C7, C8, C11
5
Murata
C1, C12
C9
2
Murata
1
Murata
C10
1
1.0pF ±0.05pF, 50V, C0G Ceramic Capacitor (0402)
0Ω Jumper 0.063W, 1/16W Chip Resistor (0402)
3.3nH ±2%, 250MHz, Ceramic Chip Inductor (0603)
0.5pF ±0.05, 50V, COG Ceramic Capacitor (0402)
C18
1
GJM1555C1H1R0WB01
CRCW04020000Z0ED
0603CS-3N3XGE
Murata
Vishay Dale
Coilcraft
L1, L3, R6
L2
3
1
R4
1
GRMC1HR50WA01
Murata
Vref at 3.3V: 174Ω ±0.5%, 0.063W, 1/16W Resistor
(0402)
TNPW0402174RDEED
TNPW04022K52BEED
Vishay Dale
Vishay Dale
R5
1
Vref at 5V: 2.5kΩ ±0.1%, 0.063W, 1/16W Resistor
(0402)
DNP
R7
J2, J3, J4, J8
J6
Edge Launch SMA (0.375-inch pitch ground, tab, 50Ω)
CONN HEADER VERT DBL 5x2 POS GOLD
CONN HEADER VERT SGL 2x1 POS GOLD
F1471_Evkit_Solder_Rev.03
F1471YAA
4
1
1
1
1
142-0701-851
961210-6404-AR
961102-6404-AR
Emerson Johnson
3M
J7
3M
EVB
Renesas
Renesas
Module
Rev.1.0
Page 18
Oct.16.20
F1471 Datasheet
Evaluation Kit Operation
7.3.1.
Power Supply Setup
Set up a power supply in the voltage range of 4.75V to 5.25V with the power supply output disabled. The voltage
is applied using the following connection (see Figure 26):
• Directly to the J2 SMA connector
Set up a control supply of either 3.3V or 5V (Use the correct value of resistance (R5) based on the applied
control voltage as indicated per the BOM). The voltage is applied using the following connection (see Figure 26):
• Directly to the J3 SMA connector
7.3.2.
Shunt Jumper Setup
• J7 Header Pins
o Always place the Shunt Jumper to bias the amplifier output (see Evaluation Schematic in Figure 27).
• J6 Header Pins
o J6 Header pins provide the VCC and VREF voltages to the DUT.
o Always place a shunt jumper on pins 5 and 6 to provide the supplied VCC to the DUT.
o Place a shunt jumper on pins 3 and 4. In this configuration, VREF is set independent to the supply voltage,
VCC.
o Place a shunt jumper on pins 1 and 2. In this configuration, VREF is set to the same level as the supply
voltage, VCC.
• Only place jumpers on Pins 3 and 4 or Pins 1 and 2 at any given time.
Important: Do not place jumpers on all four pins (1, 2, 3, and 4) simultaneously.
7.3.3.
Power-On Procedure
1. Set up the voltage supplies, and Evaluation Board as described in the Power Supply Setup section.
2. Enable the VCC supply.
3. Enable the VREF supply.
7.3.4.
Power-Off Procedure
Disable the VREF supply and then disable the VCC power supply.
Rev.1.0
Page 19
Oct.16.20
F1471 Datasheet
8. Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below.
The package information is the most current data available.
https://www.idt.com/us/en/document/psc/16-vfqfpn-package-outline-drawing30x-30-x-075-mm-body050mm-
pitchepad-160-x-160-mm-ntg16t1
9. Ordering Information
Orderable Part Number
F1471NTGI
Package
MSL Rating
Shipping Packaging
Temperature
-40° to +115°C
-40° to +115°C
3 × 3 × 0.75 mm 16-VFQFPN
3 × 3 × 0.75 mm 16-VFQFPN
1
1
Tray
Reel
F1471NTGI8
F1471EVB-2P6
F1471EVB-3P6
F1471EVB-4P0
Evaluation Board 2300MHz – 2900MHz Tune
Evaluation Board 3300MHz – 3900MHz Tune
Evaluation Board 3800MHz – 4200MHz Tune
10. Marking Diagram
• “XXX” denotes the last 3 digits of the assembly lot number
• “Y” denotes the last digit of the year
• “WW” denotes the work week
XXX
YWW$
F1471
• “$” denotes the mark location code
• F1471 Is the product name
11. Revision History
Revision
Revision Date
Description of Change
1.0
Initial release.
Oct.16.20
Rev.1.0
Oct.16.20
Page 20
16-VFQFPN, Package Outline Drawing
3.0x 3.0 x 0.75 mm Body,0.50mm Pitch,Epad 1.60 x 1.60 mm
NTG16T1, PSC-4296-03, Rev 03, Page 1
16-VFQFPN, Package Outline Drawing
3.0x 3.0 x 0.75 mm Body,0.50mm Pitch,Epad 1.60 x 1.60 mm
NTG16T1, PSC-4296-03, Rev 03, Page 2
Package Revision History
Description
Rev 03 Correct Typo Error Minimum
Rev 02 Add "K" Value 0.20 Minimum
Date Created Rev No.
July 8, 2019
Sept 5, 2018
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