F159V [RENESAS]
Dual-Path RF Transmitter IC 450MHz to 2800MHz;
| 型号： | F159V |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual-Path RF Transmitter IC 450MHz to 2800MHz |
| 文件： | 总78页 (文件大小：3262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual-Path RF Transmitter IC
450MHz to 2800MHz
F159V
Datasheet
Description
Features
The F159V is a Dual-Path RF Transmitter IC that has an operating
frequency range of 450MHz to 2800MHz. The device provides two
independent transmit paths each with 18.3dB typical maximum
gain with corresponding output noise floor of -142.5dBm/Hz,
+31dBm OIP3, and +14dBm output P1dB designed to operate with
a single +3.3V supply while consuming only 685mA DC current.
.
.
.
.
.
.
Independent dual-path operation
RF output frequency: 450MHz to 2800MHz
18.3dB typical maximum gain (no attenuation)
+31dBm OIP3 (no attenuation)
+14dBm Output P1dB (no attenuation)
13dB NF corresponds to -142.5dBm/Hz output noise floor (no
attenuation)
Each signal path includes a quadrature modulator, voltage variable
attenuator (VVA), digital step attenuator (DSA), and a fixed gain
amplifier. The device supports a total of 32dB VVA adjustment
range using a SPI-controlled 11-bit DAC, and each DSA has 31dB
gain control range in 1dB steps using SPI control.
.
.
.
.
Output noise floor -152.3dBm/Hz (VVA=14dB, DSA=1dB)
Channel Isolation: 47dB
DSA with 31dB total gain range in 1dB steps
Multiple VVAs with 32dB gain range controlled by on-chip SPI
controlled 11-bit DAC
An on-chip frequency synthesizer is shared by both paths and is
optimized for use in multi-carrier, multi-mode FDD and TDD base
station transmitters achieving GSM-grade performance. The
synthesizer offers both an integer mode and fractional mode. It
requires an external loop filter and an external reference oscillator
in the frequency range of 10MHz to 250MHz.
.
Variable Gain amplifier (VGA) is comprised of DSAs, VVAs,
and a fixed-gain amplifier
.
.
.
.
.
.
.
.
.
.
I lead Q by 90 degrees for high side LO injection
Supports ZIF or CIF architectures
The F159V is packaged in a 10mm x 10mm, 68-pin QFN with 110Ω
differential drive from external I/Q DACs and single-ended 50Ω RF
output impedance for ease of integration into the signal-path lineup
for each of the two transmitter paths. Each path has independent
power supply control thereby allowing optimum power efficiency.
Common-mode voltage range: +0.1V to +0.8V
Integer-N and Fractional-N Synthesizer
Direct 110Ω differential driven from I/Q DAC
50Ω single-ended RF output impedance
Internal or external LO select
Competitive Advantage
+3.3V supply voltage at 685mA (LO_Out not turned on)
Specified Case Temperature; -20°C to +115°C
10mm x 10mm, 68-pin QFN package
.
High level of integration includes frequency synthesizer / PLL,
dual-path DSA, Modulator, and VVA
.
.
.
.
High reliability
Block Diagram
Figure 1. Block Diagram
Low DC current
Zero DistortionTM technology
GlitchFreeTM technology
Channel 0
Amplifier MOD MOD
Enable Enable Couple
Q+
Q-
I+
I-
Typical Applications
SPI Controller
90 / 0
.
.
.
.
.
.
.
.
Application Multi-mode, Multi-carrier Transmitters
PCS1900 Base Stations
Zero-DistortionTM
RESET
Vdd
∑
DCS1800 Base Stations
LO_LD
REF_IN
CP_OUT
VTUNE
VCOM
Frequency
Synthesizer
RFOUT
Channel 0
WiMAX and LTE Base Stations
UMTS/WCDMA 3G Base Stations
PHS/PAS Base Stations
DAC
DAC
RFOUT
Channel 1
/M
Distributed Antenna Systems
Digital Radio
LO
Switch
Matrix
/2
∑
90 / 0
Glitch-FreeTM
Amplifier MOD MOD
Enable Enable Couple
+
-
+
-
Q+
Q-
I+
I-
LO_IN
LO_OUT
Channel 1
© 2020 Renesas Electronics Corporation
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F159V Datasheet
Contents
1. Pin Assignments...........................................................................................................................................................................................5
2. Pin Descriptions............................................................................................................................................................................................6
3. Absolute Maximum Ratings..........................................................................................................................................................................9
4. Recommended Operating Conditions.........................................................................................................................................................10
5. Electrical Characteristics ............................................................................................................................................................................11
6. Thermal Characteristics..............................................................................................................................................................................21
7. Typical Operating Conditions (TOC)...........................................................................................................................................................21
8. Typical Performance Characteristics..........................................................................................................................................................22
9. Typical Performance Characteristics - VVA................................................................................................................................................23
10. Typical Performance Characteristics - DSA ...............................................................................................................................................24
11. Typical Performance Characteristics - Cascaded Gain..............................................................................................................................25
12. Typical Performance Characteristics - Cascaded Gain (Cont.)..................................................................................................................26
13. Typical Performance Characteristics - Cascaded OIP3 .............................................................................................................................27
14. Typical Performance Characteristics - Cascaded OIP3 (Cont.) .................................................................................................................28
15. Typical Performance Characteristics - Cascaded OIP2 .............................................................................................................................29
16. Typical Performance Characteristics - Cascaded OIP2 (Cont.) .................................................................................................................30
17. Typical Performance Characteristics - Cascaded OP1dB..........................................................................................................................31
18. Typical Performance Characteristics - Cascaded OP1dB (Cont.)..............................................................................................................32
19. Typical Performance Characteristics - Harmonics, Current, Switching ......................................................................................................33
20. Typical Performance Characteristics - Modulator Coupled Output.............................................................................................................34
21. Typical Performance Characteristics - Modulator Coupled Output.............................................................................................................35
22. Typical Performance Characteristics - LO..................................................................................................................................................36
23. Theory of Operation....................................................................................................................................................................................37
23.1. Frequency Generator.......................................................................................................................................................................37
23.1.1. Internal (VCO) Frequency.................................................................................................................................................38
23.1.2. Reference Frequency........................................................................................................................................................38
23.1.3. Charge Pump....................................................................................................................................................................39
23.1.4. External Loop Filter...........................................................................................................................................................39
23.1.5. LO Frequency ...................................................................................................................................................................39
23.1.6. Voltage Control Oscillator (VCO)......................................................................................................................................40
23.1.7. LO Switch Matrix...............................................................................................................................................................42
23.2. Modulator.........................................................................................................................................................................................44
23.3. Variable Gain Amplifier ....................................................................................................................................................................44
23.4. General Settings ..............................................................................................................................................................................45
23.4.1. Initial Startup.....................................................................................................................................................................45
23.4.2. Logic Pins .........................................................................................................................................................................46
24. Programming..............................................................................................................................................................................................46
24.1. Special Programming Note..............................................................................................................................................................47
24.2. Register Definition............................................................................................................................................................................48
24.2.1. Register 0 (00h) ................................................................................................................................................................50
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F159V Datasheet
24.2.2. Register 1 (01h) ................................................................................................................................................................50
24.2.3. Register 2 (01h) ................................................................................................................................................................51
24.2.4. Register 3 (03h) ................................................................................................................................................................51
24.2.5. Register 4 (04h) ................................................................................................................................................................51
24.2.6. Register 5 (05h) ................................................................................................................................................................52
24.2.7. Register 6 (06h) ................................................................................................................................................................52
24.2.8. Register 7 (07h) ................................................................................................................................................................52
24.2.9. Register 8 (08h) ................................................................................................................................................................52
24.2.10. Register 9 (09h) ................................................................................................................................................................52
24.2.11. Register 10 (0Ah)..............................................................................................................................................................52
24.2.12. Register 11 (0Bh)..............................................................................................................................................................52
24.2.13. Register 12 (0Ch)..............................................................................................................................................................53
24.2.14. Register 13 (0Dh)..............................................................................................................................................................53
24.2.15. Register 14 (0Eh)..............................................................................................................................................................53
24.2.16. Register 15 (0Fh)..............................................................................................................................................................54
24.2.17. Register 16 (10h) ..............................................................................................................................................................54
24.2.18. Register 17 (11h) ..............................................................................................................................................................55
24.2.19. Register 18 (12h) ..............................................................................................................................................................56
24.2.20. Register 19 (13h) ..............................................................................................................................................................56
24.2.21. Register 20 (14h) ..............................................................................................................................................................57
24.2.22. Register 21 (15h) ..............................................................................................................................................................57
24.2.23. Register 22 (16h) ..............................................................................................................................................................58
24.2.24. Register 23 (17h) ..............................................................................................................................................................58
24.2.25. Register 24 (18h) ..............................................................................................................................................................59
24.2.26. Register 25 (19h) ..............................................................................................................................................................60
24.2.27. Register 26 (1Ah)..............................................................................................................................................................61
24.2.28. Register 27 (1Bh)..............................................................................................................................................................62
24.2.29. Register 28 (1Ch)..............................................................................................................................................................63
24.2.30. Register 29 (1Dh)..............................................................................................................................................................63
24.2.31. Register 30 (1Eh)..............................................................................................................................................................64
24.2.32. Register 31 (1Fh)..............................................................................................................................................................64
24.2.33. Register 32 (20h) ..............................................................................................................................................................65
24.2.34. Register 33 (21h) ..............................................................................................................................................................65
24.2.35. Register 34 (22h) ..............................................................................................................................................................66
24.2.36. Register 35 (23h) ..............................................................................................................................................................66
24.2.37. Register 36 (24h) ..............................................................................................................................................................67
24.2.38. Register 37 (25h) ..............................................................................................................................................................67
24.2.39. Register 38 (26h) ..............................................................................................................................................................68
24.2.40. Register 39 (27h) ..............................................................................................................................................................68
24.2.41. Register 40 (28h) ..............................................................................................................................................................68
24.2.42. Register 41 (29h) ..............................................................................................................................................................68
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F159V Datasheet
24.2.43. Register 42 (2Ah)..............................................................................................................................................................68
24.2.44. Register 43 (2Bh)..............................................................................................................................................................68
24.2.45. Register 44 (2Ch)..............................................................................................................................................................68
24.2.46. Register 45 (2Dh)..............................................................................................................................................................69
24.2.47. Register 46 (2Eh)..............................................................................................................................................................69
24.2.48. Register 47 (2Fh)..............................................................................................................................................................69
24.2.49. Register 48 (30h) ..............................................................................................................................................................69
24.2.50. Register 49 (31h) ..............................................................................................................................................................69
25. Evaluation Kit Picture .................................................................................................................................................................................70
26. Evaluation Kit / Applications Circuit............................................................................................................................................................71
27. Application Information...............................................................................................................................................................................75
27.1. Power Supplies................................................................................................................................................................................75
27.2. Power Supply Sequencing...............................................................................................................................................................75
27.3. Digital Pin Voltage and Resistance Values......................................................................................................................................75
27.4. Phase Relation between the Quadrature Input Signals: I and Q .....................................................................................................75
27.5. Signal Integrity .................................................................................................................................................................................75
28. Package Outline Drawings .........................................................................................................................................................................77
29. Ordering Information...................................................................................................................................................................................77
30. Marking Diagram........................................................................................................................................................................................77
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F159V Datasheet
1. Pin Assignments
Figure 2. Pin Assignments for 10mm x 10mm x 0.9mm QFN Package – Top View
Vdd_SPI
GND_SPI
RESET
CH0_Vdd_VVA
CH0_RDIST_AMP
CH0_RBIAS
CH0_Vdd_AMP
GND
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
1
2
SPI Controller
90 / 0
Lock
Detect
3
∑
Vdd_REF
REF_IN
NC
4
Reference
Dividers
5
Phase
GND
6
Frequency
Detector
GND_REF
Vdd_CP
DNC
CH0_RFOUT
GND
7
8
DAC
DAC
Frac-N
Divider
VVA2 DSA AMP
VVA1
GND
9
GND
10
11
12
13
14
15
16
17
GND_CP
CP_OUT
GND_VCO
VTUNE
Charge
Pump
CH1_RFOUT
GND
/M
LO
Switch
Matrix
GND
VREF_VCO
Vdd_VCO
VCOM
CH1_Vdd_AMP
CH1_RBIAS
CH1_RDIST_AMP
CH1_Vdd_VVA
/2
∑
90 / 0
Vdd_LO
© 2020 Renesas Electronics Corporation
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F159V Datasheet
2. Pin Descriptions
Table 1.
Number
1
Pin Descriptions
Name
Description
Channel 0 voltage variable attenuator (VVA) power supply. Place bypass capacitors to GND as
close to this pin as possible.
CH0_Vdd_VVA
2
3
CH0_RDIST_AMP Channel 0 VGA amplifier distortion bias.
CH0_RBIAS
Channel 0 VGA amplifier current bias.
Channel 0 variable gain amplifier (VGA) power supply. Place bypass capacitors to GND as close to
this pin as possible.
4
CH0_Vdd_AMP
5
6
GND
GND
Internally grounded. This pin must be grounded as close to the device as possible.
Internally grounded. This pin must be grounded as close to the device as possible.
Channel 0 RF output. Must be AC-coupled.
7
CH0_RFOUT
GND
8
Internally grounded. This pin must be grounded as close to the device as possible.
Internally grounded. This pin must be grounded as close to the device as possible.
Internally grounded. This pin must be grounded as close to the device as possible.
Channel 1 RF output. Must be AC-coupled.
9
GND
10
11
12
13
GND
CH1_RFOUT
GND
Internally grounded. This pin must be grounded as close to the device as possible.
Internally grounded. This pin must be grounded as close to the device as possible.
GND
Channel 1 variable gain amplifier (VGA) power supply. Place bypass capacitors to GND as close to
this pin as possible.
14
CH1_Vdd_AMP
CH1_RBIAS
15
16
Channel 1 VGA amplifier current bias.
CH1_RDIST_AMP Channel 1 VGA amplifier distortion bias.
Channel 1 voltage variable attenuator (VVA) power supply. Place bypass capacitors to GND as
close to this pin as possible.
17
CH1_Vdd_VVA
CH1_AMPEN
Channel 1 Amplifier Enable / Disable. Logic LOW enable (normal operation); logic HIGH or NC for
disable (power down).
18
19
20
CH1_MODCOUPLE Channel 1 modulator coupled output.
Channel 1 modulator power supply pin. Place bypass capacitors to GND as close to this pin as
CH1_Vdd_MODAMP
possible.
21
22
23
CH1_RDIST_MOD Channel 1 modulator amplifier bias
CH1_QBB+
Channel 1 Quadrature differential baseband input. Internally matched to 110Ω.
CH1_QBB-
NC
No internal connection. This pin can be left unconnected, have a voltage applied, or be connected to
ground (recommended).
24
25
26
CH1_IBB+
CH1_IBB-
Channel 1 In-Phase differential baseband input. Internally matched to 110Ω.
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F159V Datasheet
Table 2.
Number
27
Pin Descriptions (Cont.)
Name
Description
Enable or disable Channel 1 modulator output. Logic LOW will enable the output (normal operation).
Logic HIGH or NC will disable the output (power down).
CH1_MODEN
CH1_Vdd_MODLO2
NC
Channel 1 modulator LO driver power supply. Place bypass capacitors to GND as close as possible
to the pin.
28
29
No internal connection. This pin can be left unconnected, have a voltage applied, or be connected to
ground (recommended).
30
31
32
33
34
35
36
37
GND_LO
LO_IN+
Internally grounded. This pin must be grounded as close to the device as possible.
Local oscillator (LO) 100Ω differential input. Pins must be AC-coupled.
LO_IN-
LO_OUT+
LO_OUT-
Vdd_LO
VCOM
Local oscillator (LO) 100Ω differential output. Pins must be AC-coupled.
Power supply pin. Place bypass capacitors to GND as close as possible to the pin.
Requires a capacitor from this pin to Vdd_VCO or to VREF_VCO for noise reduction.
Power Supply Voltage. Place bypass capacitors to GND as close as possible to the pin.
Vdd_VCO
Place decoupling capacitors (≥ 0.1µF) to ground, as close to the pin as possible. This pin indicates
voltage 2.8V when part is turned on.
38
VREF_VCO
39
40
VTUNE
Voltage control input to tune the VCO.
GND_VCO
Internally grounded. This pin must be grounded as close to the device as possible.
Charge Pump Output. When enabled, this output provides ± ICP to the external loop filter. The
output of the loop filter is connected to VTUNE to drive the internal VCO.
41
CP_OUT
42
43
GND_CP
DNC
Internally grounded. This pin must be grounded as close to the device as possible.
Do not connect anything to this pin.
Charge Pump Power Supply. Vdd_CP must have the same value as Vdd. Place decoupling
capacitors to the ground plane as close to this pin as possible.
44
45
46
Vdd_CP
GND_REF
NC
Internally grounded. This pin must be grounded as close to the device as possible.
No internal connection. This pin can be left unconnected, have a voltage applied, or be connected to
ground (recommended).
Reference Input. This CMOS input has a nominal threshold of Vdd/2 and a DC equivalent input
resistance of 100kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be
AC-coupled.
47
REF_IN
48
49
Vdd_REF
RESET
Power supply for reference path. Place bypass capacitors to GND as close as possible to the pin.
HIGH: Reset PLL. Resets all settings to default.
LOW: Normal Operating
50
51
52
53
54
GND_SPI
Vdd_SPI
SPI_CSN
SPI_CLK
SPI_DIO
Internally grounded. This pin must be grounded as close to the device as possible.
SPI power supply pin. Place bypass capacitors to GND as close to this pin as possible.
Serial chip Select. CSN pin can be pulled up to Vdd and down to GND.
Serial Clock Input.
Data write/read of 3-wire serial interface.
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F159V Datasheet
Table 3.
Pin Descriptions (Cont.)
Number
55
Name
Description
SPI_DO
LO_LD
Data read of 4-wire serial interface.
56
LO Lock Detect output. Logic HIGH indicates PLL lock. Logic LOW indicates loss of PLL lock.
Power supply for DACs. Place bypass capacitors to GND as close as possible to the pin.
57
Vdd_DAC
Channel 0 modulator LO driver power supply. Place bypass capacitors to GND as close as possible
to the pin.
58
59
CH0_Vdd_MODLO2
CH0_MODEN
Channel 0 modulator Enable / Disable. Logic LOW enable (normal operation); logic HIGH or NC for
disable (power down).
60
61
CH0_IBB-
CH0_IBB+
Channel 0 In-Phase differential baseband input. Internally matched to 110Ω.
No internal connection. This pin can be left unconnected, have a voltage applied, or be connected to
ground (recommended).
62
NC
63
64
65
CH0_QBB-
CH0_QBB+
Channel 0 Quadrature differential baseband input. Internally matched to 110Ω.
CH0_RDIST_MOD Channel 0 modulator amplifier bias.
Channel 0 modulator power supply pin. Place bypass capacitors to GND as close to this pin as
66
67
68
CH0_Vdd_MODAMP
possible.
CH0_MODCOUPLE Channel 0 modulator coupled output.
Enable or disable Channel 0 modulator output. Logic LOW will enable the output (normal operation).
Logic HIGH or NC will disable the output (power down).
CH0_AMPEN
-EPAD
Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses
multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These
multiple ground vias are also required to achieve the noted RF performance.
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F159V Datasheet
3. Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.
Functional operation of the F159V at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 4.
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
All VDD pins to GND
VDD
-0.3
-0.3
+3.6
V
V
SPI_DIO, SPI_CLK, SPI_DO, SPI_CSN, LO_LD
VSPILogic
VDD + 0.25
CH0_MODEN, CH1_MODEN,
CH0_AMPEN, CH1_AMPEN
VEnableLogic
-0.3
VDD + 0.25
V
CH0_RDIST_AMP, CH1_RDIST_AMP
CH0_RBIAS, CH1_RBIAS
VRDIST
VRBIAS
-0.3
-0.3
-0.3
-0.3
0.3
V
V
V
V
1
CH0_MODCOUPLE, CH1_MODCOUPLE
CH0_RDIST_MOD, CH1_RDIST_MOD
VMODOUT
VRDIST_MOD
VDD + 0.25
0.6
CH0_QBB+, CH0_QBB-, CH0_IBB+, CH0_IBB-
CH1_QBB+, CH1_QBB-, CH1_IBB+, CH1_IBB-
VBBIQ
-0.3
1.8
V
LO_IN-, LO_IN+, LO_OUT-, LO_OUT+
REF_IN, CP_OUT, VTUNE
CH0_RFOUT, CH1_RFOUT externally applied DC voltage
RESET
VLO
VLOGIC
VRFOUT
VRESET
VVCOM
VREFVCO
Pdiss
-0.3
-0.3
0
VDD + 0.25
VDD + 0.25
1.8
V
V
V
-0.3
-0.3
-0.3
VDD + 0.25
VDD + 0.25
VDD + 0.25
2.7
V
VCOM
V
VREF_VCO
V
Continuous Power Dissipation
Junction Temperature
W
°C
°C
°C
TJ
+150
Storage Temperature Range
Lead Temperature (soldering, 10s)
TSTOR
-65
+150
+260
Electrostatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
1000
(Class 1C)
VESDHBM
VESDCDM
V
V
Electrostatic Discharge – CDM
(JEDEC 22-C101F)
750
(Class C2)
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F159V Datasheet
4. Recommended Operating Conditions
Table 5.
Recommended Operating Conditions
Parameter
Symbol
VDD
Condition
All VDD pins
Exposed Paddle Temperature
Minimum
3.15
Typical
3.3
Maximum
Units
V
Supply Voltage(s)
3.45
+115
3.15
2.95
Operating Temperature Range [a]
TEP
-20
+25
°C
VCOVOLT1 Auto-calibration off
VCOVOLT2 Auto-calibration on
0.15
Min/Max VCO Tuning Voltage
V
0.35
Based on RF Power degraded
from Maximum Gain to
Baseband Input Frequency Range
fBB
DC
600
MHz
Minimum Gain
LO Input Frequency Range [b]
LO Input Power
fLO
PLO
fRF
450
-8
2800
0
MHz
dBm
MHz
V
RF Output Frequency Range [b]
Baseband Common Mode Voltage
450
0.1
2800
0.8
VCM
TEP = -20°C to +115°C
Each baseband pin
0.325
110
Baseband Input Voltage
Compliance Range
VBB
0
1
Vpeak
ZBB0I_IN
ZBB1I_IN
ZBB0Q_IN
ZBB1Q_IN
Baseband Input Port Impedance
Differential
Ω
LO Input Port Impedance
LO Output Port Impedance
RF Output Impedance
ZLO_IN
ZLO_OUT
ZRFO
Differential
100
100
50
Ω
Ω
Ω
Ω
Differential
Single Ended
Single Ended
Modulator Output Impedance
ZMODO
50
[a] On startup of the device, the temperature can be as low as -40°C. Device will not lose PLL lock with auto-calibration on after it
warms up. Device functions normally but not specified for temperatures below -20°C.
[b] Expect a slight performance degradation from 600MHz to 450MHz.
© 2020 Renesas Electronics Corporation
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F159V Datasheet
5. Electrical Characteristics
Table 6.
General Characteristics
See the F159V Typical Application Circuit. Operated as a dual-path transmitter, VDD = +3.3V, Internal fLO = 2050MHz to generate fRF = 2000MHz,
LO_SW_OUT= +4dBm setting, TEP = +25°C, maximum gain setting, all Enable pins = GND, BB_IQ frequency = 49MHz or 50MHz, I leads Q
by 90 degrees, BB_I&Q levels = 100mVp-p each tone differential, I and Q = 0.325V common-mode bias, ZBB_DIFF = 110Ω, ZRFO = 50Ω,
parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
DC
+1.1 [a]
0.0
VDD + 0.25
+0.6
Logic Input HIGH
Logic Input LOW
VIH
VIL
JEDEC 1.8 and JEDEC 3.3
JEDEC 1.8 and JEDEC 3.3
JEDEC 1.8
V
V
VOH_1.8
VOH_3.3
VOL_1.8
VOL_3.3
IIH
+1.4
+2.0
0.0
+2.1
Logic Output High
Logic Output Low
V
V
JEDEC 3.3
+3.6
JEDEC 1.8
+0.4
JEDEC 3.3
0.0
+0.66
100
Logic Current – High Logic
Logic Current – Low Logic
µA
µA
-100
-100
IIL
100
IDD_PLL
Frequency Synthesizer
132
33
170
External LO Driver at
maximum LO_buffer gain
IDD_LO
40
IDD_2MOD
IDD_2AMP
IDD_DAC
2 modulators
2 VGAs
387
153
14
450
183
17
Supply Current – Both paths [b]
mA
2 DACs
IDD_Enable2 Standby Mode dual path
51
IDD_PLL
Frequency Synthesizer
132
170
40
External LO Driver at
maximum LO_buffer gain
IDD_LO
33
Supply Current – One path [b]
Charge Pump Current
mA
mA
IDD_1MOD
IDD_1AMP
IDD_DAC
1 modulator
1 VGA
194
79
235
95
2 DACs
14
17
Programmable in ~0.3mA
steps
ICP
0.2
6
General
LO output power
External LO input Return Loss
External LO output Return Loss
SPI
LOPout
RLLO_IN
LO_OUT Setting = +4dBm
dBm
dB
-2
8
+4
Differential 100Ω
15
15
RLLO_OUT Differential 100Ω
10
dB
Serial Clock Speed
SPICLK
MHz
20
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these
columns that are not shown in bold italics are guaranteed by design characterization.
[b] Values valid for CP current set to 0.94mA, LO_SW_OUT = 0dBm.
© 2020 Renesas Electronics Corporation
11
May 15, 2020
F159V Datasheet
Table 7.
Electrical Characteristics
See the F159V Typical Application Circuit. Operated as a dual-path transmitter, VDD = +3.3V, Internal fLO = 2050MHz to generate fRF = 2000MHz,
LO_SW_OUT= +4dBm setting, TEP = +25°C, maximum gain setting, all Enable pins = GND, BB_IQ frequency = 49MHz or 50MHz, I leads Q
by 90 degrees, BB_I&Q levels = 100mVp-p each tone differential, I and Q = 0.325V common-mode bias, ZBB_DIFF = 110Ω, ZRFO = 50Ω,
parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Parameter
Digital Step Attenuator
DSA adjustment range
DSA step
Symbol
Condition
Minimum
Typical
Maximum
Units
GDSA
31
1
dB
dB
GDSASTEP
+2 /
-2.3
Max DSA Glitching
Gain Accuracy
ATTNG
During DSA state change
dB
dB
DSAACCMAX Gain Error vs. line (AMIN ref)
Worst case 4dB step
± (0.05 + 5% ATTN value)
4
6
Worst case 8dB step
DSA_PH
Relative Phase Shift
Deg
µs
fRF = 2.8GHz
Worst case 2dB step
4
0dB to Max attenuation
Maximum attenuation to 0dB
End DSA register
configuration to output within
0.1dB
DSA Gain Settling Time
DSAST
1
2
Voltage Variable Attenuator
DAC input
0 for maximum attenuation
2047 for minimum attenuation
26 [a]
VVA adjustment range
GVVA
32
dB
VVA step
GVVASTEP Using on-chip 11-bit DAC
VVAPHASE Worst case 2dB step
0.02
4
dB
Relative Phase Shift
Deg
Gain variation from DAC code
VVAERROR 250 to 1750 relative to typical
gain variation
Relative Error
-2
2
dB
µs
Any 1dB step
TSETTL0.1dB Includes DAC + VVA
response
Settling Time to within 0.1dB
0.40
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these
columns that are not shown in bold italics are guaranteed by design characterization.
© 2020 Renesas Electronics Corporation
12
May 15, 2020
F159V Datasheet
Table 8.
Electrical Characteristics (Cont.)
See the F159V Typical Application Circuit. Operated as a dual-path transmitter, VDD = +3.3V, Internal fLO = 2050MHz to generate fRF = 2000MHz,
LO_SW_OUT= +4dBm setting, TEP = +25°C, maximum gain setting, all Enable pins = GND, BB_IQ frequency = 49MHz or 50MHz, I leads Q
by 90 degrees, BB_I&Q levels = 100mVp-p each tone differential, I and Q = 0.325V common-mode bias, ZBB_DIFF = 110Ω, ZRFO = 50Ω,
parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Parameter
Modulator Stage
Symbol
Condition
Minimum Typical Maximum Units
BB input = 210mVp-p differential
Modulator output
Maximum VVA & DSA attenuation
Modulator power coupled output
PM_OUT
-31 [a]
-9
-28
-6
dBm
dBm
dBm
P1dB at Modulator coupled output OP1dBM_OUT Maximum VVA & DSA attenuation
BB input = 210mVp-p differential per
OIP3M_OUT tone
Maximum VVA & DSA attenuation
IP3 at Modulator coupled output
fLO ± 2*fBB Rejection
10.7
fBB ≤ 100MHz
Mod output coupled node
BB input = 210mVp-p differential
Maximum VVA & DSA attenuation
2BBREJ_CPL
3BBREJ_CPL
5BBREJ_CPL
-82
-80
-96
-50
-50
dBc
dBc
dBc
fBB ≤ 100MHz
Mod output coupled node
BB input = 210mVp-p differential
Maximum VVA & DSA attenuation
fLO ± 3*fBB Rejection
FBB ≤ 100MHz
Mod output coupled node
BB input = 210mVp-p differential
Maximum VVA & DSA attenuation
fLO ± 5*fBB Rejection
Turn-on time
Enable = LOW to HIGH. Power is within
0.05dB of final power
PON
0.6
0.1
µs
µs
Enable = HIGH to LOW. Power
is -30dBc from initial output power
Turn off time
Cascaded VGA
Turn-on time
POFF
Enable = LOW to HIGH. Power is within
0.05dB of final power
PON
0.8
0.1
µs
µs
Enable = HIGH to LOW. Power
is -30dBc from initial output power
Turn off time
POFF
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these
columns that are not shown in bold italics are guaranteed by design characterization.
© 2020 Renesas Electronics Corporation
13
May 15, 2020
F159V Datasheet
Table 9.
Electrical Characteristics – Frequency Synthesizer
See the F159V Typical Application Circuit. Operated as a dual-path transmitter, VDD = +3.3V, Internal fLO = 2050MHz to generate fRF = 2000MHz,
LO_SW_OUT= +4dBm setting, TEP = +25°C, maximum gain setting, all Enable pins = GND, BB_IQ frequency = 49MHz or 50MHz, I leads Q
by 90 degrees, BB_I&Q levels = 100mVp-p each tone differential, I and Q = 0.325V common-mode bias, ZBB_DIFF = 110Ω, ZRFO = 50Ω,
parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Synthesizer conditions include: PLL Ref = 30.72MHz, CP current = 0.63mA, LO_OUT power = +4dBm, Cal_LoPN_Mode = 0, Ref Doubler =
ON, Reference Divider is set for 1. Synthesizer performance will be evaluated at the LO output pins. The evaluation board and connector losses
are de-embedded, unless otherwise noted.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Frequency Synthesizer / VCO
Synthesizer Output Frequency
Input Reference Frequency [b]
450 [a]
10
2800
250
FRFSYNTH_OUT Divider values; 1, 2, 4, 8
FREF_IN
MHz
MHz
30.72
Single-ended, peak-peak
AC coupled
PLL Reference Input Level
VCO Frequency
VREF_pp
V
0.7
3.3
FVCO
Fundamental VCO Mode
MHz
µs
2000
4000
Includes SPI configuration
time using a 10MHz SPI
Maximum Lock Time
TLOCK
360
End of SPI configuration to
LO_LD logic high
Power-up Time
TPOWERUP
1.25
ms
SPUR1
SPUR2
100kHz – 30MHz offset
>30MHz offset
< -90
< -90
-97
Spurs (non-harmonics)
dBc
PN_200K 200kHz offset
PN_400K 400kHz offset
PN_600K 600kHz offset
PN_1.2M 1.2MHz offset
PN_1.8M 1.8MHz offset
-126
-136
-140
-146
-152
-94
PLL Phase Noise Performance
LO = 942.5MHz
(Use internal VCO at 3770MHz and
divide by 4)
dBc/Hz
PN_6M
6.0MHz offset
PN_200K 200kHz offset
PN_400K 400kHz offset
PN_600K 600kHz offset
PN_1.2M 1.2MHz offset
PN_1.8M 1.8MHz offset
-123
-131
-137
-141
-150
PLL Phase Noise Performance
LO = 1847.5MHz
(Use internal VCO at 3695MHz and
divide by 2)
dBc/Hz
PN_6M
6.0MHz offset
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these
columns that are not shown in bold italics are guaranteed by design characterization.
[b] When input reference frequency is between 10MHz and 20MHz, the reference doubler must be turned on.
© 2020 Renesas Electronics Corporation
14
May 15, 2020
F159V Datasheet
Table 10. Electrical Characteristics – Frequency Synthesizer (Cont.)
See the F159V Typical Application Circuit. Operated as a dual-path transmitter, VDD = +3.3V, Internal fLO = 2050MHz to generate fRF = 2000MHz,
LO_SW_OUT= +4dBm setting, TEP = +25°C, maximum gain setting, all Enable pins = GND, BB_IQ frequency = 49MHz or 50MHz, I leads Q
by 90 degrees, BB_I&Q levels = 100mVp-p each tone differential, I and Q = 0.325V common-mode bias, ZBB_DIFF = 110Ω, ZRFO = 50Ω,
parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Synthesizer conditions include: PLL Ref = 30.72MHz, CP current = 0.63mA, LO_OUT power = +4dBm, Cal_LoPN_Mode = 0, Reference Doubler
= ON, Reference Divider is set for 1. Synthesizer performance will be evaluated at the LO output pins. The evaluation board and connector
losses are de-embedded, unless otherwise noted.
Parameter
Symbol
Condition
Minimum
Typical
-138
Maximum
Units
PN_2.1M 2.1MHz offset
PN_3.5M 3.5MHz offset
PN_7.5M 7.5MHz offset
PN_2.1M 2.1MHz offset
PN_3.5M 3.5MHz offset
PN_7.5M 7.5MHz offset
PLL Phase Noise Performance
LO = 2155MHz
(Use internal VCO frequency at
2155MHz and divide by 1)
-143
dBc/Hz
-152
-138
PLL Phase Noise Performance
LO = 2655MHz
(Use internal VCO frequency at
2655MHz and divide by 1)
-143
dBc/Hz
-151
Table 11. Electrical Characteristics – Signal Path Cascaded Performance
See the F159V Typical Application Circuit. Operated as a dual-path transmitter, VDD = +3.3V, Internal fLO = 2050MHz to generate fRF = 2000MHz,
LO_SW_OUT= +4dBm setting, TEP = +25°C, maximum gain setting, all Enable pins = GND, BB_IQ frequency = 49MHz or 50MHz, I leads Q
by 90 degrees, BB_I&Q levels = 100mVp-p each tone differential, I and Q = 0.325V common-mode bias, ZBB_DIFF = 110Ω, ZRFO = 50Ω,
parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
16 [a]
21
Input power is sum of I + Q
For BB_I = BB_Q = 94mVp-p
differential each, total power =
-17dBm
PGain max
18.3
Power Gain
dB
PGain min
-45
Gain Variation
Gain Flatness
TEP from -20°C to +115°C
-1 to +0.5
dB
GVAR_ T
∆
1400MHz to 2700MHz
measured using 100MHz
steps
GFLAT
0.0021
0.005
dB/MHz
fRF = 450MHz
fLO = 500MHz
Power Gain at 450MHz RF
G450
13.5
dB
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these
columns that are not shown in bold italics are guaranteed by design characterization.
© 2020 Renesas Electronics Corporation
15
May 15, 2020
F159V Datasheet
Table 12. Electrical Characteristics – Signal Path Cascaded Noise Figure Performance
See the F159V Typical Application Circuit. Operated as a dual-path transmitter, VDD = +3.3V, Internal fLO = 2050MHz to generate fRF = 2000MHz,
LO_SW_OUT= +4dBm setting, TEP = +25°C, maximum gain setting, all Enable pins = GND, BB_IQ frequency = 49MHz or 50MHz, I leads Q
by 90 degrees, BB_I&Q levels = 100mVp-p each tone differential, I and Q = 0.325V common-mode bias, ZBB_DIFF = 110Ω, ZRFO = 50Ω,
parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Parameter
Symbol
Condition
No attenuation
Minimum
Typical
Maximum
Units
NFGMAX
13.0
14.3 [a]
VVA 14dB attenuation
DSA 1dB attenuation
NFG-15
NFG-19
NFG-31
NFG-40
17.9
21.4
23.3
23.6
19.7
VVA 14dB attenuation
DSA 5dB attenuation
VVA 14dB attenuation
DSA 17dB attenuation
VVA 14dB attenuation
DSA 26dB attenuation
VVA 5dB attenuation
DSA 1dB attenuation
TEP = +115°C
NFG-6
NFG-10
NFG-22
NFG-31
NFG-23
NFG-27
NFG-39
15.5
16.9
18
16.8
VVA 5dB attenuation
DSA 5dB attenuation
TEP = +115°C
VVA 5dB attenuation
DSA 17dB attenuation
TEP = +115°C
Noise Figure
dB
VVA 5dB attenuation
DSA 26dB attenuation
TEP = +115°C
19.6
19.7
23
VVA 22dB attenuation
DSA 1dB attenuation
TEP = -20°C
21.2
VVA 22dB attenuation
DSA 5dB attenuation
TEP = -20°C
VVA 22dB attenuation
DSA 17dB attenuation
TEP = -20°C
24.8
VVA 22dB attenuation
DSA 26dB attenuation
TEP = -20°C
NFG-48
NFloor
30.4
VVA 14dB attenuation
DSA 1dB attenuation
Output Noise Floor
-152.3
dBm/Hz
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these
columns that are not shown in bold italics are guaranteed by design characterization.
© 2020 Renesas Electronics Corporation
16
May 15, 2020
F159V Datasheet
Table 13. Electrical Characteristics – Signal Path Cascaded IP3 Performance
See the F159V Typical Application Circuit. Operated as a dual-path transmitter, VDD = +3.3V, Internal fLO = 2050MHz to generate fRF = 2000MHz,
LO_SW_OUT= +4dBm setting, TEP = +25°C, maximum gain setting, all Enable pins = GND, BB_IQ frequency = 49MHz or 50MHz, I leads Q
by 90 degrees, BB_I&Q levels = 100mVp-p each tone differential, I and Q = 0.325V common-mode bias, ZBB_DIFF = 110Ω, ZRFO = 50Ω,
parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Parameter
Symbol
OIP31
Condition
Minimum
Typical
28.6
31
Maximum
Units
Output IP3
VVA 14dB attenuation
DSA 1dB attenuation
PIN = -13dBm/tone
fLO = 900MHz
fRF = 850MHz
dBm
OIP32
No attenuation
VVA 14dB attenuation
OIP3G-15 DSA 1dB attenuation
25 [a]
31
PIN = -13dBm/tone
VVA 14dB attenuation
OIP3G-19 DSA 5dB attenuation
PIN = -9dBm/tone
28.4
16.4
6.8
VVA 14dB attenuation
OIP3G-31 DSA 17dB attenuation
PIN = -9dBm/tone
VVA 14dB attenuation
OIP3G-40 DSA 26dB attenuation
PIN = -9dBm/tone
VVA 5dB attenuation
DSA 1dB attenuation
PIN = -13dBm/tone
TEP = +115°C
OIP3G-6
25
25
Output IP3
fLO = 2050MHz
RF = 2000MHz
dBm
f
VVA 5dB attenuation
DSA 5dB attenuation
PIN = -9dBm/tone
OIP3G-10
TEP = +115°C
VVA 5dB attenuation
DSA 17dB attenuation
PIN = -9dBm/tone
TEP = +115°C
OIP3G-22
16.4
7.4
19
VVA 5dB attenuation
DSA 26dB attenuation
PIN = -9dBm/tone
TEP = +115°C
OIP3G-31
VVA 22dB attenuation
DSA 1dB attenuation
PIN = -13dBm/tone
OIP3G-23
TEP = -20°C
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these
columns that are not shown in bold italics are guaranteed by design characterization.
© 2020 Renesas Electronics Corporation
17
May 15, 2020
F159V Datasheet
Table 14. Electrical Characteristics – Signal Path Cascaded IP3 Performance (Cont.)
See the F159V Typical Application Circuit. Operated as a dual-path transmitter, VDD = +3.3V, Internal fLO = 2050MHz to generate fRF = 2000MHz,
LO_SW_OUT= +4dBm setting, TEP = +25°C, maximum gain setting, all Enable pins = GND, BB_IQ frequency = 49MHz or 50MHz, I leads Q
by 90 degrees, BB_I&Q levels = 100mVp-p each tone differential, I and Q = 0.325V common-mode bias, ZBB_DIFF = 110Ω, ZRFO = 50Ω,
parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
VVA 22dB attenuation
DSA 5dB attenuation
PIN = -9dBm/tone
TEP = -20°C
OIP3G-27
20.4
VVA 22dB attenuation
DSA 17dB attenuation
PIN = -9dBm/tone
TEP = -20°C
Output IP3
fLO = 2050MHz
RF = 2000MHz
OIP3G-39
OIP3G-48
8.7
-2
dBm
f
VVA 22dB attenuation
DSA 26dB attenuation
PIN = -9dBm/tone
TEP = -20°C
Output IP3
fLO = 2750MHz
fRF = 2700MHz
VVA 14dB attenuation
OIP3G-15 DSA 1dB attenuation
PIN = -13dBm/tone
28
28
dBm
dBm
Output IP3
fLO = 500MHz
VVA 14dB attenuation
DSA 1dB attenuation
OIP3450
fRF = 450MHz
PIN = -13dBm/tone
© 2020 Renesas Electronics Corporation
18
May 15, 2020
F159V Datasheet
Table 15. Electrical Characteristics – Signal Path Cascaded P1dB Performance
See the F159V Typical Application Circuit. Operated as a dual-path transmitter, VDD = +3.3V, Internal fLO = 2050MHz to generate fRF = 2000MHz,
LO_SW_OUT= +4dBm setting, TEP = +25°C, maximum gain setting, all Enable pins = GND, BB_IQ frequency = 49MHz or 50MHz, I leads Q
by 90 degrees, BB_I&Q levels = 100mVp-p each tone differential, I and Q = 0.325V common-mode bias, ZBB_DIFF = 110Ω, ZRFO = 50Ω,
parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Parameter
Symbol
Condition
No attenuation
Minimum
Typical
Maximum
Units
OP1dB1
14
VVA 14dB attenuation
DSA 1dB attenuation
10 [a]
OP1dBG-15
OP1dBG-19
OP1dBG-31
OP1dBG-40
12
11.2
-0.8
-10
VVA 14dB attenuation
DSA 5dB attenuation
VVA 14dB attenuation
DSA 17dB attenuation
VVA 14dB attenuation
DSA 26dB attenuation
VVA 5dB attenuation
OP1dBG-6 DSA 1dB attenuation
TEP = +115°C
12.6
12.6
2.8
VVA 5dB attenuation
OP1dBG-10 DSA 5dB attenuation
TEP = +115°C
Output P1dB
VVA 5dB attenuation
OP1dBG-22 DSA 17dB attenuation
TEP = +115°C
fLO = 2050MHz
RF = 2000MHz
dBm
f
VVA 5dB attenuation
OP1dBG-31 DSA 26dB attenuation
TEP = +115°C
-6.2
6.6
VVA 22dB attenuation
OP1dBG-23 DSA 1dB attenuation
TEP = -20°C
VVA 22dB attenuation
OP1dBG-27 DSA 5dB attenuation
TEP = -20°C
2.9
VVA 22dB attenuation
OP1dBG-39 DSA 17dB attenuation
TEP = -20°C
-9.4
-18.7
13.8
VVA 22dB attenuation
OP1dBG-48 DSA 26dB attenuation
TEP = -20°C
Output P1dB
fLO = 500MHz
fRF = 450MHz
OP1dB450
dBm
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these
columns that are not shown in bold italics are guaranteed by design characterization.
© 2020 Renesas Electronics Corporation
19
May 15, 2020
F159V Datasheet
Table 16. Electrical Characteristics – Signal Path Cascaded General Performance
See the F159V Typical Application Circuit. Operated as a dual-path transmitter, VDD = +3.3V, Internal fLO = 2050MHz to generate fRF = 2000MHz,
LO_SW_OUT= +4dBm setting, TEP = +25°C, maximum gain setting, all Enable pins = GND, BB_IQ frequency = 49MHz or 50MHz, I leads Q
by 90 degrees, BB_I&Q levels = 100mVp-p each tone differential, I and Q = 0.325V common-mode bias, ZBB_DIFF = 110Ω, ZRFO = 50Ω,
parameters measured at RF output, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise stated.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
From CH0_IBB/QBB to
CH1_IBB_QBB and vice
versa
ISOIQBB
89
Channel Isolation
dB
ISOVGA
LOsupp
SS
See note [b]
45 [a]
47
-25
-40
LO (Carrier) Suppression
Native, uncorrected
Native, uncorrected
fLO = 900MHz, measured at
fLO + (fBB1 ± fBB2
fLO = 2050MHz, measured at
fLO + (fBB1 ± fBB2
fLO = 2900MHz, measured at
fLO + (fBB1 ± fBB2
fBB ≤ 100MHz
fBB ≤ 100MHz
fBB ≤ 100MHz
fBB ≤ 100MHz
fBB ≤ 100MHz
dBm
dBc
-18
-23
Sideband (Image) Suppression
Output IP2 at 850MHz
Output IP2 at 2.00GHz
Output IP2 at 2.85GHz
OIP21
OIP22
OIP23
78
62
61
dBm
dBm
dBm
)
59
)
)
fLO ± 2* fBB Rejection
fLO ± 3* fBB Rejection
fLO ± 5*fBB Rejection
2nd Harmonic of the LO
3rd Harmonic of the LO
2BBREJ
3BBREJ
5BBREJ
HD2
-72
-95
-87
-42
-67
-67
-75
-78
dBc
dBc
dBc
dBc
dBc
HD3
Within DPD bandwidth
VVA = 14dB
RF Output Return Loss
RLRFO
10
12
dB
DSA = 1dB
Between 2 channels with any
attenuator setting
Group Delay Error
GD
±3
ns
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these
columns that are not shown in bold italics are guaranteed by design characterization.
[b] Baseband signals applied to CH0 baseband inputs (CH1 baseband inputs) with CH1 baseband inputs (CH0 baseband inputs)
turned off. Measure the difference in the RF power between CH0_RFOUT (CH1_RFOUT) and CH1_RFOUT (CH0_RFOUT).
This difference is the channel isolation.
© 2020 Renesas Electronics Corporation
20
May 15, 2020
F159V Datasheet
6. Thermal Characteristics
Table 17. Package Thermal Characteristics
Parameter
Symbol
Value
Units
Junction to Ambient Thermal Resistance
θJA
32
°C/W
Junction to Case Thermal Resistance.
(Case is defined as the exposed paddle)
θJC-BOT
3
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL 3
7. Typical Operating Conditions (TOC)
Unless otherwise noted, for the TOC graphs on the following pages, the following conditions apply:
.
.
.
.
.
.
.
.
.
.
.
Baseband I and Q levels = -20dBm each tone (~ 100mVp-p differential/channel/tone across 110Ω)
Baseband I and Q tones = 49MHz, 50MHz
Maximum Gain Setting
Use internal LO with LO_SW_OUT for +4dBm setting
TEP = +25°C
VDD = +3.3V
VCM = +0.325V
Internal fLO = 2050MHz
OIP2 Measured at fLO + (fBB1 ± fBB2
Enable pins = GND
)
EVKit RF output trace and connector losses de-embedded
© 2020 Renesas Electronics Corporation
21
May 15, 2020
F159V Datasheet
8. Typical Performance Characteristics
Figure 3. Baseband Differential Input Return
Loss
Figure 4. LO Differential Input Return Loss
0
0
-5
-20 C / BB_I
+25 C / BB_I
+115 C / BB_I
-20 C / BB_Q
+25 C / BB_Q
+115 C / BB_Q
-5
-10
-15
-20
-25
-30
-10
-15
-20
-25
-30
-20 C
+25 C
+115 C
0
200
400
600
800
1000
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Baseband Frequency (MHz)
LO Frequency (GHz)
Figure 5. Modulator Coupled Output Return
Loss
Figure 6. LO Differential Output Return Loss
0
0
-5
-20 C / CH0_MOD
+25 C / CH0_MOD
+115 C / CH0_MOD
-20 C / CH1_MOD
+25 C / CH1_MOD
+115 C / CH1_MOD
-5
-10
-15
-20
-25
-30
-10
-15
-20
-20 C
+25 C
+115 C
-25
-30
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
Frequency (GHz)
Figure 7. RF Output Return Loss (Maximum
Gain)
Figure 8. RF Output Return Loss (+25 °C)
0
0
DSA= 5 dB / VVA= 5 dB
DSA=14 dB / VVA= 5 dB
DSA=22 dB / VVA= 5 dB
DSA= 5 dB / VVA=14 dB
DSA=14 dB / VVA=14 dB
DSA=22 dB / VVA=14 dB
DSA= 5 dB / VVA=25 dB
-20 C / CH0_RF
+25 C / CH0_RF
+115 C / CH0_RF
-20 C / CH1_RF
+25 C / CH1_RF
+115 C / CH1_RF
DSA=14 dB / VVA=25 dB
DSA=22 dB / VVA=25 dB
-5
-10
-15
-20
-25
-30
-5
-10
-15
-20
-25
-30
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
RF Frequency (GHz)
RF Frequency (GHz)
© 2020 Renesas Electronics Corporation
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May 15, 2020
F159V Datasheet
9. Typical Performance Characteristics - VVA
Figure 9. Gain versus VVA DAC Setting
(+3.3V, 2GHz)
Figure 10. Relative Phase versus VVA DAC
Setting (+3.3V, +25°C)
20
15
10
5
30
25
20
15
10
5
0
-5
-10
0
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-15
-20
-5
0.45 GHz
0.84 GHz
1.95 GHz
2.00 GHz
2.81 GHz
-10
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
DAC Setting
DAC Setting
Figure 11. OIP3 versus VVA DAC Setting
(+3.3V, 2GHz)
Figure 12. VVA Maximum to Minimum Switching
(+3.3V, +25°C, 2GHz)
35
30
25
20
15
10
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
5
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
DAC Setting
Figure 13. VVA Minimum to Maximum Switching
(+3.3V, +25°C, 2GHz)
© 2020 Renesas Electronics Corporation
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May 15, 2020
F159V Datasheet
10. Typical Performance Characteristics - DSA
Figure 14. Gain versus DSA (+3.3V)
Figure 15. Relative Phase versus DSA
(+3.3V, +25°C)
20
15
10
5
20
15
10
5
0
0
-5
-5
-10
-10
-15
-20
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-15
-20
0.45 GHz
0.84 GHz
1.95 GHz
2.00 GHz
2.81 GHz
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuator Setting (dB)
Attenuator Setting (dB)
Figure 16. Gain Accuracy versus DSA
(+3.3V)
Figure 17. DSA Maximum to Minimum Switching
(+3.3V, +25°C)
0.5
0.0
-0.5
-1.0
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-1.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuator Setting (dB)
Figure 18. Step Error versus DSA (+3.3V)
Figure 19. DSA Minimum to Maximum Switching
(+3.3V, +25°C)
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-0.3
-0.4
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuator Setting (dB)
© 2020 Renesas Electronics Corporation
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May 15, 2020
F159V Datasheet
11. Typical Performance Characteristics - Cascaded Gain
Figure 20. Gain versus Frequency (+25°C)
Figure 21. Gain versus Frequency (+3.3V)
20
20
19
18
17
16
15
14
13
12
11
10
VVA = 0 dB, DSA = 0 dB
VVA = 0 dB, DSA = 0 dB
19
18
17
16
15
14
13
12
+3.15 V / CH 0
+3.30 V / CH 0
+3.45 V / CH 0
+3.15 V / CH 1
+3.30 V / CH 1
+3.45 V / CH 1
-20 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
+25 C / CH 0
+115 C / CH 0
11
10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
RF Frequency (GHz)
RF Frequency (GHz)
Figure 22. Gain versus Frequency (+3.3V)
Figure 23. Gain versus Frequency (+3.3V)
10
-2
VVA = 5 dB, DSA = 5 dB
VVA = 5 dB, DSA = 17 dB
9
8
7
6
5
4
3
2
1
0
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
Figure 24. Gain versus Frequency (+3.3V)
Figure 25. Gain versus Frequency (+3.3V)
-2
-10
VVA = 22 dB, DSA = 1 dB
VVA = 5 dB, DSA = 26 dB
-3
-4
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-5
-6
-7
-8
-9
-10
-11
-12
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
© 2020 Renesas Electronics Corporation
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May 15, 2020
F159V Datasheet
12. Typical Performance Characteristics - Cascaded Gain (Cont.)
Figure 26. Gain versus Frequency (+3.3V)
Figure 27. Gain versus Frequency (+3.3V)
2
-6
-7
VVA = 14 dB, DSA = 5 dB
VVA = 22 dB, DSA = 5 dB
1
0
-8
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
RF Frequency (GHz)
RF Frequency (GHz)
Figure 28. Gain versus Frequency (+3.3V)
Figure 29. Gain versus Frequency (+3.3V)
-10
-18
VVA = 14 dB, DSA = 17 dB
VVA = 22 dB, DSA = 17 dB
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-19
-20
-21
-22
-23
-24
-25
-26
-27
-28
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
Figure 30. Gain versus Frequency (+3.3V)
Figure 31. Gain versus Frequency (+3.3V)
-20
-28
VVA = 14 dB, DSA = 26 dB
VVA = 22 dB, DSA = 26 dB
-21
-22
-23
-24
-25
-26
-27
-28
-29
-30
-29
-30
-31
-32
-33
-34
-35
-36
-37
-38
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
© 2020 Renesas Electronics Corporation
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May 15, 2020
F159V Datasheet
13. Typical Performance Characteristics - Cascaded OIP3
Figure 32. OIP3 versus Frequency (+25°C)
Figure 33. OIP3 versus Frequency (+3.3V)
40
40
38
36
34
32
30
28
26
24
22
20
VVA = 0 dB, DSA = 0 dB
VVA = 0 dB, DSA = 0 dB
38
36
34
32
30
28
26
24
22
20
+3.15 V / CH 0
+3.30 V / CH 0
+3.45 V / CH 0
+3.15 V / CH 1
+3.30 V / CH 1
+3.45 V / CH 1
-20 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
+25 C / CH 0
+115 C / CH 0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
RF Frequency (GHz)
RF Frequency (GHz)
Figure 34. OIP3 versus Frequency (+3.3V)
Figure 35. OIP3 versus Frequency (+3.3V)
34
30
VVA = 5 dB, DSA = 5 dB
VVA = 5 dB, DSA = 17 dB
32
30
28
26
24
22
20
18
16
14
28
26
24
22
20
18
16
14
12
10
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
Figure 36. OIP3 versus Frequency (+3.3V)
Figure 37. OIP3 versus Frequency (+3.3V)
34
20
VVA = 22 dB, DSA = 1 dB
VVA = 5 dB, DSA = 26 dB
32
30
28
26
24
22
20
18
16
14
18
16
14
12
10
8
6
4
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
© 2020 Renesas Electronics Corporation
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May 15, 2020
F159V Datasheet
14. Typical Performance Characteristics - Cascaded OIP3 (Cont.)
Figure 38. OIP3 versus Frequency (+3.3V)
Figure 39. OIP3 versus Frequency (+3.3V)
34
30
28
26
24
22
20
18
16
14
12
10
VVA = 14 dB, DSA = 5 dB
VVA = 22 dB, DSA = 5 dB
32
30
28
26
24
22
20
18
16
14
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
+25 C / CH 0
+115 C / CH 0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
RF Frequency (GHz)
RF Frequency (GHz)
Figure 40. OIP3 versus Frequency (+3.3V)
Figure 41. OIP3 versus Frequency (+3.3V)
26
16
VVA = 14 dB, DSA = 17 dB
VVA = 22 dB, DSA = 17 dB
24
22
20
18
16
14
12
10
8
14
12
10
8
6
4
2
0
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-2
-4
6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
Figure 42. OIP3 versus Frequency (+3.3V)
Figure 43. OIP3 versus Frequency (+3.3V)
16
6
VVA = 14 dB, DSA = 26 dB
VVA = 22 dB, DSA = 26 dB
14
12
10
8
4
2
0
-2
6
-4
4
-6
2
-8
0
-10
-12
-14
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-2
-4
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
© 2020 Renesas Electronics Corporation
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May 15, 2020
F159V Datasheet
15. Typical Performance Characteristics - Cascaded OIP2
Figure 44. OIP2 versus Frequency (+25°C)
Figure 45. OIP2 versus Frequency (+3.3V)
85
85
80
75
70
65
60
55
50
45
40
VVA = 0 dB, DSA = 0 dB
VVA = 0 dB, DSA = 0 dB
80
75
70
65
60
55
+3.15 V / CH 0
+3.30 V / CH 0
+3.45 V / CH 0
+3.15 V / CH 1
+3.30 V / CH 1
+3.45 V / CH 1
-20 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
50
45
+25 C / CH 0
+115 C / CH 0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
RF Frequency (GHz)
RF Frequency (GHz)
Figure 46. OIP2 versus Frequency (+3.3V)
Figure 47. OIP2 versus Frequency (+3.3V)
90
80
VVA = 5 dB, DSA = 5 dB
VVA = 5 dB, DSA = 17 dB
85
80
75
70
65
60
55
50
75
70
65
60
55
50
45
40
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
Figure 48. OIP2 versus Frequency (+3.3V)
Figure 49. OIP2 versus Frequency (+3.3V)
80
70
VVA = 22 dB, DSA = 1 dB
VVA = 5 dB, DSA = 26 dB
75
70
65
60
55
50
45
40
65
60
55
50
45
40
35
30
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
© 2020 Renesas Electronics Corporation
29
May 15, 2020
F159V Datasheet
16. Typical Performance Characteristics - Cascaded OIP2 (Cont.)
Figure 50. OIP2 versus Frequency (+3.3V)
Figure 51. OIP2 versus Frequency (+3.3V)
85
80
75
70
65
60
55
50
45
40
VVA = 14 dB, DSA = 5 dB
VVA = 22 dB, DSA = 5 dB
80
75
70
65
60
55
50
45
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
+25 C / CH 0
+115 C / CH 0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
RF Frequency (GHz)
RF Frequency (GHz)
Figure 52. OIP2 versus Frequency (+3.3V)
Figure 53. OIP2 versus Frequency (+3.3V)
80
70
VVA = 14 dB, DSA = 17 dB
VVA = 22 dB, DSA = 17 dB
75
70
65
60
55
50
45
40
65
60
55
50
45
40
35
30
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
Figure 54. OIP2 versus Frequency (+3.3V)
Figure 55. OIP2 versus Frequency (+3.3V)
65
65
VVA = 14 dB, DSA = 26 dB
VVA = 22 dB, DSA = 26 dB
60
55
50
45
40
35
30
25
60
55
50
45
40
35
30
25
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
© 2020 Renesas Electronics Corporation
30
May 15, 2020
F159V Datasheet
17. Typical Performance Characteristics - Cascaded OP1dB
Figure 56. Output P1dB vs Frequency (+25°C)
Figure 57. Output P1dB vs Frequency (+3.3V)
16
16
VVA = 0 dB, DSA = 0 dB
VVA = 0 dB, DSA = 0 dB
14
12
10
8
14
12
10
8
6
6
4
4
2
2
0
0
+3.15 V / CH 0
+3.30 V / CH 0
+3.45 V / CH 0
+3.15 V / CH 1
+3.30 V / CH 1
+3.45 V / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-2
-4
-2
-4
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
RF Frequency (GHz)
RF Frequency (GHz)
Figure 58. Output P1dB vs Frequency (+3.3V)
Figure 59. Output P1dB vs Frequency (+3.3V)
16
6
VVA = 5 dB, DSA = 5 dB
VVA = 5 dB, DSA = 17 dB
14
12
10
8
4
2
0
-2
-4
-6
-8
-10
6
4
2
0
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-2
-4
-12
-14
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
Figure 60. Output P1dB vs Frequency (+3.3V)
Figure 61. Output P1dB vs Frequency (+3.3V)
16
-4
VVA = 22 dB, DSA = 1 dB
VVA = 5 dB, DSA = 26 dB
14
12
10
8
-6
-8
-10
-12
-14
-16
-18
-20
6
4
2
0
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-2
-4
-22
-24
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
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F159V Datasheet
18. Typical Performance Characteristics - Cascaded OP1dB (Cont.)
Figure 62. Output P1dB vs Frequency (+3.3V)
Figure 63. Output P1dB vs Frequency (+3.3V)
14
6
VVA = 14 dB, DSA = 5 dB
VVA = 22 dB, DSA = 5 dB
12
10
8
4
2
0
6
-2
-4
-6
-8
-10
4
2
0
-2
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-4
-6
-12
-14
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
RF Frequency (GHz)
RF Frequency (GHz)
Figure 64. Output P1dB vs Frequency (+3.3V)
Figure 65. Output P1dB vs Frequency (+3.3V)
4
-6
VVA = 14 dB, DSA = 17 dB
VVA = 22 dB, DSA = 17 dB
2
0
-8
-10
-12
-14
-16
-18
-20
-22
-2
-4
-6
-8
-10
-12
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-14
-16
-24
-26
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
Figure 66. Output P1dB vs Frequency (+3.3V)
Figure 67. Output P1dB vs Frequency (+3.3V)
-6
-16
VVA = 14 dB, DSA = 26 dB
VVA = 22 dB, DSA = 26 dB
-8
-10
-12
-14
-16
-18
-20
-22
-18
-20
-22
-24
-26
-28
-30
-32
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-24
-26
-34
-36
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
RF Frequency (GHz)
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F159V Datasheet
19. Typical Performance Characteristics - Harmonics, Current, Switching
Figure 68. Second Harmonic vs Frequency
(+3.3V)
Figure 69. Current vs Frequency (+3.3V)
-60
0.9
0.8
0.7
0.6
0.5
0.4
VVA = 0 dB, DSA = 0 dB
VVA = 0 dB, DSA = 0 dB
-65
-70
-75
-80
-85
-90
-95
-100
-20 C / CH 0
-20 C / CH 1
+25 C / CH 0
-20 C / CH 0
-20 C / CH 1
+25 C / CH 0
-20 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
+25 C / CH 0
+115 C / CH 0
-105
-110
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
RF Frequency (GHz)
RF Frequency (GHz)
Figure 70. Third Harmonic vs Frequency
(+3.3V)
Figure 71. Amplifier Enable Pin Switched from
LOW to HIGH
-60
VVA = 0 dB, DSA = 0 dB
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
Figure 72. Fifth Harmonic vs Frequency
(+3.3V)
Figure 73. Amplifier Enable Pin Switched from
HIGH to LOW
-60
VVA = 0 dB, DSA = 0 dB
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
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F159V Datasheet
20. Typical Performance Characteristics - Modulator Coupled Output
Figure 74. Gain versus Frequency (+3.3V)
Figure 75. Output Power versus Frequency
(+3.3V)
-15
-16
-17
-18
-19
-20
-21
-22
-20
-21
-22
-23
-24
-25
-26
-27
-28
-29
-30
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-23
-24
-25
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
RF Frequency (GHz)
RF Frequency (GHz)
Figure 76. OIP3 versus Frequency (+3.3V)
Figure 77. OIP2H versus Frequency (+3.3V)
20
18
16
14
12
10
8
80
75
70
65
60
55
50
6
4
2
0
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
45
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
RF Frequency (GHz)
RF Frequency (GHz)
Figure 78. OP1dB versus Frequency (+3.3V)
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
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F159V Datasheet
21. Typical Performance Characteristics - Modulator Coupled Output
nd
Figure 79. 2 Baseband Harmonic versus
Figure 80. LO Leakage
Frequency (+3.3V, fLO +/- 2fIF)
-60
0
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-10
-20
-30
-40
-50
-60
-70
-80
-90
-70
-80
-90
-100
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-110
-120
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
RF Frequency (GHz)
RF Frequency (GHz)
rd
Figure 81. 3 Baseband Harmonic versus
Frequency (+3.3V, fLO +/- 3fIF)
Figure 82. Switching Time ON to OFF
-60
-70
-80
-90
-100
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-110
-120
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
th
Figure 83. 5 Baseband Harmonic versus
Frequency (+3.3V, fLO +/- 5fIF)
Figure 84. Switching Time OFF to ON
-60
-70
-80
-90
-100
-20 C / CH 0
+25 C / CH 0
+115 C / CH 0
-20 C / CH 1
+25 C / CH 1
+115 C / CH 1
-110
-120
0.0
0.5
1.0
1.5
2.0
2.5
3.0
RF Frequency (GHz)
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F159V Datasheet
22. Typical Performance Characteristics - LO
Figure 85. LO Output Power versus Frequency
(+3.3V)
Figure 86. Lock Detect (fLO = 1.8745GHz)
10
8
6
SPI_CSN
Lock Detect
4
2
0
-2
-4
-6
+25 C / Pin = -2 dBm
+115 C / Pin = -2 dBm
+25 C / Pin = +4 dBm
+115 C / Pin = +4 dBm
-8
-10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
LO Frequency (GHz)
Figure 87. LO Output Phase Noise
(0.9425GHz)
Figure 88. LO Output Phase Noise
(1.8475GHz)
0
0
-20 C
+25 C
+115 C
-20 C
+25 C
+115 C
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Offset Frequency (Hz)
Offset Frequency (Hz)
Figure 89. LO Output Phase Noise
(2.1550GHz)
Figure 90. LO Output Phase Noise
(2.6550GHz)
0
0
-20 C
-20 C
+25 C
+115 C
+25 C
+115 C
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Offset Frequency (Hz)
Offset Frequency (Hz)
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F159V Datasheet
23. Theory of Operation
The F159V transmit chip can be defined as three separate functions:
. Frequency Generator – The F159V uses either an internal voltage controlled oscillator (VCO) that is locked using a fractional-N phase
lock loop (PLL) or an external frequency source. The internal VCO has a frequency range of 2GHz–4GHz. If an external frequency is used
this must be supplied using a 100Ω differential signal. There is only one frequency generator per device but this signal is split into two
different paths.
. Modulator – The baseband signals, which are 100Ω differential I/Q signals, are up-converted with the signal generated from the
frequency generator. There are two modulators per device.
. Variable Gain Amplifier – After a signal is modulated for each of the paths, the signal is amplified and can be attenuated with both a
digital step attenuator (DSA) and voltage variable attenuator (VVA). There are two variable gain amplifiers (VGA) per device.
Controlling the F159V is done using fifty 8-bit registers.
23.1. Frequency Generator
The signal used as the carrier for the modulator can be supplied via an external source or internally generated via a fractional-N phase lock
loop (PLL). The block diagram is shown in Figure 91. Controlling the various switches, dividers, and PLL is done by serially programming
registers to generate the required frequency. The registers are described in the following section.
Figure 91. Phase Lock Loop (PLL) Schematic
Reference
Divider
fREF
REF_in
1+D
R
LD
fPDF
Lock Detect
R
Phase
Frequency
Detector
Charge
Pump
CP_out
D
Divider
Filter
NFrac
NMod
NInt +
fVCO
Divider
/M
VTune
VCO
fLO_Internal
Divider
/D2
Switch
fLO
fLO_External
fLO_Out_Ext
LO in
LO out
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F159V Datasheet
23.1.1.
Internal (VCO) Frequency
The fractional-N architecture is implemented via a cascaded programmable dual modulus prescaler. The N divider offers a division ratio in the
feedback path of the PLL, and is given by programming the values of NInt, NFrac, and NMod. The VCO frequency is determined by the following
equation:
ꢇꢋꢌꢍꢎ
ꢇꢏꢐꢑ
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ
= ꢀꢄꢅꢆ �ꢇꢈꢉꢊ +
ꢒ ꢐꢌ ꢀ
=
ꢄꢅꢆ
ꢇꢋꢌꢍꢎ
ꢇꢏꢐꢑ
ꢇꢈꢉꢊ +
ꢓ
ꢔ
Each of the values is a 16-bit word that requires the programming of two registers.
Table 18. Feedback Divider Values
Name
Register
Description
Register Name
Function
This sets the integer value for feedback divider which is a
16-bit word. The value is limited between 7 and 65,535.
NInt_0 is the lower 8 bits.
17
18
Feedback Divider
Integer Value
NInt_0
NInt_1
NInt
NInt_1 is the upper 8 bits.
The default value is 63 = 0000_0000_0011_1111b.
This sets the fractional value for feedback divider which
is a 16-bit word. There is no limit to the value and can be
between 0 and 65,535.
NFrac_0 is the lower 8 bits.
NFrac_1 is the upper 8 bits.
19
20
Feedback Divider
Fractional Value
NFrac_0
NFrac_1
NFrac
NMod
The default value is 31232 = 0111_1010_0000_0000b.
This sets the modulus value for feedback divider which is
a 16-bit word. The value must be between 2 and 65,535.
NMod_0 is the lower 8 bits.
21
22
Feedback Divider
Modulus Value
NMod_0
NMod_1
NMod_1 is the upper 8 bits.
The default value is 65535 = 1111_1111_1111_1111b.
The Fractional-N PLL can be put into an integer N mode. This is accomplished by setting the fractional value, NFrac, to 0.
23.1.2. Reference Frequency
The Phase Frequency Detector also requires a reference frequency for proper operation. The externally applied reference signal can be either
a sine or square wave. This signal can be translated for various performance enhancements.
1 + D
ꢀ
ꢄꢅꢆ
= ꢀ
�
ꢒ
ꢕꢖꢅ
ꢗ
When setting the frequency for the phase frequency detector, fPFD, it is possible to double (D=1) the reference frequency before dividing the
frequency (R). The phase frequency detector has an upper frequency limit of 250MHz in the Integer-N mode. When used in the Fractional-N
mode, the upper frequency is limited to 105MHz.
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F159V Datasheet
Table 19. Reference Frequency Divider Values
Name
Register
Description
Register Name
Function
This is a 1-bit control word that will double the externally
applied reference frequency. This is the fifth bit on the
word of the 8-bit word.
Reference
Frequency Doubler
D
16
Ref_Doubler
The default value is 1 (doubler is on).
This is a 4-bit control word that sets the divider for the
externally applied reference frequency. The value is
Ref_Doubler between 1 and 15. If the value is 0 then the divider is set
Reference
Frequency Divider
R
16
for 1. This is the first four bits of the word.
The default value is 1 = 0000b.
23.1.3.
Charge Pump
The charge pump current is programmable via the ICP register for maximum flexibility for PLL Bandwidth and performance. We recommend
that default value be used.
Table 20. Charge Pump
Name
Register
Description
Register Name
Function
This is a 4-bit control word that sets the output current of
the charge pump. This is the first four bits of the word.
The default value is 0.94mA = 0010b.
Charge Pump
Current
ICP
24
ChrgPmp
23.1.4.
External Loop Filter
An external loop filter is required which is connected between CP_OUT and VTUNE. The design is application specific. See Application Note
849 for a general description for a loop filter design.
23.1.5.
LO Frequency
The frequency that is used for the modulator is obtained from one of two paths. The first is from the internal VCO and PLL circuit. The output
frequency of the VCO can be divided by up to a factor of 8 using a 3-bit control word.
ꢀ
ꢁꢂꢃ
ꢀ
=
ꢘꢃ_ꢙꢚꢛꢜꢝꢚꢞꢟ
ꢏ
There is a switch that allows this internal signal or an external signal to be used. There is another divider that can be used to further reduce the
frequency by a factor of 2. This divider can be used on either the internal signal or the external frequency supplied.
ꢀ
ꢀ
ꢘꢃ_ꢖꢡꢛꢜꢝꢚꢞꢟ
ꢘꢃ_ꢙꢚꢛꢜꢝꢚꢞꢟ
ꢀ
ꢘꢃ
=
ꢐꢌ
ꢠ2
ꢠ2
It is important to note that for the lower frequency LO signals (ꢀ ) lower than 1.15GHz, the quadrature divider must be enabled to generate
ꢘꢃ
the quadrature LO signal. At higher frequencies, an optimized filter is provided that properly splits the signal for the two paths, therefore the
quadrature divider must be disabled.
© 2020 Renesas Electronics Corporation
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F159V Datasheet
Table 21. LO Frequency Divider Values
Name
Register
Description
Register Name
Function
This is a 3-bit control word that divides the VCO signal.
This is first three bits of the word.
MDiv
23
Output Divide Ratio
MDiv
The default value is 1 = 001b (divide by 2).
This is a 1-bit control word that sets the divide by 2 option
for signal used in the modulator. This can be applied to
either the internal or external signal. This is the fourth bit
of the word.
D2
23
Quadrature Divider
MDiv
The default value is to divide by 1.
23.1.6.
Voltage Control Oscillator (VCO)
The VCO should be set for automatic calibration. If needed, the user can manually change the frequency. There are also different ways to set
how the VCO is locked.
Table 22. VCO setting
Name
Register
Description
Register Name
Function
This is a 1-bit control word that forces the PLL to
recalibrate itself. The default value is to not relock (0b).
When the value is enabled (1b), the PLL is recalibrated
and then the bit is self-clearing (reset to 0b).
Force_Relock
36
VCO Locking
Force_Relock
This is a 1-bit control word that deals with the PLL
recalibration. If any registers from 16 to 22 are written to,
Band_Select_Disable
Auto_Recal_Enable
BandSelDiv
36
36
Band Selection
Recalibration
Force_Relock then the PLL is recalibrated with the default value of 0b.
When the value is enabled (1b), the PLL is not
recalibrated.
This is a 1-bit control word that sets the PLL in the auto-
recalibration mode. The default value of 0b will disable
the auto recalibration. When the value is enabled (1b),
the PLL will allow auto-recalibration mode.
Force_Relock
This is a 12-bit word that will manually set the VCO band
to be used.
38
39
BandSelect_0
Band Select Divider
BandSelect_0 is the lower 8 bits.
BandSelect_1
BandSelect_1 has the upper 4 bits.
The default value is 256 = 0001_0000_0000b.
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F159V Datasheet
Table 23. LO Signal Power
Name
Register
Description
Register Name
Function
This 1-bit word sets the operation of the LO frequency
range.
If set for logic LOW then frequency range is 1.50GHz to
2.00GHz. If set for logic HIGH, the frequency range is
either 0.45GHz to 1.50GHz or 2.00GHz to 2.80GHz.
The default value is the 1.50GHz to 2.00GHz frequency
range = 0b.
Sets the LO
frequency range
LO_BAND
33
Freq_Band
This 1-bit word sets the operation of the RF frequency
range.
If set for logic LOW then frequency range is 0.55GHz to
2.80GHz. If set for logic HIGH, the frequency range is
either 0.45GHz to 0.55GHz.
The default value is the 1.50GHz to 2.00GHz frequency
range = 0b.
Sets the RF
frequency range
RF_BAND
33
34
Freq_Band
Logic
This 1-bit word sets the logic level for the device
operation.
If set for logic LOW, then JEDEC 1.8V logic is used. If set
for logic HIGH, then JEDEC 3.3V logic is used
The default value is JEDEC 1.8V logic = 0b.
Sets the logic
voltage
Dig_Out_Level
This 3-bit word sets the precision setting for the
frequency lock detection.
The default value is 11.5ns = 000b
Sets the lock time for
the frequency
LDP
35
35
Freq_Lock
Freq_Lock
This 2-bit word sets how the voltage on the Lock pin is
set.
The default value is for Normal lock detection = 00b
Set operation of the
LOCK pin
LDPinMode
© 2020 Renesas Electronics Corporation
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F159V Datasheet
23.1.7.
LO Switch Matrix
Through the LO Switch matrix, the F159V will route an LO signal from the internal PLL or from an external source. The device can also route
the internal LO externally for use in other components. The external LO signals are differential signals and the impedance is 100Ω. In addition,
the power can be modified to adjust the performance.
Table 24. LO Signal Power
Name
Register
Description
Register Name
Function
This is a 2-bit control word that sets the output power to
the quadrature divider. The power can be adjusted
from -2dBm to +4dBm in 2dB steps.
LO Power to
Quadrature Divider
LO_Out_Pwr
25
LO_Set_1
The default value is 0dBm = 01b.
This is a 2-bit control word that sets the output power to
the external LO port. The power can be adjusted
from -2dBm to +4dBm in 2dB steps.
LO Power to
External LO Port
LO_SW_Out_Pwr
LO_Out_Pwr_extra
25
25
LO_Set_1
LO_Set_1
The default value is 0dBm = 01b.
This 1-bit word will increase the LO output power by
adding 9.6mA of current to the pre-driver.
The default value is no extra power= 0b.
Add extra power
Table 25. LO Signal Routing
Name
Register
Description
Register Name
Function
This is a 1-bit control word that enables or disables the
LO input amplifier. The default has this amplifier disabled
(turned off).
LO_In_Enable
26
LO Input Amplifier
LO_Set_2
This is a 1-bit control word that enables or disables the
LO output amplifier. The default has this amplifier
disabled (turned off).
LO_Out_Enable
26
LO Output Amplifier
LO_Set_2
This is a 1-bit control word that enables or disables the
switch to route the LO from the PLL to the output LO port.
The default has switch enabled (turned on).
LO_SW_Out_Enable
DAC_Enable
26
26
26
LO Output Switch
DAC Control
LO_Set_2
LO_Set_2
LO_Set_2
This is a 1-bit control word that enables or disables the
DAC. The default has this enabled (turned on).
This is a 1-bit control word that enables or disables the
PLL. The default has the PLL enabled (turned on or
internal LO signal).
PLL_Enable
PLL Control
When this bit is set for logic LOW, the switch selects the
output of the internal VCO. When this bit is set for logic
HIGH, the switch selects the LO_IN (external) input. This
is the control for the switch shown in Figure 92.
LO_SW_Out_Select
26
PLL Control
LO_Set_2
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The LO_IN+/LO_IN- inputs are 100Ω differential inputs. The 100Ω termination is provided internal to the synthesizer die (as shown below). In
addition, an internal bias ensures the proper DC operating level. For this input configuration, it is preferred that the inputs are AC coupled into
LO_IN+/LO_IN-
Figure 92. LO Input Schematic
LO_IN+
50Ω
Internal
Bias
50Ω
LO_IN-
Equivalent Circuit
for LO Input
The LO_OUT+/LO_OUT- output pair is derived from the drain of an NMOS differential pair with on-chip termination resistors to VDD (as shown
below).
Figure 93. LO Output Schematic
VDD
50Ω
50Ω
LO_OUT+
LO_OUT-
Equivalent Circuit
for LO Output
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F159V Datasheet
23.2. Modulator
There are two modulators, one for each channel. The LO generated by the frequency generator is shared by both modulators. Each modulator
has its own differential IF signal input. Figure 94 shows a general schematic to interface a Digital to Analog Converter (DAC) to the modulator
input. There is a coupled output of the RF signal before the variable gain amplifier. There is no control of the modulator.
Figure 94. Generic DAC Interface
IDC= IBIAS+0.5*IFS
0 to 20mA
LCM DAC
F159V
VCM
VCM
IDC
IDC
IOUTxP
RINT
LPF
BBP
BBN
IOUTxN
RINT
RDAC
50Ω
RDAC
50Ω
F159V Baseband Impedance
DC = RINT = 62Ω single ended for each port
AC ~ 110Ω differential
LCM DAC: Low Current Mode Voltage DAC which usually has a high output impedance and will
source an output current.
IBIAS
IFS
LPF:
VCM
:
Internal bias current of the DAC
:
Full Scale current of the DAC
Differential Low Pass Filter for unwanted harmonics.
:
Common Mode Voltage is determined by the DAC bias current and DC impedance of the
IQ Modulator and DAC. It is given as
23.3. Variable Gain Amplifier
There are two variable gain amplifiers, one for each channel, which are used to adjust the output signal amplitude. There is both a digital step
attenuator (DSA) which has 31dB of attenuation in 1dB steps and a voltage variable attenuator (VVA) that has 33dB of attenuation. The VVA
can be set with a 12-bit word. Minimum attenuation is at the maximum digital word of 2047.
Table 26. Digital Step Attenuator Setting
Name
Register
Description
Register Name
Function
This is a 5-bit control word that sets the attenuation setting
for the DSA Channel 0. This is the first 5 bits of the word.
The default value is 0dB = 0 0000b.
Attenuator setting for
DSA in Path 0
DSA0
27
DSA0
This is a 5-bit control word that sets the attenuation setting
for the DSA Channel 1. This is the first 5 bits of the word.
The default value is 0dB = 0 0000b.
Attenuator setting for
DSA in Path 1
DSA1
28
DSA1
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Table 27. Digital Step Attenuator Truth Table
Attenuator
Setting (dB)
DSA[4]
DSA[3]
DSA[2]
DSA[1]
DSA[0]
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
HIGH
0
1
2
4
8
16
31
Table 28. Voltage Variable Attenuator Setting
Name
Register
Description
Register Name
Function
This is a 12-bit control word that sets the attenuation
setting for the VVA in Channel 0.
DAC0_0 is the lower 8 bits.
29
30
Voltage setting for
VVA in Path 0
DAC0_0
DAC0_1
VVA0
DAC0_1 is the upper 4 bits.
The default value is 2047 = 0111_1111_1111b.
This is a 12-bit control word that sets the attenuation
setting for the VVA in Channel 1.
DAC1_0 is the lower 8 bits.
31
32
Voltage setting for
VVA in Path 1
DAC1_0
DAC1_1
DSA1
DAC1_1 has the upper 4 bits.
The default value is 2047 = 0111_1111_1111b.
23.4. General Settings
23.4.1.
Initial Startup
When the F159V is initially powered up, power is applied to all the VDD pins, or the RESET pin is set to logic LOW, the device is placed in the
following state:
.
.
.
.
.
.
.
.
.
Default logic is 1.8V.
The reference frequency doubler is enabled.
The PLL is set for integer mode with a divider of 63.
The LO signal used for the modulator is set for half the frequency of the PLL frequency and 0dBm.
The LO is set for the 1.50GHz to 2.00GHz range.
The internal LO signal is used for the modulator.
The PLL is enabled.
Digital step attenuators are set for the minimum attenuation (0dB).
Voltage variable attenuators are set for the minimum attenuation (state 2047) and the DAC used to control them is turned on.
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23.4.2.
Logic Pins
The following pins are individual pins to the F159V to reset the device, enable the channel modulator output ports, and enable the channel
amplifiers.
Table 29. Amplifier Enable Pin Truth Table
Parameter
Logic Level
Function
LOW
Amplifier in channel path has the DC power turned on.
CH0_AMPEN (pin 68)
CH1_AMPEN (pin 18)
HIGH or No Connect Amplifier in channel path has the DC power turned off.
Table 30. Coupled Modulator Output Enable Pin Truth Table
Parameter
Logic Level
Function
LOW
Coupled modulator output path has the DC power turned on.
CH0_MODEN (pin 59)
CH1_MODEN (pin 27)
HIGH or No Connect Coupled modulator output path has the DC power turned off.
Table 31. RESET Pin Truth Table
Parameter
Logic Level
Function
LOW
Resets all registers to the default states.
RESET (pin 49)
HIGH or No Connect Normal operation.
24. Programming
Figure 95. Serial Timing Diagram
Note: Falling edge of the last clock period is required in order to properly program the SPI.
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Figure 96. Serial Timing Diagram for Multiple Bits
Table 32. SPI Timing Parameters
Minimum for SPI
Timing (ns)
Maximum for SPI
Timing (ns)
Parameter
Description
tds
tdh
SDIO to SCLK rising edge Setup
SCLK rising edge to SDIO Hold
8
10
10
8
50
(default)
tclk
Period of SCLK
thi
tlo
High width of SPI clock
25
Low width of SPI clock
CS falling edge to SCLK rising edge,
setup time
SCLK rising edge to CS rising edge,
hold time
25
10
ts
tc
20
30
10
SCLK falling edge to valid readback
data, SDIO/SDO, tdv
tdv
24.1. Special Programming Note
LD Mode must be programmed to be logic HIGH for proper operation of the lock detection circuit. This is set in Register 37 and the digital word
to be used is 129 = 81h = 1000_0001b.
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24.2. Register Definition
The F159V is programmed via a 3 or 4 wire SPI connection. There are 50 registers that can be programmed for various components of the
device including the PLL, voltage variable attenuators, digital step attenuators, LO output power. Each register is 8-bits long. There are some
parameters that require two registers to fulfill the functionality.
Note: The following numbering nomenclature is used. If the letter “h” is after characters, the number is a hexadecimal. If “b” follows characters,
the number is binary. The binary number is also separated into groups of 4 bits (e.g., 1010_0011b). Otherwise, the number is decimal.
Table 33. Register Definition
Hex
Address
Default
Value
Register
Type
Description
0
1
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
R/W 0000_0000b This register configures the Reset and bit definition.
R/W 0000_0000b This register configures the Single instruction.
R/W 0000_0000b This register configures the data transfer.
2
3
R
R
R
R
0000_0001b Chip type.
4
0000_0000b Chip ID – lower 8 bits (total 16 bits).
0000_0000b Chip ID – higher 8 bits (total 16 bits).
0000_0011b Chip version.
5
6
7
R/W 0000_0000b Unused at this time.
R/W 0000_0000b Unused at this time.
R/W 0000_0000b Unused at this time.
R/W 0000_0000b Unused at this time.
R/W 0000_0000b Unused at this time.
8
9
10
11
12
13
14
15
16
17
18
19
20
R
R
0010_0110b Vendor ID – lower 8 bits (total of 16 bits).
0000_0100b Vendor ID – higher 8 bits (total of 16 bits).
R/W 0000_0000b Unused at this time.
R/W 0000_0000b Unused at this time.
R/W 0001_0000b 5-bit word to control the Reference Divider and Reference Doubler.
R/W 0011_1111b FB divider integer part, lower 8 bits (total of 16 bits). Minimum divide ratio is 7.
R/W 0000_0000b FB divider integer part, higher 8 bits (total of 16-bits).
R/W 0000_0000b FB divider fractional numerator, lower 8 bits (total of 16 bits). Default = 31,232.
R/W 0111_1010b FB divider fractional numerator, higher 8 bits (total of 16-bits).
FB divider fractional denominator, lower 8 bits (total of 16 bits). Minimum modulus value is 2.
21
15h
R/W 1111_1111b
Default = 65,535.
22
23
24
16h
17h
18h
R/W 1111_1111b FB divider fractional denominator, higher 8 bits (total of 16 bits).
R/W 0000_0001b 1-bit for the Quadrature Divider, 3-bit for the output divider.
R/W 0000_0010b Charge pump current setting, 4 bits.
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Table 34. Register Definition–(Cont.)
Hex
Address
Default
Value
Register
Type
Description
Setting for LO output: 2 bits for Output Power, 2 bits for Switched Output Power, 1 bit for
additional pre-driver current (output power).
25
19h
R/W 0000_0101b
26
27
28
29
30
31
32
33
34
35
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
R/W 0001_1100b Set the various LO switch parameters, and if the PLL and DAC are enabled.
R/W 0000_0000b 5-bit word to control the DSA in Channel 0 (1dB LSB).
R/W 0000_0000b 5-bit word to control the DSA in Channel 1 (1dB LSB).
R/W 1111_1111b Lower 8 bits of 11-bit word to control the VVA in Channel 0.
R/W 0000_0111b Higher 3 bits of 11-bit word to control the VVA in Channel 0.
R/W 1111_1111b Lower 8-bits of 11-bit word to control the VVA in Channel 1.
R/W 0000_0111b Higher 3-bits of 11-bit word to control the VVA in Channel 1.
R/W 0000_0000b 1 bit for the RF Band, 1 bit for the LO Band.
R/W 0000_0000b 1 bit for Digital Output Logic.
R/W 0000_0000b 3 bits for Lock Detect Precision, 2 bits for Lock Detect.
1 bit for a force recalibration. 1 bit for Disabling the VCO recalibration,
1 bit for Automatic recalibration.
36
24h
R/W 0000_0000b
37
38
39
40
41
42
43
44
45
46
47
48
49
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
R/W 0000_0001b 1 bit for Lock Detection.
R/W 0000_0000b Lower 8 bits of a 12-bit word for the Band Select Divider.
R/W 0000_0001b Higher 4 bits of a 12-bit word for the Band Select Divider.
R/W 0000_0000b Reserved for Vendor Use. Use only the default value.
R/W 0000_0000b Reserved for Vendor Use. Use only the default value.
R/W 0000_0010b Reserved for Vendor Use. Use only the default value.
R/W 1100_1011b Reserved for Vendor Use. Use only the default value.
R/W 0000_0000b Reserved for Vendor Use. Use only the default value.
R/W 0000_0000b Reserved for Vendor Use. Use only the default value.
R
R
N/A
N/A
N/A
N/A
Reserved for Vendor Use. Use only the default value.
Reserved for Vendor Use. Use only the default value.
Reserved for Vendor Use. Use only the default value.
Reserved for Vendor Use. Use only the default value.
R
R/W
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24.2.1.
Register 0 (00h)
This register sets how the entire serial communication functions. Since the device can use either the most significant bit (MSB) or least significant
bit (LSB) order, only four parameters are set. By mirroring the bits, the parameters can be used properly in either mode. The default value is 0
= 00h = 0000_0000b.
Table 35. Register 0: Bit Definition
Bit
Bit Field Name
Default
Definition
Set to logic LOW is for normal operation.
Set to logic HIGH to reset all registers above register 2 (02h), with write capability, to a default
state. Registers 0 and 1 are not reset.
0
SoftReset
0
Defines the bit transmitted first in SPIN transfers between the master and slave.
If this bit is set to logic LOW, data is oriented as MSB first.
If this bit is set to logic HIGH, data is oriented as LSB first.
1
2
LSBFirst
0
0
Defines how the addresses are incremented in streaming SPI mode.
If this bit is set to logic LOW, addresses are auto-decremented.
If this bit is set to logic HIGH, addresses are auto-incremented.
AddressAscend
Selects the unidirectional or bidirectional data transfer mode for the SDIO pin.
If this bit is cleared or set to logic LOW, then SPI 3-wire mode is used and:
- SDIO is the SPI bidirectional data I/O pin
3
SDO Active
0
- SDO pin is not used and is in high-impedance
If this-bit is cleared or set to logic HIGH, then SPI 4-wire mode is used and:
- SDIO is the SPI data input pin
- SDO is the SPI data output pin
4
5
6
7
SDO Active
AddressAscend
LSBFirst
0
0
0
0
Must be equal to bit 3 (Mirror image to be independent of MSB or LSB).
Must be equal to bit 2 (Mirror image to be independent of MSB or LSB).
Must be equal to bit 1 (Mirror image to be independent of MSB or LSB).
Must be equal to bit 0 (Mirror image to be independent of MSB or LSB).
SoftReset
24.2.2.
Register 1 (01h)
This register is used to determine how data is read back from the device. The default value is 0 = 00h = 0000_0000b.
Table 36. Register 1: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
0
0
0
0
0
Unused.
Unused.
Unused.
Unused.
Unused.
Double Buffer. Vendor can choose to design in a secondary buffer for reading.
If set for logic HIGH, then when reading from the device the information is obtained for the
second buffer. If set for logic LOW, then when reading from the device the information is
obtained for the active register.
5
BufferReadMode
0
6
7
0
0
Unused.
Unused.
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24.2.3.
Register 2 (01h)
This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b.
24.2.4. Register 3 (03h)
This register is used to define what type of Chip this is and is READ ONLY. It is 8 bits long. The default value is 1 = 01h = 0000_0001b.
Table 37. Register 3: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
ChipType[0]
ChipType[1]
ChipType[2]
ChipType[3]
ChipType[4]
ChipType[5]
ChipType[6]
ChipType[7]
1
0
0
0
0
0
0
0
Bit 0 of the value.
Bit 1 of the value.
Bit 2 of the value.
Bit 3 of the value.
Bit 4 of the value.
Bit 5 of the value.
Bit 6 of the value.
Bit 7 of the value.
24.2.5.
Register 4 (04h)
Register 5 and 4 define the value for the ChipID. The ChipID is a 16-bit word with a default value of 0 = 0000h = 0000_0000_0000_0000b.
Register 4 is the lower 8 bits of the word and the default value is 0 = 00h = 0000_0000b. This register is READ ONLY.
Table 38. Register 4: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
ChipID[0]
ChipID[1]
ChipID[2]
ChipID[3]
ChipID[4]
ChipID[5]
ChipID[6]
ChipID[7]
0
0
0
0
0
0
0
0
Bit 0 of the value.
Bit 1 of the value.
Bit 2 of the value.
Bit 3 of the value.
Bit 4 of the value.
Bit 5 of the value.
Bit 6 of the value.
Bit 7 of the value.
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24.2.6.
Register 5 (05h)
Register 5 and 4 define the value for the ChipID. The ChipID is a 16-bit word with a default value of 0 = 0000h = 0000_0000_0000_0000b.
Register 5 is the higher 8 bits of the word and the default value is 0 = 00h = 0000_0000b. This register is READ ONLY.
Table 39. Register 5: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
ChipID[8]
ChipID[9]
0
0
0
0
0
0
0
0
Bit 8 of the value.
Bit 9 of the value.
Bit 10 of the value.
Bit 11 of the value.
Bit 12 of the value.
Bit 13 of the value.
Bit 14 of the value.
Bit 15 of the value.
ChipID[10]
ChipID[11]
ChipID[12]
ChipID[13]
ChipID[14]
ChipID[15]
24.2.7.
Register 6 (06h)
This register is READ ONLY and contains the Chip Version value. The Chip Version is an 8-bit word. The default value is 3 = 03h= 0000_0011b.
Table 40. Register 6: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
ChipVersion[0]
ChipVersion[1]
ChipVersion[2]
ChipVersion[3]
ChipVersion[4]
ChipVersion[5]
ChipVersion[6]
ChipVersion[7]
1
1
0
0
0
0
0
0
Bit 0 of the value.
Bit 1 of the value.
Bit 2 of the value.
Bit 3 of the value.
Bit 4 of the value.
Bit 5 of the value.
Bit 6 of the value.
Bit 7 of the value.
24.2.8.
Register 7 (07h)
This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b.
24.2.9. Register 8 (08h)
This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b.
24.2.10. Register 9 (09h)
This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b.
24.2.11. Register 10 (0Ah)
This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b.
24.2.12. Register 11 (0Bh)
This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b.
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24.2.13. Register 12 (0Ch)
Register 13 and 12 define the value of the Vendor ID. The Vendor ID is a 16-bit word. IDT’s vendor code is 1062 = 0426h. Register 12 is the
lower 8 bits of the word and the default value is 38 = 26h= 0010_0110b. This register is READ ONLY.
Table 41. Register 12: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
VendorID[0]
VendorID[1]
VendorID[2]
VendorID[3]
VendorID[4]
VendorID[5]
VendorID[6]
VendorID[7]
0
1
1
0
0
1
0
0
Bit 0 of the value.
Bit 1 of the value.
Bit 2 of the value.
Bit 3 of the value.
Bit 4 of the value.
Bit 5 of the value.
Bit 6 of the value.
Bit 7 of the value.
24.2.14. Register 13 (0Dh)
Register 13 and 12 define the value of the Vendor ID. The Vendor ID is a 16-bit word. IDT’s vendor code is 1062 = 0426h. Register 13 is the
higher 8 bits of the word and the default value is 4 = 04h= 0000_0100b. This register is READ ONLY.
Table 42. Register 13: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
VendorID[8]
VendorID[9]
VendorID[10]
VendorID[11]
VendorID[12]
VendorID[13]
VendorID[14]
VendorID[15]
0
0
1
0
0
0
0
0
Bit 8 of the value.
Bit 9 of the value.
Bit 10 of the value.
Bit 11 of the value.
Bit 12 of the value.
Bit 13 of the value.
Bit 14 of the value.
Bit 15 of the value.
24.2.15. Register 14 (0Eh)
This register is unused and reserved for future use. The default value is 0 = 00h = 0000_0000b.
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24.2.16. Register 15 (0Fh)
This register determines how the data in transferred from the buffers in the active register when a multi-byte word is sent. The default value is
0 = 00h= 0000_0000b.
Table 43. Register 15: Bit Definition
Bit
Bit Field Name
Default
Definition
This device implements double-buffered registers for various parameters that are larger than one
byte (8 bits).
If this is set to logic LOW, then there is no transfer.
If this is set to logic HIGH, then the data (multiple bytes) into the device is synchronized so as to
not affect the operation of the device.
0
TransferOn
0
This bit is always reset to logic LOW 0 after the operation, and this is called Auto-Clear.
1
2
3
4
5
6
7
0
0
0
0
0
0
0
Unused.
Unused.
Unused.
Unused.
Unused.
Unused.
Unused.
24.2.17. Register 16 (10h)
This register controls the Reference Frequency Divider within the PLL. The reference frequency can be first be doubled, then divided. The
default value is 16 = 10h = 0001_0000b.
Table 44. Register 16: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
R[0]
R[1]
R[2]
R[3]
0
0
0
0
Bit 0 of a 4-bit word to determine the divider ratio (R) of the reference frequency (Table 45).
Bit 1 of a 4-bit word to determine the divider ratio (R) of the reference frequency (Table 45).
Bit 2 of a 4-bit word to determine the divider ratio (R) of the reference frequency (Table 45).
Bit 3 of a 4-bit word to determine the divider ratio (R) of the reference frequency (Table 45).
If this is set to logic LOW, then the reference frequency doubler (D) is disabled (multiplier is set
for 1).
4
RefDoub
1
If this is set to logic HIGH, then the reference frequency doubler (D) is enable (multiplier is set for
2). This is the default value.
5
6
7
0
0
0
Unused.
Unused.
Unused.
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Table 45. 4-bit Pre Divider Value (R) Description
Decimal Bit 3 Bit 2 Bit 1 Bit 0
Definition
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Divide by 1 (default)
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 6
Divide by 7
Divide by 8
Divide by 9
Divide by 10
Divide by 11
Divide by 12
Divide by 13
Divide by 14
Divide by 15
2
3
4
5
6
7
8
9
10
11
12
13
14
15
24.2.18. Register 17 (11h)
Registers 18 and 17 control the Feedback Frequency Divider within the PLL. This is a 16-bit word that gives the integer value of the divider.
The integer can vary from 7 to 65,535. The default value is 63 = 003Fh = 0000_0000_0011_1111b. Register 17 is the lower 8 bits of the word
and has a default value 63 = 3Fh = 0011_1111b.
Table 46. Register 17: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
NInt[0]
NInt[1]
NInt[2]
NInt[3]
NInt[4]
NInt[5]
NInt[6]
NInt[7]
1
1
1
1
1
1
0
0
Bit 0 of a 16-bit word to determine Integer value for the feedback divider.
Bit 1 of a 16-bit word to determine Integer value for the feedback divider.
Bit 2 of a 16-bit word to determine Integer value for the feedback divider.
Bit 3 of a 16-bit word to determine Integer value for the feedback divider.
Bit 4 of a 16-bit word to determine Integer value for the feedback divider.
Bit 5 of a 16-bit word to determine Integer value for the feedback divider.
Bit 6 of a 16-bit word to determine Integer value for the feedback divider.
Bit 7 of a 16-bit word to determine Integer value for the feedback divider.
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24.2.19. Register 18 (12h)
Registers 18 and 17 control the Feedback Frequency Divider within the PLL. This is a 16-bit word that gives the integer value of the divider.
The integer can vary from 7 to 65,535. The default value is 63 = 003Fh = 0000_0000_0011_1111b. Register 18 is the higher 8 bits of the word
and has a default value of 0 = 00h = 0000_0000b.
Table 47. Register 18: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
NInt[8]
NInt[9]
0
0
0
0
0
0
0
0
Bit 8 of a 16-bit word to determine integer value for the feedback divider.
Bit 9 of a 16-bit word to determine integer value for the feedback divider.
Bit 10 of a 16-bit word to determine integer value for the feedback divider.
Bit 11 of a 16-bit word to determine integer value for the feedback divider.
Bit 12 of a 16-bit word to determine integer value for the feedback divider.
Bit 13 of a 16-bit word to determine integer value for the feedback divider.
Bit 14 of a 16-bit word to determine integer value for the feedback divider.
Bit 15 of a 16-bit word to determine integer value for the feedback divider.
NInt[10]
NInt[11]
NInt[12]
NInt[13]
NInt[14]
NInt[15]
24.2.20. Register 19 (13h)
Registers 20 and 19 control the NFrac term, which is the numerator in the fractional part of the equation for the PLL’s Feedback Frequency
Divider: NInt + (NFrac / NMod). NFrac is a 16-bit word that can vary from 0 to 65,535. There is a restriction that NFrac must be less than the
denominator value NMod (see registers 21 and 22). The default value for NFrac is 31232 = 7A00h = 0111_1010_0000_0000b. Register 19 is
the lower 8 bits of NFrac, and its default value is 0 = 00h = 0000_0000b.
Table 48. Register 19: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
NFrac[0]
NFrac[1]
NFrac[2]
NFrac[3]
NFrac[4]
NFrac[5]
NFrac[6]
NFrac[7]
0
0
0
0
0
0
0
0
Bit 0 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 1 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 2 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 3 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 4 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 5 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 6 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 7 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
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24.2.21. Register 20 (14h)
Registers 20 and 19 control the NFrac term, which is the numerator in the fractional part of the equation for the PLL’s Feedback Frequency
Divider: NInt + (NFrac / NMod). NFrac is a 16-bit word that can vary from 0 to 65,535. There is a restriction that NFrac must be less than the
denominator value NMod (see registers 21 and 22). The default value for NFrac is 31232 = 7A00h = 0111_1010_0000_0000b. Register 20 is
the upper 8 bits of NFrac, and its default value is 122 = 7Ah = 0111_1010b.
Table 49. Register 20: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
NFrac[8]
NFrac[9]
0
1
0
1
1
1
1
0
Bit 8 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 9 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 10 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 11 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 12 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 13 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 14 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
Bit 15 in the 16-bit NFrac numerator in the fraction term in the feedback divider equation.
NFrac[10]
NFrac[11]
NFrac[12]
NFrac[13]
NFrac[14]
NFrac[15]
24.2.22. Register 21 (15h)
Registers 22 and 21 control the NMod term, which is the denominator in the fractional part of the equation for the PLL’s Feedback Frequency
Divider: NInt + (NFrac / NMod). NMod is a 16-bit word that can vary from 2 to 65,535. There is a restriction that NMod must be greater than the
numerator NFrac value (see registers 19 and 20). The default value for NMod is 65535 = FFFFh = 1111_1111_1111_1111b. Register 21 is the
lower 8 bits of NMod, and its default value is 255 = FFh = 1111_1111b.
Table 50. Register 21: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
NMod[0]
NMod[1]
NMod[2]
NMod[3]
NMod[4]
NMod[5]
NMod[6]
NMod[7]
1
1
1
1
1
1
1
1
Bit 0 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 1 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 2 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 3 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 4 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 5 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 6 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 7 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
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24.2.23. Register 22 (16h)
Registers 22 and 21 control the NMod term, which is the denominator in the fractional part of the equation for the PLL’s Feedback Frequency
Divider: NInt + (NFrac / NMod). NMod is a 16-bit word that can vary from 2 to 65,535. There is a restriction that NMod must be greater than the
numerator NFrac value (see registers 19 and 20). The default value for NMod is 65535 = FFFFh = 1111_1111_1111_1111b. Register 22 is the
upper 8 bits of NMod, and its default value is 255 = FFh = 1111_1111b.
Table 51. Register 22: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
NMod[8]
NMod[9]
1
1
1
1
1
1
1
1
Bit 8 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 9 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 10 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 11 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 12 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 13 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 14 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
Bit 15 in the 16-bit NMod denominator in the fraction term in the feedback divider equation.
NMod[10]
NMod[11]
NMod[12]
NMod[13]
NMod[14]
NMod[15]
24.2.24. Register 23 (17h)
Register 23 creates the proper frequency that is used by the modulator. There are two separate dividers. The Quad Divider is a divide by 2 and
will work with both the internal frequency generator and an external frequency generator. The other divider, MDiv, only works on the internal
frequency generator and is 3-bit word that allows values of 1 to 8. The Quad Divider default is 0 and the other divider, MDiv, is 1. Bits 4 to 7 are
not used. The default value is 1 = 01h = 0000_0001b.
Table 52. Register 23: Bit Definition
Bit
Bit Field Name
Default
Definition
Bit 0 of 3-bit word for divider (see Table 53).
0
1
2
MDiv[0]
MDiv[1]
MDiv[2]
1
0
0
Bit 1 of 3-bit word for divider (see Table 53).
Bit 2 of 3-bit word for divider (see Table 53).
Quadrature Divider.
Set for logic LOW for divide by 1. This is the default value.
Set for logic HIGH for divide by 2.
3
Quad_Divider
0
4
5
6
7
0
0
0
0
Unused.
Unused.
Unused.
Unused.
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Table 53. 3-Bit Divider Value (MDiv) Description
Decimal Bit 2 Bit 1 Bit 0
Definition
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Divide by 1
Divide by 2 (default)
Divide by 4
Divide by 8
Unused
Unused
Unused
Unused
24.2.25. Register 24 (18h)
This register changes the characteristics of the charge pump. This is a 4-bit word that will adjust the current of the charge pump. The default
current is 0.94mA. Bits 4 to 7 are not used. The default value is 2 = 02h = 0000_0010b.
Table 54. Register 24: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
ChrgPmp[0]
ChrgPmp[1]
ChrgPmp[2]
ChrgPmp[3]
0
1
0
0
0
0
0
0
Bit 0 of 4-bit word for charge pump current (see Table 55).
Bit 1 of 4-bit word for charge pump current (see Table 55).
Bit 2 of 4-bit word for charge pump current (see Table 55).
Bit 3 of 4-bit word for charge pump current (see Table 55).
Unused.
Unused.
Unused.
Unused.
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Table 55. 4-Bit Charge Pump Current
Decimal Bit 3 Bit 2 Bit 1 Bit 0
Definition
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Set current for 0.31mA
Set current for 0.63mA
2
Set current for 0.94mA (default)
Set current for 1.25mA
Set current for 1.56mA
Set current for 1.88mA
Set current for 2.19mA
Set current for 2.50mA
Set current for 2.81mA
Set current for 3.13mA
Set current for 3.44mA
Set current for 3.75mA
Set current for 4.06mA
Set current for 4.38mA
Set current for 4.69mA
Set current for 5.00mA
3
4
5
6
7
8
9
10
11
12
13
14
15
24.2.26. Register 25 (19h)
This register controls the LO power levels for the modulator and external LO port. Each power level defaults to 0dBm. If needed, the modulator
LO power can be increased by setting a 1 bit word. Bits 5 to 7 are unused. The register default is 5 = 05h = 0000_0101b.
Table 56. Register 25: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
LO_Out_Pwr[0]
LO_Out_Pwr[1]
1
0
1
0
Bit 0 of a 2-bit word to set the LO power to the modulator (see Table 57).
Bit 1 of a 2-bit word to set the LO power to the modulator (see Table 57).
Bit 0 of a 2-bit word to set LO power to the external port (see Table 58).
Bit 1 of a 2-bit word to set LO power to the external port (see Table 58).
LO_SW_Out_Pwr[0]
LO_SW_Out_Pwr[1]
If this bit is set for logic HIGH, then the LO predriver increases the output power to the
modulator. The addition power is different for each of the LO_Out_Pwr settings.
If this bit is set for logic LOW (default), then the LO predriver will not increase the output power.
4
LO_Out_Pwr_extra
0
5
6
7
0
0
0
Unused.
Unused.
Unused.
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Table 57. 2-Bit Power Setting for the Modulator Signal
Decimal Bit 1 Bit 0
Definition
0
1
2
3
0
0
1
1
0
1
0
1
Set for -2dBm
Set for 0dBm (default)
Set for +2dBm
Set for +4dBm
Table 58. 2-Bit LO Power for the External LO Port (LO_OUT)
Decimal Bit 1 Bit 0 Definition
0
1
2
3
0
0
1
1
0
1
0
1
Set for -2dBm
Set for 0dBm (default)
Set for +2dBm
Set for +4dBm
24.2.27. Register 26 (1Ah)
This register controls the LO Switch matrix. There are five single-bit words for various configurations. Bits 6 and 7 are unused. The default value
is 28 = 1Ch = 0001_1100b.
Table 59. Register 26: Bit Definition
Bit
Bit Field Name
Default
Definition
This bit turns on the signal buffer that allows an external LO signal to be used as the signal for
the modulator. If this bit is set for logic LOW (default), then the buffer is turned off. If this bit is set
for logic HIGH, then the buffer is turned on. This bit works with bit LO_SW_Out_Select to use an
external signal for the LO.
0
LO_IN_Enable
0
This bit turns on the signal buffer that allows the LO signal to be sent to other devices. If this bit
is set for logic LOW (default), then the buffer is turned off. If this bit is set for logic HIGH, then the
buffer is turned on.
1
LO_Out_Enable
0
This bit turns on the switch buffer that controls which signal to use for modulator. If this bit is set
for logic LOW then the buffer is turned off. If this bit is set for logic HIGH (default), then the buffer
is turned on.
2
3
4
LO_SW_Out_Enable
DAC_Enable
1
1
1
This bit allows the DAC to control the VVAs. If this bit is set for logic LOW, then the DAC is
disabled. If this bit is set for logic HIGH (default), then the DAC is enabled.
This bit controls power to the PLL. If this bit is set for logic LOW, then the power to the PLL is
disabled for minimum current. If this bit is set for logic HIGH (default), then the power to the PLL
is enabled.
PLL_Enable
This bit selects which signal is used for the modulator. If this bit is set for logic LOW (default),
then the internal signal from the PLL is used. If this bit is set for logic HIGH, then the external
signal from LO_IN is used.
5
LO_SW_Out_Select
0
6
7
0
0
Unused.
Unused.
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24.2.28. Register 27 (1Bh)
This register controls the Digital Step Attenuator in Channel 0. This is a 5-bit word. Bits 5 to 7 are unused. The default is 0dB, 0 = 00h =
0000_0000b.
Table 60. Register 27: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
DSA0[0]
DSA0[1]
DSA0[2]
DSA0[3]
DSA0[4]
0
0
0
0
0
0
0
0
Bit 0 of a 5-bit word to set the DSA for Channel 0 (see Table 61).
Bit 1 of a 5-bit word to set the DSA for Channel 0 (see Table 61).
Bit 2 of a 5-bit word to set the DSA for Channel 0 (see Table 61).
Bit 3 of a 5-bit word to set the DSA for Channel 0 (see Table 61).
Bit 4 of a 5-bit word to set the DSA for Channel 0 (see Table 61).
Unused.
Unused.
Unused.
Table 61. 5-Bit Digital Attenuator Setting used for both DSA0 and DSA1
Definition
Decimal Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
1
0dB (default)
1dB
2
2dB
4
4dB
8
8dB
16
31
16dB
31dB
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24.2.29. Register 28 (1Ch)
This register controls the Digital Step Attenuator in Channel 1. This is a 5-bit word. Bits 5 to 7 are unused. The default is 0dB, 0 = 0h =
0000_0000b.
Table 62. Register 28: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
DSA1[0]
DSA1[1]
DSA1[2]
DSA1[3]
DSA1[4]
0
0
0
0
0
0
0
0
Bit 0 of a 5-bit word to set the DSA for Channel 1 (see Table 61).
Bit 1 of a 5-bit word to set the DSA for Channel 1 (see Table 61).
Bit 2 of a 5-bit word to set the DSA for Channel 1 (see Table 61).
Bit 3 of a 5-bit word to set the DSA for Channel 1 (see Table 61).
Bit 4 of a 5-bit word to set the DSA for Channel 1 (see Table 61).
Unused.
Unused.
Unused.
24.2.30. Register 29 (1Dh)
Registers 30 and 29 control the Voltage Variable Attenuator in Channel 0, and is an 11-bit word. The minimum attenuation (0dB) is at the
maximum DAC setting (2047). The default is 2047 = 7FFh = 111_1111_1111b. Register 29 is the lower 8 bits of the word and the default is 255
= FFh = 1111_1111b.
Table 63. Register 29: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
DAC0[0]
DAC0[1]
DAC0[2]
DAC0[3]
DAC0[4]
DAC0[5]
DAC0[6]
DAC0[7]
1
1
1
1
1
1
1
1
Bit 0 of an 11-bit word to set the VVA for Channel 0.
Bit 1 of an 11-bit word to set the VVA for Channel 0.
Bit 2 of an 11-bit word to set the VVA for Channel 0.
Bit 3 of an 11-bit word to set the VVA for Channel 0.
Bit 4 of an 11-bit word to set the VVA for Channel 0.
Bit 5 of an 11-bit word to set the VVA for Channel 0.
Bit 6 of an 11-bit word to set the VVA for Channel 0.
Bit 7 of an 11-bit word to set the VVA for Channel 0.
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24.2.31. Register 30 (1Eh)
Registers 30 and 29 control the Voltage Variable Attenuator in Channel 0, and is an 11-bit word. The minimum attenuation (0dB) is at the
maximum DAC setting (2047). The default is 2047 = 7FFh = 111_1111_1111b. Bits 3 to 7 of this register are unused. Register 30 is the higher
3 bits of the word and the default is 7 = 7h = 0000_0111b.
Table 64. Register 30: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
DAC0[8]
DAC0[9]
DAC0[10]
Unused
Unused
Unused
Unused
Unused
1
1
1
0
0
0
0
0
Bit 8 of an 11-bit word to set the VVA for Channel 0.
Bit 9 of an 11-bit word to set the VVA for Channel 0.
Bit 10 of an 11-bit word to set the VVA for Channel 0.
Unused.
Unused.
Unused.
Unused.
Unused.
24.2.32. Register 31 (1Fh)
Registers 32 and 31 control the Voltage Variable Attenuator in Channel 1, and is an 11-bit word. The minimum attenuation (0dB) is at the
maximum DAC setting (2047). The default is 2047 = 7FFh = 111_1111_1111b. . Register 31 is the lower 8 bits of the word and the default is
255 = FFh = 1111_1111b.
Table 65. Register 31: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
DAC1[0]
DAC1[1]
DAC1[2]
DAC1[3]
DAC1[4]
DAC1[5]
DAC1[6]
DAC1[7]
1
1
1
1
1
1
1
1
Bit 0 of an 11-bit word to set the VVA for Channel 1.
Bit 1 of an 11-bit word to set the VVA for Channel 1.
Bit 2 of an 11-bit word to set the VVA for Channel 1.
Bit 3 of an 11-bit word to set the VVA for Channel 1.
Bit 4 of an 11-bit word to set the VVA for Channel 1.
Bit 5 of an 11-bit word to set the VVA for Channel 1.
Bit 6 of an 11-bit word to set the VVA for Channel 1.
Bit 7 of an 11-bit word to set the VVA for Channel 1.
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24.2.33. Register 32 (20h)
Registers 32 and 31 control the Voltage Variable Attenuator in Channel 1, and is an 11-bit word. The minimum attenuation (0dB) is at the
maximum DAC setting (2047). The default is 2047 = 7FFh = 111_1111_1111b. Bits 3 to 7 of this register are unused. Register 30 is the higher
3 bits of the word and the default is 7 = 7h = 0000_0111b.
Table 66. Register 32: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
DAC1[8]
DAC1[9]
DAC1[10]
Unused
Unused
Unused
Unused
Unused
1
1
1
0
0
0
0
0
Bit 8 of an 11-bit word to set the VVA for Channel 1.
Bit 9 of an 11-bit word to set the VVA for Channel 1.
Bit 10 of an 11-bit word to set the VVA for Channel 1.
Unused.
Unused.
Unused.
Unused.
Unused.
24.2.34. Register 33 (21h)
This register selects the RF and LO bands used for the device. Bits 2 to 7 are unused. The default is 0 = 0h = 0000_0000b.
Table 67. Register 33: Bit Definition
Bit
Bit Field Name
Default
Definition
Set the LO band of operation.
Set to logic LOW to select the 1.50GHz to 2.00GHz range for the LO band. This is the default.
Set to logic HIGH to select the either the 0.45GHz to 1.50GHz range or the 2.00GHz to 2.80GHz
range for the LO band.
0
LO_BAND
0
Set the RF band of operation.
Set to logic LOW to select the 0.55GHz to 2.80GHz range for the RF band. This is the default.
Set to logic HIGH to select the 0.45GHz to 0.55GHz range for the RF band.
1
RF_BAND
0
2
3
4
5
6
7
Unused
Unused
Unused
Unused
Unused
Unused
0
0
0
0
0
0
Unused.
Unused.
Unused.
Unused.
Unused.
Unused.
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24.2.35. Register 34 (22h)
This register selects the logic levels used for the digital output. Default is JEDEC 1.8 V logic and the default value is 0 = 00h = 0000_0000b.
Bits 1 to 7 are unused.
Table 68. Register 34: Bit Definition
Bit
Bit Field Name
Default
Definition
Set for logic LOW for JEDEC 1.8 Volt logic (default).
Set for logic HIGH for JEDEC 3.3 V logic.
0
Dig_Out_Level
0
1
2
3
4
5
6
7
Unused
Unused
Unused
Unused
Unused
Unused
Unused
0
0
0
0
0
0
0
Unused.
Unused.
Unused.
Unused.
Unused.
Unused.
Unused.
24.2.36. Register 35 (23h)
This register selects the precision of the Lock Detection and how the LO Lock Detection pin (56) is used. Bit 3, 6, and 7 are unused. The default
is 0 = 0h = 0000_0000b.
Table 69. Register 35: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
7
LDP[0]
LDP[1]
0
0
0
0
0
0
0
0
Bit 0 of a 3-bit word to set when the VCO precision lock detection is set (see Table 70).
Bit 1 of a 3-bit word to set when the VCO precision lock detection is set (see Table 70).
LDP[2]
Bit 2 of a 3-bit word to set when the VCO precision lock detection is set (see Table 70).
Unused
Unused.
LDPinMode[0]
LDPinMode[1]
Unused
Bit 0 of a 2-bit word to set the LD pin operation (see Table 71).
Bit 1 of a 2-bit word to set the LD pin operation (see Table 71).
Unused.
Unused.
Unused
Table 70. 3-bit VCO Lock Precision Detection Description
Decimal Bit 2 Bit 1 Bit 0
Definition
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Set for lock detection to within 11.5ns (default).
Set for lock detection to within 6.5ns.
Set for lock detection to within 6.5ns.
Set for lock detection to within 3.0ns.
Set for lock detection to within 5.0ns.
Set for lock detection to within 5.0ns.
Set for lock detection to within 1.5ns.
Set for lock detection to within 1.5ns.
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F159V Datasheet
Table 71. 2-bit Lock Detection Pin Description
Decimal Bit 1 Bit 0
Definition
0
1
2
3
0
0
1
1
0
1
0
1
Digital Lock (normal operation) (default).
VCO calibration is done.
Set for logic LOW.
Set for logic HIGH.
24.2.37. Register 36 (24h)
This register controls how the PLL locks the VCO frequency. The default value is 0 = 00h = 0000_0000b. Bits 3 to 7 are unused.
Table 72. Register 36: Bit Definition
Bit
Bit Field Name
Default
Definition
0 = No VCO relocking (default).
1 = Force the VCO to recalibrate. This-bit is self-clearing.
0
Force_Relock
0
0 = If registers16-22 are written, then the VCO will recalibrate (default).
1 = No VCO recalibration is done.
1
2
Band_Sel_Disable
Auto_Recal_Enable
0
0
0 = Disable Auto Recalibration (default).
1 = Enable Auto Recalibration.
3
4
5
6
7
Unused
Unused
Unused
Unused
Unused
0
0
0
0
0
Unused.
Unused.
Unused.
Unused.
Unused.
24.2.38. Register 37 (25h)
This register controls the lock detection of the PLL. The default value is 1 = 01h = 0000_0001b.
Note: LD Mode must be programmed to be logic HIGH for proper operation of the lock detection circuit. IDT requires the following
digital word to be used 129 = 81h = 1000_0001b.
Table 73. Register 37: Bit Definition
Bit
Bit Field Name
Default
Definition
0
1
2
3
4
5
6
Vendor Supplied
Vendor Supplied
Vendor Supplied
Vendor Supplied
Vendor Supplied
Vendor Supplied
Vendor Supplied
1
0
0
0
0
0
0
Reserved for vendor use. Use only the default value.
Reserved for vendor use. Use only the default value.
Reserved for vendor use. Use only the default value.
Reserved for vendor use. Use only the default value.
Reserved for vendor use. Use only the default value.
Reserved for vendor use. Use only the default value.
Reserved for vendor use. Use only the default value.
Changes the lock timing loop. The default is logic LOW. This pin is required to be
programmed to logic HIGH.
7
LD Mode
0
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F159V Datasheet
24.2.39. Register 38 (26h)
Register 39 and 38 select the VCO Band within the PLL. This is a 12-bit word that can vary from 1 to 4095. The default value is 256 = 100h =
0001_0000_0000b. Register 38 is the lower 8 bits of the word and the default value is 0 = 00h = 0000_0000b.
Table 74. Register 38: Bit Definition
Bit
Bit Field Name
Default
Definition
Bit 0 of a 12-bit word to select the VCO Band.
0
1
2
3
4
5
6
7
BndSelDiv[0]
BndSelDiv[1]
BndSelDiv[2]
BndSelDiv[3]
BndSelDiv[4]
BndSelDiv[5]
BndSelDiv[6]
BndSelDiv[7]
0
0
0
0
0
0
0
0
Bit 1 of a 12-bit word to select the VCO Band.
Bit 2 of a 12-bit word to select the VCO Band.
Bit 3 of a 12-bit word to select the VCO Band.
Bit 4 of a 12-bit word to select the VCO Band.
Bit 5 of a 12-bit word to select the VCO Band.
Bit 6 of a 12-bit word to select the VCO Band.
Bit 7 of a 12-bit word to select the VCO Band.
24.2.40. Register 39 (27h)
Register 39 and 38 select the VCO Band within the PLL. This is a 12-bit word that can vary from 1 to 4095. The default value is 256 = 100h =
0001_0000_0000b. Register 39 is the higher 4 bits of the word and the default value is 1 = 01h = 0000_0001b.
Table 75. Register 39: Bit Definition
Bit
Bit Field Name
Default
Definition
Bit 8 of a 12-bit word to select the VCO Band.
0
1
2
3
4
5
6
7
BndSelDiv[8]
BndSelDiv[9]
BndSelDiv[10]
BndSelDiv[11]
Unused
1
0
0
0
0
0
0
0
Bit 9 of a 12-bit word to select the VCO Band.
Bit 10 of a 12-bit word to select the VCO Band.
Bit 11 of a 12-bit word to select the VCO Band.
Unused.
Unused.
Unused.
Unused.
Unused
Unused
Unused
24.2.41. Register 40 (28h)
This register is reserved for internal use. The default value is 0 = 00h = 0000_0000b.
24.2.42. Register 41 (29h)
This register is reserved for internal use. The default value is 0 = 00h = 0000_0000b.
24.2.43. Register 42 (2Ah)
This register is reserved for internal use. The default value is 2 = 02h = 0000_0010b.
24.2.44. Register 43 (2Bh)
This register is reserved for internal use. The default value is 203 = CBh = 1100_1011b.
24.2.45. Register 44 (2Ch)
This register is reserved for internal use. The default value is 0 = 00h = 0000_0000b.
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F159V Datasheet
24.2.46. Register 45 (2Dh)
This register is reserved for internal use. The default value is 0 = 00h = 0000_0000b.
24.2.47. Register 46 (2Eh)
This register is reserved for internal use and is READ ONLY. The default value does not apply.
24.2.48. Register 47 (2Fh)
This register is reserved for internal use and is READ ONLY. The default value does not apply.
24.2.49. Register 48 (30h)
This register is reserved for internal use and is READ ONLY. The default value does not apply.
24.2.50. Register 49 (31h)
This register is reserved for internal use. The default value does not apply.
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F159V Datasheet
25. Evaluation Kit Picture
Figure 97. Top View – Differential Board
Figure 98. Bottom View – Differential Board
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F159V Datasheet
26. Evaluation Kit / Applications Circuit
Figure 99. Electrical Schematic for the Differential Evaluation Board
All differential ports have transmission lines of equal length.
J1
J3
J4
J2
CH0_BBI-
J5
CH0_BBQ+
CH0_BBQ-
CH0_BBI+
CH0_MOD_C
HEADER 8X2
J6
C1
C2
C3
C4
CH0_MODEN
Vdd_MODLO_CH0
Vdd_DAC
2
4
6
1
3
5
7
D1
LED
8
10
12
14
16
9
CH0_AMPEN
CH1_AMPEN
CH0_MODEN
CH1_MODEN
VDD_MODAMP_CH0
11
13
15
R28
R29
R31
R35
R25
R23
C11
C12
C14
CH0_AMPEN
R26
R27
R30
R34
C22 C21 C20 C19
R33
C13
CH0_RDST_MOD
C15
C16
C17 C18
R32
B1
B
A1
A
Vdd_SPI
SW1
SPST 5N PANASONIC
Vdd_SPI
5
C24
R36
R37 C23
Vdd_VVA_CH0
C25
U1
J8
REF_IN
R40
C62
CH0_RDIST_AMP CH0_RBIAS
R39
Vdd_REF
C29
C28
R42
R43
R41
CH0_RF_OUT
TP30
J10
C30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
R44
Vdd_AMP_CH0
R45
CH0_Vdd_VVA
CH0_RDIST_AMP
CH0_RBIAS
CH0_Vdd_AMP
GND
GND
CH0_RFOUT
GND
GND
GND
CHI_RFOUT
GND
GND
Vdd_SPI
GND_SPI
RESET
Vdd_REF
REF_IN
NC
GND_REF
Vdd_CP
DNC
GND_CP
CP_OUT
GND_VCO
VTUNE
C33
C27
R46
C31
Vdd_CP
C26
C32
TP6
R48
C35
C36
R50
C38
R49
CH1_RF_OUT
C39
J11
C40
CH1_Vdd_AMP
CH1_RBIAS
CH1_RDIST_AMP
CH1_Vdd_VVA
VREF_VCO
Vdd_VCO
VCOM
R51
Vdd_AMP_CH1
C41
C42
Vdd_LO
C43
VREF_VCO
R52
R54
C47
C46
C44
J12
HEADER
Vdd_VCO
1
R53
4
C48
2
3
4
DATA
CLK
CSB
These pins are only
used by IDT.
CH1_RDIST_AMP CH1_RBIAS
VCOM
Vdd_VVA_CH1
Vdd_LO
C50
C49
J17
J14
J16
J13
C58
C57
C55
C51
LO_OUT-
LO_OUT+
LO_IN-
C56
CH1_RDIST_MOD
R55
C53
CH1_AMPEN
Vdd_MODAMP_CH1
C52
CH1_MODEN
Vdd_MODLO_CH1
J15
CH1_MOD_C
LO_IN+
C67
J19
C69
J21
C66
C68
J18
J20
CH1_BBQ+
CH1_BBQ-
CH1_BBI+
CH1_BBI-
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F159V Datasheet
Figure 100. DC Electrical Schematic for the Differential Evaluation Board
VDD_DAC
L2
100mA
VDD_DAC
C70
C80
C88
C72
C81
C92
C73
C82
C93
J24
BEAD FERRITE/SM
HEADER
3
R87
R89
VDD_VVA_CH0
L4
50mA
C77
VDD_CP
L1
VDD_VVA_CH0
R91
R93
VDD_3_3V_EXT
100mA
VDD_CP
VDD_LO
VDD_SPI
C79
BEAD FERRITE/SM
L6
J26
HEADER
VDD_MODLO_CH0
3
BEAD FERRITE/SM
C71
C74
C75
VREG_5V
U2
50mA
VDD_MODLO_CH0
J28
VDD_LO
L3
VDD_3_3V_EXT
J30
1
1
2
3
4
12
BEAD FERRITE/SM
L8
50mA
VDD
GND
EN
VR1
2
3
4
5
11
10
9
VDD_AMP_CH0
VR2
VR3
VR4
C83
C84
C85
HEADER
3
BEAD FERRITE/SM
300mA
VDD_AMP_CH0
REF
C100
C101
C102
C87
VDD_SPI
BEAD FERRITE/SM
L11
L5
VDD_3_3V_EXT
50mA
VDD_MODAMP_CH0
VDD_MODAMP_CH0
R99
C95
J32
HEADER
C89
C90
C91
300mA
3
R101
C97
BEAD FERRITE/SM
C114
C145
C109
C118
C123
C104
C115
C146
C110
C119
C124
C105
C116
R103
R106
BEAD FERRITE/SM
L17
VDD_VCO
L7
VDD_3_3V_EXT
VDD_3_3V_EXT
VDD_AMP_CH1
300mA
VDD_VCO
300mA
C98
C99
C103
VDD_AMP_CH1
BEAD FERRITE/SM
J49
C147
C111
C120
C125
C106
BEAD FERRITE/SM
L10
2
1
VREF_VCO
VDD_VVA_CH1
GND1
GND4
HEADER 1x2
50mA
GND
GND
GND
VDD_VVA_CH1
VDD_3_3V
GND2
GND3
J45
GND5
BEAD FERRITE/SM
L12
R136
VDD_3_3V_EXT
VDD_MODLO_CH1
VDD_3_3V_EXT
GND
GND
C139
C140
C141
50mA
VDD_MODLO_CH1
BEAD FERRITE/SM
L13
VCC_5V
J47
R137
VDD_MODAMP_CH1
VREG_5V
VREG_5V
300mA
C142
C143
C144
VDD_MODAMP_CH1
BEAD FERRITE/SM
L9
VDD_REF
100mA
VDD_REF
BEAD FERRITE/SM
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F159V Datasheet
Table 76. Bill of Material (BOM)
Part Reference
QTY
Description
Manufacturer Part #
Manufacturer
C14, C30, C40, C51,
C55, C56, C57, C58
8
100pF ±5%, 50V, C0G Ceramic Capacitor (0402)
GRM1555C1H101J
Murata
C11, C13, C25, C27,
C43, C49, C52, C53
8
1000pF ±5%, 50V, C0G Ceramic Capacitor (0402)
GRM1555C1H102J
Murata
C72, C74, C81, C84,
C90, C92, C99, C101,
C105, C110, C115,
C119, C124, C140,
C146
15
10nF ±5%, 50V, X7R Ceramic Capacitor (0402)
GRM155R71H103J
Murata
C12, C24, C28, C29,
C32, C48, C50
7
100nF ±10%, 16V, X7R Ceramic Capacitor (0402)
10µF ±20%, 16V, X6S Ceramic Capacitor (0603)
GRM155R71C104K
GRM188C81C106M
Murata
Murata
C70, C71, C80, C83,
C88, C89, C100,
C104, C109, C114,
C118, C123, C145
13
C139
1
1
1
1
1
1
1
10µF ±10%, 16V, X6S Ceramic Capacitor (0805)
2700pF ±10%, 50V, X7R Ceramic Capacitor (0402)
47nF ±10%, 50V, X7R Ceramic Capacitor (0402)
680pF ±5%, 50V, C0G Ceramic Capacitor (0402)
2.2µF ±10%, 10V, X5R Ceramic Capacitor (0402)
33nF ±10%, 50V, X7R Ceramic Capacitor (0402)
150µF ±20%, 6.3V, X5R Ceramic Capacitor (1210)
GRM21BC81C106K
GRM155R71H272K
GRM155R71H473K
GRM1555C1H681
GRM155R61A225K
GRM155R71H333K
JMK325ABJ157M
Murata
Murata
C35
C38
Murata
C36
Murata
C44
Murata
C46
C98
Murata
Taiyo Yuden
R25, R36, R40, R45,
C1, C2, C3, C4, C62, 13
C66, C67, C68, C69
0Ω Resistor (0402)
ERJ-2GE0R00X
Panasonic
R136
R23
1
1
0Ω Resistor (0805)
ERJ-6GEY0R00
ERJ-2RKF33R0X
Panasonic
Panasonic
33Ω ±1%, 1/10W, Resistor (0402)
R28, R29, R31, R32,
R35
5
Panasonic
100Ω ±1%, 1/10W, Resistor (0402)
360Ω ±1%, 1/10W, Resistor (0402)
1kΩ ±1%, 1/10W, Resistor (0402)
ERJ-2RKF1000X
ERJ-2RKF3600X
ERJ-2RKF1001X
R50
1
3
Panasonic
Panasonic
R39, R46, R54
R26, R27, R30, R34,
R33, R55, C15, C16,
C17, C18
10
2kΩ ±1%, 1/10W, Resistor (0402)
ERJ-2RKF2001X
Panasonic
R41, R52
R37
2
1
3.9kΩ ±1%, 1/10W, Resistor (0402)
ERJ-2RKF3901X
ERJ-2RKF5111X
Panasonic
Panasonic
5.11kΩ ±1%, 1/10W, Resistor (0402)
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F159V Datasheet
Table 77. Bill of Material (BOM) (Cont.)
Part Reference
QTY
Description
Manufacturer Part #
Manufacturer
L1- L13, L17
14
1
EMI Filter Beads Chips 220 Ohm 450mA (0603)
LED GREEN CLEAR SMD (0603)
BLM18BB221SN1D
LTST-C191KGKT
EVQ-PBG05R
Murata
LITE-ON
Panasonic
3M
D1
SW1
1
SWITCH TACTILE SPST-NO 0.02A 15V
CONN HEADER VERT SGL 3 X 1 POS GOLD
CONN HEADER VERT SGL 4 X 1 POS GOLD
CONN HEADER VERT SGL 5 X 1 POS GOLD
CONN HEADER VERT DBL 8 X 2 POS GOLD
J24, J26, J30, J32
4
961103-6404-AR
961104-6404-AR
961105-6404-AR
67997-116HLF
J12
J28
J6
1
3M
1
3M
1
FCI
J1, J2, J3, J4, J5, J8,
J10, J11, J13, J14,
J15, J16, J17,J18,
J19, J20, J21
17
Edge Launch SMA (0.375 inch pitch ground, tab)
142-0701-851
Emerson Johnson
J45
U1
1
1
1
Edge Launch SMA (0.250 inch pitch ground, round)
RF Transmitter 2 Channels
142-0711-821
F159VNLGN
Emerson Johnson
IDT
IDT
Printed Circuit Board
F159V EVKIT REV 02
Note: All other parts noted in the schematic that are not contained in this Bill of Material are not installed.
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F159V Datasheet
27. Application Information
The F159V is optimized for use in high-performance RF applications from 450MHz to 2800MHz.
27.1. Power Supplies
A common VDD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to
minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail.
Supply voltage change or transients should have a slew rate smaller than 1V/20µS. In addition, all control pins should remain at 0V (+/-0.3V)
while the supply voltage ramps or while it returns to zero. For multiple devices driven by a single control line, values will need to be adjusted so
as to not load the control line.
27.2. Power Supply Sequencing
All power supply pins must be turned on simultaneously.
27.3. Digital Pin Voltage and Resistance Values
The following table provides open-circuit DC voltage referenced to ground and resistance values for each of the control pins listed.
Table 78. Digital Pin Voltages and Resistance
Pull-up or Pull-down
Resistance Value (kΩ)
Pin
Name
DC Voltage (volts)
18
27
49
52
53
54
59
68
CH1_AMPEN
CH1_MODEN
RESET
3.3
3.3
0
50
50
51
51
51
51
50
50
SPI_CSN
0
SPI_CLK
0
SPI_DIO
1.8
3.3
3.3
CH0_MODEN
CH0_AMPEN
27.4. Phase Relation between the Quadrature Input Signals: I and Q
When BBI leads BBQ by 90 degrees, HS LO injection is used. When BBQ leads BBI by 90 degrees, LS LO injection is used.
27.5. Signal Integrity
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of each control pin is recommended. This applies to all SPI and control pins as shown below. Note that the recommended resistor
and capacitor values do not necessarily match the EVKit BOM for the case of poor control signal integrity.
© 2020 Renesas Electronics Corporation
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F159V Datasheet
Figure 101. Control Pin Interface
5 kΩ
5 kΩ
SPI_DIO
SPI_DO
SPI_CLK
SPI_CSN
2 pF
2 pF
5 kΩ
5 kΩ
5 kΩ
CH0_AMPEN
5 kΩ
CH0_MODEN
2 pF
2 pF
2 pF
2 pF
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
1
2
5 kΩ
RESET
3
2 pF
4
5
6
7
8
9
10
11
12
13
14
15
16
17
5 kΩ
5 kΩ
CH1_AMPEN
CH1_MODEN
2 pF
2 pF
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F159V Datasheet
28. Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/us/en/document/psc/nlnlg68-package-outline-100-x-100-mm-epad-770-mm-sq-vfqfp-n
29. Ordering Information
Orderable Part Number
Package
MSL Rating
Shipping Packaging
Temperature
F159VNLGN
F159VNLGN8
F159VEVBN
10 x 10 x 0.9 mm 68-VFQFPN
10 x 10 x 0.9 mm 68-VFQFPN
3
Tray
Reel
-20° to +115°C
-20° to +115°C
3
Evaluation Board
30. Marking Diagram
.
.
.
.
.
Line 1 and 2 are the part number.
Line 3 “ZK” is for die version.
IDT
F159VNLGN
ZK1729L
Line 3 “yyww” = 1729 has two digits for the year and week that the part was assembled.
Line 3 “L” denotes assembly site.
Line 4 “Q57BO12PY THA” is the assembly lot number.
Q57BO12PY THA
Revision History
Revision Date
Description of Change
May 15, 2020
Rebranded/reformatted document.
Updated for format, theory of operation, and register definition.
Initial release.
November 10, 2017
December 23, 2016
© 2020 Renesas Electronics Corporation
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