F1975 [RENESAS]
6-Bit, 75Ω Digital Step Attenuator 5MHz to 3GHz;
| 型号： | F1975 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 6-Bit, 75Ω Digital Step Attenuator 5MHz to 3GHz |
| 文件： | 总27页 (文件大小：3963K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6-Bit, 75Ω Digital Step Attenuator
5MHz to 3GHz
F1975
Datasheet
Description
Features
The F1975 Digital Step Attenuator (DSA) is a product in IDT’s
Glitch-FreeTM DSA Family, which is optimized for the demanding
requirements of CATV and satellite systems. It operates in the
frequency range of 5MHz to 3000MHz. This device is offered in a
compact 4mm 4mm, 20-pin Thin QFN package with a 75Ω
impedance for ease of integration.
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Frequency: 5MHz to 3000MHz
Serial and 6-bit parallel interface
31.5dB control range
0.5dB step
Glitch-FreeTM technology, low transient overshoot
3.0V to 5.25V supply
1.8V or 3.3V control logic
Attenuator step error: 0.1dB at 1GHz
Low insertion loss: 1.2dB at 1GHz
Ultra-linear IIP3: +64dBm
Advantages
Digital step attenuators are used in receivers and transmitters to
provide gain control. The F1975 is a 6-bit step attenuator optimized
for these demanding applications. The silicon design has very low
insertion loss and low distortion (+64dBm IIP3). The device has
pinpoint attenuation accuracy. Most importantly, the F1975
includes IDT’s Glitch-FreeTM technology, which results in low over-
shoot and ringing during most significant bit (MSB) transitions.
IIP2: +125dBm typical
Stable integral non-linearity over temperature
Low current consumption: 550µA typical
Bi-directional
Operating temperature: -40°C to +105°C
4mm 4mm, 20-pin QFN package
.
Glitch-FreeTM technology protects the power amplifier or
analog-to-digital converter (ADC) from damage during
transitions between attenuation states
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Extremely accurate attenuation levels
Ultra-low distortion
Block Diagram
Figure 1. Block Diagram
Low insertion loss for best signal-to-noise ratio (SNR)
Typical Applications
Glitch-FreeTM
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CATV infrastructure
CATV set-top boxes
CATV satellite modems
Data network equipment
Fiber networks
RF2
RF1
SPI
Decoder
Bias
1
Rev 1 September 21, 2017
Pin Assignments
Figure 2. Pin Assignments for 4mm 4mm 0.75mm, 20-pin QFN Package – Top View (Through Package)
20
19
18
17
16
1
2
3
4
5
15
14
13
12
11
D5
RF1
D4
RF2
VMODE
NC
DATA
CLK
LE
Exposed Pad
GND
6
7
8
9
10
2
Rev 1 September 21, 2017
Pin Descriptions
Table 1.
Pin Descriptions
Number
Name
Description
1
2
3
4
D5
RF1
16dB attenuation control bit. This pin is activated by logic HIGH (see Table 11). [a]
Device RF input or output (bi-directional).
Serial interface data input.
DATA
CLK
Serial interface clock input.
Serial interface latch enable input. Internal pull-up (100kΩ). See “Programming” section for proper
usage of this line.
5
LE
VDD
NC
6
Power supply pin.
No internal connection. These pins can be left unconnected, have a voltage applied, or be connected to
ground (recommended)
7–9, 12, 18
Internally grounded. Connect pin directly to paddle ground or as close as possible to the pin with thru
vias.
10, 11
GND
13
14
15
16
17
19
20
VMODE
RF2
D4
Pull this pin HIGH for Serial Control Mode. Ground this pin for Parallel Control Mode.
Device RF input or output (bi-directional).
8dB attenuation control bit. This pin is activated by logic HIGH (see Table 11).[a]
4dB attenuation control bit. This pin is activated by logic HIGH (see Table 11).[a]
2dB attenuation control bit. This pin is activated by logic HIGH (see Table 11).[a]
1dB attenuation control bit. This pin is activated by logic HIGH (see Table 11).[a]
0.5dB attenuation control bit. This pin is activated by logic HIGH (see Table 11).[a]
D3
D2
D1
D0
Exposed paddle. Internally connected to ground (GND). Solder this exposed paddle to a printed circuit
board (PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the PCB
ground planes. These multiple ground vias are also required to achieve the specified RF performance.
EPAD
[a] There is a 100kΩ pull-up resistor to the internally regulated 2.5V power supply.
3
Rev 1 September 21, 2017
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.
Functional operation of the F1975 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions could affect
device reliability.
Table 2.
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
VDD to GND
VDD
-0.3
+5.5
V
Minimum
(VDD+0.3, 3.6)
DATA, LE, CLK, D[5:0], VMODE
VLogic
-0.3
-0.3
V
RF1, RF2
VRF
PRF
+0.3
+34
V
Maximum Input Power Applied to RF1 or RF2 (>100MHz)
Continuous Power Dissipation
Junction Temperature
dBm
dBm
°C
Pdiss
TJ
1.75
+140
+150
+260
Storage Temperature Range
Lead Temperature (soldering, 10s)
TSTOR
-65
°C
°C
Electrostatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
2000
(Class 2)
VESDHBM
VESDCDM
V
V
Electrostatic Discharge – CDM
(JEDEC 22-C101F)
250
(Class C1)
4
Rev 1 September 21, 2017
Recommended Operating Conditions
Table 3.
Recommended Operating Conditions
Parameter
Symbol
VDD
Condition
Minimum
Typical
Maximum
5.25
Units
V
Supply Voltage(s)
3.00
5
Frequency Range
fRF
3000
MHz
°C
Operating Temperature Range
RF CW Input Power
RF1 Impedance
TEP
Exposed paddle
RF1 or RF2
-40
105
PCW
ZRF1
ZRF2
See Figure 3
dBm
Ω
Single-ended
Single-ended
75
75
RF2 Impedance
Ω
Figure 3. Maximum Continuous Operating RF Input Power versus Input Frequency (+25C)
30
28
26
24
22
20
18
16
14
+25 C - CW
12
10
8
0.01
0.1
1
10
100
1000
10000
Frequency (MHz)
5
Rev 1 September 21, 2017
Electrical Characteristics
The specifications in Table 4 apply at VDD = +3.3V, TEP = +25°C, fRF = 1000MHz, PIN = 0dBm, Serial Mode, ZS = ZL = 75Ω, Evaluation Board
(EVKit) trace and connector losses are de-embedded, unless otherwise noted.
Table 4.
Electrical Characteristics
Parameter
Symbol
Condition
All control pins
Minimum
Typical
Maximum
Units
Logic Input High Threshold
VIH
VDD > 3.6V
1.17 [a]
1.17
3.6
VDD
0.63
+35
830
900
V
3.0V ≤ VDD ≤ 3.6V
All control pins
All control pins
VDD = 3.3V
Logic Input Low Threshold
Logic Current
VIL
V
IIH, IIL
-35
µA
550
620
18
Supply Current [b]
IDD
µA
VDD = 5.0V
RF1 Return Loss
RF2 Return Loss
Attenuation Step
S11
S22
dB
dB
dB
18
LSB
Least significant bit
0.5
Insertion Loss
(Minimum Attenuation)
AMIN
D[5:0]=[000000BIN] (IL State)
D[5:0]=[111111BIN]=31.5dB
1.2
2.0
dB
Attenuation Range
Step Error
ARANGE
DNL
INL
30.5
31.1
0.1
31.7
dB
dB
dB
Absolute Error
D[5:0]=[100111BIN]= 19.5dB
-0.7
+0.5
fRF = 0.5GHz (AMAX to AMIN
)
)
10
20
Insertion Phase Delta
Input IP3
ΦΔ
deg
fRF = 1.0GHz (AMAX to AMIN
PIN = +10dBm/tone,
f1 = 900MHz, f2 = 950MHz
IIP3
Attn = 0.0dB, RFIN = RF1
Attn =15.5dB, RFIN = RF1
60
59
64
62
dBm
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns
that are not shown in bold italics are guaranteed by design characterization.
[b] Current is tested using the Serial Mode with parallel pins floating. If parallel pins are grounded, add 25µA per pin.
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Rev 1 September 21, 2017
Electrical Characteristics (continued)
The specifications in Table 5 apply at VDD = +3.3V, TEP = +25°C, fRF = 1000MHz, PIN = 0dBm, Serial Mode, ZS = ZL = 75Ω, Evaluation Board
(EVKit) trace and connector losses are de-embedded, unless otherwise noted.
Table 5.
Electrical Characteristics
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
PIN = +12dBm/tone
f1= 945MHz,
Input IP2
IIP2
f2 = 949MHz
125
dBm
f1 + f2 = 1894MHz
RFIN = RF1
PIN = +15dBm
RFIN = 945MHz
RFOUT = 1890MHz
RFIN = RF1
Second Harmonic
H2
IP0.1
tLSB
108
30.5
500
dBc
dBm
ns
D[5:0] = [000000] = AMIN
RFIN = RF1
,
Input 0.1dB Compression [c]
MSB Step Time
Start at LE rising edge
End ±0.10dB Pout
settling for 15.5dB to
16.0dB transition
Maximum Spurious Level on any
RF Port [d]
SPURMAX
SWRATE
-130
25
dBm
kHz
Maximum Switching Rate
Maximum to minimum
attenuation to settle to
within 0.5dB of final
value
0.9
[e]
DSA Settling Time
µs
SET
Maximum to minimum
attenuation to settle to
within 0.5dB of final
value
1.8
6
Control Interface
SPIBIT
SPICLK
bit
Serial Clock Speed
25
MHz
[c] The input 0.1dB compression point is a linearity figure of merit. Refer to “Absolute Maximum Ratings” section for the maximum RF input
power. This specification is measured in a 50Ω system.
[d] Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2MHz.
[e] Speeds are measured after SPI programming is completed (data latched with LE = HIGH).
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Rev 1 September 21, 2017
Thermal Characteristics
Table 6.
Package Thermal Characteristics
Parameter
Symbol
Value
Units
Junction to Ambient Thermal Resistance
θJA
50
°C/W
Junction to Case Thermal Resistance
(Case is defined as the exposed paddle)
θJC-BOT
3
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL 1
Typical Operating Conditions (TOC)
Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply.
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VDD = +3.3V
ZL = ZS = 75Ω single-ended
TEP = +25°C
fRF = 1GHz
PIN = 0dBm for single tone measurements
PIN = +10dBm/tone for multi-tone measurements
Tone spacing = 50MHz
Evaluation Board connector and board losses are de-embedded
Measured in a 75Ω system unless otherwise specified
8
Rev 1 September 21, 2017
Typical Performance Characteristics
Figure 4. Insertion Loss vs. Frequency
Figure 5. Insertion Loss vs. Attenuation State
0.0
0
1 GHz, -40 C
-40 C
-0.5
1 GHz, +25 C
1 GHz, +105 C
+25 C
-5
-10
+105 C
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-15
-20
-25
-30
-35
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3.5
3.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Figure 6. RF1 Return Loss vs. Frequency
(All States)
Figure 7. RF1 Return Loss vs. Attenuation
State
0
-5
0
0.01 GHz
1.25 GHz
0.50 GHz
1.50 GHz
0.75 GHz
1.75 GHz
1.00 GHz
2.00 GHz
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Figure 8. RF2 Return Loss vs. Frequency
(All States)
Figure 9. RF2 Return Loss vs. Attenuation
State
0
-5
0
0.01 GHz
1.25 GHz
0.50 GHz
1.50 GHz
0.75 GHz
1.75 GHz
1.00 GHz
2.00 GHz
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
9
Rev 1 September 21, 2017
Typical Performance Characteristics
Figure 10. Relative Insertion Phase vs.
Frequency (All States)
Figure 11. Relative Insertion Phase vs.
Attenuation
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
0.01 GHz
1.25 GHz
0.50 GHz
1.50 GHz
0.75 GHz
1.75 GHz
1.00 GHz
2.00 GHz
0
0
-5
-5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Figure 12. Worst-Case Absolute Accuracy Error
Figure 13. Accuracy Error vs. Attenuation
0.5
0.5
0.01 GHz
1.25 GHz
0.50 GHz
1.50 GHz
0.75 GHz
1.75 GHz
1.00 GHz
2.00 GHz
0.0
-0.5
-1.0
0.0
-0.5
-1.0
-1.5
-2.0
-40 C Min
+25 C Min
+105 C Min
-40 C Max
+25 C Max
+105 C Max
-1.5
-2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Figure 14. Worst-Case Step Accuracy
Figure 15. Step Error vs. Attenuation
0.3
0.3
0.01 GHz
1.25 GHz
0.50 GHz
1.50 GHz
0.75 GHz
1.75 GHz
1.00 GHz
2.00 GHz
-40 C Min
+25 C Min
+105 C Min
-40 C Max
+25 C Max
+105 C Max
0.2
0.1
0.2
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
10
Rev 1 September 21, 2017
Typical Performance Characteristics
Figure 16. Compression versus Input Power
[Attenuation = 0.0dB]
Figure 17. Input IP3 versus Attenuation Setting
0.5
75
70
65
60
55
50
45
40
0.005 GHz
1.000 GHz
0.050 GHz
1.500 GHz
0.100 GHz
2.000 GHz
0.500 GHz
0.0
-0.5
-1.0
-1.5
-2.0
0.035 GHz
0.920 GHz
0.065 GHz
1.400 GHz
0.130 GHz
2.000 GHz
0.500 GHz
35
30
25
Measured in a 50 ohm system
16
18
20
22
24
26
28
30
32
34
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation Setting (dB)
Input Power (dBm)
11
Rev 1 September 21, 2017
Programming
The F1975 can be programmed using either the parallel or the serial interface, which is selectable via VMODE (pin 13). Serial Mode is selected
by floating VMODE or pulling it to a logic HIGH, and Parallel Mode is selected by setting VMODE to a logic LOW.
For a comparison of the F1975 and F1975 products, see the Application Note AN945 – Comparison of F1975 and F1975 Digital Step Attenuator
Serial Programming Methods.
Serial Control Mode
The F1975 Serial Mode is selected by floating VMODE (pin 13) or pulling it to a logic HIGH. The serial interface is a 6-bit shift register and shifts
in the most significant bit (MSB) (D5 bit) first.
Table 7.
6 Bit SPI DATA Word Sequence
Bit
D5
D4
D3
D2
D1
D0
Definition
Attenuation 16dB Control Bit
Attenuator 8dB Control Bit
Attenuator 4dB Control Bit
Attenuator 2dB Control Bit
Attenuator 1dB Control Bit
Attenuator 0.5dB Control Bit
Table 8.
Truth Table for Serial Control Word Bits
D5
(MSB)
D0
(LSB)
D4
D3
D2
D1
Attenuation (dB)
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0.5
1
2
4
8
16
31.5
12
Rev 1 September 21, 2017
Serial Mode Programming
In the Serial Mode, the F1975 is programmed via the serial port on the rising edge of the Latch Enable (LE) signal. It is required that LE be kept
at logic LOW until all data bits are clocked into the shift register. The F1975 will change its attenuation state after the data word is latched into
the active register as illustrated in Figure 18. After the data word in the shift register has been latched into the active register, the LE signal must
be dropped LOW. This allows shifting new data into the shift register without uploading it to the active register until the next time LE goes HIGH.
The timing specification intervals are shown in blue font in Figure 18.
Figure 18. Serial Register Timing Diagram
Note: If the Serial Register programming method is used, the attenuator will change to the new attenuation state only after the data word is
latched into the active register, a single programming event.
Table 9.
Serial Mode Timing Table
Interval Symbol
tmc
tds
Description
Min Spec
Max Spec
Units
ns
Parallel Mode to Serial Mode setup time: from the rising edge of VMODE
to the rising edge of CLK for the D5 bit
100
10
Clock HIGH pulse width
ns
LE setup time: from the rising edge of the CLK pulse for D0 to LE rising
edge minus half the clock period
tcls
10
ns
LE hold time: from the falling edge of the LE pulse to the rising edge of
CLK
tclh
tlew
tdcs
tdht
10
10
10
10
ns
ns
ns
ns
LE pulse width
Data setup time: from the starting edge of the data bit to the rising edge
of CLK
Data hold time: from rising edge of CLK to falling edge of the data bit
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Rev 1 September 21, 2017
Serial Mode Default Startup Condition
When the device is first powered up, it will default to the maximum attenuation of 31.5dB independent of the parallel pin [D5:D0] conditions.
Table 10. Default Control Word for the Serial Mode
D5 (MSB)
D4
D3
D2
D1
D0 (LSB) Attenuation (dB)
31.5
1
1
1
1
1
1
Parallel Control Mode
For the F1975, the user has the option of programming in one of two parallel modes: Direct Parallel Mode or Latched Parallel Mode.
Direct Parallel Mode
Direct Parallel Mode is selected when VMODE (pin 13) is set to a logic LOW and LE (pin 5) is set to a logic HIGH. In this mode, the device will
immediately react to any voltage changes in the parallel control pins (1, 15, 16, 17, 19, and 20). Use direct parallel mode for the fastest settling
time.
Direct Parallel Default Startup Condition
In the Direct Parallel Mode, the attenuation value is determined by the logic condition of the parallel pins (1, 15, 16, 17, 19, and 20) at the time
of start-up.
Latched Parallel Mode
The Latched Parallel Mode is selected when VMODE is set to a logic LOW and LE (pin 5) is toggled from a logic LOW to a logic HIGH.
To utilize the Latched Parallel Mode, complete these steps:
.
.
Set the LE pin to a logic LOW.
Set pins 1, 15, 16, 17, 19, and 20 for the desired attenuation setting. (While LE is set to a logic LOW, the attenuation state will not
change.)
.
Toggle LE to a logic HIGH. The device will then transition to the attenuation settings reflected by pins D5 through D0.
14
Rev 1 September 21, 2017
Latched Parallel Default Startup Condition
The Latched Parallel Mode establishes a default attenuation state when the device is first powered up which is the maximum attenuation.
Table 11. Truth Table for the Parallel Pins
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Attenuation (dB)
0
0.5
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
2
0
0
1
0
0
0
4
0
1
0
0
0
0
8
1
0
0
0
0
0
16
31.5
1
1
1
1
1
1
Figure 19. Latched Parallel Mode Timing Diagram
VMODE
tSPS
tLE
tPDH
tPDS
Data Word Latched
into the Register
LE
D[5:0]
Time
Table 12. Latched Parallel Mode Timing
Interval Symbol
Description
Serial Mode to Parallel Mode setup time
Parallel data hold time
Min Spec
Max Spec
Units
ns
tSPS
tPDH
tPDS
tLE
100
10
ns
LE minimum pulse width
10
ns
Parallel data setup time
10
ns
15
Rev 1 September 21, 2017
Applications Information
F1975 Digital Pin Voltage and Resistance Values (Pins not Connected)
Table 13 lists the resistance between various pins and ground when no DC power is applied. When the device is powered up with +5V DC,
these pins will exhibit a voltage to ground as indicated.
Table 13. Voltage and Resistance to Ground for the Logic Pins
Pin
13
Name
VMODE
DC Voltage (Volts)
Resistance (Ohms)
100kΩ pull-up resistor to internally regulated 2.5V.
100kΩ pull-up resistor to internally regulated 2.5V.
2.5V
2.5V
3, 4, 5
DATA, CLK, LE
1, 15–17,
19, 20
D5, D4, D3,
D2, D1, D0
2.5V
100kΩ pull-up resistor to internally regulated 2.5V.
16
Rev 1 September 21, 2017
F1975 Evaluation Kit
Figure 20. F1975EVBI Evaluation Board – Top View
VDD
Set U2 Switches D0 to D5
for Parallel Data
Logic HIGH Switch Position (+)
Open Circuit Switch Position (O)
Logic LOW Switch Position (–)
VMODE
J4 Parallel Control Pins
RF1
RF2
J11 Serial Control Pins
17
Rev 1 September 21, 2017
Figure 21. F1975EVBI Evaluation Board – Back View
18
Rev 1 September 21, 2017
Evaluation Kit / Applications Circuit
Figure 22. Electrical Schematic
LENGTH
=
RF1
+
RF2 LINES
J12
J13
F-TYPE
F-TYPE
Thru Cal
75 ohm
VLOGIC
VDD
J1
J8
VDD
C1
C2
C11
C10
HEADER 1x2
J2
J3
R1
U2
J5
VDD
1
2
HEADER 1x2
R2
HEADER 1x2
8 pin DIP Switch
Logic Low
switch to '-' position
switch to '+' position
1
2
3
4
5
6
7
8
9
Logic High
D0
D1
Open Circuit switch to 'O' position
D2
D3
D4
D5
VMODE
VDD
GND
VDD
R5
R3
R4
R6
R7
R8
R9
J4
HEADER 1x9
C3
C4
C5
C6
C7
C8
C9
R11
R12
R13
R10
U1
RF1
RF2
F-TYPE
J7
R16
F-TYPE
R18
1
2
3
4
5
15
14
13
12
11
D5
D4
RF2
J11
HEADER 4X2
J6
Z0
=
75 OHM
Z0
= 75 OHM
RF1
R25
R26
R27
DATA
CLK
LE
VMODE
NC
GND
GND
R21
DATA
CLK
LE
R22
R23
R24
VDD
C12
C13
C14
C15
19
Rev 1 September 21, 2017
Bill of Materials (BOM)
Table 14. Evaluation Kit Bill of Material
Part Reference
C1, C11, C15
C2, C10
QTY
Description
Manufacturer Part #
GRM155R71C104K
GRM188R71H103J
Manufacturer
MURATA
3
2
100nF ±10%, 16V, X7R Ceramic Capacitor (0402)
10nF ±5%, 50V, X7R Ceramic Capacitor (0603)
MURATA
C3 - C9,
C12, C13, C14
10
7
100pF ±5%, 50V, C0G Ceramic Capacitor (0402)
100Ω ±1%, 1/10W, Resistor (0402)
0Ω Resistor (0402)
GRM1555C1H101J
ERJ-2RKF1000X
ERJ-2GE0R00X
MURATA
R3 - R9
PANASONIC
PANASONIC
R10-R13, R15-R18,
R24-R27
12
R21, R22, R23
3
1
1
3
1
1
3kΩ ±1%, 1/10W, Resistor (0402)
8.25kΩ ±1%, 1/10W, Resistor (0402)
10kΩ ±5%, 1/10W, Resistor (0402)
Conn Header Vert SGL 2 X 1 Pos Gold
Conn Header Vert DBL 4 X 2 Pos Gold
Conn Header Vert SGL 9 X 1 Pos Gold
ERJ-2RKF3001X
ERJ-2RKF8251X
ERJ-2RKF1002X
961102-6404-AR
67997-108HLF
PANASONIC
PANASONIC
PANASONIC
3M
R1
R2
J2, J3, J5
J11
FCI
J4
961109-6404-AR
3M
Edge Launch SMA
(0.250 inch pitch ground, round)
J1, J8
2
142-0711-821
Emerson Johnson
J6, J7, J12, J13
4
1
1
1
Edge Launch F-type 75 Ohm
Switch 8-Position Dip Switch
DSA
222181
KAT1108E
Amphenol
E-Switch
IDT
U2
U1
F1975NCGI
Printed Circuit Board
F1975 EVKit Rev 02
IDT
20
Rev 1 September 21, 2017
Evaluation Kit Operation
Power Supply Setup
Set up a power supply in the voltage range of 3.0V to 5.25V with the power supply output disabled. The voltage can be applied via one of the
following connections (see Figure 23):
.
.
.
J8 connector
J5 header connection (note the polarity of the GND pin on this connector)
Pin 8 (VDD) and pin 9 (GND) on the J4 header connection
Figure 23. Power Supply and Logic Voltage Connections
J3
J2
J5
J1 Connector
J8 Connector
VDD – J4, Pin 8
GND – J4, Pin 9
Parallel Logic Control Setup
The Evaluation Board has the ability to control the F1975 in the Parallel Mode. For external control, apply logic voltages to the J4 header pins 1
through 6 (see Figure 20). For manual control, switches 1 through 6 on U2 can be set. The switch is a three-position switch. The bottom position
“–” will ground the pin. The center position “O” will leave the pin open circuited. Setting the switch to the top position “+” will apply a voltage that
is supplied to the switch.
The logic voltage can be applied in one of two ways (see Figure 23):
.
.
Direct connection to connector J1.
Leave J1 open circuit, and add jumpers to headers J2 and J3. This will apply a logic voltage that is 0.24VDD.
The F1975 has internal pull-up resistors for the D0 – D5 parallel pins and VMODE. The switches can be used to apply a logic LOW (ground) for
proper operation. To use the Parallel Mode, either apply a ground to the VMOD pin 7 on J4 or set U2 switch 7 (VMOD) to the “–” position (see
Figure 20). The attenuation setting can be set via the U2 switches 1 through 6 (D0 through D5) according to Table 11.
21
Rev 1 September 21, 2017
Serial Logic Control Setup
The Evaluation Board has the ability to control the F1975 in the Serial Mode. Connect the serial controller to the J11 header connection as
shown in Figure 24. To use the Serial Mode, set U2 switch 7 to the “+” or “O” position.
The attenuation setting can be programmed according to Table 8.
Figure 24. Serial Logic Connections
Power-On Procedure
Set up the voltage supplies and Evaluation Board as described in the “Power Supply Setup” section and either the “Parallel Logic Control Setup”
or “Serial Logic Control Setup” sections above.
Enable the VDD supply.
Enable the proper attenuation setting according to Figure 20 and Table 8 for Serial Mode or Table 11 for the Parallel Mode.
Power-Off Procedure
Set the logic control pins to a logic LOW.
Disable the VDD supply.
22
Rev 1 September 21, 2017
Package Drawings
The package outline drawings are located at the end of this document. The package information is the most current data available and is subject
to change without notice or revision of this document.
Marking Diagram
1. Line 1 and 2 are the part number.
IDTF19
2. Line 3: “ZA” is for die version.
75NCGI
ZA515BEG
3. Line 3: “yww” = “515” = one digit year and two digit week that the part was assembled.
4. Line 3: “BEG” denotes assembly site.
Ordering Information
Orderable Part Number
Description and Package
MSL Rating
Shipping Packaging
Temperature
-40°C to +105°C
-40°C to +105°C
F1975NCGI
4mm x 4mm x 0.75mm QFN
4mm x 4mm x 0.75mm QFN
Evaluation Board
1
1
Tray
Reel
F1975NCGI8
F1975EVBI
Evaluation Solution including the Evaluation Board, Controller Board, and cable. The Evaluation Software is
available for download on the product page on the IDT website: www.IDT.com/F1975
F1975EVSI
23
Rev 1 September 21, 2017
Revision History
Revision
Revision Date
September 21, 2017 Updated evaluation board images, top markings, and updated to the latest template.
July 31, 2017 Initial release of the datasheet.
Description of Change
1
O
24
Rev 1 September 21, 2017
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NCG20P1ꢃ PSC-4445ꢄ0ꢅ, Rev 01ꢆ Page 2
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1ꢅ ALꢆ DIMENSꢇON ARE IN MM. ANGLES IN DEGREES
2ꢈ ꢉOP DOWN VIꢀW AS VꢇEWED ON PCB
3ꢈ ꢊND PAꢋꢌꢀRN RꢀCOMMꢀNDAꢌION PꢀR IPCꢍ7351B GꢀNꢀRIC RꢀQUIRꢀMꢀNꢎ
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Description
Date Created Rev No.
Sept 12, 20ꢀ7 Rev 0ꢁ Correct Title
Initial Rꢂꢃease
Sept 11, 20ꢀ7 Rev 00
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