F2251 [RENESAS]
Voltage Variable RF Attenuator 50MHz to 6000MHz;
| 型号： | F2251 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Voltage Variable RF Attenuator 50MHz to 6000MHz |
| 文件： | 总23页 (文件大小：2331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Voltage Variable RF Attenuator
50MHz to 6000MHz
F2251
Datasheet
Description
Features
The F2251 is a low insertion loss Voltage Variable RF Attenuator
(VVA) designed for a multitude of wireless and RF applications.
The device covers a broad frequency range from 50MHz to
6000MHz. In addition to providing low insertion loss, the F2251
provides excellent linearity performance over its entire voltage
control and attenuation range.
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Frequency range: 50MHz to 6000MHz
Low insertion loss: 1.4dB at 2000MHz
Typical/Minimum IIP3: 67dBm / 47dBm
Typical/Minimum IIP2: 105dBm / 95dBm
33.6dB attenuation range
Bi-directional RF ports
The F2251 uses a single positive supply voltage of 3.15V to 5.25V.
Other features include an enhancement to the Phase Noise
performance of the device compared to its predecessor (F2250).
The device also features a positive attenuation slope only.
+34.4dBm Input P1dB compression
Enhanced phase noise performance
Linear-in-dB attenuation characteristic
Supply voltage: 3.15V to 5.25V
Competitive Advantage
VCTRL range: 0V to 3.6V using 5V supply
+105°C maximum operating temperature
3 × 3 mm 16-VFQFPN package
The F2251 provides extremely low insertion loss and superb IP3,
IP2, Return Loss, and Slope Linearity across the control range.
Comparing to the previous state-of-the-art for silicon VVAs, this
device provides superior performance:
Block Diagram
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Insertion loss at 2000MHz: 1.4dB
Insertion loss at 6000MHz: 2.6dB
Figure 1. Block Diagram
Maximum attenuation slope: 29dB/Volt
Minimum return loss up to 6000MHz: 14dB
Minimum output IP3 at maximum attenuation: 34dBm
Minimum input IP2: 95dBm
Maximum operating temperature: +105°C
Control
Typical Applications
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Base station 2G, 3G, 4G
Portable wireless
RF1
RF2
Repeaters and E911 systems
Digital pre-distortion
Point-to-Point infrastructure
Public safety infrastructure
WIMAX receivers and transmitters
Military systems, JTRS radios
RFID handheld and portable readers
Cable infrastructure
Wireless LAN
Test / ATE equipment
© 2020 Renesas Electronics Corporation
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F2251 Datasheet
Contents
Pin Assignments....................................................................................................................................................................................................4
Pin Descriptions.....................................................................................................................................................................................................4
Absolute Maximum Ratings...................................................................................................................................................................................5
Recommended Operating Conditions ...................................................................................................................................................................6
Electrical Characteristics .......................................................................................................................................................................................7
Thermal Characteristics.........................................................................................................................................................................................8
Typical Operating Conditions (TOCs)....................................................................................................................................................................8
Typical Operating Conditions (VDD = 3.3V)............................................................................................................................................................9
Typical Operating Conditions (VDD = 3.3V)..........................................................................................................................................................10
Typical Operating Conditions (VDD = 3.3V)..........................................................................................................................................................11
Typical Operating Conditions (Frequency = 2GHz, VDD = 3.3V)..........................................................................................................................12
Typical Operating Conditions (Frequency = 2GHz, VDD = 3.3V)..........................................................................................................................13
Typical Operating Conditions (VDD = 3.3V)..........................................................................................................................................................14
Applications Information ......................................................................................................................................................................................15
VCTRL Pin.....................................................................................................................................................................................................15
Bypass Pin..................................................................................................................................................................................................15
RF1 and RF2 Ports.....................................................................................................................................................................................15
Power Supplies...........................................................................................................................................................................................15
Control Pin Interface...................................................................................................................................................................................16
Evaluation Kit/ Applications Circuit.............................................................................................................................................................17
Evaluation Kit BOM .............................................................................................................................................................................................19
Package Outline Drawings ..................................................................................................................................................................................19
Marking Diagram .................................................................................................................................................................................................19
Ordering Information............................................................................................................................................................................................20
Revision History...................................................................................................................................................................................................20
List of Figures
Figure 1. Block Diagram .....................................................................................................................................................................................1
Figure 2. Pin Assignments for 3mm × 3mm 16-VFQFPN-Package – Top View.................................................................................................4
Figure 3. Maximum RF Input Power vs. RF Frequency......................................................................................................................................6
Figure 4. Attenuation ..........................................................................................................................................................................................9
Figure 5. Attenuation Slope................................................................................................................................................................................9
Figure 6. Input Return Loss ................................................................................................................................................................................9
Figure 7. Output Return Loss .............................................................................................................................................................................9
Figure 8. Insertion Phase Δ................................................................................................................................................................................9
Figure 9. Insertion Phase Slope .........................................................................................................................................................................9
Figure 10. Attenuation ........................................................................................................................................................................................10
Figure 11. Attenuation Slope..............................................................................................................................................................................10
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F2251 Datasheet
Figure 12. Input Return Loss ..............................................................................................................................................................................10
Figure 13. Output Return Loss ...........................................................................................................................................................................10
Figure 14. Insertion Phase Δ..............................................................................................................................................................................10
Figure 15. Insertion Phase Slope .......................................................................................................................................................................10
Figure 16. Input Return Loss (vs Temperature)..................................................................................................................................................11
Figure 17. Input Return Loss (vs Frequency) .....................................................................................................................................................11
Figure 18. Output Return Loss (vs Temperature)...............................................................................................................................................11
Figure 19. Output Return Loss (vs Frequency) ..................................................................................................................................................11
Figure 20. Insertion Phase Δ (vs Temperature)..................................................................................................................................................11
Figure 21. Insertion Phase Slope (vs Frequency)...............................................................................................................................................11
Figure 22. Input IP3............................................................................................................................................................................................12
Figure 23. Output IP3 .........................................................................................................................................................................................12
Figure 24. Input IP2............................................................................................................................................................................................12
Figure 25. Output IP2 .........................................................................................................................................................................................12
Figure 26. 2nd Harmonic Intercept Point .............................................................................................................................................................12
Figure 27. 3rd Harmonic Intercept Point..............................................................................................................................................................12
Figure 28. Input IP3............................................................................................................................................................................................13
Figure 29. Output IP3 .........................................................................................................................................................................................13
Figure 30. Input IP2............................................................................................................................................................................................13
Figure 31. Output IP2 .........................................................................................................................................................................................13
Figure 32. 2nd Harmonic Intercept Point .............................................................................................................................................................13
Figure 33. 3rd Harmonic Intercept Point..............................................................................................................................................................13
Figure 34. 1dB Compression..............................................................................................................................................................................14
Figure 35. Phase Noise at 350MHz, 0dBm and Frequency Offset = 1kHz.........................................................................................................14
Figure 36. Min and Max Attenuation...................................................................................................................................................................14
Figure 37. Min and Max Attenuation Slope.........................................................................................................................................................14
Figure 38. Attenuation vs. Frequency.................................................................................................................................................................14
Figure 39. Control Pin Interface Diagram ...........................................................................................................................................................16
Figure 40. Evaluation Kit Applications Circuit Diagram.......................................................................................................................................17
Figure 41. Evaluation Kit Picture / Layout (Top Side).........................................................................................................................................18
Figure 42. Evaluation Kit Picture / Layout (Bottom Side)....................................................................................................................................18
List of Tables
Table 1. Pin Descriptions...................................................................................................................................................................................4
Table 2. Absolute Maximum Ratings.................................................................................................................................................................5
Table 3. Recommended Operating Conditions .................................................................................................................................................6
Table 4. Electrical Characteristics .....................................................................................................................................................................7
Table 5. Thermal Characteristics.......................................................................................................................................................................8
Table 6. Evaluation Kit Bill-of Materials (BOM)................................................................................................................................................19
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F2251 Datasheet
Pin Assignments
Figure 2. Pin Assignments for 3 × 3 mm 16-VFQFPN-Package – Top View
16
15
14
13
1
2
3
GND
NC
12
11
10
GND
NC
Control
RF1
NC
RF2
4
9
NC
5
6
7
8
GND
GND
GND
GND
Pin Descriptions
Table 1.
Pin Descriptions
Pin Number
Name
Description
Ground these pins as close to the device as possible.
1, 5, 6, 7, 8, 12, 13
2, 4, 9, 11
GND
No internal connection. These pins can be left unconnected or connected to ground
(recommended).
NC
RF port 1. Matched to 50 ohms. Must use an external AC coupling capacitor as close to the device
as possible. For low frequency operation, increase the capacitor value to result in a low reactance
at the frequency of interest.
3
RF1
RF port 2. Matched to 50 ohms. Must use an external AC coupling capacitor as close to the device
as possible. For low frequency operation, increase the capacitor value to result in a low reactance
at the frequency of interest.
10
RF2
Attenuator control voltage. Apply a voltage in the range as specified in the Operating Conditions.
14
15
16
VCTRL
VDD
See application section for details about VCTRL
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Power supply input. Bypass to GND with capacitors close as possible to pin.
Bypass to GND with capacitors close as possible to the pin. This pin works with an internal resistor
and thereby adds low pass filtering.
BYPASS
Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses
multiple ground vias to achieve the specified RF performance.
EP
© 2020 Renesas Electronics Corporation
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F2251 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.
Functional operation of the F2251 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 2.
Symbol
Absolute Maximum Ratings
Parameter
Conditions
Minimum
Maximum
Units
VDD
VCTRL
VRF
VDD to GND
-0.3
5.5
V
Minimum
(VDD, 4.0)
VCTRL to GND
VDD = 0V to 5.25V
-0.3
-0.3
V
V
RF1, RF2 to GND
0.3
30
RF1 or RF2 Input Power applied for
24 hours maximum
PMAX24
VDD applied at 2GHz and +85°C
dBm
RF1 or RF2 Continuous Operating
Power
PMAX_OP
See Figure 3
dBm
TJMAX
TST
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature
+150
+150
+260
°C
°C
°C
-65
TLEAD
Soldering, 10s
ESD Voltage–HBM (Per ESD
STM5.1-2007)
VESDHBM
VESDCDM
1000
250
V
V
ESD Voltage–CDM (Per ESD
STM5.3.1-2009)
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F2251 Datasheet
Recommended Operating Conditions
Table 3.
Recommended Operating Conditions
Symbol
fRF
Parameter
Operating Frequency Range
Supply Voltage
Conditions
Minimum
Typical
Maximum
Units
MHz
V
50
3.15
0
6000
VDD
5.25
V
DD = 3.9V to 5.25V
3.6
VCTRL
VCTRL Range
V
VDD = 3.15V to 3.9V
0
VDD-0.3
IDD
ICTRL
Supply Current
0.1 [a]
-1
0.8
2
14
mA
μA
ICTRL Current
PMAX, CW
ZRF1
RF Operating Power [c]
RF1 Port Impedance
RF2 Port Impedance
Operating Temperature Range
See Figure 3
dBm
50
50
Ω
ZRF2
TCASE
Exposed paddle temperature
-40
+105
°C
[a] Items in min/max columns in bold italics are guaranteed by test.
[b] Items in min/max columns that are not bold italics are guaranteed by design characterization.
[c] Refer to Figure 3.
Figure 3. Maximum RF Input Power vs. RF Frequency
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F2251 Datasheet
Electrical Characteristics
Refer to the Evaluation Kit/ Applications Circuit. VDD = +3.3V, TC = +25°C. The specifications in this table apply at RF1 input, FRF = 2000MHz,
minimum attenuation, PIN = 0dBm for small signal parameters, +20dBm for single tone linearity tests, +20dBm per tone for two tone tests, two
tone delta frequency = 50MHz, PCB board traces and connector losses are de-embedded unless otherwise noted. Refer to Typical Operating
Curves for performance over entire frequency band.
Table 4.
Electrical Characteristics
Parameter
Symbol
Conditions
Minimum
Typical
1.4
1.6
2.6
35
Maximum
Units
fRF = 2GHz
fRF = 3GHz
fRF = 6GHz
1.9[a]
Insertion Loss, IL
AMIN
dB
(minimum attenuation)
3.1
Maximum Attenuation
Insertion Phase Δ
AMAX
ΦΔMAX
ΦΔMID
P1dB
34[b]
dB
deg
dBm
At 36dB attenuation relative to insertion loss
At 18dB attenuation relative to insertion loss
28
20
Input 1dB Compression [c]
34.4
16
fRF = 50MHz[d]
fRF = 700MHz
fRF = 2000MHz
fRF = 6000MHz
fRF = 50MHz
Minimum RF1 Return Loss
over Control Voltage
Range
17
S11
S22
dB
17
15
16
Minimum RF2 Return Loss
over Control Voltage
Range
fRF = 700MHz
fRF = 2000MHz
fRF = 6000MHz
15
dB
16
13
Input IP3
IIP3
IIP3ATTEN
OIP3MIN
IIP2
67
Input IP3 over Attenuation
Minimum Output IP3
Input IP2
All attenuation settings
Maximum attenuation
PIN + IM2dBC, IM2 term is F1+F2
All attenuation settings
PIN + H2dBc
44
47
dBm
34
105
95
dBm
dBm
dBm
dBm
Minimum Input IP2
Input IH2
IIP2MIN
HD2
107
70
Input IH3
HD3
PIN + (H3dBc/2)
Any 1dB step in the 0dB to 33dB control range
50% VCTRL to RF settled to within ± 0.1dB
Settling Time
TSETTL0.1dB
15
µsec
[a] Items in minimum/maximum columns in bold italics are guaranteed by test.
[b] Items in minimum/maximum columns that are not bold/italics are guaranteed by design characterization.
[c] The input 1dB compression point is a linearity figure of merit. Refer to Absolute Maximum Ratings section along with Figure 3 for the maximum
RF input power vs. RF frequency.
[d] Set blocking capacitors C7 and C8 to 0.01µF to achieve best return loss performance at 50MHz.
© 2020 Renesas Electronics Corporation
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F2251 Datasheet
Thermal Characteristics
Table 5.
Thermal Characteristics
Symbol
Parameter
Value
80.6
Units
°C/W
°C/W
θJA
θJC
Theta JA. Junction to ambient.
Theta JC. Junction to case (case is defined as the exposed paddle)
Moisture Sensitivity Rating (per J-STD-020)
5.1
MSL 1
Typical Operating Conditions (TOCs)
Unless otherwise noted:
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VDD = +3.3V or +5.0V
TC = +25°C
PIN = 0dBm for all small signal tests
PIN = +20dBm for single tone linearity tests (RF1 port driven)
PIN = +20dBm/tone for two tone linearity tests (RF1 port driven)
Two tone frequency spacing = 50MHz
RF trace and connector losses are de-embedded for S-parameters
© 2020 Renesas Electronics Corporation
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F2251 Datasheet
Typical Operating Conditions (VDD = 3.3V)
Figure 4.
Attenuation
Figure 5.
Attenuation Slope
Figure 6.
Input Return Loss
Figure 7.
Output Return Loss
Figure 9.
Insertion Phase Slope
Figure 8.
Insertion Phase Δ
© 2020 Renesas Electronics Corporation
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February 18, 2020
F2251 Datasheet
Typical Operating Conditions (VDD = 3.3V)
Figure 10. Attenuation
Figure 11. Attenuation Slope
Figure 12. Input Return Loss
Figure 13. Output Return Loss
Figure 14. Insertion Phase Δ
Figure 15. Insertion Phase Slope
© 2020 Renesas Electronics Corporation
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F2251 Datasheet
Typical Operating Conditions (VDD = 3.3V)
Figure 16. Input Return Loss (vs Temperature)
Figure 17. Input Return Loss (vs Frequency)
Figure 18. Output Return Loss (vs Temperature)
Figure 19. Output Return Loss (vs Frequency)
Figure 20. Insertion Phase Δ (vs Temperature)
Figure 21. Insertion Phase Slope (vs Frequency)
© 2020 Renesas Electronics Corporation
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F2251 Datasheet
Typical Operating Conditions (Frequency = 2GHz, VDD = 3.3V)
Figure 22. Input IP3
Figure 23. Output IP3
Figure 24. Input IP2
Figure 25. Output IP2
nd
rd
Figure 26. 2 Harmonic Intercept Point
Figure 27. 3 Harmonic Intercept Point
© 2020 Renesas Electronics Corporation
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February 18, 2020
F2251 Datasheet
Typical Operating Conditions (Frequency = 2GHz, VDD = 3.3V)
Figure 28. Input IP3
Figure 29. Output IP3
Figure 30. Input IP2
Figure 31. Output IP2
nd
rd
Figure 32. 2 Harmonic Intercept Point
Figure 33. 3 Harmonic Intercept Point
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F2251 Datasheet
Typical Operating Conditions (VDD = 3.3V)
Figure 34. 1dB Compression
Figure 35. Phase Noise at 350MHz, 0dBm and
Frequency Offset = 1kHz
Figure 36. Min and Max Attenuation
Figure 37. Min and Max Attenuation Slope
Figure 38. Attenuation vs. Frequency
© 2020 Renesas Electronics Corporation
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February 18, 2020
F2251 Datasheet
Applications Information
VCTRL Pin
The VCTRL pin controls the attenuation of the F2251. The VCTRL pin has an on-chip pull-up ESD diode so VDD should be applied before VCTRL is
applied. If this sequencing is not possible, then resistor R2 should be set for 1kΩ to limit the current into the VCTRL pin.
Bypass Pin
Bypass to GND with capacitors close as possible to the pin. This pin works with an internal resistor and thereby adds low pass filtering. For
more information, see Figure 40.
RF1 and RF2 Ports
The F2251 is a bi-directional device thus allowing RF1 or RF2 to be used as the RF input. As displayed in the Typical Operating Conditions
curves, RF1 shows some enhanced linearity performance and therefore should be used as the RF input, if possible, for best results. This F2251
has been designed to accept high RF input power levels, therefore VDD must be applied prior to the application of RF power to ensure reliability.
DC blocking capacitors are required on the RF pins and should be set to a value that results in a low reactance over the frequency range of
interest.
Power Supplies
The supply pin should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade noise figure and
fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than
1V/20µs. In addition, all control pins should remain at 0V (±0.3V) while the supply voltage ramps or while it returns to zero.
© 2020 Renesas Electronics Corporation
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F2251 Datasheet
Control Pin Interface
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of control pin 14 is recommended as shown below.
Figure 39. Control Pin Interface Diagram
5kOhm
VCTRL
2pF
100nF
GND
16
15
14
13
1
2
3
GND
NC
12
11
10
GND
NC
Control
RF1
NC
RF2
4
9
NC
5
6
7
8
GND
GND
GND
GND
© 2020 Renesas Electronics Corporation
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February 18, 2020
F2251 Datasheet
Evaluation Kit/ Applications Circuit
Figure 40. Evaluation Kit Applications Circuit Diagram
© 2020 Renesas Electronics Corporation
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February 18, 2020
F2251 Datasheet
Figure 41. Evaluation Kit Picture / Layout (Top Side)
Figure 42. Evaluation Kit Picture / Layout (Bottom Side)
© 2020 Renesas Electronics Corporation
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February 18, 2020
F2251 Datasheet
Evaluation Kit BOM
Table 6.
Evaluation Kit Bill-of Materials (BOM)
Part Reference Quantity
Description
10nF ±5%, 50V, X7R Ceramic Capacitors (0603)
1000pF ±5%, 50V, C0G Ceramic Capacitors (0402)
0.1uF ±10%, 16V, X7R Ceramic Capacitors (0402)
0Ω Resistors (0402)
Manufacturer Part Number
GRM188R71H103J
GRM1555C1H102J
GRM155R71C104K
ERJ-2GE0R00X
Manufacturer
Murata
C1, C4
C2, C3, C7, C8
C6
2
4
1
2
2
2
4
1
Murata
Murata
R1, R2
Panasonic
Panasonic
R3, R4
100kΩ ±1%, 1/10W, Resistor (0402)
DNP
ERJ-2RKF1003X
R5, C5
J1, J2, J3, J4
Edge Launch SMA (0.375 inch pitch ground tabs)
Printed Circuit Board
142-0701-851
Emerson Johnson
IDT (Renesas)
F225x Rev (02)
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
https://www.idt.com/document/psc/16-vfqfpn-package-outline-drawing-30-x-30-x-09-mm-05-mm-170-x-170-mm-epad-nlnlg16p2
Marking Diagram
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Line 1 is the last 3 characters of the ASM lot number
Line 2:
• “YWW” is the last digit of the year and week that the part was assembled.
• “$” denotes the mark code.
XXX
YWW$
F2251
.
Line 3 is the truncated part number.
© 2020 Renesas Electronics Corporation
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F2251 Datasheet
Ordering Information
Orderable Part Number
Description and Package
MSL Rating
Carrier Type
Tray
Temperature
-40°C to +105°C
-40°C to +105°C
F2251NLGI
3.0 × 3.0 × 0.9 mm 16-VFQFPN
3.0 × 3.0 × 0.9 mm 16-VFQFPN
1
F2251NLGI8
1
Reel
F2251EVB
Evaluation Board
Revision History
Revision Date
February 18, 2020
February 14, 2020
Description of Change
Replotting Insertion phase figures.
Initial release.
© 2020 Renesas Electronics Corporation
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February 18, 2020
16-VFQFPN Package Outline Drawing
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad
NL/NLG16P2, PSC-4169-02, Rev 05, Page 1
16-VFQFPN Package Outline Drawing
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad
NL/NLG16P2, PSC-4169-02, Rev 05, Page 2
Package Revision History
Description
Rev 04 Remove Bookmak at Pdf Format & Update Thickness Tolerance
Change QFN to VFQFPN
Date Created Rev No.
Oct 25, 2017
Jan 18, 2018
Rev 05
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