F2913NLGK [RENESAS]
High Isolation SP2T RF Switch 50MHz to 6000MHz;
| 型号： | F2913NLGK |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | High Isolation SP2T RF Switch 50MHz to 6000MHz |
| 文件： | 总20页 (文件大小：1249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Isolation SP2T RF Switch
50MHz to 6000MHz
F2913
Datasheet
Description
Features
.
.
Low insertion loss: 0.79dB at 2GHz
The F2913 is a high isolation, low insertion loss, 50Ω SP2T
absorptive RF switch designed for a multitude of wireless and RF
applications. This device covers a broad frequency range of
50MHz to 6000MHz. In addition to providing low insertion loss,
the F2913 also delivers high linearity and high isolation
performance while providing a 50Ω termination at all RF ports.
High isolation:
.
.
.
71dB at 1GHz
65dB at 2GHz
58dB at 4GHz
.
.
.
.
.
High IIP3: +65dBm at 2.6GHz
Supply voltage: +2.7V to +5.5V
1.8V and 3.3V compatible control logic
Operating temperature: -40°C to +110°C
4 × 4 mm 20-VFQFPN package
The F2913 uses a single positive supply voltage of +2.7V to
+5.5V and supports three states using either +1.8V or +3.3V
control logic.
Competitive Advantage
.
.
.
.
.
.
Low insertion loss
High isolation
Excellent linearity
Fast switching time
High termination power handling
Extended temperature range
Block Diagram
Figure 1. Block Diagram
VDD
C1
C2
RF1
RF2
Typical Applications
.
.
.
.
.
.
.
.
.
.
Base Station 2G, 3G, 4G, 5G
Portable Wireless
50Ω
50Ω
RFC
Repeaters and E911 Systems
Digital Pre-Distortion
50Ω
Point-to-Point Infrastructure
Public Safety Infrastructure
WIMAX Receivers and Transmitters
Military Systems, JTRS Radios
RFID Handheld and Portable Readers
Test / ATE Equipment
1
January 31, 2019
Pin Assignments
Figure 2. Pin Assignments for 4mm x 4mm x 0.95mm 20-QFN – Top View
VDD GND GND C1 C2
20 19 18 17 16
1
2
3
4
5
15
14
13
12
11
GND
GND
RF1
GND
GND
RF2
F2913
GND
GND
GND
GND
EP
6
7
8
9
10
GND GND RFC GND GND
Pin Descriptions
Table 1.
Pin Descriptions
Pin
Name
Function
This pin is internally connected to the exposed paddle. Connect this pin to ground as close as possible to
the pin.
1, 15, 18
GND
2, 4, 5, 6, 7,
9, 10, 11, 12,
14, 19
GND
Connect this pin directly to ground as close as possible to the pin with thru vias.
3
RF1
RFC
RF2
C2
RF1 Port. If this pin is not 0V DC, then an external coupling capacitor must be used.
RF Common Port. If this pin is not 0V DC, then an external coupling capacitor must be used.
RF2 Port. If this pin is not 0V DC, then an external coupling capacitor must be used.
Logic control pin. See Table 7 for proper logic setting.
8
13
16
17
20
C1
Logic control pin. See Table 7 for proper logic setting.
VDD
Power supply. Bypass to GND with capacitors shown in the Figure 30 as close as possible to the pin.
Exposed Pad. This is internally connected to GND. Solder this exposed pad to a PCB pad that uses
multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple
ground vias are also required to achieve the specified RF performance.
EP
2
January 31, 2019
Absolute Maximum Ratings
Stresses beyond those listed below may cause permanent damage to the device. Functional operation of the device at these or any other
conditions beyond those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table 2.
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
VDD to GND
VDD
-0.5
+6.0
V
Lower of
(VDD + 0.3, 3.9)
C1, C2 to GND
VLOGIC
-0.3
-0.3
V
V
RF1, RF2, RFC to GND
VRF
0.3
33
Maximum Input CW Power,
ZS = ZL = 50Ω, TEP = 25°C,
VDD = 5.5V (any port) [a]
Insertion loss states
Terminated states
Insertion loss states
Terminated states
PABSCW
dBm
dBm
PABSCW_TERM
PABSPK
27
36
30
Maximum Input Peak Power,
ZS = ZL = 50Ω, TEP = 25°C,
VDD = 5.5V (any port) [a, b]
PABSPK_TERM
Junction Temperature
TJMAX
TST
140
150
260
°C
°C
°C
Storage Temperature Range
Lead Temperature (soldering, 10s)
-65
TLEAD
Electrostatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
2500
(Class 2)
VESDHBM
VESDCDM
V
V
Electrostatic Discharge – CDM
(JEDEC 22-C101F)
1000
(Class C2)
a. TEP = Temperature of the exposed paddle.
b. 5% duty cycle of a 4.6ms period.
3
January 31, 2019
Recommended Operating Conditions
Table 3.
Recommended Operating Conditions
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Supply Voltage
VDD
TEP
fRF
2.7
-40
50
3.3
5.5
+110
V
°C
Operating Temperature Range
RF Frequency Range
Exposed Paddle
ZS = ZL = 50Ω
6000
MHz
dBm
Ω
Maximum Operating Input Power
Port Impedance (RFC, RF1, RF2)
PMAX
ZRF
See Figure 3
50
Figure 3. Maximum RF Input Operating Power vs. RF Frequency (ZS = ZL = 50Ω)
4
January 31, 2019
Electrical Characteristics
Table 4.
Electrical Characteristics
See the F2913 Typical Application Circuit. Specifications apply when operated with VDD = +3.3V, TEP = +25°C, ZS = ZL = 50Ω, RF signals
applied at RF1 or RF2 and measured at RFC, and Evaluation Board trace and connector losses are de-embedded, unless otherwise noted.
Parameter
Logic Input High
Symbol
Condition
Min
Typ
Max
Units
Lower of
(VDD, 3.6)
VIH
C1, C2 pins
C1, C2 pins
1.17 [b]
V
Logic Input Low
Logic Current
VIL
IIH, IIL
IDD
-0.3
V
0.6
+1
-1 [a]
µA
µA
DC Current (VDD)
90
0.77
0.79
0.79
0.88
1.03
1.15
1.25
79
170
0.97
1.00
1.00
1.10
1.40
1.50
1.65
50MHz ≤ fRF ≤ 400MHz
400MHz < fRF ≤ 1GHz [c]
1GHz < fRF ≤ 2GHz
2GHz < fRF ≤ 3GHz
3GHz < fRF ≤ 4GHz
4GHz < fRF ≤ 5GHz
5GHz < fRF ≤ 6GHz
50MHz ≤ fRF ≤ 400MHz
400MHz < fRF ≤ 1GHz
1GHz < fRF ≤ 2GHz
2GHz < fRF ≤ 3GHz
3GHz < fRF ≤ 4GHz
4GHz < fRF ≤ 5GHz
5GHz < fRF ≤ 6GHz
50MHz ≤ fRF ≤ 400MHz
400MHz < fRF ≤ 1GHz
1GHz < fRF ≤ 2GHz
2GHz < fRF ≤ 3GHz
3GHz < fRF ≤ 4GHz
4GHz < fRF ≤ 5GHz
5GHz < fRF ≤ 6GHz
50MHz ≤ fRF ≤ 4GHz
4GHz < fRF ≤ 6GHz
50MHz ≤ fRF ≤ 4GHz
4GHz < fRF ≤ 6GHz
Insertion Loss
RF1 to RFC or RF2 to RFC
IL
dB
dB
dB
74
66
60
57
53
50
46
80
75
67
62
57
53
51
71
65
Isolation
(RFC to RF1, RF2)
(one path on)
ISO1
62
58
54
51
85
80
72
Isolation
(RF1 to RF2, RF2 to RF1)
(one path on)
ISO2
67
62
58
56
Return Loss RF1, RF2 [d]
Insertion Loss State
20
RL1
RL2
dB
dB
18.7
18.0
15.2
Return Loss RFC [d]
Insertion Loss State
a. Items in min/max columns in bold italics are guaranteed by test.
b. Items in min/max columns that are not bold italics are guaranteed by design characterization.
c. Maximum spec guaranteed by test at 1GHz and by design characterization over the whole frequency range.
d. Return loss includes mismatch effects of Evaluation Kit PCB and RF connectors.
5
January 31, 2019
Electrical Characteristics
Table 5.
Electrical Characteristics
See F2913 Typical Application Circuit. Specifications apply when operated with VDD = +3.3V, TEP = +25°C, ZS = ZL = 50Ω, RF signals applied
at RF1 or RF2 and measured at RFC, Evaluation Board trace and connector losses are de-embedded, unless otherwise noted.
Parameter
Symbol
Condition
50MHz ≤ fRF ≤ 4GHz
Min
Typ
Max
Units
Return Loss RF1, RF2 [c]
Terminated State, All Off State
20.3
19.3
17.5
15.3
RL3
dB
4GHz < fRF ≤ 6GHz
50MHz ≤ fRF ≤ 4GHz
4GHz < fRF ≤ 6GHz
Return Loss RFC [c]
All Off State
RL4
IIP2
dB
f1 = 2.55GHz
f2 = 2.65GHz
PIN = +20dBm/tone
Measure 5.2GHz product
Input IP2
115
65
dBm
(RF1, RF2 to RFC)
f1 = 2.55GHz
f2 = 2.65GHz
PIN = +13dBm/tone
Measure 2.75GHz product
Input IP3
IIP3
60 [b]
dBm
(RF1, RF2 to RFC)
fRF = 50MHz
35
35
34
34
37
37
36
36
fRF = 100MHz
fRF = 2400MHz
fRF = 6000MHz
Input 1dB Compression [d]
IP1dB
PSPUR
dBm
dBm
Spurious Output
(No RF Applied) [e]
All unused ports terminated
RBW = 100Hz
-127
-120
0.2
Insertion Loss Flatness
Group Delay
ILFLAT
GD
Any 400MHz range
0.1
0.05
155
142
234
205
dB
ns
50% control to 90% RF
50% control to 10% RF
50% control to 99% RF
50% control to 1% RF
230
200
300
265
25
Switching Time [f]
SWTIME
ns
Switching Rate
SWRATE
kHz
a. Items in min/max columns in bold italics are guaranteed by test.
b. Items in min/max columns that are not bold italics are guaranteed by design characterization.
c. Return loss includes mismatch effects of Evaluation Kit PCB and RF connectors.
d. The input 1 dB compression point is a linearity figure of merit. Refer to Figure 3 for the maximum RF operating input
power levels.
e. Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2MHz.
f. Measured at fRF = 1GHz.
6
January 31, 2019
Thermal Characteristics
Table 6.
Package Thermal Characteristics
Parameter
Symbol
Value
Units
Junction to Ambient Thermal Resistance
θJA
60.2
°C/W
Junction to Case Thermal Resistance
(Case is defined as the exposed paddle)
θJC_BOT
9.5
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL1
Typical Operating Conditions (TOCs)
Unless otherwise noted:
.
.
.
.
.
.
.
.
V
T
DD = +3.3V
EP = 25°C. All temperatures are referenced to the exposed paddle.
ZS = ZL = 50Ω
RF = 1GHz
f
Small signal tests done at 0dBm input power.
+13dBm per tone for IIP3 measurements.
RF1 or RF2 are the driven ports.
Evaluation Kit traces and connector losses are de-embedded for the insertion loss and isolation plots. All other plots include the loss and
effects of the PCB.
7
January 31, 2019
Typical Performance Characteristics (1)
Figure 4. RFC to RF1 Insertion Loss vs. Freq.
Figure 5. RFC to RF2 Insertion Loss vs. Freq.
over Temperature and Voltage
over Temperature and Voltage
0
0
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
-2.5
-2.5
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Frequency (GHz)
Figure 6. RFC to RF1 Isolation vs. Freq. over
Figure 7. RFC to RF2 Isolation vs. Freq. over
Temp. and Voltage (RF2 On State]
Temp. and Voltage (RF1 On State]
0
0
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Frequency (GHz)
Figure 8. RF1 to RF2 Isolation vs. Freq. over
Figure 9. RF2 to RF1 Isolation vs. Freq. over
Temp. and Voltage (RF1 On State)
Temp. and Voltage (RF2 On State)
0
0
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Frequency (GHz)
8
January 31, 2019
Typical Performance Characteristics (2)
Figure 10. RFC to RF1 Isolation vs. Freq. over
Figure 11. RFC to RF2 Isolation vs. Freq. over
Temp. and Voltage (All Off State)
Temp. and Voltage (All Off State)
0
0
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Frequency (GHz)
Figure 12. RF1 to RF2 Isolation vs. Freq. over
Figure 13. Evaluation Board Thru Line
Temp. and Voltage (All Off State)
Loss over Temperature
0
0
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
-20
-40
-0.2
-0.4
-0.6
-0.8
-60
-80
-100
-120
-40C
25C
110C
-1
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Frequency (GHz)
Figure 14. Evaluation Board Thru Line Match
over Temperature
0
-40C
25C
110C
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
9
January 31, 2019
Typical Performance Characteristics (3)
Figure 15. RF1 Return Loss vs. Frequency over
Figure 16. RF1 Return Loss vs. Frequency over
Temp. and Voltage (RF1 On State)
Temp. and Voltage (RF2 On State)
0
0
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
-5
-10
-15
-20
-25
-30
-35
-40
-5
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Frequency (GHz)
Figure 17. RF2 Return Loss vs. Frequency over
Figure 18. RF2 Return Loss vs. Frequency over
Temp. and Voltage (RF2 On State)
Temp. and Voltage (RF1 On State)
0
0
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
-5
-10
-15
-20
-25
-30
-35
-40
-5
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Frequency (GHz)
Figure 19. RFC Return Loss vs. Frequency over
Figure 20. RFC Return Loss vs. Frequency over
Temp. and Voltage (RF1 On State)
Temp. and Voltage (RF2 On State)
0
0
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
-5
-10
-15
-20
-25
-30
-35
-40
-5
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Frequency (GHz)
10
January 31, 2019
Typical Performance Characteristics (4)
Figure 21. RF1 Return Loss vs. Frequency over
Figure 22. RF2 Return Loss vs. Frequency over
Temp. and Voltage (All Off State)
Temp. and Voltage (All Off State)
0
0
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
-5
-10
-15
-20
-25
-30
-35
-40
-5
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Frequency (GHz)
Figure 24. RF1 Input IP3 vs. Frequency over
Temp. and Voltage (RF1 On State)
Figure 23. RFC Return Loss vs. Frequency over
Temp. and Voltage (All Off State)
0
70
65
60
55
50
45
40
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
-5
-10
-15
-20
-25
-30
-35
-40
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Frequency (GHz)
Figure 25. RF2 Input IP3 vs. Frequency over
Figure 26. Input P1dB vs. Frequency over Temp.
Temp. and Voltage (RF2 On State)
and Voltage (On States)
70
39
38
37
36
35
34
65
60
55
50
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
2.7V, -40C
2.7V, 25C
2.7V, 110C
3.3V, -40C
3.3V, 25C
3.3V, 110C
5.5V, -40C
5.5V, 25C
5.5V, 110C
45
40
33
32
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Frequency (GHz)
Frequency (GHz)
11
January 31, 2019
Control Mode
Table 7.
Switch Control Truth Table
C1
C2
RFC – RF1
RFC – RF2
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
OFF
OFF
ON
OFF
ON
OFF
N/A
N/A
Application Information
Default Start-up
The C1 and C2 control pins include no internal pull-down resistors to logic LOW or pull-up resistors to logic HIGH.
Power Supplies
A common VDD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to
minimize noise and fast transients. Supply noise can degrade the noise figure, and fast transients can trigger ESD clamps and cause them to
fail. Supply voltage change or transients should have a slew rate slower than 1V / 20µs. In addition, all control pins should remain at 0V
(± 0.3V) while the supply voltage ramps up or while it returns to zero.
Control Pin Interface
If a clean control signal for pins 16 and 17 cannot be guaranteed due to overshoot, undershoot, or ringing, etc., the following circuit at the
input of the control pins is recommended.
Figure 27. Control Pin Signal Integrity Improvement Circuit
5 kΩ
C1
2 pF
V DD GND GND
20 19 18 17 16
5 kΩ
1
2
3
4
5
15
14
13
12
11
GND
GND
RF1
GND
GND
RF2
C2
2 pF
F2913
GND
GND
GND
GND
EP
6
7
8
9
10
GND GND RFC GND GND
12
January 31, 2019
Evaluation Kit Picture
Figure 28. Top View
Figure 29. Bottom View
13
January 31, 2019
Evaluation Kit / Applications Circuit
Figure 30. Electrical Schematic
Table 8.
Bill of Material (BOM)
Part Reference
C1
QTY
Description
Manufacturer Part #
Manufacturer
1
0
3
5
1
1
1
0.1µF ±10%, 16V X7R Ceramic Capacitor (0402)
Not Installed (0402)
GRM155R71C104KA88D
Murata
C2 – C9
R1 – R3
J1 – J5
J6
0Ω ±1%, 1/10W, Resistor (0402)
SMA Edge Mount
ERJ-2RKF1000X
142-0761-881
961216-6404-AR
F2913NLGK
Panasonic
Cinch Connectivity
Amphenol FCI
IDT
8x2 Vertical Pin Strip Header
SP2T Switch 4mm x 4mm QFN
Printed Circuit Board
U1
F2913 PCB
IDT
14
January 31, 2019
Evaluation Kit (EVKit) Operation
External Supply Setup
1. Set up a VDD power supply in the range of +2.7V to +5.5V with the power supply output disabled.
2. Connect the disabled VDD supply connection to J6 pins 1, 3, 13, or 15 and GND to J6 pins 2, 4, 6, 8, 10, 12, 14, or 16.
Logic Control Setup
1. With the logic control lines disabled, set the HIGH and LOW logic levels to satisfy the levels stated in the electrical specifications table.
2. Connect the disabled logic control to J6 VCTRL1 (pins 5 or 7) and VCTRL2 (pins 9 or 11).
3. See Table 7 for the logic truth table. Note that C1 in the table corresponds to VCTRL1 on the EVKIT and C2 corresponds to VCTRL2.
Turn On Procedure
1. Set up the supplies and EVKIT as noted in the External Supply Setup and Logic Control Setup sections above.
2. Enable the VDD supply.
3. Enable the logic control signals.
4. Set the logic settings to achieve the desired Table 7 configuration. Note that external control logic should not be applied without VDD
being present.
Turn Off Procedure
1. Set the logic control pins to 0V.
2. Disable the VDD supply.
15
January 31, 2019
Package Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/document/psc/20-vfqfpn-package-outline-drawing-40-x-40-x-095-mm-body-05mm-pitch-epad-20-x-20-mm-nlg20t1
Marking Diagram
Lines 1 and 2 – Part number
Line 3 “ZE” – Die version
Line 3 “705” – Production period, last digit of year plus workweek
Line 3 “AHG” – Production process
IDTF29
13NLGK
ZE705AHG
Ordering Information
Orderable Part Number
Package
MSL Rating
Shipping Packaging
Temperature
F2913NLGK
F2913NLGK8
F2913EVBI
4 × 4 × 0.95 mm 20-VFQFPN
4 × 4 × 0.95 mm 20-VFQFPN
MSL1
MSL1
Cut Tape
Reel
-40°C to +110°C
-40°C to +110°C
Evaluation Board
16
January 31, 2019
Revision History
Revision Date
Description of Change
Updated package for correct drawing number
January 31, 2019
September 29, 2017
Initial release
20-VFQFPN, Package Outline Drawing
4.0 x 4.0 x 0.95 mm Body, 0.5mm Pitch, Epad 2.0 x 2.0 mm
NLG20T1, PSC-4170-03, Rev 02, Page 1
ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ
20-VFQFPN, Package Outline Drawing
4.0 x 4.0 x 0.95 mm Body, 0.5mm Pitch, Epad 2.0 x 2.0 mm
NLG20T1, PSC-4170-03, Rev 02, Page 2
Package Revision History
Description
Rev 02 New Format, Add T1,Recalculate Land Pattern
Rev 01 Change Max Dimension "A"
Date Created Rev No.
March 2, 2018
Jan 23, 2017
ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ
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