F2955EVBK [RENESAS]
High Reliability SP5T RF Switch 50MHz to 8000MHz;
| 型号： | F2955EVBK |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | High Reliability SP5T RF Switch 50MHz to 8000MHz |
| 文件： | 总22页 (文件大小：1760K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Reliability SP5T RF Switch
50MHz to 8000MHz
F2955
Datasheet
Description
Features
The F2955 is a high reliability, low insertion loss, 50Ω SP5T
absorptive RF switch designed for a multitude of RF applications,
including wireless communications. This device covers a broad
frequency range from 50MHz to 8000MHz. In addition to providing
low insertion loss, the F2955 also delivers excellent linearity and
isolation performance while providing a 50Ω termination to the
unused RF input ports. The F2955 also includes a patent-pending
constant impedance (K|Z|™) feature. K|Z| improves system hot
switching ruggedness, minimizes LO pulling in VCOs, and reduces
phase and amplitude variations in distribution networks. It is also
ideal for dynamic switching/selection between two or more
amplifiers while avoiding damage to upstream/downstream
sensitive devices, such as power amplifiers (PAs) and analog-to-
digital converters (ADCs).
.
.
.
.
Five symmetric, absorptive RF ports
High isolation: 49dB at 4000MHz
Low insertion loss: 1.1dB at 4000MHz
High linearity:
• IIP2 of 114dBm at 2000MHz
• IIP3 of 60.5dBm at 4000MHz
High operating power handling:
• 33dBm CW on selected RF port
• 27dBm on terminated ports
Single 2.7V to 5.5V supply voltage
External negative supply option
3.3V and 1.8V compatible control logic
Operating temperature: -40°C to +105°C
4 x 4 mm 24-QFN package
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.
.
.
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The F2955 uses a single positive supply voltage supporting three
logic control pins using either 3.3V or 1.8V control logic.
Connecting a negative voltage to pin 20 disables the internal
negative voltage generator and becomes the negative supply.
Pin compatible with competitors
Block Diagram
Competitive Advantage
The F2955 provides constant impedance in all RF ports during
transitions, improving a system’s hot-switching ruggedness. The
device also supports high-power handling and high isolation,
particularly important for DPD receiver use.
Figure 1. Block Diagram
RFC
.
.
.
.
.
Constant impedance K|Z| during switching transition
RFX to RFC isolation = 49dB at 4GHz
Insertion loss = 1.1dB at 4GHz
K|Z|
RF4
RF1
IIP3: +60.5dBm at 4GHz
Extended temperature: -40°C to +105°C
50Ω
50Ω
RF3
RF2
Typical Applications
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Base Station 2G, 3G, 4G
Portable Wireless
50Ω
50Ω
Control
Repeaters and E911 Systems
Digital Pre-distortion
Point-to-Point Infrastructure
Public Safety Infrastructure
Military Systems, JTRS Radios
Cable Infrastructure
VDD VSSEXT
V1 V2 V3
Test / ATE Equipment
1
October 11, 2018
Pin Assignments
Figure 2. Pin Assignments for 4 x 4 x 0.75 mm 24-QFN – Top View
1
18
17
16
15
14
13
GND
V2
Control
Circuit
E.P.
2
RF5
V1
50Ω
50Ω
3
4
5
6
VDD
GND
RF1
GND
GND
RF4
50Ω
50Ω
50Ω
GND
GND
Pin Descriptions
Table 1.
Pin Descriptions
Number
Name
Description
Ground these pins as close to the device as possible.
1, 3, 4, 6, 7, 9, 10, 12,
13, 15, 21, 23, 24
GND
2
5
RF5
RF4
RF3
RF2
RF1
RF5 Port. Matched to 50Ω. If this pin is not 0V DC, then an external coupling capacitor must be used.
RF5 Port. Matched to 50Ω. If this pin is not 0V DC, then an external coupling capacitor must be used.
RF5 Port. Matched to 50Ω. If this pin is not 0V DC, then an external coupling capacitor must be used.
RF5 Port. Matched to 50Ω. If this pin is not 0V DC, then an external coupling capacitor must be used.
RF5 Port. Matched to 50Ω. If this pin is not 0V DC, then an external coupling capacitor must be used.
8
11
14
Power Supply. Bypass to GND with capacitors as shown in the “Typical Application Circuit” (Figure 39) as
close as possible to the pin.
16
VDD
17
18
19
V1
V2
V3
Control pin to set the switch state. See Table 8.
Control pin to set the switch state. See Table 8.
Control pin to set the switch state. See Table 8.
External VSS negative voltage control. Connect to ground to enable on-chip negative voltage generator.
To bypass and disable on chip generator connect this pin to an external VSS.
20
22
VSSEXT
RFC
RF Common Port. Matched to 50Ω when one of the 5 RF ports is selected. If this pin is not 0V DC, then
an external coupling capacitor must be used.
Exposed Paddle. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple
ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground
vias are also required to achieve the specified RF performance.
EPAD
2
October 11, 2018
Absolute Maximum Ratings
Stresses beyond those listed below may cause permanent damage to the device. Functional operation of the device at these or any other
conditions beyond those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Table 2.
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
VDD to GND
VDD
-0.3
+5.5
V
Lower of
(3.6,VDD+0.3)
V1, V2, V3 to GND
VCNTL
-0.3
V
RF1, RF2, RF3, RF4, RF5, RFC to GND
VSSEXT to GND
VRF
-0.3
-4.0
+0.3
+0.3
V
V
VSSEXT
Input Power for Any One Selected RF Through Port
(VDD applied at 2GHz and TEPAD = +85°C)
PMAXTHRU
PMAXTERM
PMAXCOM
37
30
33
dBm
dBm
dBm
Input Power for Any One Selected RF Terminated Port
(VDD applied at 2GHz and TEPAD = +85°C)
Input Power for RFC When in the All Off State
(VDD applied at 2GHz and TEPAD = +85°C)
Continuous Power Dissipation[a] (TEPAD = +95°C Max)
Maximum Junction Temperature
PCONT
TJMAX
TST
3
W
°C
°C
°C
+125
+150
+260
Storage Temperature Range
-65
Lead Temperature (soldering, 10s)
TLEAD
1500
(Class 1C)
ESD Voltage– HBM (Per JESD22-A114)
VESDHBM
V
V
10001000
(Class C3)
ESD Voltage – CDM (Per JESD22-C101)
VESDCDM
[a] TEPAD = Temperature of the exposed paddle
3
October 11, 2018
Recommended Operating Conditions
Table 3.
Recommended Operating Conditions
Parameter
Symbol
Condition
Minimum Typical Maximum Units
Pin 20 grounded
2.7
2.7
-3.6
-40
50
5.25
5.25
-3.2
+105
8000
33
VDD
Power Supply Voltages
Pin 20 driven with VSSEXT
Negative supply [a]
V
VSSEXT
TEPAD
fRF
-3.4
Operating Temperature Range
RF Frequency Range
Exposed paddle
°C
MHz
Selected ports
RF Continuous Input
CW Power [b]
PRF
dBm
dBm
Ω
Terminated ports [c]
27
Switch to RF1 through RF5
27
RFC as the
input
Switched into or out of all off
state
24
RF Continuous Input
CW Power for
PRFSW
[c]
Switched to RFC or into term[c]
27
27
Hot RF Switching
RF1 through
RF5 as the
inputs
Switch into or out of all off
conditions
RF1 through 5 Port Impedance
RFC Port Impedance
ZRFx
ZRFC
50
50
[a] For normal operation, connect VSSEXT (pin 20) = 0V to GND to enable the internal negative voltage generator. If VSSEXT is applied to pin 20,
the on-chip negative voltage generator is disabled, completely eliminating any generator spurious responses.
[b] Levels based on TEPAD ≤ 85°C. See Figure 3 for the power de-rating curve for higher case temperatures.
[c] In any of the insertion loss modes or when switching into any insertion loss mode, any 3 of the 4 remaining terminated port paths can be each
exposed to the maximum stated power level during continuous or hot switching operation.
Figure 3. Maximum CW RF Input Operating Power vs. RF Frequency
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October 11, 2018
Electrical Characteristics
Table 4.
Electrical Characteristics
Typical application circuit (Figure 39), Normal Mode (VDD = 3.3V, VSSEXT = 0V) or Bypass Mode (VDD = 3.3V, VSSEXT = -3.3V), TEPAD = +25°C,
fRF = 2000MHz, input power = 0dBm, ZS = ZL = 50Ω, RFX = one of the five input ports, and PCB board trace and connector losses are de-
embedded unless otherwise noted.
Parameter
Logic Input High
Symbol
Condition
Minimum
Typical
Maximum
Units
Lower of
(3.6, VDD)
VIH
1.1 [a]
V
Logic Input Low
Logic Current
VIL
-0.3
-2
0.6
+2
V
IIH, IIL
For each control pin
µA
Normal Mode 3.3V or 1.8V logic
Bypass Mode 3.3V or 1.8V logic
VSSEXT = -3.3V
290
270
-46
0.93
1.1
360
340
-60
1.4
1.5
1.6
1.65
VDD DC Current
IDD
µA
µA
DC Current (VSSEXT
)
IVSS
fRF = 900MHz
fRF = 2100MHz
Insertion Loss
RFX to RFC
IL
fRF = 2700MHz
1.2
dB
dB
dB
2700MHz < fRF ≤ 4000MHz
4000MHz < fRF ≤ 8000MHz
1.1
2.3
400MHz to 3800MHz
Any 400MHz range
Insertion Loss Flatness
ILFLAT
ISOC
0.1
0.4
400MHz ≤ fRF ≤ 900MHz
900MHz < fRF ≤ 2100MHz
2100MHz < fRF ≤ 2700MHz
2700MHz < fRF ≤ 4000MHz
4500MHz ≤ fRF ≤ 5500MHz
400MHz ≤ fRF ≤ 900MHz
900MHz < fRF ≤ 2100MHz
2100MHz < fRF ≤ 2700MHz
2700MHz < fRF ≤ 4000MHz
4500MHz ≤ fRF ≤ 5500MHz
57.5
51
62
55
Minimum Isolation
RFX to RFC [b][c]
49.5
45
54
49
43
44.8
59
56.5
50
53
Minimum Isolation
RFX to RFX [b][d]
ISOX
48
51
dB
44.5
41
48
43
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that
are not shown in bold italics are guaranteed by design characterization.
[b] With one path always active.
[c] Minimum value specified for RFC to RF1 through RF4 only. Specification does not apply to RF5.
[d] Each of the 4 inputs to any other input, 4 states only, RF5 removed.
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October 11, 2018
Electrical Characteristics
Table 5.
Electrical Characteristics
Typical application circuit (Figure 39), Normal Mode (VDD= 3.3V, VSSEXT = 0V) or Bypass Mode (VDD = 3.3V, VSSEXT = -3.3V), TEPAD = +25°C,
fRF = 2000MHz, input power = 0dBm, ZS = ZL = 50Ω, RFX = one of the five input ports, and PCB board trace and connector losses are
de-embedded unless otherwise noted.
Parameter
Symbol
Condition
400MHz ≤ fRF ≤ 900MHz
Minimum
Typical
23
Maximum
Units
900MHz < fRF ≤ 2100MHz
2100MHz < fRF ≤ 2700MHz
2700MHz < fRF ≤ 4000MHz
4500MHz ≤ fRF ≤ 5500MHz
400MHz ≤ fRF ≤ 900MHz
18
Minimum RFC Return Loss [b]
RLRFC
16
dB
16
23
23
900MHz < fRF ≤ 2100MHz
2100MHz < fRF ≤ 2700MHz
2700MHz < fRF ≤ 4000MHz
4500MHz ≤ fRF ≤ 5500MHz
400MHz ≤ fRF ≤ 900MHz
16
Minimum RFX Return Loss [b]
(Active Thru)
RLRFC_A
15
dB
dB
14
17
30
900MHz < fRF ≤ 2100MHz
2100MHz < fRF ≤ 2700MHz
2700MHz < fRF ≤ 4000MHz
4500MHz ≤ fRF ≤ 5500MHz
From RFX Active to RFX Terminated
From RFX Terminated to RFX Active
22
Minimum RFX Return Loss [b]
(Terminated State)
RLRFX_T
20
15
14
1.7:1
2:1
36.5
35
Maximum RFX Port VSWR
During Switching
VSWRT
Input 1dB Compression [c]
Input 0.1dB Compression [c]
ICP1dB
34 [a]
28
dBm
dBm
ICP0.1dB
f
RF1 = 2000MHz, fRF2 = 2010MHz
RF input = RFX, PIN = +20dBm / tone
fRF1 + fRF2 = 4010MHz
114
106
111
fRF1 = 4900MHz, fRF2 = 4910MHz
RF Input = RFX, PIN = +20dBm / tone
fRF1 + fRF2 = 9810MHz
Input IP2
(Insertion Loss State)
IIP2
dBm
fRF1 = 5500MHz, fRF2 = 5510MHz
RF input = RFX, PIN = +20dBm / tone
fRF1 + fRF2 = 11010MHz
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns
that are not shown in bold italics are guaranteed by design characterization.
[b] With one path always active.
[c] The input 0.1dB and 1dB compression points are linearity figures of merit. Refer to the “Absolute Maximum Ratings” section 0 for the
maximum RF input power and for maximum operating RF input power.
6
October 11, 2018
Electrical Characteristics
Table 6.
Electrical Characteristics
Typical application circuit (Figure 39), Normal Mode (VDD = 3.3V, VSSEXT = 0V) or Bypass Mode (VDD = 3.3V, VSSEXT = -3.3V), TEPAD = +25°C,
fRF = 2000MHz, input power = 0dBm, ZS = ZL = 50Ω, RFX = one of the five input ports, and PCB board trace and connector losses are
de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Minimum
45 [a]
Typical
60.5
60
Maximum
Units
fRF = 400MHz
fRF = 2000MHz
fRF = 4000MHz
fRF = 4900MHz
fRF = 5500MHz
56
Δf = 5MHz
Input IP3
IIP3
RF Input = RFX
PIN = +15dBm/tone
60.5
55
dBm
55
Group Delay
GD
0.43
256
1
ns
ns
tBP-ON1
50% CTRL to 90% maximum RF power
345
Switching Time – Bypass
(VSSEXT = -3.3V) [b][c]
50% CTRL to RF power settled to within
± 0.1dB of maximum power
tBP-ON2
285
tBP-OFF
tN-ON1
50% CTRL to 10% maximum RF power
50% CTRL to 90% maximum RF power
256
245
345
50% CTRL to RF power settled to within
± 0.1dB of maximum power
tN-ON2
tN-ON3
295
350
Switching Time –Normal
(VSSEXT = 0V) [b][c]
50% CTRL to 99% RF maximum RF
power
ns
tn-OFF1
tn-OFF2
50% CTRL to 10% maximum RF power
50% CTRL to 1% maximum RF power
Pin 20 = GND
200
245
25
Maximum Switching Rate [d]
kHz
Pin 20 = VSSEXT applied
290
RF ports terminated into 50Ω
Maximum spurious level on
any RF port [e]
SpurMAX
-120
dBm
RFX connected to RFC
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that
are not shown in bold italics are guaranteed by design characterization.
[b]
fRF = 1GHz.
[c] RFC to RFX. In and out of all-off state [000].
[d] Minimum time required between switching of states =1/ (Maximum Switching Rate).
[e] Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2MHz.
7
October 11, 2018
Thermal Characteristics
Table 7.
Package Thermal Characteristics
Parameter
Symbol
Value
Units
Junction-to-Ambient Thermal Resistance
θJA
41
°C/W
Junction-to-Case Thermal Resistance
(Case is defined as the exposed paddle)
θJC
6.4
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL1
Typical Operating Conditions (TOCs)
Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply.
.
.
.
.
.
.
.
.
.
.
VDD = 3.3V.
TEPAD = +25ºC (Temperature of exposed paddle).
fRF = 2000MHz.
RFX is the driven RF port, and RFC is the output port.
PIN = 10dBm for all small signal tests.
PIN = +15dBm / tone applied to selected RFX port for two-tone linearity tests.
Two-tone frequency spacing = 5MHz.
ZS = ZL = 50Ω.
All unused RF ports terminated into 50Ω.
For insertion loss and isolation plots, RF trace and connector losses are de-embedded (see Figure 36 for the “EVKIT Trace and
Connector Loss vs. Temperature” plot).
.
Plots for isolation and insertion loss over temperature and voltage are for a typical path. For performance of a specific path, refer to the
online S-Parameter file.
8
October 11, 2018
Typical Performance Characteristics [1]
Figure 4. Insertion Loss vs. Frequency over
Figure 5. Insertion Loss vs. Frequency over
Selected Switch
Temperature
0
0
-0.5
-1
RF1
-40C
25C
RF2
RF3
RF4
RF5
-0.5
-1
105C
-1.5
-2
-1.5
-2
-2.5
-3
-2.5
-3
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Frequency (GHz)
Frequency (GHz)
Figure 6. Insertion Loss vs. Frequency over
Voltage
Figure 7. RFC to RFX Isolation vs. Frequency
0
0
2.7V
RFC to RF1 - RF5 Isolations.
-10
-20
-30
-40
-50
-60
-70
-80
-90
Switch Control States 1 thru 5
3.3V
-0.5
-1
5.0V
5.5V
-1.5
-2
-2.5
-3
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Frequency (GHz)
Frequency (GHz)
Figure 8. RFC to RFX Isolation vs. Frequency
Figure 9. Typical RFC to RFX Isolation vs.
Frequency over Temperature
9
October 11, 2018
Typical Performance Characteristics [2]
Figure 10. Typical RFC to RFX Isolation vs.
Figure 11. RFX to RFX Isolation vs. Frequency
Frequency over VDD
Figure 12. RFX to RFX Isolation vs. Frequency
Figure 13. Typical RFX to RFX Isolation vs.
Frequency over Temperature
Figure 14. Typical RFX to RFX Isolation vs.
Frequency over VDD
Figure 15. RFX Return Loss vs. Frequency over
Switch Path [Selected State]
10
October 11, 2018
Typical Performance Characteristics [3]
Figure 16. Typical RFX Return Loss vs. Freq.
Figure 17. Typical RFX Return Loss vs.
over Temp. [Selected State]
Frequency over VDD [Selected State]
Figure 18. RFC Return Loss vs. Frequency over
Switch Path [Selected State]
Figure 19. Typical RFC Return Loss vs. Freq.
over Temp. [Selected State]
Figure 20. Typical RFC Return Loss vs. Freq.
over VDD [Selected State]
Figure 21. RFX Return Loss vs. Frequency over
Switch Path [Terminated State]
0
-10
-20
-30
RF1
RF2
RF3
-40
RF4
RF5
-50
0
1
2
3
4
5
6
7
8
Frequency (GHz)
11
October 11, 2018
Typical Performance Characteristics [4]
Figure 22. Typical RFX Return Loss vs. Freq.
Figure 23. Typical RFX Return Loss vs. Freq.
over Temp. [Terminated State]
over VDD [Terminated State]
Figure 24. Return Loss (During Switching) vs.
Time
Figure 25. VSWR (During Switching) vs. Time
Figure 26. RFX Switching Time [RFX
Terminated to RFX Active]
Figure 27. RFX Switching Time [RFX Active to
RFX Terminated]
12
October 11, 2018
Typical Performance Characteristics [5]
Figure 28. Switching Speed RFX to RFC All Off
Figure 29. Switching Speed RFX to RFC On to
to On
All Off
5
Normal Mode (Internal NVG)
0
RFX to RFC. Measurement system
floor = 45 dB
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
RF1
RF2
RF3
RF4
RF5
0
50
100
150
200
250
300
Time (nsec)
Figure 30. RFX IIP3 vs. Frequency over Switch
Path [Selected State]
Figure 31. RF1 IIP3 vs. Frequency over
Temperature and Voltage
Figure 32. RF2 IIP3 vs. Frequency over
Temperature and Voltage
Figure 33. RF3 IIP3 vs. Frequency over
Temperature and Voltage
13
October 11, 2018
Typical Performance Characteristics [6]
Figure 34. RF4 IIP3 vs. Frequency over
Figure 35. RF5 IIP3 vs. Frequency over
Temperature and Voltage
Temperature and Voltage
Figure 36. EVKIT Trace and Connector Loss vs.
Temperature
14
October 11, 2018
Control Mode
To select the path of the F2915 use Table 8 to see the control voltage with either 1.8V or 3.3V logic.
Table 8.
Switch Control Truth Table
Mode
All Off
V3
0
V2
0
V1
0
RF1 On
RF2 On
RF3 On
RF4 On
RF5 On
All Off
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
All Off
1
1
1
15
October 11, 2018
Evaluation Kit Picture
Figure 37. Top View
Figure 38. Bottom View
16
October 11, 2018
Evaluation Kit / Applications Circuit
Figure 39. Electrical Schematic
Table 9.
Part Reference
C1, C3, C5, C7, C8, C9
Bill of Material (BOM)
QTY
6
Description
Manufacturer Part #
Manufacturer
100pF ±5%, 50V, C0G Ceramic Capacitor (0402)
Not Installed (0603)
GRM1555C1H101J
Murata
C2
C4
0
0
Not Installed (0603)
C6
1
1000pF ±5%, 50V, C0G Ceramic Capacitor (0603)
0Ω ±1%, 1/10W, Resistor (0402)
100kΩ ±1%, 1/10W, Resistor (0402)
15kΩ ±1%, 1/10W, Resistor (0402)
22kΩ ±1%, 1/10W, Resistor (0402)
Edge Launch SMA (0.375 inch pitch ground tabs)
CONN HEADER VERT DBL 10 X 2 POS GOLD
SP5T Switch 4mm x 4mm QFN24-EP
Printed Circuit Board
GRM1885C1H102J
ERJ-2GE0R00X
ERJ-2RKF1003X
ERJ-2RKF1502X
ERJ-2RKF2202X
142-0701-851
Murata
Panasonic
Panasonic
Panasonic
Panasonic
Emerson Johnson
FCI
R1, R2, R3
R4, R5, R6
R7
3
3
1
R8
1
J1-J8
J9
8
1
67997-120HLF
U1
1
F2955NBGK
IDT
1
F29XX EVKIT Rev 02.0
IDT
17
October 11, 2018
Evaluation Kit (EVKit) Operation
External Supply Setup
1. Set up a VDD power supply in the voltage range of 2.7V to 5.5V and disable the power supply output.
2. If using the on-chip negative voltage generator, install a 2-pin shunt to short pins 3 (GND) and 4 (VSSEXT) of J9.
3. If an external negative voltage supply is to be used, set its voltage within the range of -3.6V to -3.2V and disable it. Also, ensure there are
no jumper connections on pins 3 and 4 of J9.
Logic Control Setup
Using the EVKIT to Manually Set the Control Logic
1. On connector J9, connect a 2-pin shunt from pin 7 (VDD) to pin 8 (VDD_CTRL). This connection provides the VDD voltage supply to the
Evaluation Board logic control pull-up network.
2. On connector J9 connect a 2-pin shunt from pin 9 (LVSEL2) to pin 10 (LVSEL). This connection enables R7 (15kΩ) and R8 (22kΩ) to
form a voltage divider to set the proper logic control levels to support the full voltage range of VDD. Note that when using the on-board
R7 / R8 voltage divider, the current draw from the VDD supply will be higher by approximately VDD/37kΩ.
3. Connector J9 has 3 logic input pins: V1 (pin 20), V2 (pin 18), and V3 (pin 16). See Table 8 for the logic truth table. With the pull-up network
enabled (as noted above), if these pins are left open, a logic HIGH will be provided through pull-up resistors R4, R5, and R6. To set a logic
LOW to V1, V2, and V3, connect 2-pin shunts from pin 16 to pin 15, pin 18 to pin 17 and pin 20 to pin 19, respectively.
Using the External Control Logic
Pins 6, 7, 8, 9, and 10 of J9 should have no connection. External logic controls can be applied to J9 pins 16 (V3), 18 (V2) and 20 (V1). See
Table 8 for the logic truth table.
Turn On Procedure
1. Set up the supplies and Evaluation Board as noted in “External Supply Setup” and “Logic Control Setup” above.
2. Connect the preset disabled VDD power supply to pin 2 (VDD) and pin 1 (GND) of J9.
3. If the external negative voltage source is to be used, connect the disabled supply to pin 4 (VSSEXT) and pin 3 (GND) of J9. If using the
on-chip negative supply, ensure that the 2-pin shunt is installed connecting pin 3 to pin 4.
4. Enable the VDD supply and then enable the VSSEXT supply (if used).
5. Set the desired logic setting using V1, V2, and V3 to achieve the desired path setting, see Table 8. Note that external control logic should
not be applied without VDD being applied first.
Turn Off Procedure
1. If using external control logic, V1, V2, and V3 must be set to a logic LOW.
2. Disable any external VSSEXT supply.
3. Disable the VDD supply.
18
October 11, 2018
Application Information
Default Start-up
There are no internal pull-up or pull-down resistors on the control pins.
Logic Control
Control pins V1, V2, and V3 are used to set the state of the SP5T switch (See Table 8).
External VSS
The F2955 is designed with an on-chip negative voltage generator. This on-chip generator is enabled by connecting pin 20 of the device to
ground. To disable the on-chip generator, apply a negative voltage to pin 20 (VSSEXT) of the device within the range stated in the “Recommended
Operating Conditions” (Table 3).
Power Supplies
A common VDD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to
minimize noise and fast transients. Supply noise can degrade the noise figure, and fast transients can trigger ESD clamps and cause them to
fail. Supply voltage change or transients should have a slew rate smaller than 1V / 20µs. In addition, all control pins should remain at 0V (±0.3V)
while the supply voltage ramps or while it returns to zero.
Control Pin Interface
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of each control pin is recommended. This applies to control pins 17, 18, and 19 as shown below.
Figure 40. Control Pin Interface Schematic
19
October 11, 2018
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/document/psc/nbnbg24-package-outline-40-x-40-mm-bodyepad-270mm-sq-050-mm-pitch-qfn
Marking Diagram
Line 1 and 2 are the part number.
Line 3: “Z” is for the ASM Test Step.
Line 3: “YYWW” is the last two digits of the year plus the work week.
Line 3: “UZL” denotes the Assembler Code.
IDTF2955
NBGK
Z1528UZL
Ordering Information
Orderable Part Number
Package
MSL Rating
MSL1
Carrier Type
Tray
Operating Temperature
-40°C to +105°C
F2955NBGK
F2955NBGK8
F2955EVBK
4mm x 4mm x 0.75mm 24-QFN
4mm x 4mm x 0.75mm 24-QFN
Evaluation Board
MSL1
Reel
-40°C to +105°C
20
October 11, 2018
Revision History
Revision Date
Description of Change
October 11, 2018
.
.
.
Changed maximum value for “Maximum Junction Temperature” in Table 2
Changed maximum value for “VDD to GND” in Table 2
Updated maximum value for “Power Supply Voltages” in Table 3
September 25, 2018
Initial release.
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