HAT2068R-EL-E

更新时间:2024-09-18 08:32:05
品牌:RENESAS
描述:Silicon N Channel Power MOS FET Power Switching

HAT2068R-EL-E 概述

Silicon N Channel Power MOS FET Power Switching 硅N通道功率MOS FET电源开关

HAT2068R-EL-E 数据手册

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HAT2068R  
Silicon N Channel Power MOS FET  
Power Switching  
REJ03G1176-0500  
(Previous: ADE-208-1225C)  
Rev.5.00  
Sep 07, 2005  
Features  
Capable of 4.5 V gate drive  
Low drive current  
High density mounting  
Low on-resistance  
RDS (on) = 7 mtyp. (at VGS = 10 V)  
Outline  
RENESAS Package code: PRSP0008DD-D  
(Package name: SOP-8 <FP-8DAV> )  
5 6 7 8  
D D D D  
5
6
7
8
1, 2, 3  
4
5, 6, 7, 8  
Source  
Gate  
Drain  
4
G
4
3
2
1
S S S  
1 2 3  
Rev.5.00 Sep 07, 2005 page 1 of 6  
HAT2068R  
Absolute Maximum Ratings  
(Ta = 25°C)  
Item  
Drain to source voltage  
Symbol  
VDSS  
VGSS  
ID  
Value  
Unit  
V
30  
±20  
Gate to source voltage  
V
Drain current  
14  
A
Note 1  
Drain peak current  
ID (pulse)  
112  
A
Body-drain diode reverse drain current  
Channel dissipation  
IDR  
Pch Note 2  
θ ch-a Note 2  
Tch  
14  
A
2.5  
W
Channel to ambient thermal impedance  
Channel temperature  
50  
°C/W  
°C  
°C  
150  
Storage temperature  
Tstg  
–55 to +150  
Notes: 1. PW 10 µs, duty cycle 1%  
2. When using the glass epoxy board (FR4 40 × 40 × 1.6 mm), PW 10 s  
Electrical Characteristics  
(Ta = 25°C)  
Item  
Symbol  
V (BR) DSS  
V (BR) GSS  
IGSS  
Min  
30  
±20  
1.0  
16  
Typ  
Max  
Unit  
V
Test Conditions  
Drain to source breakdown voltage  
Gate to source breakdown voltage  
Gate to source leak current  
ID = 10 mA, VGS = 0  
IG = ±100 µA, VDS = 0  
VGS = ±16 V, VDS = 0  
VDS = 30 V, VGS = 0  
VDS = 10 V, ID = 1 mA  
ID = 7 A, VGS = 10 V Note 3  
ID = 7 A, VGS = 4.5 V Note 3  
ID = 7 A, VDS = 10 V Note 3  
VDS = 10 V  
V
±10  
1
µA  
µA  
V
Zero gate voltage drain current  
Gate to source cutoff voltage  
Static drain to source on state resistance  
IDSS  
VGS (off)  
RDS (on)  
RDS (on)  
|yfs|  
2.5  
9
7
mΩ  
mΩ  
S
11  
28  
1650  
400  
220  
26  
5
16  
Forward transfer admittance  
Input capacitance  
Ciss  
Coss  
Crss  
Qg  
pF  
pF  
pF  
nC  
nC  
nC  
ns  
ns  
ns  
ns  
V
VGS = 0  
Output capacitance  
f = 1 MHz  
Reverse transfer capacitance  
Total gate charge  
VDD = 10 V  
V
GS = 10 V  
Gate to source charge  
Gate to drain charge  
Turn-on delay time  
Qgs  
ID = 14 A  
Qgd  
5
td (on)  
tr  
td (off)  
tf  
15  
30  
50  
10  
0.80  
50  
VGS = 10 V, ID = 7 A  
V
DD 10 V  
Rise time  
RL = 1.43 Ω  
Turn-off delay time  
Rg = 4.7 Ω  
Fall time  
Body-drain diode forward voltage  
Body-drain diode reverse recovery time  
VDF  
1.10  
IF = 14 A, VGS = 0 Note 3  
IF = 14 A, VGS = 0  
diF/dt = 50 A/µs  
trr  
ns  
Note: 3. Pulse test  
Rev.5.00 Sep 07, 2005 page 2 of 6  
HAT2068R  
Main Characteristics  
Maximum Safe Operation Area  
Power vs. Temperature Derating  
500  
100  
4.0  
3.0  
2.0  
1.0  
0
Test Condition:  
When using the glass epoxy board  
(FR4 40 × 40 × 1.6 mm), PW 10 s  
10  
1
Operation in  
this area is  
limited by RDS (on)  
0.1  
Ta = 25°C  
1 shot Pulse  
0.01  
0.1 0.3  
1
3
10  
30  
100  
0
50  
100  
150  
200  
Drain to Source Voltage VDS (V)  
Note 4:  
Ambient Temperature Ta (°C)  
When using the glass epoxy board  
(FR4 40 × 40 × 1.6 mm)  
Typical Output Characteristics  
Typical Transfer Characteristics  
50  
40  
30  
20  
10  
0
50  
40  
30  
20  
10  
0
Pulse Test  
3.5 V  
10 V  
VDS = 10 V  
Pulse Test  
4.5 V  
4 V  
VGS = 3 V  
25°C  
Tc = 75°C  
–25°C  
0
2
4
6
8
10  
0
1
2
3
4
5
Gate to Source Voltage VGS (V)  
Drain to Source Voltage VDS (V)  
Drain to Source Saturation Voltage vs.  
Gate to Source Voltage  
Static Drain to Source on State Resistance  
vs. Drain Current  
0.20  
100  
Pulse Test  
Pulse Test  
50  
0.16  
0.12  
0.08  
0.04  
0
20  
VGS = 4.5 V  
10  
ID = 10 A  
10 V  
5
5 A  
2 A  
2
1
0
4
8
12  
16  
20  
0.1 0.2 0.5 1  
2
5 10 20 50 100  
Gate to Source Voltage VGS (V)  
Drain Current ID (A)  
Rev.5.00 Sep 07, 2005 page 3 of 6  
HAT2068R  
Static Drain to Source on State Resistance  
vs. Temperature  
Forward Transfer Admittance vs.  
Drain Current  
50  
100  
Pulse Test  
Tc = –25°C  
30  
10  
40  
30  
75°C  
3
1
25°C  
ID = 2 A, 5 A  
10 A  
20  
VGS = 4.5 V  
10  
0.3  
0.1  
VDS = 10 V  
Pulse Test  
2 A, 5 A, 10 A  
10 V  
0
–40  
0
40  
80  
120  
160  
0.1 0.3  
1
3
10  
30  
100  
Case Temperature Tc (°C)  
Drain Current ID (A)  
Typical Capacitance vs.  
Drain to Source Voltage  
Body-Drain Diode Reverse  
Recovery Time  
100  
10000  
3000  
1000  
Ciss  
50  
Coss  
Crss  
300  
100  
20  
10  
30  
10  
di / dt = 50 A / µs  
VGS = 0, Ta = 25°C  
VGS = 0  
f = 1 MHz  
0.1 0.2  
0.5  
1
2
5
10 20  
0
10  
20  
30  
40 50  
Reverse Drain Current IDR (A)  
Drain to Source Voltage VDS (V)  
Dynamic Input Characteristics  
Switching Characteristics  
20  
16  
12  
8
200  
100  
50  
50  
40  
30  
20  
10  
0
ID = 14 A  
VGS  
t
d(off)  
t
f
VDD = 25 V  
10 V  
5 V  
t
r
VDS  
20  
10  
5
t
d(on)  
4
VDD = 25 V  
10 V  
5 V  
VGS = 10 V, VDS = 10 V  
Rg = 4.7 , duty 1 %  
0
100  
2
0
20  
40  
60  
80  
0.1 0.2  
0.5  
1
2
5
10 20  
Gate Charge Qg (nc)  
Drain Current ID (A)  
Rev.5.00 Sep 07, 2005 page 4 of 6  
HAT2068R  
Reverse Drain Current vs.  
Source to Drain Voltage  
50  
40  
30  
20  
10  
0
10 V  
5 V  
VGS  
= 0  
Pulse Test  
1.6 2.0  
Source to Drain Voltage VSD (V)  
0
0.4  
0.8  
1.2  
Normalized Transient Thermal Impedance vs. Pulse Width  
10  
1
D = 1  
0.5  
0.1  
0.1  
θch – f (t) = γ s (t) • θch – f  
θch – f = 83.3°C/W, Ta = 25°C  
When using the glass epoxy board  
(FR4 40 × 40 × 1.6 mm)  
0.01  
PW  
D =  
PDM  
T
0.001  
PW  
T
0.0001  
10 µ  
100 µ  
1 m  
10 m  
100 m  
1
10  
100  
1000  
10000  
Pulse Width PW (S)  
Switching Time Test Circuit  
Switching Time Waveform  
90%  
Vout  
Monitor  
Vin Monitor  
D.U.T.  
Rg  
10%  
10%  
Vin  
RL  
Vout  
10%  
VDS  
= 10 V  
Vin  
10 V  
90%  
90%  
t
t
t
d(off)  
t
f
d(on)  
r
Rev.5.00 Sep 07, 2005 page 5 of 6  
HAT2068R  
Package Dimensions  
JEITA Package Code  
RENESAS Code  
PRSP0008DD-D  
Package Name  
FP-8DAV  
MASS[Typ.]  
0.085g  
P-SOP8-3.95 × 4.9-1.27  
1
D
*
bp  
5
8
1
Index mark  
NOTE)  
1. DIMENSIONS "*1(Nom)" AND "*2"  
4
Terminal cross section  
(Ni/Pd/Au plating)  
Z
DO NOT INCLUDE MOLD FLASH.  
2. DIMENSION "*3" DOES NOT  
INCLUDE TRIM OFFSET.  
3
bp  
*
M
x
e
Dimension in Millimeters  
Reference  
Symbol  
Min  
Nom  
4.90  
3.95  
Max  
5.3  
D
E
L1  
A2  
A1  
A
0.10  
0.14  
0.40  
0.20  
0.25  
1.75  
0.46  
bp  
b1  
0.34  
0.15  
c
0.25  
c1  
L
0
°
8°  
y
HE  
e
5.80  
6.10  
1.27  
6.20  
Detail F  
x
0.25  
0.1  
y
Z
0.75  
1.27  
L
0.40  
0.60  
1.08  
L1  
Ordering Information  
Part Name  
Quantity  
Shipping Container  
HAT2068R-EL-E  
2500 pcs  
Taping  
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of  
production before ordering the product.  
Rev.5.00 Sep 07, 2005 page 6 of 6  
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan  
Keep safety first in your circuit designs!  
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may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.  
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary  
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.  
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http://www.renesas.com  
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.  
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© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.  
Colophon .3.0  

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