HCTS163D/SAMPLE [RENESAS]
HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16;
| 型号： | HCTS163D/SAMPLE |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16 CD 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCTS163MS
Radiation Hardened
Synchronous Counter
September 1995
Features
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
MR
CP
P0
1
2
3
4
5
6
7
8
16 VCC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 TE
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Standard Outputs 10 LSTTL Loads
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
P1
P2
P3
PE
9
SPE
GND
- VIL = 0.8V Max
- VIH = VCC/2 Min
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
MR
CP
P0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
TC
The Intersil HCTS163MS is a Radiation Hardened synchronous
presettable counter that feature look-ahead carry logic for use in
high speed counting application. HCTS163MS is a binary counter,
and is reset synchronously with the clock. Counting and parallel
presetting are both accomplished synchronously with the negative
to positive transition of the clock.
Q0
P1
Q1
P2
Q2
P3
Q3
PE
TE
The HCTS163MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
GND
SPE
The HCTS163MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCTS163DMSR
TEMPERATURE RANGE
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
PACKAGE
o
o
-55 C to +125 C
16 Lead SBDIP
o
o
HCTS163KMSR
-55 C to +125 C
16 Lead Ceramic Flatpack
16 Lead SBDIP
o
HCTS163D/Sample
HCTS163K/Sample
HCTS163HMSR
+25 C
o
+25 C
Sample
16 Lead Ceramic Flatpack
Die
o
+25 C
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518600
File Number 2480.2
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
570
HCTS163MS
Functional Block Diagram
Q0 Q1 Q2 Q3
P3
P0
P1
4
P2
6
3
5
7
PE
10
TE
TE
TE
9
SPE
P
T0
D0
P
T1
D1
P
T3
D3
P
T2
D2
1
Q0
Q1
Q2
Q3
MR
MR
MR
MR
MR
CP
CP
CP
CP
VCC
2
CP
14
13
Q1
12
11
15
TC
Q0
Q2
Q3
TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
Reset (clear)
MR
CP
PE
X
TE
SPE
PN
X
l
QN
L
TC
l
X
X
l
L
Parallel Load
h (Note 3)
h (Note 3)
h (Note 3)
h (Note 3)
h (Note 3)
X
X
X
h
L
L
X
l
h
H
(Note 1)
(Note 1)
(Note 1)
L
Count
Inhibit
h
h (Note 3)
h (Note 3)
h (Note 3)
X
X
X
Count
Qn
X
X
l (Note 2)
X
X
l (Note 2)
Qn
H = HIGH Voltage Level
L = LOW Voltage Level
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition
X = Immaterial
q = Lower case letter indicate the state of the referenced output prior to the LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
NOTES:
1. The TC output is HIGH when TE is HIGH and the counter is at terminal count (HLLH for 162 and HHHH for 163)
2. The HIGH-to-LOW transition of PE or TE on the 54/74163 and 54/74160 should only occur while CP is high for conventional operation
3. The LOW-to-HIGH transition of SPE or MR on the 54/74163 should only occur while CP is high for conventional operation
Spec Number 518600
571
Specifications HCTS163MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Thermal Resistance
SBDIP Package. . . . . . . . . . . . . . . . . . . .
Ceramic Flatpack Package . . . . . . . . . . . 114 C/W
Maximum Package Power Dissipation at +125 C Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/ C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/ C
θ
θ
JA
JC
o
o
73 C/W
24 C/W
o
o
29 C/W
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
o
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265 C
o
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
o
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5 VCC (TR, TF) . . . . . . . .500ns Max
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
o
o
Operating Temperature Range (T ) . . . . . . . . . . . . -55 C to +125 C
A
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
LIMITS
(NOTE 1)
PARAMETER
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
UNITS
µA
o
Quiescent Current
ICC
VCC = 5.5V,
VIN = VCC or GND
1
2, 3
1
+25 C
-
40
o
o
+125 C, -55 C
-
750
µA
o
Output Current
(Sink)
IOL
IOH
VOL
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
+25 C
4.8
4.0
-4.8
-4.0
-
-
mA
mA
mA
mA
V
o
o
2, 3
1
+125 C, -55 C
-
-
o
Output Current
(Source)
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V
+25 C
o
o
2, 3
1, 2, 3
+125 C, -55 C
-
o
o
o
Output Voltage Low
VCC = 4.5V, VIH = 2.25V,
+25 C, +125 C, -55 C
0.1
IOL = 50µA, VIL = 0.8V
o
o
o
VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.8V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C
-
0.1
V
V
V
o
o
o
Output Voltage High
VOH
VCC = 4.5V, VIH = 2.25V,
IOH = -50µA, VIL = 0.8V
+25 C, +125 C, -55 C
VCC
-0.1
-
-
o
o
o
VCC = 5.5V, VIH = 2.75V,
IOH = -50µA, VIL = 0.8V
+25 C, +125 C, -55 C
VCC
-0.1
o
Input Leakage
Current
IIN
FN
VCC = 5.5V, VIN = VCC or
GND
1
+25 C
-
-
-
±0.5
±5.0
-
µA
µA
-
o
o
2, 3
+125 C, -55 C
o
o
o
Noise Immunity
Functional Test
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V (Note 2)
7, 8A, 8B
+25 C, +125 C, -55 C
NOTES:
1. All voltages referenced to device GND.
2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number 518600
572
Specifications HCTS163MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
LIMITS
(NOTES 1, 2)
A SUB-
PARAMETER
CP to Qn
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
25
UNITS
ns
o
TPHL
TPLH
VCC = 4.5V
9
10, 11
9
+25 C
2
2
2
2
2
2
2
2
o
o
+125 C, -55 C
29
ns
o
CP to TC
MR to Qn, TC
TE to TC
TPHL
TPLH
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
+25 C
28
ns
o
o
10, 11
9
+125 C, -55 C
33
ns
o
TPHL
TPHL
+25 C
50
ns
o
o
10, 11
9
+125 C, -55 C
75
ns
o
+25 C
23
ns
o
o
10, 11
+125 C, -55 C
29
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
(NOTE 1)
PARAMETER
SYMBOL
CONDITIONS
TEMPERATURE
MIN
MAX
78
UNITS
pF
o
Capacitance Power Dissipation
CPD
VCC = 5.0V, f = 1MHz
+25 C
-
-
-
-
-
-
o
o
+125 C, -55 C
176
10
pF
o
Input Capacitance
Output Transition Time
NOTE:
CIN
VCC = 5.0V, f = 1MHz
VCC = 4.5V
+25 C
pF
o
+125 C
10
pF
o
TTHL
TTLH
+25 C
15
ns
o
+125 C
22
ns
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD
LIMITS
(NOTES 1, 2)
PARAMETER
Quiescent Current
Output Current (Sink)
SYMBOL
ICC
CONDITIONS
TEMPERATURE
MIN
-
MAX
0.75
-
UNITS
mA
o
VCC = 5.5V, VIN = VCC or GND
+25 C
o
IOL
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
+25 C
4.0
mA
o
Output Current
(Source)
IOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25 C
-4.0
-
mA
Spec Number 518600
573
Specifications HCTS163MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
200K RAD
LIMITS
(NOTES 1, 2)
PARAMETER
SYMBOL
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
o
Output Voltage Low
VOL
VCC = 4.5V and 5.5V, VIH = VCC/2,
+25 C
-
0.1
V
VIL = 0.8V , IOL = 50µA
o
Output Voltage High
VOH
VCC = 4.5V and 5.5V, VIH = VCC/2,
VIL = 0.8V , IOH = -50µA
+25 C
VCC
-0.1
-
V
o
Input Leakage Current
IIN
FN
VCC = 5.5V, VIN = VCC or GND
+25 C
-
-
±5
µA
o
Noise Immunity
Functional Test
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
(Note 3)
+25 C
-
-
o
CP to Qn
CP to TC
TPHL
TPLH
VCC = 4.5V
VCC = 4.5V
+25 C
2
2
29
33
ns
ns
o
TPLH
TPLH
+25 C
o
MR to Qn, TC
TE to TC
TPHL
TPHL
VCC = 4.5V
VCC = 4.5V
+25 C
2
2
75
29
ns
ns
o
+25 C
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
o
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 C)
GROUP B
PARAMETER
SUBGROUP
DELTA LIMIT
12µA
ICC
IOL/IOH
5
5
-15% of 0 Hour
Spec Number 518600
574
Specifications HCTS163MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test (Preburn-In)
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
Sample/5005
Sample/5005
Sample/5005
Sample/5005
GROUP A SUBGROUPS
READ AND RECORD
ICC, IOL/H
1, 7, 9
1, 7, 9
Interim Test I (Postburn-In)
Interim Test II (Postburn-In)
PDA
ICC, IOL/H
ICC, IOL/H
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
Interim Test III (Postburn-In)
PDA
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Final Test
Group A (Note 1)
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Group D
NOTE:
1, 7, 9
1. Alternate group A testing in accordance with method 5005 of MIL-STD-883 may be exercised.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
CONFORMANCE
GROUPS
Group E Subgroup 2
NOTE:
METHOD
PRE RAD
POST RAD
PRE RAD
1, 9
POST RAD
5005
1, 7, 9
Table 4
Table 4 (Note 1)
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
11 - 15 1 - 10
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
11 - 15
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
4, 6, 8
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
16
50kHz
25kHz
-
-
-
-
-
-
8
-
1 - 7, 9, 10, 16
1, 3, 5, 7, 9, 10, 16
-
11 - 15
2
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
11 - 15
8
1 - 7, 9, 10, 16
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518600
575
HCTS163MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% PIND, Method 2020, Condition A
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number 518600
576
HCTS163MS
AC Load Circuit
AC Timing Diagrams
DUT
TEST
POINT
VIH
INPUT
VS
VIL
CL
RL
TPLH
TPHL
VOH
VOL
VOH
VOL
CL = 50pF
VS
OUTPUT
RL = 500Ω
TTLH
TTHL
80%
80%
20%
20%
OUTPUT
AC VOLTAGE LEVELS
PARAMETER
VCC
HCTS
4.50
3.00
1.30
0
UNITS
V
V
V
V
V
VIH
VS
VIL
GND
0
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
Spec Number 518600
577
HCTS163MS
Die Characteristics
DIE DIMENSIONS:
104 x 86 mils
METALLIZATION:
Type: AlSi
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
< 2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 mils x 4 mils
Metallization Mask Layout
HCTS163MS
CP
(2)
MR
(1)
VCC
(16)
(15) TC
(14) Q0
P0 (3)
P1 (4)
(13) Q1
P2 (5)
P3 (6)
(12) Q2
(11) Q3
PE (7)
(8)
GND
(9)
SPE
(10)
TE
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location.
The mask series for the HCTS163 is TA14448A.
Spec Number 518600
578
相关型号：
HCTS163DMSH
Binary Counter, HCT Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, CDIP16,
RENESAS
HCTS163K/SAMPLE
HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16, CERAMIC, DFP-16
RENESAS
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