HD404314H [RENESAS]
microcomputer designed to increase program productivity; 微机，旨在提高生产力的计划
| 型号： | HD404314H |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | microcomputer designed to increase program productivity |
| 文件： | 总68页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Cautions
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Remember to give due consideration to safety when making your circuit designs, with appropriate
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Notes regarding these materials
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contained therein.
HD404318 Series
Rev. 6.0
Sept. 1998
Description
The HD404318 Series is 4-bit HMCS400-series microcomputer with large-capacity memory designed to
increase program productivitch microcomputer has an A/D converter and input capture timer built in.
They also come with high-pins that can directly drive a fluorescent display.
The HD404318 Series includes s: the HD404318 with 8-kword ROM; the HD404316 with 6-
kword ROM; the HD404314 with 4M; the HD4074318 with 8-kword PROM.
The HD4074318 is a PROM version ZTcomputer. Programs can be written to the PROM by a
PROM writer, which can dramatically shordevelopment periods and smooth the process from
debugging to mass production. (The PROM proifications are the same as for the 27256.)
ZTAT : Zero Turn Around Time ZTAT is a trademchi Ltd.
Features
•
34 I/O pins
One input-only pin
33 input/output pins: 21 pins are high-voltage pins (40 V, max.)
On-chip A/D converter (8-bit × 8-channel)
Three timers
•
•
One event counter input
One timer output
One input capture timer
•
•
•
8-bit clock-synchronous serial interface (1 channel)
Alarm output
Built-in oscillators
Ceramic or crystal oscillator
External clock drive is also possible
HD404318 Series
•
Seven interrupt sources
Two by external sources
Three by timers
One each by the A/D converter and serial interface
Two low-power dissipation modes
Standby mode
•
•
Stop mode
Instruction cycle time 1 µs (fosc = 4 MHz)
Ordering Information
Type
Model Name
ROM (words)
RAM (digit)
Package
DP-42S
FP-44A
DP-42S
FP-44A
DP-42S
FP-44A
DP-42S
FP-44A
Mask ROM
HD404314S
HD40
HD404
HD404316
HD404318S
HD404318H
HD4074318S
HD4074318H
4,096
384
6,144
2
8
ZTAT
Recommended PROM Programmers and Sockers
PROM Programmer
Manufacture
Socket Adapter
Package
DP-42S
Model Name
Man
Model Name
DATA I/O Corp.
121B
Hitachi
HS4318ESS01H
HS4318ESH01H
HS4318ESS01H
HS4318ESH01H
FP-44A
AVAL Corp.
PKW-1000
DP-42S
Hitachi
FP-44A
2
HD404318 Series
Pin Arrangement
RA1/Vdisp
R00/SCK
R01/SI
R02/SO
R03/TOC
TEST
RESET
OSC1
OSC2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
R23
R22
R21
R20
R13
R12
R11
R10
R83
R82
R81
R80
D8
1
2
3
4
5
6
7
8
9
GND
AVSS
10
11
12
13
14
15
16
2
DP-42S
R30/AN0
R/AN1
N2
R41
R42/A
R43/AN7
AVCC
D7
D6
D5
D4/STOPC
D3/BUZZ
D2/EVNB
D1/INT1
VCC
D0/INT0
1
2
3
4
5
6
7
8
3
R12
R11
R10
R83
R82
R81
R80
D8
TEST
RESET
OSC1
OSC2
GND
32
31
30
29
28
27
26
25
24
23
FP-44A
AVSS
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
9
10
11
D7
D6
D5
3
HD404318 Series
PinDescription
Pin Number
Item
Power supply VCC
GND
Symbol
DP-42S FP-44A I/O Function
21
10
16
5
Applies power voltage
Connected to ground
Vdisp (shared 1
with RA1)
39
Used as a high-voltage output power supply pin when
selected by the mask option
Test
TEST
6
1
I
Cannot be used in user applications. Connect this pin
to GND.
Reset
RESET
7
8
2
3
I
I
Resets the MCU
Oscillator
OSC1
Input/output pin for the internal oscillator. Connect these
pins to the ceramic or crystal oscillator, or OSC1 to an
external oscillator circuit.
OSC2
D0–D8
4
O
Port
221, I/O Input/output pins addressed individually by bits; D0–D8
are all high-voltage I/O pins. Each pin can be
individually configured as selected by the mask option.
RA1
1
3
One-bit high-voltage input port pin
R00–R03,
R30–R43
R10–R23,
R80–R83
INT0, INT1
STOPC
SCK
2–5,
40–43ur-bit input/output pins consisting of standard voltage
12–19 7–14
31–42 27–38 I/O ut/output pins consisting of high voltage pins
Interrupt
22, 23 17, 18
I
I
Input pinal interrupts
Stop clear
26
2
21
40
Input pin forom stop mode to active mode
Serial
interface
I/O Serial interface output pin
SI
3
41
42
43
19
20
15
I
Serial interface receivinput pin
Serial interface transmit data output pin
Timer output pin
SO
4
O
O
I
Timer
Alarm
TOC
EVNB
BUZZ
AVCC
5
24
25
20
Event count input pin
O
Square waveform output pin
A/D
converter
Power supply for the A/D converter. Connect this pin as
close as possible to the VCC pin and at the same voltage
as VCC. If the power supply voltage to be used for the
A/D converter is not equal to VCC, connect a 0.1-µF
bypass capacitor between the AVCC and AVSS pins.
(However, this is not necessary when the AVCC pin is
directly connected to the VCC pin.)
AVSS
11
6
Ground for the A/D converter. Connect this pin as close
as possible to GND at the same voltage as GND.
AN0–AN7
12–19 7–14
I
Analog input pins for the A/D converter
4
HD404318 Series
Pin Description in PROM Mode
The HD4074318 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops
operating, thus allowing the user to program the on-chip PROM.
Pin Number
MCU Mode
Pin
PROM Mode
Pin
DP-42S
1
FP-44A
39
40
41
42
43
1
I/O
I
I/O
RA1/Vdisp
R00/SCK
R01/SI
R02/SO
R03/TOC
TEST
2
I/O
I/O
I/O
I/O
I
VCC
VCC
3
4
5
6
VPP
7
2
RESET
C1
I
RESET
VCC
I
8
3
I
9
4
O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
5
GND
GND
O0
6
AVSS
7
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
R41/AN5
R42/AN6
R43/AN7
AVCC
O
I/
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
O1
9
O2
10
11
12
13
14
15
16
17
18
19
20
21
23
24
25
26
O3
O4
VCC
VCC
M0
VCC
D0/INT0
D1/INT1
D2/EVNB
D3/BUZZ
D4/STOPC
D5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
M1
A1
A2
A3
I
I
I
D6
A4
D7
A9
D8
VCC
5
HD404318 Series
Pin Number
MCU Mode
Pin
PROM Mode
DP-42S
31
FP-44A
27
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin
CE
OE
A13
A14
A5
I/O
R80
I
I
I
I
I
I
I
I
I
I
I
I
32
28
R81
33
29
R82
34
30
R83
35
31
R10
36
32
R11
A6
37
33
R12
A7
38
34
R13
A8
39
35
R20
A0
40
36
R21
A10
A11
A12
41
37
R22
42
38
I/O: Input/output pin; I: Input pin; in
6
HD404318 Series
Block Diagram
INT
0
System control
RAM
Interrupt
control
D
D
D
D
D
D
D
D
D
0
1
2
3
4
5
6
7
8
INT
1
× 4 bits)
(384
W
(2 bits)
Timer A
Time
Timer C
X
(4 bits)
R0
R0
R0
R0
0
1
2
3
EVNB
TOC
SPX
(4 bits)
Y
(4 bits)
R1
R1
R1
R1
0
1
2
SPY
bits)
3
SI
SO
R2
R2
R2
R2
0
1
2
3
Serial
interface
SCK
CA
AV
SS
R3
0
AN
0
R3
R3
R3
1
2
•
•
•
•
•
•
A/D
converter
ST
(1 bit)
(1 bit)
3
AN
7
A
AV
CC
(4 bits)
R4
R4
R4
R4
0
1
2
3
B
(4 bits)
BUZZ
Buzzer
SP
(10 bits)
R8
R8
R8
R8
0
1
2
Data bus
Instruction
decoder
PC
(14 bits)
3
High voltage
pin
ROM
(4,096 × 10 bits)
(6,144 × 10 bits)
(8,192 × 10 bits)
RA
1
Directional
signal line
7
HD404318 Series
Memory Map
ROM Memory Map
Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines.
Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.
Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000–$0FFF (HD404314), $0000–$17FF (HD404316), $0000–$1FFF (HD404318,
HD4074318)): The entire ROM area can be used for program coding.
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
0008
09
$
$000
$000E
$000F
JMPL instruction
(jump to RESET, STOPC routine)
Vecto
(16 w
JMPL instruction
(jump to INT0 routine)
$000F
$0010
JMPL instruction
(jump to INT1 routine)
Zero-page subroutine
(64 words)
JMPL instruction
(jump to timer A routine)
$003F
$0040
JMPL instruction
(jump to timer B routine)
Pattern
(4,096 words)
HD404314
Program
JMPL instruction
(jump to timer C routine)
(4,096 words)
JMPL instruction
A/D converter routine)
$0FFF
$1000
L instruction
serial routine)
HD404316
Program
(6,144 words)
$17FF
$1800
HD404318, HD4074318
Program
(8,192 words)
$1FFF
Note: Since the ROM address areas between $0000-$0FFF overlap, the user can determine how these areas
are to be used.
Figure 1 ROM Memory Map
8
HD404318 Series
RAM MemoryMap
Initial values
after reset
$000
$000
$003
$004
$005
Interrupt control bits area
RAM-mapped registers
Port mode register A
Serial mode register
(PMRA)
(SMR)
W
W
0000
$040
$050
0000
Memory registers (MR)
Undefined
$006
Serial data register lower (SRL)
R/W
R/W
W
Undefined
-000
$007 Serial data register upper (SRU)
$008 Timer mode register A
(TMA)
Data (304 digits)
$009
$00A
$00B
Timer mode register B1 (TMB1)
0000
W
R/W
R/W
*1
*2
Timer B
(TRBL/TWBL)
(TRBU/TWBU)
/0000
Undefined
$00C Miscellaneous register
(MIS)
00--
W
W
$180
$00D
Timer mode register C
(TMC)
0000
*2
$00E
$00F
R/W
R/W
Timer C
(TRCL/TWCL)
(TRCU/TWCU)
/0000
Undefined
Not used
Not used
$3C0
$3FF
Stack (64
A/D channel register
(ACR)
-000
0000
1000
0000
--00
$016
$017
$018
W
R
A/D data register lower (ADRL)
A/D data register upper (ADRU)
019 A/D mode register 1
R
W
W
(AMR1)
(AMR2)
A
A/D mode register 2
Not used
$020
$023
$024
$025
ter flag area
Port
Port mo
(PMRB)
(PMRC)
TMB2)
0000
00-0
-000
W
W
W
$026 Timer mode
Not used
Notes: 1. Two registers are mapped
on the same area ($00A,
$00B, $00E, $00F).
$030
Port R0 DCR
(DCR0)
W
0000
2. Undefined.
Not used
Not used
R: Read only
W: Write only
R/W: Read/write
$033
$034
Port R3 DCR
Port R4 DCR
(DCR3)
(DCR4)
0000
0000
W
W
$03F
Timer read register B lower (TRBL)
Timer read register B upper (TRBU)
Timer write register B lower (TWBL)
Timer write register B upper (TWBU)
$00A
$00B
R
R
W
W
Timer read register C lower (TRCL)
Timer read register C upper (TRCU)
R
R
$00E
$00F
Timer write register C lower (TWCL)
Timer write register C upper (TWCU)
W
W
Figure 2 RAM Memory Map and Initial Values
9
HD404318 Series
Table 1
Initial Values of Flags after MCU Reset
Item
Initial Value
Interrupt flags/mask
Interrupt enable flag (IE)
Interrupt request flag (IF)
Interrupt mask (IM)
0
0
1
0
0
0
0
0
0
Bit registers
Watchdog timer on flag (WDON)
A/D start flag (ADSF)
Input capture status flag (ICSF)
Input capture error flag (ICEF)
IAD off flag (IAOF)
RAM enable flag (RAME)
RAM Address
Bit 2
Bit 1
RSP
Bit 0
IE
(I
IF0
(IF of INT0)
$0000
$0001
$0002
$0003
(Interrupt
enable flag)
(Reset SP bit)
IMTA
(IM of timer
IFTA
timer A)
IM1
(IM of INT1)
IF1
(IF of INT1)
IMTC
(IM of timer C)
(I
IMTB
(IM of timer B)
IFTB
(IF of timer B)
IMS
(IM of serial)
IF
(IF of se
IMAD
M of A/D)
IFAD
(IF of A/D)
Interrupt coea
Bit 3
Bit 2
Bit 0
W
(Watch
on flag)
ADSF
(A/D start flag)
Not used
Not used
$020
$021
$022
$023
RAME
(RAM enable
flag)
ICEF
(Input capture
error flag)
ICSF
(Input capture
status flag)
IAOF
(IAD off flag)
IF: Interrupt
request flag
IM: Interrupt
mask
IE: Interrupt
enable flag
SP: Stack pointer
Not used
Register flag area
Figure 3 Interrupt Control Bits and Register Flag Areas Configuration
10
HD404318 Series
TM/TMD
SEM/SEMD
Allowed
REM/REMD
Allowed
IE
IM
Allowed
IAOF
IF
ICSF
ICEF
RAME
RSP
Not executed
Allowed
Allowed
Not executed
Allowed
Allowed
Not executed
Inhibited
Inhibited
Inhibited
Allowed
Inhibited
WDON
ADSF
Not used
Allowed
Not executed
Not executed
Note:
WDON is reset by or by STOPC enable for stop mode cancellation. The REM or REMD
instruction must not bfor ADSF during A/D conversion. If the TM or TMD instruction is
executed for the inhibiten-existing bits, the value in ST becomes invalid.
Figure 4 Usage Liof RAM Bit Manipulation Instructions
Memory registers
$040 MR(0)
Stack are
$3C0
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)
MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
S
Bit 2
Bit 1
Bit 0
$3FC
$3FD
$3FE
$3FF
PC13
PC12
PC11
PC10
CA
PC9
PC6
PC2
PC8
PC5
PC1
PC7
PC4
PC0
PC3
$3FF
PC13–PC0 : Program counter
ST: Status flag
CA: Carry flag
Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position
11
HD404318 Series
Registers and Flags
3
3
0
0
0
(A)
(B)
Accumulator
Initial value: Undefined, R/W
B register
W register
Initial value: Undefined, R/W
Initial value: Undefined, R/W
1
(W)
3
3
3
3
0
0
0
0
X register
Initvalue: Undefined, R/W
Initindefined, R/W
Initial value: R/W
Initial value: Undefine
Initial value: Undefined, R/W
(X)
(Y)
Y register
SPX register
(SPX)
(SPY)
SPY register
Carry
0
(CA)
0
Status
Initial value: 1, no R/W
13
(ST)
0
0
Program counter
Initial value: 0,
no R/W
(PC)
1
9
1
5
Stack pointer
Initial value: $3FF, no R/W
1
1
(SP)
Figure 6 Registers and Flags
12
HD404318 Series
Addressing Modes
RAM Addressing Modes
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as
a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode (LAMR, XMRA): The memory registers (MR), which are located
in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.
0
3
0
3
0
3
0
0
Y
X
Instruction
Opcode
9
0
9
RAM address
Register Indirect Addressi
RAM address 0 0 0 1 0 0
Memory Register Addressing
1st instructio
word
instruction
ord
9
0
Opcode
Instruction
9
RAM address
Direct Addressing
Figure 7 RAM Addressing Modes
13
HD404318 Series
ROM Addressing Modes
Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the
JMPL, BRL, or CALL instruction.
Current Page Addressing Mode: A program can branch to any address in the current page (256 words
per page) by executing the BR instruction.
Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page
subroutine area ($0000–$003F) by executing the CAL instruction.
Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.
1st
2nd
instruction worction word
9
3
0
9
5
0
Opcode
Opcode
O
Operand
13
13
0
Program counter
Direct Addressing
Program counter 0 0 0 0 0 0 0 0
Zero-Page Addressing
Operand
9
7
0
3
0
7
3
0
Opcode
Operand
e
B
A
13
0
0
Program counter * * * * * *
Current Page Addressing
Program counter 0
Table Data Addressing
Figure 8 ROM Addressing Modes
14
HD404318 Series
Table 2
Instruction Set Classification
Number of
Instruction Type
Immediate
Function
Instructions
Transferring constants to the accumulator, B register, and RAM.
4
8
Register-to-register
Transferring contents of the B, Y, SPX, SPY, or memory registers to
the accumulator
RAM addressing
RAM register
Arithmetic
Available when accessing RAM in register indirect addressing mode 13
Transferring data between the accumulator and memory. 10
Performing arithmetic operations with the contents of the accumulator, 25
B register, or memory.
Compare
Comparing contents of the accumulator or memory with a constant
12
6
RAM bit manipulation Bit set, bit reset, and bit test.
ROM addressing
Input/output
Brancand jump instructions based on the status condition.
8
Coinput/output of the R and D ports; ROM data reference 11
with thtion
Control
Controllincommunication interface and low-power
dissipation m
4
Total: 101
instructions
15
HD404318 Series
Interrupts
$000,0
IE
Interrupt
request
(RESET, STOPC)
Priority Controller
$000,2
IF0
Priority Order
Vector Address
$0000
INT interrupt
0
1
2
3
4
5
6
7
$0002
$000,3
I
$0004
$0006
$00
IF1
$0008
$000A
INT interrupt
1
$000C
$001,1
IM1
$000E
$001,2
Timer A interrupt
Timer B interrupt
Timer C interrupt
A/D interrupt
IFTA
$001,3
IMTA
$002,0
IFTB
$002,1
IMTB
$002,2
IFTC
$002,3
IMTC
$003,0
IFAD
$003,1
IMAD
$003,2
IFS
Serial interrupt
$003,3
IMS
Figure 9 Interrupt Control Circuit
16
HD404318 Series
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Stacking
Interrupt
acceptance
Vector address
generation
IE reset
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Note: * The stack ithe IE reset after the instruction
is executed, eo-cycle instruction.
Figurrupt Processing Sequence
17
HD404318 Series
Operating Modes
The MCU has three operating modes as shown in table 3. Transitions between operating modes are shown
in figure 11.
Table 3
Operations in Each Operating Mode
Function
Active Mode
Standby Mode
OP
Stop Mode
Stopped
Reset
System oscillator
CPU
OP
OP
OP
OP
OP
O
OP
Retained
Retained
OP
RAM
Retained
Reset
Timer A
Timers B, C
Serial interface
A/D
OP
Reset
OP
Reset
OP
Reset
I/O
Retained
Reset
Note: OP implies in operation
18
HD404318 Series
Reset by
RESET input or
by watchdog timer
RAME = 0
RESET 1
RAME = 1
RESET 2
STOPC
Active
mode
Standby mode
Stop mode
BY
ion
fOSC: Oscillate
fOSC: Oscillate
STOP
instruction
fOSC: Stop
øCPU: Stop
øPER: Stop
øCPU: Stop
øPER: fcyc
øCPU: fcyc
øPER: fcyc
I
fOSC: Main oscillation frequency
fcyc fOSC/4
:
øCPU: System clock
øPER: Clock for other peripheral
functions
Figure 11 MCU Status Transit
In stop mode, the system oscillator is stopped. To ensure a proper oscillatstabilization period of at least
tRC when clearing stop mode, execute the cancellation according to the timing chart in figure12.
Stop mode
Oscillator
Internal
clock
RESET
or
STOPC
tres
t
res ≥ tRC (stabilization period)
STOP instruction execution
Figure 12 Timing of Stop Mode Cancellation
19
HD404318 Series
MCU Operation Sequence: The MCU operates in the sequence shown in figure 13 and figure 14.
The low-power mode operation sequence is shown in figure 14. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power ON
No
RESET = 0?
Yes
MCU operation cycle
RAME = 0
Yes
IF = 1?
Reset MCU
No
No
IM = 0
IE = 1
Yes
ion
Reset input
IE ← 0
Stack ← (PC),
(CA), (ST)
SBY/STOP
instruction
No
PC ← vector
Low-power mode
operation cycle
(figure 15)
PC ← (PC)+1
address
Figure 13 MCU Operating Sequence (Power ON)
20
HD404318 Series
Low-power mode
operation cycle
No
IF = 1 and
IM = 0?
Yes
Stop mode
Standby mode
No
No
IF = 1 and
IM = 0?
STOPC = 0?
Yes
Yes
Hardware
execution
Hardware NOP
execution
RAME = 1
←
Iocation
PC Next
ext
Reset MCU
Instructio
execution
MCU operation
cycle
Figure 14 MCU Operating Sequence (Low-Power Mode Operation)
21
HD404318 Series
Oscillator Circuit
Figure 15 shows a block diagram of the clock generation circuit.
CPU with ROM,
RAM, registers,
flags, and I/O
fOSC
fcyc
tcyc
øCPU
Timing
generator
circuit
OSC2
OSC1
1/4
division
circuit
System
oscillator
Peripheral
function
øPER
interrupt
15 Clock Generation Circuit
TEST
RESET
OSC1
G
AVSS
Figure 16 Typical Layout of Crystal and Ceramic Oscillator
22
HD404318 Series
Table 4
Oscillator Circuit Examples
Circuit Configuration
Circuit Constants
External clock
operation
External
oscillator
OSC1
Open
OSC2
Ceramic oscillator
(OSC1, OSC2)
Ceramic oscillator: CSA4.00MG (Murata)
Rf = 1 MΩ ±20%
C1
OSC1
OSC2
C1 = C2 = 30 pF ±20%
Ceramic
Rf
GND
Crystal oscillator
(OSC1, OSC2)
Rf = 1 MΩ ±20%
C1
Crystal
C2
C1 = C2 = 10 to 22 pF ±20%
Crystal: Equivalent to circuit shown below
C0 = 7 pF max.
OSC1
Rf
RS = 100 Ω max.
GND
L
CS
RS
OSC1
OSC2
CO
Notes: 1. Since the circuit constants change depending on the crystal oscillator and stray
capacitance of the board, the user should consult with the crysceramic oscillator
manufacturer to determine the circuit parameters.
2. Wiring among OSC1, OSC2, and elements should be as short as possible, and must not cross
other wiring (see figure 16).
23
HD404318 Series
I/O Ports
The MCU has 33 input/output pins (D0–D8, R0–R4, R8) and one input-only pin (RA1). The following
describes the features of the I/O ports.
•
The 21 pins consisting of D0–D8, R1, R2, and R8 are all high-voltage I/O pins. RA1 is a high-voltage
input-only pin. These high-voltage pins can be equipped with or without pull-down resistance, as
selected by the mask option.
•
All standard output pins are CMOS output pins. However, the R02/SO pin can be programmed for
NMOS open-drain output.
•
•
In stop mode, input/output pins go to the high-impedance state
All standard input/output pins have pull-up MOS built in, which can be individually turned on or off by
software
Table 5
Control of StaI/O Pins by Program
MIS3 (bit 3 of MIS)
1
DCR
PDR
1
0
1
0
0
1
0
1
0
1
CMOS buffer
PMOS
NMOS
—
—
—
—
—
On
—
—
—
—
—
—
—
On
—
On
—
On
—
On
Pull-up MOS
Note: — indicates off.
Data control register (DCR0: $030, DCR3: $033, DCR
DCR0, DCR3,
DCR4
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
Bits 0 to 3 CMOS Buffer Control
W
W
W
W
0
CMOS buffer off
(high impedance)
DCR03, DCR02, DCR01, DCR00,
DCR33, DCR32, DCR31, DCR30,
DCR43, DCR42, DCR41, DCR40
1
CMOS buffer on
Correspondence between ports and DCR bits
Register
DCR0
DCR3
DCR4
Bit 3
R03
R33
R43
Bit 2
R02
R32
R42
Bit 1
R01
R31
R41
Bit 0
R00
R30
R40
Figure 17 Data Control Register (DCR)
24
HD404318 Series
Table 6
Circuit Configurations of Standard I/O Pins
I/O Pin Type
Circuit
Pins
Input/output pins
R00, R01, R03
R30–R33,
HLT
VCC
Pull-up control signal
VCC
MIS3
Buffer control
signal
R40–R43
DCR
PDR
Output data
Input data
Input control signal
R02
HLT
VCC
Pull-up control signal
VCC
MIS3
Buffer control
signal
DCR
MIS2
PDR
Output data
Input data
ut control signal
Peripheral
function pins
Input/ output
pins
SCK
HLT
Pull-up control signal
MIS3
Output data
SCK
data
SCK
Output pins
SO
HLT
VCC
Pulignal
VCC
MIS3
Pl
sig
MIS2
SO
Output data
TOC
HLT
VCC
Pull-up control signal
VCC
MIS3
Output data
TOC
Notes on next page.
25
HD404318 Series
I/O Pin Type
Circuit
Pins
VCC
Peripheral
Input/ pins
SI
function pins
HLT
MIS3
PDR
SI
Input data
VCC
AN0–AN7
HLT
MIS3
PDR
A/D input
Input control
Notes: 1. In stop mode, the is reset and the peripheral function selection is cancelled. The HLT
signal goes low/output pins the enter high-impedance state.
2. The HLT signal is and standby modes.
26
HD404318 Series
Table 7
Circuit Configurations for High-Voltage Input/Output Pins
I/O Pin Type
With Pull-Down Resistance
Without Pull-Down Resistance
Pins
VCC
VCC
Input/output
pins
D0–D8,
HLT
Output
data
HLT
Output
data
R10–R13,
R20–R23,
R80–R83
Pull-down
resistance
Input data
Input control
signal
Vdisp
Input data
Input control
signal
Input pins
Input data RA1
Input control
signal
VCC
VCC
Peripheral
function pins
Output
pins
BUZZ
HLT
HLT
Output
data
Output
data
l-down
ance
t data
Input data
Input
pins
INT0,
INT1,
Pull-dow
resistance
EVNB,
STOPC
Vdisp
Notes: 1. In stop mode, the MCU is reset and the periphn selection is cancelled. The HLT
signal goes low, and input/output pins the enter hnce state.
2. The HLT signal is 1 in active and standby modes.
3. The circuits of HD4074318 are without pull-down resist
27
HD404318 Series
Port mode register A (PMRA: $004)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
PMRA3 PMRA2 PMRA1 PMRA0
PMRA0
R02/SO Mode Selection
0
1
R02
SO
PMRA2
R03/TOC Mode Selection
0
1
R03
TOC
PMRA1
R01/SI Mode Selection
0
1
R01
SI
PMRA3
D3/BUZZ Mode Selection
0
1
D3
BUZZ
Figrt Mode Register A (PMRA)
Port mode register B (PMRB:
Bit
3
0
2
0
0
0
Initial value
Read/Write
Bit name
W
W
W
*
PMRB3 PMRB2 PMRB1 PM
P
D0/INT0 Mode Selection
0
1
PMRB2 D2/EVNB Mode Selection
T0
0
1
D2
EVNB
PMRB1
D1/INT1 Mode Selection
0
1
D1
PMRB3 D4/STOPC Mode Selection
INT1
0
1
D4
STOPC
PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode,
PMRB3 is not reset but retains its value.
Note: *
Figure 19 Port Mode Register B (PMRB)
28
HD404318 Series
Miscellaneous register (MIS: $00C)
Bit
3
0
2
0
1
0
Initial value
Read/Write
Bit name
—
—
—
—
W
W
MIS3
MIS2 Not used Not used
CMOS Buffer
On/Off Selection
for Pin R02/SO
Pull-Up MOS
On/Off Selection
MIS3
MIS2
Pull-up MOS off
0
1
CMOS on
CMOS off
0
1
Pull-up MOS on
(refer to table 5)
Note: The on/each transistor and the peripheral function mode of each
pin can be ndently.
Figiscellaneous Register (MIS)
29
HD404318 Series
Prescaler
The MCU has a built-in prescaler labeled as prescaler S (PSS), which divides the system clock and then
outputs divided clock signals to the peripheral function modules, as shown in figure21.
Timer A
Timer B
System
clock
Clock
selector
Prescaler S
Timer C
Serial
e 21 Prescaler Output Supply
30
HD404318 Series
Timers
The MCU has three built-in timers: A, B, and C. The functions of each timer are listed in table 7.
Timer A
Timer A is an 8-bit free-running timer that has the following features:
•
One of eight internal clocks can be selected from prescaler S according to the setting of timer mode
register A (TMA: $008)
•
•
An interrupt request can be generated when timer counter A (TCA) overflows
Input clock frequency must not be modified during timer A operation
Table 7
Timer Functions
Functions
Timer A
Timer B
Available
Available
Available
Available
Available
—
Timer C
Available
—
Clock source
Prescale
Available
External eve
Timer functions
Free-running
Event counter
Reload
ble
Available
—
—
—
—
—
Available
Available
—
Watchdog
Input capture
PWM
Available
Timer output
Available
31
HD404318 Series
Timer A interrupt
request flag
(IFTA)
Timer
counter A
(TCA)
Overflow
Selector
øPER
System
clock
3
Prescaler S (PSS)
Timer mode
register A
(TMA)
Figure 22 Block Diagram
Timer mode register A (T
Bit
3
2
0
0
Initial value
Read/Write
Bit name
—
—
0
W
Not used TMA2
TMA1
Source
Prescaler frequency
Input clock
TMA2 TMA1 TMA0
0
1
0
0
1
0
1
0
1
0
1
PSS
PSS
PSS
PSS
PSS
PSS
PSS
PSS
2048tcyc
1024tcyc
512tcyc
128tcyc
32tcyc
8tcyc
1
0
1
4tcyc
2tcyc
Figure 23 Timer Mode Register A (TMA)
32
HD404318 Series
Timer B
Timer B is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features.
These are described as follows.
•
By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler
S can be selected, or timer B can be used as an external event counter
•
•
By setting timer mode register B2 (TMB2: $026), detection edge type of EVNB can be selected
By setting timer write register BL, BU (TWBL, BU: $00A, $00B), timer counter B (TCB) can be
written to during reload timer operation
•
•
•
By setting timer read register BL, BU (TRBL, BU: $00A, $00B), the contents of timer counter B can
be read out
Timer B can be used as an input capture timer to count the clock cycles between trigger edges input as
an external event
An interrupt can be requhen timer counter B overflows or when a trigger input edge is received
during input capture op
33
HD404318 Series
Interrupt request
flag of timer B
(IFTB)
Timer read
register BU
(TRBU)
Timer read
register B lower
(TRBL)
Clock
Timer counter B
(TCB)
Overflow
Free-running
timer control
signal
Timer write
register B upper
(TWBU)
Timer write
register B lower
(TWBL)
S
EVNB
Edge
detector
3
Timer mode
register B1
(TMB1)
øPER
System
Prescaler S (PSS)
Edge detectional
clock
2
Timer mode
register B2
(TMB2)
Figure 24 Timer B Free-Running and Reload Operatiolock Diagram
34
HD404318 Series
Input capture
status flag
(ICSF)
Input capture
error flag
(ICEF)
Interrupt request
flag of timer B
(IFTB)
Error
controller
Timer read
register BU
(TRBU)
Timer read
register B lower
(TRBL)
EVNB
Clock
Timer counter B
(TCB)
Edge
detector
Overflow
ut capture
control
ignal
Selector
3
Timer mode
register B1
(TMB1)
øPER
System
clock
Prescaler S (PSS)
Edge detection control signa
2
Timer mode
register B2
(TMB2)
Figure 25 Timer B Input Capture Operation Block Diagram
35
HD404318 Series
Timer mode register B1 (TMB1: $009)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
TMB13 TMB12 TMB11 TMB10
Free-Running/Reload
TMB13 Timer Selection
Input Clock Period and Input
Clock Source
TMB12 TMB11 TMB10
0
1
Free-running timer
Reload timer
0
1
0
1
0
1
0
1
2048tcyc
0
0
512tcyc
1
128tcyc
32tcyc
1
8tcyc
0
1
4tcyc
2tcyc
D2/EVNB (external event input)
Figure 26 Timer ster B1 (TMB1)
Timer mode register B2 (TMB2: $026)
Bit
3
2
0
1
0
0
0
Initial value
Read/Write
Bit name
—
—
W
W
W
Not used TMB22 TMB21 TMB20
TMB21 TMB20
EVNB Edge Detection Selection
No detection
0
1
0
1
0
1
Falling edge detection
Rising edge detection
Rising and falling edge detection
TMB22
Free-Running/Reload and Input Capture Selection
Free-Running/Reload
0
1
Input capture
Figure 27 Timer Mode Register B2 (TMB2)
36
HD404318 Series
Timer C
Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features,
which are described as follows.
•
•
•
•
By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S
can be selected
By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output
(PWM output) is enabled
By setting timer write register CL, CU (TWCL, CU: $00E, $00F), timer counter C (TCC) can be
written to
By setting timer read register CL, CU (TRCL, CU: $00E, $00F), the contents of timer counter C can be
read out
•
•
An interrupt can be requested when timer counter C overflows
Timer counter C can be a watchdog timer for detecting runaway program
37
HD404318 Series
System reset signal
Interrupt request
flag of timer C
(IFTC)
Watchdog on
flag (WDON)
Watchdog timer
controller
Timer read register CU (TRCU)
TOC
Timer output
control logic
Timer read
register C lower
(TRCL)
Clock
Timer counter C
(TCC)
Overflow
Timer
output
control
ignal
Timer write
register C upper
(TWCU)
Timer write
register C lower
(TWCL)
Selector
Free-running
mer control
al
3
Timer mode
register C (TMC)
øPER
System
clock
Prescaler S (PSS)
Port mode
egister A (PMRA)
Figure 28 Timer C Block Diagram
38
HD404318 Series
Timer mode register C (TMC: $00D)
Bit
3
0
2
0
1
0
0
0
Initial value
Read/Write
Bit name
W
W
W
W
TMC3
TMC2
TMC1
TMC0
Free-Running/Reload
Timer Selection
TMC2
TMC1
TMC0
Input Clock Period
TMC3
2048tcyc
1024tcyc
0
1
0
1
0
1
0
1
0
1
0
0
1
Free-running timer
Reload timer
1
512tcyc
128tcyc
32tcyc
8tcyc
0
1
4tcyc
2tcyc
Figure 29 TimRegister C (TMC)
×
T
(N +
TMC3 = 0
(Free-running
timer)
×
T
256
T
TMC3 = 1
(Reload timer)
T × (256 – N)
Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are
determined by timer mode register C.)
N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.)
Figure 30 PWM Output Waveform
39
HD404318 Series
$FF + 1
Overflow
Timer C
count value
$00
Time
CPU
operation
Normal
operation
Normal
operation
Timer C
clear
Normal
operation
Timer C
clear
Program
runaway
Reset
Figure 31 Watchdog Timer Operation Flowchart
Notes on Use
When using the timer output as ut, note the following point. From the update of the timer write
register until the occurrence of the interrupt, the PWM output differs from the period and duty
settings, as shown in table 8. The Pt should therefore not be used until after the overflow
interrupt following the update of the timester. After the overflow, the PWM output will have the
set period and duty cycle.
Table 8
PWM Output Following Update of ite Register
PWM Output
Timer Write Register is Updated during
High PWM Output
te Register is Updated during
Lutput
Mode
Timer write
register
mer write
er
Free running
updated to Interrupt
to
N
Interrupt
request
value N
request
T × (N' + 1)
T × (255 – N) T × (N + 1)
T × (255 – N) T × (N + 1)
Timer write
register
Timer write
register
Reload
updated to Interrupt
updated to
value N
Interrupt
request
value N
request
T
T
T × (255 – N)
T
T × (255 – N)
T
40
HD404318 Series
Alarm Output Function
The MCU has an alarm output function built in. By setting port mode register C (PMRC: $025), one of
four alarm frequencies supplied from the PSS can be selected.
Table 9
Port Mode Register C
PMRC
Bit 3
0
Bit 2
System Clock Divisor
0
1
0
1
÷ 2048
÷ 1024
÷ 512
1
÷ 256
BUZZ
Alarm output
ontrol signal
Port mode
register A
(PMRA)
Alarm ou
controller
Selector
ort mode
ster C
C)
øPER
System
clock
Prescaler S (PSS)
Figure 32 Alarm Output Function Block Diagram
41
HD404318 Series
Serial Interface
The MCU has a one-channel serial interface built in with the following features.
•
One of 13 different internal clocks or an external clock can be selected as the transmit clock. The
internal clocks include the six prescaler outputs divided by two and by four, and the system clock.
•
•
•
During idle states, the serial output pin can be controlled to be high or low output
Transmit clock errors can be detected
An interrupt request can be generated after transfer has completed when an error occurs
Table 10
Serial Interface Operating Modes
SMR
Bit 3
1
PMRA
Bit 1
Bit 0
Operating Mode
0
0
1
Continuous clock output mode
Transmit mode
1
eceive mode
smit/receive mode
42
HD404318 Series
Serial interrupt
request flag
(IFS)
Octal
counter (OC)
SO
Idle
controller
SCK
I/O
Serial data
controller
register (SR)
SI
Clock
1/2
Transfer
control
signal
1/2
or
3
Serial mode
register
(SMR)
øPER
System
clock
Prescaler S (PSS
Port mode
register C
(PMRC)
Figure 33 Serial Interfacagram
43
HD404318 Series
STS wait state
(Octal counter = 000,
transmit clock disabled)
MCU reset
SMR write
←
SMR write (IFS 1)
STS instruction
Transmit clock
Transfer state
Transmit clock wait state
(Octal counter = 000)
(Octal counter = 000)
8 transmit clocks or
←
STS instruction (IFS
1)
External clock mode
STS wait state
(Octal counter = 000,
MCU reset
SMR write
transmit clock disabled)
Continuous clock output state
(PMRA 0, 1 = 0, 0)
R write
8 transmit clocks or
←
SMR write (IFS 1)
STS instruction
Transmit clock
Transmit clock
Transfer state
Transmit clock wait state
(Octal counter = 000)
(Octal counter = 000)
←
Sn (IFS
1)
Internal clock m
Figure 34 Serial Interface Statns
Transmit clock
1
2
3
4
5
6
7
8
Serial output
data
LSB
MSB
Serial input
data latch
timing
Figure 35 Serial Interface Timing
44
HD404318 Series
Transmit clock
wait state
Transmit clock
wait state
State
STS wait state
Transfer state
STS wait state
MCU reset
PMRA write
SMR write
PMRC write
Port selection
External clock selection
Dummy write for
state transition
Output level control in
idle states
Output level control in
idle states
Data write for transmission
SRL, SRU
write
STS
instruction
SCK pin
(input)
SO pin
IFS
Undefined
LSB
MSB
Flag reset at transfer completion
clock mode
ck
State
STS wait state
nsfer state
STS wait state
MCU reset
PMRA write
SMR write
PMRC write
Port selection
Internal clock selection
Output level control in
idle states
Output level control in
idle states
Data write for transmission
SRL, SRU
write
STS
instruction
SCK pin
(output)
Undefined
LSB
MSB
SO pin
IFS
Flag reset at transfer completion
Internal clock mode
Figure 36 Example of Serial Interface Operation Sequence
45
HD404318 Series
Transmit clock erors are detected as illustrated in figure 37.
Transfer completion
←
(IFS 1)
Interrupts inhibited
←
IFS
0
SMR write
Yes
Transmit clock
error processing
Normal
termination
Transmit clock error dowchart
smit clock wait state
Transfer state
Transmit clock
wait state
Transfer state
State
SCK pin (input)
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit
clock error. When SMR
is written, IFS is set.
SMR write
IFS
Flag set because octal
counter reaches 000.
Flag reset at
transfer completion.
Transmit clock error detection procedure
Figure 37 Transmit Clock Error Detection
46
HD404318 Series
Table 11
Transmit Clock Selection
PMRC
Bit 0
0
SMR
Bit 2
Bit 1
Bit 0
0
System Clock Divisor
Transmit Clock Frequency
0
0
÷ 2048
÷ 512
÷ 128
÷ 32
4096tcyc
1024tcyc
256tcyc
64tcyc
1
1
0
0
1
0
0
1
1
0
0
÷ 8
16tcyc
1
÷ 2
4tcyc
1
0
÷ 4096
÷ 1024
÷ 256
÷ 64
8192tcyc
2048tcyc
512tcyc
128tcyc
32tcyc
1
1
÷ 16
1
8tcyc
Serial mode register (SMR: $005)
Bit
3
0
2
0
1
0
0
Initial value
Read/Write
Bit name
W
W
W
W
SMR3
SMR2
SMR1
SMR0
Prescaler
Clock Source Division Ratio
R00/SCK
SMR3
SMR2
SMR1
0
SMR0
SCK
Mode Selection
0
1
Output Prescaler
R00
0
1
0
1
0
1
0
1
Refer to
table 11
0
SCK
1
0
1
—
—
Output System clock
1
Input
External clock
Figure 38 Serial Mode Register (SMR)
47
HD404318 Series
Port mode register C (PMRC: $025)
Bit
3
0
2
0
1
0
0
Initial value
Read/Write
Bit name
Undefined
W
W
W
W
PMRC3
PMRC1
PMRC2
PMRC0
PMRC0
Serial Clock Division Ratio
Prescaler output divided by 2
Prescaler output divided by 4
Alarm output function.
Refer to table 9.
0
1
PMRC1
Output Level Control in Idle States
Low level
0
1
High level
Fiort Mode Register C (PMRC)
48
HD404318 Series
A/D Converter
The MCU also contains a built-in A/D converter that uses a sequential comparison method with a
resistance ladder. It can perform digital conversion of eight analog inputs with 8-bit resolution. The
following describes the A/D converter.
•
•
A/D mode register 1 (AMR1: $019) is used to select digital or analog ports
A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed and to select digital or
analog ports
•
•
The A/D channel register (ACR: $016) is used to select an analog input channel
A/D conversion is started by setting the A/D start flag (ADSF: $020, 2) to 1. After the conversion is
completed, converted data is stored in the A/D data register, and at the same time, the A/D start flag is
cleared to 0
•
By setting the IAD off flag (OF: $021, 2) to 1, the current flowing through the resistance ladder can be
cut off even while operatandby or active mode
4
A/D mode
register 1
(AMR1)
pt
r
(
A/D mode
register 2
(AMR2)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
A/D data
register
DRU, L)
Encoder
+
Comp
–
A/D channel
register (ACR)
A/D
controller
Control signal
for conversion
time
AVCC
AVSS
A/D start flag
(ADSF)
IAD off flag
(IAOF)
D/A
Operating mode signal (1 in stop mode)
Figure 40 A/D Converter Block Diagram
49
HD404318 Series
Notes on Usage
•
•
•
•
Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)
Do not write to the A/D start flag during A/D conversion
Data in the A/D data register during A/D conversion is undefined
Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop mode. In addition, to save power while in stop mode, all current
flowing through the converter’s resistance ladder is cut off.
•
•
If the power supply for the A/D converter is to be different from VCC, connect a 0.1-µF bypass capacitor
between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly
connected to the VCC pin.)
The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a
shared R port/analog input n as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to selected by bit 1 of the A/D mode register as an analog pin will remain
pulled up.
A/D mode register 1 (A)
Bit
3
0
2
0
0
0
Initial value
Read/Write
Bit name
W
W
W
AMR13 AMR12 AMR0
10
R30/AN0 Mode Selection
R30
N0
AMR12
R32/AN2 Mode Selection
0
1
R32
AN2
AMR11
1/AN1 Mode Selection
0
1
R31
AN1
AMR13
R33/AN3 Mode Selection
0
1
R33
AN3
Figure 41 A/D Mode Register 1 (AMR1)
50
HD404318 Series
A/D mode register 2 (AMR2: $01A)
Bit
3
2
1
0
0
0
Initial value
Read/Write
Bit name
—
—
—
—
W
W
Not used Not used AMR21 AMR20
AMR20
Conversion Time
0
1
34tcyc
67tcyc
AMR21
R4/AN4–AN7 Pin Selection
0
1
R4
AN4–AN7
A/D Mode Register (AMR2)
A/D channel CR: $016)
Bit
1
0
0
0
Initial value
Read/Write
Bit name
—
—
W
W
Not used AC
1
ACR0
ACR2 ACR1 ACR0 Analog Inn
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
0
0
1
0
1
1
Figure 43 A/D Channel Register (ACR)
51
HD404318 Series
A/D start flag (ADSF: $020, bit 2)
Bit
3
2
0
1
0
0
Initial value
Read/Write
Bit name
—
—
—
—
R/W
W
Not used ADSF WDON Not used
WDON
A/D Start Flag (ADSF)
0
1
A/D conversion completed
A/D conversion started
Refer to the description of timers
igure 44 A/D Start Flag (ADSF)
IAD off flag (IAOF: )
Bit
3
0
0
1
0
0
Initial value
Read/Write
Bit name
R/W
RAME
R/W
IAOF
I
R/W
SF
ICSF
IAD Off Flag (IAOF)
IAD current flows
0
1
Refer to tion of timers
IAD current is cut off
ICEF
RAME
Refer to the description of timers
Refer to the description of operating
modes
Figure 45 IAD Off Flag (IAOF)
52
HD404318 Series
ADRU: $018
ADRL: $017
3
2
1
0
3
2
1
0
MSB
bit 7
LSB RESULT
bit 0
Figure 46 A/D Data Registers
A/D data register (lower digit) (ADRL: $017)
Bit
3
2
1
0
0
Initial va
Read
Bit nam
0
R
0
R
0
R
R
ADRL3
ADRL2
ADRL1
ADRL0
Figure 4ta Register Lower Digit (ADRL)
A/D data register (upper digit018)
Bit
3
1
0
Initial value
Read/Write
Bit name
1
R
0
R
0
R
ADRU3
ADR
RU1
ADRU0
Figure 48 A/D Data Register Upper Di)
53
HD404318 Series
Notes on Mounting
Assemble all parts including the HD404318 Series on a board, noting the points described below.
1. Connect layered ceramic type capacitors (about 0.1 µF) between AVCC and AVSS, between VCC and
GND, and between used analog pins and AVSS.
2. Connect unused analog pins to AVSS.
1. When not using an A/D converter.
VCC
AVCC
AN0
AN1
to
0.1 µF
AN7
AVSS
GND
2. When using pins AN0 and AN1 ing AN2 to AN7.
AVCC
VCC
AN7
AVSS
GND
0.1 µF × 3
3. When using all analog pins.
VCC
AVCC
AN0
AN1
AN2 to
AN7
AVSS
GND
0.1 µF × 9
Figure 49 Example of Connections (1)
54
HD404318 Series
Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits.
An example connection is described in figure 50.
No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in
parallel. The capacitors are a large capacitance C1 and a small capacitance C2.
VCC
VCC
C1
C2
GND
GND
50 Example of Connections (2)
55
HD404318 Series
Absolute Maximum Ratings
Item
Symbol
Value
Unit
V
Notes
Supply voltage
Programming voltage
Pin voltage
VCC
VPP
VT
–0.3 to +7.0
–0.3 to +14.0
V
1
2
3
–0.3 to VCC + 0.3 V
VCC – 45 to
CC + 0.3
V
V
Total permissible input current
Total permissible output current
Maximum input current
∑IO
–∑IO
IO
70
mA
mA
mA
mA
mA
mA
°C
4
150
5
4
6, 7
6, 8
9, 10
10, 11
20
Maximum output current
–IO
4
30
Operating temperature
Storage temperature
–20 to +75
–55 to +125
°C
Notes: Permanent damage may occusolute maximum ratings are exceeded. Normal operation
must be under the conditions statectrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction ility may be affected.
1. Applies to pin TEST (VPP) of HD407
2. Applies to all standard voltage pins.
3. Applies to high-voltage pins.
4. The total permissible input current is the total rrents simultaneously flowing in from all
the I/O pins to GND.
5. The total permissible output current is the total of onts simultaneously flowing out from
VCC to all I/O pins.
6. The maximum input current is the maximum current flowih I/O pin to GND.
7. Applies to ports R3 and R4.
8. Applies to port R0.
9. Applies to ports R0, R3, and R4.
10. The maximum output current is the maximum current flowing from VCC to each I/O pin.
11. Applies to ports D0–D8, R1, R2, and R8.
56
HD404318 Series
Electrical Characteristics
DC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20 to +75°C,
unless otherwise specified)
Item
Symbol Pins
Min
Typ Max
VCC + 0.3
Unit Test Condition
Notes
Input high
voltage
VIH
RESET, SCK, 0.8VCC
SI, INT0, INT1,
—
V
STOPC, EVNB
OSC1
VCC – 0.5 —
VCC + 0.3
0.2VCC
V
V
Input low voltage VIL
RESET, SCK, –0.3
—
—
—
SI
INT0, INT1,
SC, EVNB
VCC – 40
0.2VCC
V
V
–0.3
0.5
—
Output high
voltage
VOH
VOL
|IIL|
SCVCC – 0.5 —
V
–IOH = 0.5 mA
IOL = 0.4 mA
Output low
voltage
SCK, SO,
—
—
0.4
1
V
I/O leakage
current
RESET, SCK,
SI, SO, TOC,
OSC1
µA
Vin = 0 V to VCC
1
INT0, INT1,
STOPC, EVNB
VCC
—
—
—
µA
Vin = VCC – 40 to VCC
1
Current
dissipation in
active mode
ICC
5
A VCC = 5 V,
fOSC = 4 MHz
2, 5
—
—
—
—
8.0
2.0
2, 6
3
Current
dissipation in
standby mode
ISBY
VCC
mA VCC = 5 V,
fOSC = 4 MHz
Current
dissipation in
stop mode
ISTOP
VCC
—
—
10
µA
VCC = 5 V
4, 5
4, 6
—
2
—
—
20
—
µA
Stop mode
VSTOP
VCC
V
retaining voltage
Notes: 1. Excludes current flowing through pull-up MOS and output buffers.
2. ICC is the source current when no I/O current is flowing while the MCU is in reset state.
Test conditions: MCU: Reset
Pins: RESET, TEST at GND
R0, R3, R4 at VCC
D0–D8, R1, R2, R8, RA1 at Vdisp
57
HD404318 Series
3. ISBY is the source current when no I/O current is flowing while the MCU timer is operating.
Test conditions: MCU: I/O reset
Standby mode
Pins:
RESET at VCC
TEST at GND
R0, R3, R4 at VCC
D0–D8, R1, R2, R8, RA1 at Vdisp
4. This is the source current when no I/O current is flowing.
Test conditions:
Pins:
R0, R3, R4 at VCC
D0–D8, R1, R2, R8, RA1 at GND
5. Applies to the HD404314, HD404316 and HD404318.
6. Applies to the HD4074318.
I/O Characteristics for Standrd Pins (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta =
–20 to +75°C, unless otherecified)
Item
Symbol P
Min
Typ Max
Unit Test Condition
Note
Input high
voltage
VIH
R0, R7VCC
—
VCC + 0.3 V
Input low voltage VIL
R0, R3, R4
—
0.3VCC
—
V
Output high
voltage
VOH
R0, R3, R4 VC
V
V
V
–IOH = 0.5 mA
IOL = 1.6 mA
IOL = 10 mA
Output low
voltage
VOL
R3, R4
—
4
R0
—
—
—
—
1
Input leakage
current
|IIL|
R0, R3, R4
Vin = 0 V to VCC
1
Pull-up MOS
–IPU
R0, R3, R4 30
30
150
80
300
180
= 5 V, Vin = 0 V
µ
2
3
Notes: 1. Output buffer current is excluded.
2. Applies to the HD404314, HD404316, and HD404318.
3. Applies to the HD4074318.
58
HD404318 Series
I/O Characteristics for High-Voltage Pins (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC,
Ta = –20 to +75°C, unless otherwise specified)
Item
Symbol Pins
Min
Typ Max
Unit Test Condition
Note
Input high
voltage
VIH
D0–D8, R1,
0.7VCC
—
VCC + 0.3 V
R2, R8, RA1
D0–D8, R1,
Input low
voltage
VIL
VCC – 40
—
0.3VCC
—
V
R2, R8, RA1
D0–D8, R1,
Output high VOH
voltage
VCC – 3.0 —
V
–IOH = 15 mA
R2, R8, BUZZ
VCC – 2.0 —
VCC – 1.0 —
—
V
V
V
–IOH = 10 mA
–IOH = 4 mA
—
Output low
voltage
VOL
D0–DR1,
—
—
VCC – 37
Vdisp = VCC – 40 V
1
RZZ
—
—
—
—
VCC – 37
20
V
150 kΩ at VCC – 40 V 2
I/O leakage |IIL|
current
D0–D8,
R8, RA1, B
D0–D8, R1,
µA Vin = VCC – 40 V to VCC
3
Pull-down
IPD
600
1000
µA Vdisp = VCC – 35 V,
1
MOS current
R2, R8, BUZZ
Vin = VCC
Notes: 1. Applies to pins with pull-down MOS aby the mask option .
2. Applies to pins without pull-down MOS aby the mask option.
3. Excludes output buffer current.
A/D Converter Characteristics (VCC = 4.0 to 5.5 V, GND = VCC – 40 V to VCC, Ta = –20 to
+75°C, unless otherwise specified)
Item
Symbol Pins
AVCC
Min
Typ Max
Test Condition
Note
Analog supply voltage AVCC
VCC – 0.3 VCC
VCC + 0.3 V
1
Analog input voltage
AVin
IAD
AN0–AN7 AVSS
—
—
—
AVCC
200
V
Current flowing
µA
VCC = AVCC = 5.0 V
between AVCC and AVSS
Analog input
capacitance
CAin
AN0–AN7 —
—
30
pF
Bit
Resolution
8
0
8
8
8
Number of input
channels
—
Chan
nel
Absolute accuracy
Conversion time
Input impedance
—
34
—
—
—
±2.0
67
LSB
tcyc
AN0–AN7 1
—
MΩ
Note: 1. Connect this to VCC if the A/D converter is not used.
59
HD404318 Series
AC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20 to +75°C)
Item
Symbol Pins
Min
Typ Max Unit Test Condition
Note
Clock oscillation
frequency
fOSC
OSC1, OSC2 0.4
4
4.5
MHz System clock
divided by 4
Instruction cycle time
tcyc
tRC
0.89
1
10
µs
Oscillation stabilization
time (ceramic oscillator)
OSC1, OSC2
OSC1, OSC2
—
—
7.5
ms
1
1
Oscillation stabilization
time (crystal oscillator)
tRC
—
—
40
ms
External clock high width tCPH
External clock low width tCPL
OSC1
92
92
—
—
2
—
—
—
—
—
—
—
20
20
—
ns
ns
ns
ns
tcyc
2
2
2
2
3
OSC1
External clock rise time
External clock fall time
tCPr
t
OSC1
OSC1
INT0, INT1, EVNB high
NT0, INT1,
B
widths
INT0, INT1, EVNB low
widths
tIL
,
E
2
—
—
tcyc
3
RESET low width
STOPC low width
RESET rise time
STOPC rise time
Input capacitance
tRSTL
tSTPL
tRSTr
tSTPr
Cin
RESE
STOPC
RESET
STOPC
—
—
—
—
20
20
tcyc
tRC
ms
ms
4
5
4
5
—
—
All input pins
except TEST
pF
f = 1 MHz, Vin = 0 V
TEST
—
—
—
—
6
7
18
Notes: 1. The oscillation stabilization time is the period required for the r to stabilize in the
following situations:
a. After VCC reaches 4.0 V at power-on.
b. After RESET input goes low when stop mode is cancelled.
c. After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of tRC.
When using a crystal or ceramic oscillator, consult with the manufacturer to determine what
stabilization time is required, since it will depend on the circuit constants and stray capacitance.
2. Refer to figure 51.
3. Refer to figure 52.
4. Refer to figure 53.
5. Refer to figure 54.
6. Applies to the HD404314, HD404316, and HD404318.
7. Applies to the HD4074318.
60
HD404318 Series
Serial Interface Timing Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta =
–20 to +75°C, unless otherwise specified)
During Transmit Clock Output
Item
Symbol Pins
Min Typ Max Unit Test Condition
Note
Transmit clock cycle time tScyc
Transmit clock high width tSCKH
Transmit clock low width tSCKL
Transmit clock rise time tSCKr
SCK
SCK
SCK
SCK
SCK
SO
1
—
—
—
—
—
—
—
—
—
80
80
tcyc
tScyc
tScyc
ns
Load shown in figure 56
Load shown in figure 56
Load shown in figure 56
Load shown in figure 56
Load shown in figure 56
Load shown in figure 56
1
1
1
1
1
1
0.4
0.4
—
—
—
Transmit clock fall time
tSCKf
ns
Serial output data delay tDSO
time
300 ns
Serial input data setup
time
tS
SI
100
200
—
—
—
—
ns
ns
1
1
Serial input data hold time tHS
During Transmit Clock Input
Item
Symbol Pins
yp Max Unit Test Condition
Note
Transmit clock cycle time tScyc
Transmit clock high width tSCKH
Transmit clock low width tSCKL
Transmit clock rise time tSCKr
SCK
SCK
SCK
SCK
SCK
SO
1
—
—
—
—
—
80
tcyc
tScyc
tScyc
1
1
1
1
1
1
0.4
0.4
—
—
—
Transmit clock fall time
tSCKf
Serial output data delay tDSO
time
300
d shown in figure 56
Serial input data setup
time
tSSI
SI
SI
100
200
—
—
—
—
ns
ns
1
1
Serial input data hold time tHSI
Note: 1. Refer to figure 55.
OSC1
1/fCP
VCC – 0.5 V
tCPH
tCPL
0.5 V
tCPr
tCPf
Figure 51 External Clock Timing
61
HD404318 Series
INT0, INT1, EVNB
0.8VCC
0.2VCC
tIL
tIH
Figure 52 Interrupt Timing
RESET
0.8VCC
0.2VCC
tRSTL
tRSTr
53 RESET Timing
STOPC
0.8VCC
0.2VCC
Figure 54 STOPC Timing
62
HD404318 Series
tScyc
t SCKf
tSCKr
tSCKL
VCC – 2.0 V (0.8VCC)*
0.8 V (0.2VCC)*
SCK
SO
SI
tSCKH
tDSO
VCC – 2.0 V
0.8 V
t SSI
t HSI
0.8VCC
0.2VCC
Note:
*VCC-2.0V and 0.8V athe threshold voltages for transmit clock output.
0.8VCC and 0.2VChreshold voltages for transmit clock input.
e 55 Serial Interface Timing
VCC
RL = 2.6 kΩ
Test
point
Hitachi
R =
C =
2074
12 kΩ
30 pF
uivalent
Figure 56 Timing Load Circuit
63
HD404318 Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404314 and
HD404316 as an 8-kword version
(HD404318). An 8-kword data size is required to change ROM data to mask manufacturing data since the
program used is for an 8-kword version.
This limitation applies when using an EPROM or a data base.
ROM 4-kword version:
HD404314
ROM 6-kword version:
HD404316
Address $10$1FFF
Address $1800–$1FFF
$0000
$0000
Vector add
Vector address
$000F
$0010
$000F
$0010
Zero-page subroutine
(64 words)
Zero-page subroutine
(64 words)
$003F
$0040
Pattern & program
(4,096 words)
Pattern & program
(6,144 words)
$0FFF
$1000
$17FF
$1800
Not used
Not used
$1FFF
$1FFF
Fill this area with 1s
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HD404318 Series
HD404314/HD404316/HD404318 Option List
Please check off the appropriate applications and enter the necessary information.
Date of order
Customer
1. ROM Size
Department
HD404314
HD404316
HD404318
4-kword
6-kword
8-kword
Name
ROM code name
LSI number
2. I/O Options
D: Without pull-down resistance
E: With pull-down resistance
I/O option
I/O option
Pin name
D0/INT0
D1/INT1
D2/EVNB
D3/BUZZ
D4/STOPC
D5
I/O
Pin name
R10
I/O
E
D
E
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R1
R2
RA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
R11
R12
R13
R20
R21
R22
R23
R80
R81
82
D6
D7
D8
Selected in option (3)
3. RA1/Vdisp
RA1 without pull-down resistance
Vdisp
Note: If even only one pin is selected with I/O option
E, pin RA1/Vdisp must be selected to function
as Vdisp.
4. ROM Code Media
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
6. Stop mode
7. Package
5. System Oscillator for OSC1 and OSC2
Used
DP-42S
FP-44A
Ceramic oscillator
Crystal oscillator
External clock
f =
f =
f =
MHz
MHz
MHz
Not used
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HD404318 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so t the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, opply voltage range, heat radiation characteristics, installation
conditions and other charHitachi bears no responsibility for failure or damage when used
beyond the guaranteed rangethin the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in ctor devices and employ systemic measures such as fail-
safes, so that the equipment incorpochi product does not cause bodily injury, fire or other
consequential damage due to operation achi product.
5. This product is not designed to be radiatio
6. No one is permitted to reproduce or duplicate, m, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarocument or Hitachi semiconductor
products.
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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