HD6473298VC [RENESAS]
UVPROM, 5MHz, MICROCONTROLLER, CDIP64, WINDOWED, SHRINK, DIP-64;
| 型号： | HD6473298VC |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | UVPROM, 5MHz, MICROCONTROLLER, CDIP64, WINDOWED, SHRINK, DIP-64 可编程只读存储器 时钟 CD 外围集成电路 |
| 文件： | 总321页 (文件大小：1040K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OMC942723054
HITACHI SINGLE-CHIP MICROCOMPUTER
H8/329 SERIES
H8/329
HD6473298, HD6433298, HD6413298
H8/328
HD6433288
H8/327
HD6473278, HD6433278, HD6413278
H8/326
HD6433268
HARDWARE MANUAL
Preface
The H8/329 Series is a series of high-performance single-chip microcomputers having a fast
H8/300 CPU core and a set of on-chip supporting functions optimized for embedded control.
These include ROM, RAM, two types of timers, a serial communication interface, an A/D
converter, I/O ports, and other functions needed in control system configurations, so that compact,
high-performance systems can be realized easily. The H8/329 Series includes four chips: the
H8/329 with 32K-byte ROM and 1K-byte RAM; the H8/328 with 24K-byte ROM and 1K-byte
RAM; the H8/327 with 16K-byte ROM and 512-byte RAM; and the H8/326 with 8K-byte ROM
and 256-byte RAM.
The H8/329 and H8/327 are available in a masked ROM version, a ZTAT™* (Zero Turn-Around
Time) version, and a ROMless version, providing a quick and flexible response to conditions from
ramp-up through full-scale volume producion, even for applications with frequently-changing
specifications.
This manual describes the hardware of the H8/329 Series. Refer to the H8/300 Series
Programming Manual for a detailed description of the instruction set.
Notes: * ZTAT is a registered trademark of Hitachi, Ltd.
Contents
Section 1. Overview...............................................................................................................
1.1 Overview...............................................................................................................................
1.2 Block Diagram......................................................................................................................
1.3 Pin Assignments and Functions............................................................................................
1.3.1 Pin Arrangement......................................................................................................
1.3.2 Pin Functions...........................................................................................................
1
1
5
6
6
8
Section 2. MCU Operating Modes and Address Space................................................ 15
2.1 Overview............................................................................................................................... 15
2.1.1 Mode Selection........................................................................................................ 15
2.1.2 Mode and System Control Registers (MDCR and SYSCR) ................................... 16
2.2 System Control Register (SYSCR)—H'FFC4...................................................................... 16
2.3 Mode Control Register (MDCR)—H'FFC5 ......................................................................... 18
2.4 Address Space Maps............................................................................................................. 19
Section 3. CPU........................................................................................................................ 23
3.1 Overview............................................................................................................................... 23
3.1.1 Features.................................................................................................................... 23
3.2 Register Configuration.......................................................................................................... 24
3.2.1 General Registers..................................................................................................... 24
3.2.2 Control Registers..................................................................................................... 25
3.2.3 Initial Register Values.............................................................................................. 26
3.3 Addressing Modes ................................................................................................................ 27
3.3.1 Addressing Mode..................................................................................................... 27
3.3.2 How to Calculate Where the Execution Starts ........................................................ 29
3.4 Data Formats......................................................................................................................... 33
3.4.1 Data Formats in General Registers.......................................................................... 34
3.4.2 Memory Data Formats............................................................................................. 35
3.5 Instruction Set....................................................................................................................... 36
3.5.1 Data Transfer Instructions ....................................................................................... 38
3.5.2 Arithmetic Operations ............................................................................................. 40
3.5.3 Logic Operations ..................................................................................................... 41
3.5.4 Shift Operations....................................................................................................... 41
3.5.5 Bit Manipulations .................................................................................................... 43
3.5.6 Branching Instructions............................................................................................. 47
3.5.7 System Control Instructions .................................................................................... 49
i
3.5.8 Block Data Transfer Instruction .............................................................................. 50
3.6 CPU States............................................................................................................................ 51
3.6.1 Program Execution State ......................................................................................... 52
3.6.2 Exception-Handling State........................................................................................ 52
3.6.3 Power-Down State................................................................................................... 53
3.7 Access Timing and Bus Cycle.............................................................................................. 53
3.7.1 Access to On-Chip Memory (RAM and ROM) ...................................................... 53
3.7.2 Access to On-Chip Register Field and External Devices........................................ 55
Section 4. Exception Handling............................................................................................ 59
4.1 Overview............................................................................................................................... 59
4.2 Reset ..................................................................................................................................... 59
4.2.1 Overview ................................................................................................................. 59
4.2.2 Reset Sequence........................................................................................................ 59
4.2.3 Disabling of Interrupts after Reset........................................................................... 62
4.3 Interrupts............................................................................................................................... 62
4.3.1 Overview ................................................................................................................. 62
4.3.2 Interrupt-Related Registers...................................................................................... 64
4.3.3 External Interrupts................................................................................................... 66
4.3.4 Internal Interrupts .................................................................................................... 67
4.3.5 Interrupt Handling ................................................................................................... 67
4.3.6 Interrupt Response Time.......................................................................................... 72
4.3.7 Precaution................................................................................................................ 72
4.4 Note on Stack Handling........................................................................................................ 73
Section 5. I/O Ports................................................................................................................ 75
5.1 Overview............................................................................................................................... 75
5.2 Port 1..................................................................................................................................... 77
5.3 Port 2..................................................................................................................................... 80
5.4 Port 3..................................................................................................................................... 84
5.5 Port 4..................................................................................................................................... 88
5.6 Port 5..................................................................................................................................... 96
5.7 Port 6.....................................................................................................................................100
5.8 Port 7..................................................................................................................................... 111
Section 6. 16-Bit Free-Running Timer.............................................................................. 113
6.1 Overview............................................................................................................................... 113
6.1.1 Features.................................................................................................................... 113
ii
6.1.2 Block Diagram......................................................................................................... 113
6.1.3 Input and Output Pins.............................................................................................. 115
6.1.4 Register Configuration ............................................................................................ 115
6.2 Register Descriptions............................................................................................................ 116
6.2.1 Free-Running Counter (FRC)—H'FF92.................................................................. 116
6.2.2 Output Compare Registers A and B (OCRA and OCRB)—H'FF94....................... 117
6.2.3 Input Capture Registers A to D (ICRA to ICRD)—
H'FF98, H'FF9A, H'FF9C, H'FF9E......................................................................... 117
6.2.4 Timer Interrupt Enable Register (TIER)—H'FF90 .................................................120
6.2.5 Timer Control/Status Register (TCSR)—H'FF91 ...................................................122
6.2.6 Timer Control Register (TCR)—H'FF96 ................................................................125
6.2.7 Timer Output Compare Control Register (TOCR)—H'FF97..................................127
6.3 CPU Interface .......................................................................................................................128
6.4 Operation ..............................................................................................................................130
6.4.1 FRC Incrementation Timing....................................................................................130
6.4.2 Output Compare Timing..........................................................................................132
6.4.3 Input Capture Timing ..............................................................................................133
6.4.4 Setting of FRC Overflow Flag (OVF).....................................................................136
6.5 Interrupts...............................................................................................................................137
6.6 Sample Application...............................................................................................................137
6.7 Application Notes .................................................................................................................138
Section 7. 8-Bit Timers .........................................................................................................143
7.1 Overview...............................................................................................................................143
7.1.1 Features....................................................................................................................143
7.1.2 Block Diagram.........................................................................................................143
7.1.3 Input and Output Pins..............................................................................................144
7.1.4 Register Configuration ............................................................................................145
7.2 Register Descriptions............................................................................................................145
7.2.1 Timer Counter (TCNT)—H'FFCC (TMR0), H'FFD4 (TMR1)...............................145
7.2.2 Time Constant Registers A and B (TCORA and TCORB)—
H'FFCA and H'FFCB (TMR0), H'FFD2 and H'FFD3 (TMR1)..............................146
7.2.3 Timer Control Register (TCR)—H'FFC8 (TMR0), H'FFD0 (TMR1) ....................146
7.2.4 Timer Control/Status Register (TCSR)—H'FFC9 (TMR0), H'FFD1 (TMR1).......149
7.2.5 Serial/Timer Control Register (STCR)—H'FFC3 ...................................................151
7.3 Operation ..............................................................................................................................152
7.3.1 TCNT Incrementation Timing.................................................................................152
7.3.2 Compare Match Timing...........................................................................................153
iii
7.3.3 External Reset of TCNT..........................................................................................155
7.3.4 Setting of TCSR Overflow Flag (OVF) ..................................................................156
7.4 Interrupts...............................................................................................................................157
7.5 Sample Application...............................................................................................................157
7.6 Application Notes .................................................................................................................158
Section 8. Serial Communication Interface .....................................................................163
8.1 Overview...............................................................................................................................163
8.1.1 Features....................................................................................................................163
8.1.2 Block Diagram.........................................................................................................164
8.1.3 Input and Output Pins..............................................................................................164
8.1.4 Register Configuration ............................................................................................165
8.2 Register Descriptions............................................................................................................166
8.2.1 Receive Shift Register (RSR)..................................................................................166
8.2.2 Receive Data Register (RDR)—H'FFDD................................................................166
8.2.3 Transmit Shift Register (TSR).................................................................................166
8.2.4 Transmit Data Register (TDR)—H'FFDB...............................................................167
8.2.5 Serial Mode Register (SMR)—H'FFD8 ..................................................................167
8.2.6 Serial Control Register (SCR)—H'FFDA ...............................................................170
8.2.7 Serial Status Register (SSR)—H'FFDC ..................................................................174
8.2.8 Bit Rate Register (BRR)—H'FFD9.........................................................................177
8.2.9 Serial/Timer Control Register (STCR)—H'FFC3 ...................................................181
8.3 Operation ..............................................................................................................................182
8.3.1 Overview .................................................................................................................182
8.3.2 Asynchronous Mode................................................................................................184
8.3.3 Clocked Synchronous Operation.............................................................................197
8.4 SCI Interrupts........................................................................................................................206
8.5 Application Notes .................................................................................................................206
Section 9. A/D Converter .....................................................................................................209
9.1 Overview...............................................................................................................................209
9.1.1 Features....................................................................................................................209
9.1.2 Block Diagram.........................................................................................................210
9.1.3 Input Pins................................................................................................................. 211
9.1.4 Register Configuration ............................................................................................ 211
9.2 Register Descriptions............................................................................................................212
9.2.1 A/D Data Registers (ADDR)—H'FFE0 to H'FFE6.................................................212
9.2.2 A/D Control/Status Register (ADCSR)—H'FFE8 ..................................................212
iv
9.2.3 A/D Control Register (ADCR)—H'FFEA...............................................................215
9.3 Operation ..............................................................................................................................215
9.3.1 Single Mode (SCAN = 0)........................................................................................216
9.3.2 Scan Mode (SCAN = 1) ..........................................................................................219
9.3.3 Input Sampling Time and A/D Conversion Time....................................................222
9.3.4 External Trigger Input Timing.................................................................................223
9.4 Interrupts...............................................................................................................................224
Section 10. RAM.......................................................................................................................225
10.1 Overview...............................................................................................................................225
10.2 Block Diagram......................................................................................................................225
10.3 RAM Enable Bit (RAME) in System Control Register (SYSCR) .......................................225
10.4 Operation ..............................................................................................................................226
10.4.1 Expanded Modes (Modes 1 and 2)..........................................................................226
10.4.2 Single-Chip Mode (Mode 3) ...................................................................................226
Section 11. ROM.......................................................................................................................227
11.1 Overview...............................................................................................................................227
11.1.1 Block Diagram.........................................................................................................228
11.2 PROM Mode (H8/329, H8/327)...........................................................................................228
11.2.1 PROM Mode Setup .................................................................................................228
11.2.2 Socket Adapter Pin Assignments and Memory Map...............................................229
11.3 Programming ........................................................................................................................232
11.3.1 Writing and Verifying..............................................................................................232
11.3.2 Notes on Writing......................................................................................................236
11.3.3 Reliability of Written Data ......................................................................................236
11.3.4 Erasing of Data........................................................................................................237
11.4 Handling of Windowed Packages.........................................................................................238
Section 12. Power-Down State..............................................................................................239
12.1 Overview...............................................................................................................................239
12.2 System Control Register: Power-Down Control Bits...........................................................240
12.3 Sleep Mode ...........................................................................................................................241
12.3.1 Transition to Sleep Mode.........................................................................................242
12.3.2 Exit from Sleep Mode .............................................................................................242
12.4 Software Standby Mode........................................................................................................242
12.4.1 Transition to Software Standby Mode.....................................................................243
12.4.2 Exit from Software Standby Mode..........................................................................243
v
12.4.3 Sample Application of Software Standby Mode.....................................................243
12.4.4 Application Note .....................................................................................................244
12.5 Hardware Standby Mode ......................................................................................................245
12.5.1 Transition to Hardware Standby Mode....................................................................245
12.5.2 Recovery from Hardware Standby Mode................................................................245
12.5.3 Timing Relationships...............................................................................................246
Section 13. Clock Pulse Generator.......................................................................................247
13.1 Overview...............................................................................................................................247
13.1.1 Block Diagram.........................................................................................................247
13.2 Oscillator Circuit...................................................................................................................247
13.3 System Clock Divider...........................................................................................................250
Section 14. Electrical Specifications....................................................................................251
14.1 Absolute Maximum Ratings.................................................................................................251
14.2 Electrical Characteristics ......................................................................................................251
14.2.1 DC Characteristics...................................................................................................251
14.2.2 AC Characteristics...................................................................................................257
14.2.3 A/D Converter Characteristics.................................................................................261
14.3 MCU Operational Timing.....................................................................................................262
14.3.1 Bus Timing ..............................................................................................................262
14.3.2 Control Signal Timing.............................................................................................263
14.3.3 16-Bit Free-Running Timer Timing ........................................................................266
14.3.4 8-Bit Timer Timing..................................................................................................267
14.3.5 Serial Communication Interface Timing .................................................................268
14.3.6 I/O Port Timing........................................................................................................269
Appendices
Appendix A. CPU Instruction Set......................................................................................271
A.1 Instruction Set List................................................................................................................271
A.2 Operation Code Map.............................................................................................................278
A.3 Number of States Required for Execution............................................................................280
Appendix B. Register Field.................................................................................................286
B.1 Register Addresses and Bit Names.......................................................................................286
B.2 Register Descriptions............................................................................................................290
vi
Appendix C. Pin States.........................................................................................................317
C.1 Pin States in Each Mode.......................................................................................................317
Appendix D. Timing of Transition to and Recovery from Hardware
Standby Mode................................................................................................319
Appendix E. Package Dimensions ....................................................................................320
vii
Section 1. Overview
1.1 Overview
The H8/329 Series of single-chip microcomputers features an H8/300 CPU core and a complement
of on-chip supporting modules implementing a variety of system functions.
The H8/300 CPU is a high-speed processor with an architecture featuring powerful bit-
manipulation instructions, ideally suited for realtime control applications. The on-chip supporting
modules implement peripheral functions needed in system configurations. These include ROM,
RAM, two types of timers (a 16-bit free-running timer and 8-bit timers), a serial communication
interface (SCI), an A/D converter, and I/O ports.
The H8/329 Series can operate in a single-chip mode or in two expanded modes, depending on the
requirements of the application. (The operating mode will be referred to as the MCU mode in this
manual.)
The entire H8/329 Series is available with masked ROM. The H8/329 and H8/327 are also
available in ZTAT™ versions* that can be programmed at the user site, and in ROMless versions.
Notes: * ZTAT is a registered trademark of Hitachi, Ltd.
Table 1-1 lists the features of the H8/329 Series.
1
Table 1-1. Features
Item
Specification
CPU
Two-way general register configuration
• Eight 16-bit registers, or
• Sixteen 8-bit registers
High-speed operation
• Maximum clock rate: 10MHz
• Add/subtract:
0.2µs
1.4µs
• Multiply/divide:
Streamlined, concise instruction set
• Instruction length: 2 or 4 bytes
• Register-register arithmetic and logic operations
• MOV instruction for data transfer between registers and memory
Instruction set features
• Multiply instruction (8 bits × 8 bits)
• Divide instruction (16 bits ÷ 8 bits)
• Bit-accumulator instructions
• Register-indirect specification of bit positions
• H8/329: 32k-byte ROM; 1k-byte RAM
• H8/328: 24k-byte ROM; 1k-byte RAM
• H8/327: 16k-byte ROM; 512-byte RAM
• H8/326: 8k-byte ROM; 256-byte RAM
• One 16-bit free-running counter (can also count external events)
• Two output-compare lines
Memory
16-bit free-
running timer
(1 channel)
8-bit timer
• Four input capture lines (can be buffered)
Each channel has
(2 channels)
• One 8-bit up-counter (can also count external events)
• Two time constant registers
Serial
• Asynchronous or clocked synchronous mode (selectable)
• Full duplex: can transmit and receive simultaneously
• On-chip baud rate generator
communication
interface (SCI)
(1 channel)
2
Table 1-1. Features (cont.)
Item
Specification
A/D converter
• 8-bit resolution
• Eight channels: single or scan mode (selectable)
• Start of A/D conversion can be externally triggered
• Sample-and-hold function
I/O ports
Interrupts
• 43 input/output lines (16 of which can drive LEDs)
• 8 input-only lines
• Four external interrupt lines: NMI, IRQ0, IRQ1, IRQ2
• 18 on-chip interrupt sources
Operating
modes
• Expanded mode with on-chip ROM disabled (mode 1)
• Expanded mode with on-chip ROM enabled (mode 2)
• Single-chip mode (mode 3)
Power-down
modes
• Sleep mode
• Software standby mode
• Hardware standby mode
Other features
• On-chip oscillator
3
Table 1-1. Features (cont.)
Item
Specification
Series lineup
5-V version
3-V version
Package
ROM
H8/329 HD6473298C
HD6473298VC
64-pin windowed shrink DIP PROM
(DC-64S)
HD6473298P
HD6473298F
HD6473298VP
HD6473298VF
HD6473298VCP
HD6433298VP
HD6433298VF
HD6433298VCP
HD6413298VP
HD6413298VF
HD6413298VCP
HD6433288VP
HD6433288VF
HD6433288VCP
HD6473278VC
64-pin shrink DIP (DP-64S)
64-pin QFP (FP-64A)
HD6473298CP
HD6433298P
68-pin PLCC (CP-68)
64-pin shrink DIP (DP-64S)
64-pin QFP (FP-64A)
68-pin PLCC (CP-68)
64-pin shrink DIP (DP-64S)
64-pin QFP (FP-64A)
68-pin PLCC (CP-68)
64-pin shrink DIP (DP-64S)
64-pin QFP (FP-64A)
68-pin PLCC (CP-68)
Masked ROM
HD6433298F
HD6433298CP
HD6413298P
ROMless
HD6413298F
HD6413298CP
H8/328 HD6433288P
HD6433288F
Masked ROM
HD6433288CP
H8/327 HD6473278C
64-pin windowed shrink DIP PROM
(DC-64S)
HD6473278P
HD6473278F
HD6473278VP
HD6473278VF
HD6473278VCP
HD6433278VP
HD6433278VF
HD6433278VCP
HD6413278VP
HD6413278VF
HD6413278VCP
HD6433268VP
HD6433268VF
HD6433268VCP
64-pin shrink DIP (DP-64S)
64-pin QFP (FP-64A)
HD6473278CP
HD6433278P
68-pin PLCC (CP-68)
64-pin shrink DIP (DP-64S)
64-pin QFP (FP-64A)
68-pin PLCC (CP-68)
64-pin shrink DIP (DP-64S)
64-pin QFP (FP-64A)
68-pin PLCC (CP-68)
64-pin shrink DIP (DP-64S)
64-pin QFP (FP-64A)
68-pin PLCC (CP-68)
Masked ROM
HD6433278F
HD6433278CP
HD6413278P
ROMless
HD6413278F
HD6413278CP
H8/326 HD6433268P
HD6433268F
Masked ROM
HD6433268CP
4
1.2 Block Diagram
Figure 1-1 shows a block diagram of the H8/329 Series.
*1
Clock
pulse
gener-
ator
CPU
H8/300
Data bus (Low)
P40 /IRQ2/ADTRG
P41 /IRQ1
P42 /IRQ0
P43 /RD
P44 /WR
P45 /AS
P10/A0
P11/A1
P12/A2
P13/A3
P14/A4
P15/A5
P16/A6
P17/A7
PROM *2
(or masked ROM)
RAM
P46 /Ø
P47 /WAIT
Serial
communication
interface
16-bit free-
running timer
P30/D0
P31/D1
P32/D2
P33/D3
P34/D4
P35/D5
P36/D6
P37/D7
P20/A8
P21/A9
P22 /A10
P23 /A11
P24 /A12
P25 /A13
P26 /A14
P27 /A15
8-bit timer
(2 channels)
8-bit A/D converter
(8 channels)
Port 6
Port 7
Port 5
Memory Sizes
Notes: *1 CP-68 package only.
*2 PROM is available only in
the H8/329 and H8/327.
H8/329
H8/328
H8/327
H8/326
ROM
RAM
32k bytes
1k byte
24k bytes
1k byte
16k bytes
512 bytes
8k bytes
256 bytes
Figure 1-1. Block Diagram
5
1.3 Pin Assignments and Functions
1.3.1 Pin Arrangement
Figure 1-2 shows the pin arrangement of the DC-64S and DP-64S packages. Figure 1-3 shows the
pin arrangement of the FP-64A package. Figure 1-4 shows the pin arrangement of the CP-68
package.
P40/ADTRG/IRQ2
P41/IRQ1
P42/IRQ0
P43/RD
P44/WR
P45/AS
P46/Ø
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P37/D7
2
P36/D6
3
P35/D5
4
P34/D4
5
P33/D3
6
P32/D2
7
P31/D1
P47/WAIT
P50/TxD
P51/RxD
P52/SCK
RES
8
P30/D0
9
P10/A0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P11/A1
P12/A2
P13/A3
NMI
P14/A4
VCC
P15/A5
STBY
P16/A6
VSS
P17/A7
XTAL
VSS
EXTAL
MD1
P20/A8
P21/A9
MD0
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
VCC
AVSS
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
AVCC
P67/TMO1
P66/FTOB/TMRI1
P65/FTID/TMCI1
P64/FTIC/TMO0
P63/FTIB/TMRI0
P62/FTIA
P60/FTCI/TMCI0
P61/FTOA
Figure 1-2. Pin Arrangement (DC-64S and DP-64S, Top View)
6
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P50/TxD
P51/RxD
P52/SCK
RES
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P10/A0
P11/A1
P12/A2
P13/A3
P14/A4
P15/A5
P16/A6
P17/A7
VSS
2
3
4
NMI
5
VCC
6
STBY
VSS
7
8
XTAL
EXTAL
MD1
9
10
11
12
13
14
15
16
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
MD0
AVSS
P70/AN0
P71/AN1
P72/AN2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 1-3. Pin Arrangement (FP-64A, Top View)
7
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
P50/TxD
P51/RxD
P52/SCK
RES
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
P10/A0
P11/A1
P12/A2
P13/A3
P14/A4
P15/A5
P16/A6
P17/A7
VSS
NMI
VCC
STBY
VSS
VSS
XTAL
EXTAL
MD1
VSS
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
MD0
AVSS
P70/AN0
P71/AN1
P72/AN2
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Figure 1-4. Pin Arrangement (CP-68, Top View)
8
1.3.2 Pin Functions
(1) Pin Assignments in Each Operating Mode: Table 1-2 lists the assignments of the pins of the
DC-64S, DP-64S, FP-64A, and CP-68 packages in each operating mode.
Table 1-2. Pin Assignments in Each Operating Mode (1)
Pin No.
DC-64S
Expanded modes
Mode 2
Single-chip mode
Mode 3
VSS
PROM
mode
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VPP
EA9
VCC
VSS
VSS
VSS
NC
NC
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
DP-64S FP-64A CP-68
Mode 1
VSS
—
1
—
57
58
59
60
61
62
63
64
1
1
VSS
2
P40/IRQ2/ADTRG
P41/IRQ1
P42/IRQ0
RD
P40/IRQ2/ADTRG
P41/IRQ1
P42/IRQ0
RD
P40/IRQ2/ADTRG
P41/IRQ1
P42/IRQ0
P43
2
3
3
4
4
5
5
6
WR
WR
P44
6
7
AS
AS
P45
7
8
Ø
Ø
P46/Ø
8
9
WAIT
WAIT
P47
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
P50/TxD
P51/RxD
P52/SCK
RES
P50/TxD
P51/RxD
P52/SCK
RES
P50/TxD
P51/RxD
P52/SCK
RES
10
11
12
13
14
15
16
—
17
18
19
20
21
22
23
24
25
26
27
28
29
2
3
4
5
NMI
NMI
NMI
6
VCC
VCC
VCC
7
STBY
VSS
STBY
VSS
STBY
8
VSS
—
9
VSS
VSS
VSS
XTAL
EXTAL
MD1
XTAL
EXTAL
MD1
XTAL
10
11
12
13
14
15
16
17
18
19
20
21
EXTAL
MD1
MD0
MD0
MD0
AVSS
AVSS
AVSS
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
Notes: 1. Pins marked NC should be left unconnected.
2. For details on PROM mode, refer to 11.2, “PROM Mode.”
9
Table 1-2. Pin Assignments in Each Operating Mode (2)
Pin No.
DC-64S
Expanded modes
Mode 2
Single-chip mode
PROM
mode
VCC
NC
DP-64S FP-64A CP-68
Mode 1
Mode 3
30
31
32
—
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
—
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
22
23
24
—
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
—
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
AVCC
AVCC
AVCC
P60/FTCI/TMCI0
P60/FTCI/TMCI0
P61/FTOA
VSS
P60/FTCI/TMCI0
P61/FTOA
P61/FTOA
NC
VSS
VSS
VSS
P62/FTIA
P62/FTIA
P63/FTIB/TMRI0
P64/FTIC/TMO0
P65/FTID/TMCI1
P66/FTOB/TMRI1
P67/TMO1
VCC
P62/FTIA
NC
P63/FTIB/TMRI0
P63/FTIB/TMRI0
VCC
VCC
NC
P64/FTIC/TMO0
P64/FTIC/TMO0
P65/FTID/TMCI1
P65/FTID/TMCI1
P66/FTOB/TMRI1
P66/FTOB/TMRI1
NC
P67/TMO1
VCC
A15
A14
A13
A12
A11
A10
A9
P67/TMO1
VCC
P27
P26
P25
P24
P23
P22
P21
P20
VSS
VSS
P17
P16
P15
P14
P13
P12
P11
P10
P30
P31
P32
P33
P34
P35
P36
P37
NC
VCC
CE
A27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
VSS
EA14
EA13
EA12
EA11
EA10
OE
A8
EA8
VSS
VSS
VSS
A7
VSS
VSS
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
D0
EA7
EA6
EA5
EA4
EA3
EA2
EA1
EA0
EO0
EO1
EO2
EO3
EO4
EO5
EO6
EO7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Notes: 1. Pins marked NC should be left unconnected.
2. For details on PROM mode, refer to 11.2, “PROM Mode.”
10
(2) Pin Functions: Table 1-3 gives a concise description of the function of each pin.
Table 1-3. Pin Functions (1)
Pin No.
DC-64S
Type
Symbol
DP-64S FP-64A CP-68
I/O Name and function
Power
VCC
14, 39
16, 48
17
6, 31
8, 40
9
15, 42
I
I
I
Power: Connected to the power supply
(+5V). Connect both VCC pins to the
system power supply (+5V).
VSS
1, 17, 18,
35, 51, 52
Ground: Connected to ground (0V).
Connect all VSS pins to the system power
supply (0V).
Clock
XTAL
19
Crystal: Connected to a crystal oscillator.
The crystal frequency should be double
the desired system clock frequency.
If an external clock is input at the EXTAL
pin, a reverse-phase clock should be input
at the XTAL pin.
EXTAL
18
10
20
I
External crystal: Connected to a crystal
oscillator or external clock. The frequency
of the external clock should be double the
desired system clock frequency. See
section 13.2, “Oscillator Circuit” for
examples of connections to a crystal and
external clock.
Ø
7
63
4
8
O
I
System clock: Supplies the system clock
to peripheral devices.
System
control
RES
STBY
12
15
13
16
Reset: A Low input causes the chip to
reset.
7
I
Standby: A transition to the hardware
standby mode (a power-down state) occurs
when a Low input is received at the STBY
pin.
Address
bus
A15 to A0
40 to 47, 32 to 39, 43 to 50,
49 to 56 41 to 48 53 to 60
O
Address bus: Address output pins.
11
Table 1-3. Pin Functions (2)
DC-64S
Pin No.
Type
Symbol
D7 to D0
WAIT
DP-64S FP-64A CP-68
I/O Name and function
Data bus
Bus
57 to 64 49 to 56 61 to 68
I/O Data bus: 8-Bit bidirectional data bus.
8
64
9
I
Wait: Requests the CPU to insert TW
states into the bus cycle when an external
address is accessed.
control
RD
WR
AS
4
5
6
60
61
62
5
6
7
O
O
O
Read: Goes Low to indicate that the CPU
is reading an external address.
Write: Goes Low to indicate that the CPU
is writing to an external address.
Address Strobe: Goes Low to indicate
that there is a valid address on the address
bus.
Interrupt
signals
NMI
13
5
14
I
NonMaskable Interrupt: Highest-
priority interrupt request. The NMIEG bit
in the system control register (SYSCR)
determines whether the interrupt is
requested on the rising or falling edge of
the NMI input.
IRQ0 to
IRQ2
1 to 3
57 to 59 2 to 4
I
I
Interrupt Request 0 to 2: Maskable
interrupt request pins.
Operating MD1,
19,
20
11,
12
21,
22
Mode: Input pins for setting the MCU
operating mode according to the table
below.
mode
MD0
control
MD1 MD0 Mode
Description
0
1
1
1
0
1
Mode 1 Expanded mode
with on-chip ROM
disabled
Mode 2 Expanded mode
with on-chip ROM
enabled
Mode 3 Single-chip mode
12
Table 1-3. Pin Functions (3)
DC-64S
Pin No.
Type
Symbol
DP-64S FP-64A CP-68
I/O Name and function
Serial com- TxD
munication
9
1
2
3
10
11
12
O
Transmit Data: Data output pin for the
serial communication interface.
interface
RxD
10
11
I
Receive Data: Data input pin for the
serial communication interface.
SCK
I/O Serial ClocK: Input/output pin for the
serial clock.
16-bit free- FTOA,
32,
37
24,
29
34,
40
O
I
FRT Output compare A and B: Output
pins controlled by comparators A and B
of the free-running timer.
running
timer
FTOB
FTCI
31
23
33
FRT counter Clock Input: Input pin
for an external clock signal for the
free-running timer.
FTIA to
FTID
33 to 36 25 to 28 36 to 39
I
FRT Input capture A to D: Input capture
pins for the free-running timer.
8-bit TiMer Output: Compare-match
output pins for the 8-bit timers.
8-bit TiMer counter Clock Input:
External clock input pins for the 8-bit
timer counters.
8-bit
TMO0,
TMO1
TMCI0,
TMCI1
35,
38
27,
30
38,
41
O
I
timer
31,
36
23,
28
33,
39
TMRI0,
TMRI1
34,
37
26,
29
37,
40
I
8-bit TiMer counter Reset Input:
A High input at these pins resets the 8-bit
timer counters.
A/D
AN7 to AN0 22 to 29 14 to 21 24 to 31
I
I
I
ANalog input: Analog signal input pins
for the A/D converter.
converter
ADTRG
AVCC
1
57
22
2
A/D Trigger: External trigger input for
starting the A/D converter.
30
32
Analog reference Voltage: Reference
voltage pin for the A/D converter. If the
A/D converter is not used, connect AVCC
to the system power supply (+5V).
Analog ground: Ground pin for the A/D
converter.
AVSS
21
13
23
I
13
Table 1-3. Pin Functions (4)
DC-64S
Pin No.
Type
Symbol
DP-64S FP-64A CP-68
I/O Name and function
General-
purpose
I/O
P17 to P10 49 to 56 41 to 48 53 to 60
P27 to P20 40 to 47 32 to 39 43 to 50
P37 to P30 57 to 64 49 to 56 61 to 68
I/O Port 1: An 8-bit input/output port with
programmable MOS input pull-ups and
LED driving capability. The direction of
each bit can be selected in the port 1 data
direction register (P1DDR).
I/O Port 2: An 8-bit input/output port with
programmable MOS input pull-ups and
LED driving capability. The direction of
each bit can be selected in the port 2 data
direction register (P2DDR).
I/O Port 3: An 8-bit input/output port with
programmable MOS input pull-ups. The
direction of each bit can be selected in the
port 3 data direction register (P3DDR).
I/O Port 4: An 8-bit input/output port. The
direction of each bit can be selected in the
port 4 data direction register (P4DDR).
I/O Port 5: A 3-bit input/output port. The
direction of each bit can be selected in the
port 5 data direction register (P5DDR).
I/O Port 6: An 8-bit input/output port. The
direction of each bit can be selected in the
port 6 data direction register (P6DDR).
P47 to P40 1 to 8
57 to 64 2 to 9
P52 to P50 9 to 11 1 to 3
10 to 12
P67 to P60 31 to 38 23 to 30 33, 34,
36 to 41
P77 to P70 22 to 29 14 to 21 24 to 31
I
Port 7: An 8-bit input port.
14
Section 2. MCU Operating Modes and Address Space
2.1 Overview
2.1.1 Mode Selection
The H8/329 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the
inputs at the mode pins (MD1 and MD0) when the chip comes out of a reset. See table 2-1.
The ROMless versions (HD6413298 and HD6413278) can be used only in mode 1 (expanded mode
with on-chip ROM disabled.)
Table 2-1. Operating Modes
Mode
MD1
Low
Low
High
High
MD0
Low
High
Low
High
Address space
—
On-chip ROM
—
On-chip RAM
—
Mode 0
Mode 1
Mode 2
Mode 3
Expanded
Expanded
Single-chip
Disabled
Enabled
Enabled
Enabled*
Enabled*
Enabled
Note: * If the RAME bit in the system control register (SYSCR) is cleared to 0, off-chip memory
can be accessed instead.
Modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices.
The maximum address space supported by these externally expanded modes is 64K bytes.
In mode 3 (single-chip mode), only on-chip ROM and RAM and the on-chip register field are used.
All ports are available for general-purpose input and output.
Mode 0 is inoperative in the H8/329 Series. Avoid setting the mode pins to mode 0.
15
2.1.2 Mode and System Control Registers (MDCR and SYSCR)
Table 2-2 lists the registers related to the operating mode: the system control register (SYSCR) and
mode control register (MDCR). The mode control register indicates the inputs to the mode pins
MD1 and MD0.
Table 2-2. Mode and System Control Registers
Name
Abbreviation
SYSCR
Read/Write
Address
H'FFC4
H'FFC5
System control register
Mode control register
R/W
R
MDCR
2.2 System Control Register (SYSCR)—H'FFC4
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
—
1
2
NMIEG
0
1
—
1
0
RAME
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
—
R/W
—
R/W
The system control register (SYSCR) is an 8-bit register that controls the operation of the chip.
Bit 7—Software Standby (SSBY): Enables transition to the software standby mode. For details,
see section 12, “Power-Down State.”
On recovery from software standby mode by an external interrupt, the SSBY bit remains set to “1.”
It can be cleared by writing “0.”
Bit 7
SSBY
Description
0
1
The SLEEP instruction causes a transition to sleep mode.
The SLEEP instruction causes a transition to software standby mode.
(Initial value)
16
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from the software standby mode by an external interrupt. During the
selected time the CPU and on-chip supporting modules continue to stand by. These bits should be
set according to the clock frequency so that the settling time is at least 10ms. For specific settings,
see section 12.2, “System Control Register: Power-Down Control Bits.”
Bit 6
Bit 5
Bit 4
STS2 STS1 STS0
Description
0
0
0
0
1
0
0
0
1
Settling time = 8192 states
Settling time = 16384 states
Settling time = 32768 states
Settling time = 65536 states
Settling time = 131072 states
(Initial value)
1
0
1
1
—
—
Bit 3—Reserved: This bit cannot be modified and is always read as “1.”
Bit 2—NMI Edge (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG Description
0
1
An interrupt is requested on the falling edge of the NMI input.
An interrupt is requested on the rising edge of the NMI input.
(Initial value)
Bit 1—Reserved: This bit cannot be modified and is always read as “1.”
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized
by a reset, but is not initialized in the software standby mode.
Bit 0
RAME
Description
0
1
The on-chip RAM is disabled.
The on-chip RAM is enabled.
(Initial value)
17
2.3 Mode Control Register (MDCR)—H'FFC5
Bit
7
—
1
6
—
1
5
—
1
4
—
0
3
—
0
2
—
1
1
0
MDS1 MDS0
Initial value
Read/Write
*
*
—
—
—
—
—
—
R
R
Note: * Initialized according to MD1 and MD0 inputs.
The mode control register (MDCR) is an eight-bit register that indicates the operating mode of the
chip.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as “1.”
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as “0.”
Bit 2—Reserved: This bit cannot be modified and is always read as “1.”
Bits 1 and 0—Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the
mode pins (MD1 and MD0), thus indicating the current operating mode of the chip. MDS1
corresponds to MD1 and MDS0 to MD0. These bits can be read but not written. When the mode
control register is read, the levels at the mode pins (MD1 and MD0) are latched in these bits.
18
2.4 Address Space Maps
Figures 2-1 to 2-4 show memory maps of the H8/329, H8/328, H8/327, and H8/326 in modes 1, 2,
and 3.
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
H'0000
H'0000
H'0000
Vector Table
Vector Table
Vector Table
H'0047
H'0048
H'0047
H'0048
H'0047
H'0048
On-Chip ROM,
32k bytes
On-Chip ROM,
32k bytes
External Address Space
H'7FFF
H'8000
H'7FFF
External Address Space
H'FB7F
H'FB80
H'FB7F
H'FB80
H'FB80
H'FF7F
*
*
On-Chip RAM ,
On-Chip RAM ,
On-Chip RAM,
1k byte
1k byte
1k byte
H'FF7F
H'FF80
H'FF87
H'FF88
H'FF7F
H'FF80
H'FF87
H'FF88
External Address Space
On-Chip Register Field
External Address Space
On-Chip Register Field
H'FF88
H'FFFF
On-Chip Register Field
H'FFFF
H'FFFF
Note: * External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Figure 2-1. H8/329 Address Space Map
19
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
H'0000
H'0000
H'0000
Vector Table
Vector Table
Vector Table
H'0047
H'0048
H'0047
H'0048
H'0047
H'0048
On-Chip ROM,
24k bytes
On-Chip ROM,
24k bytes
H'5FFF
H'6000
H'5FFF
External Address Space
Reserved*1
H'7FFF
H'8000
External Address Space
H'FB7F
H'FB80
H'FB7F
H'FB80
H'FB80
H'FF7F
On-Chip RAM*2,
1k byte
On-Chip RAM*2,
1k byte
On-Chip RAM, 1k byte
On-Chip Register Field
H'FF7F
H'FF80
H'FF87
H'FF88
H'FF7F
H'FF80
H'FF87
H'FF88
External Address Space
On-Chip Register Field
External Address Space
On-Chip Register Field
H'FF88
H'FFFF
H'FFFF
H'FFFF
Notes: *1 Do not access these reserved areas.
*2 External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Figure 2-2. H8/328 Address Space Map
20
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
H'0000
H'0000
H'0000
Vector Table
Vector Table
Vector Table
H'0047
H'0048
H'0047
H'0048
H'0047
H'0048
On-Chip ROM,
16k bytes
On-Chip ROM,
16k bytes
H'3FFF
H'4000
H'3FFF
External Address Space
Reserved*1
H'7FFF
H'8000
External Address Space
Reserved*1, *2
H'FB7F
H'FB80
H'FB7F
H'FB80
Reserved*1, *2
H'FD7F
H'FD80
H'FD7F
H'FD80
H'FD80
H'FF7F
On-Chip RAM*2,
512 Bytes
On-Chip RAM*2,
512 Bytes
On-Chip RAM,
512 Bytes
H'FF7F
H'FF80
H'FF87
H'FF88
H'FF7F
H'FF80
H'FF87
H'FF88
External Address Space
External Address Space
H'FF88
H'FFFF
On-Chip Register Field
On-Chip Register Field
On-Chip Register Field
H'FFFF
H'FFFF
Notes: *1 Do not access these reserved areas.
*2 External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Figure 2-3. H8/327 Address Space Map
21
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
H'0000
H'0000
H'0000
Vector Table
Vector Table
Vector Table
H'0047
H'0048
H'0047
H'0048
H'0047
H'0048
On-Chip ROM,
8k bytes
On-Chip ROM,
8k bytes
H'1FFF
H'2000
H'1FFF
External Address Space
Reserved*1
H'7FFF
H'8000
External Address Space
Reserved*1, *2
H'FB7F
H'FB80
H'FB7F
H'FB80
Reserved*1, *2
H'FE7F
H'FE80
H'FE7F
H'FE80
H'FE80
H'FF7F
On-Chip RAM*2,
256 Bytes
On-Chip RAM*2,
256 Bytes
On-Chip RAM,
256 Bytes
H'FF7F
H'FF80
H'FF87
H'FF88
H'FF7F
H'FF80
H'FF87
H'FF88
External Address Space
External Address Space
H'FF88
H'FFFF
On-Chip Register Field
On-Chip Register Field
On-Chip Register Field
H'FFFF
H'FFFF
Notes: *1 Do not access these reserved areas.
*2 External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Figure 2-4. H8/326 Address Space Map
22
Section 3. CPU
3.1 Overview
The H8/329 Series has the H8/300 CPU: a fast central processing unit with eight 16-bit general
registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-
speed operation.
3.1.1 Features
The main features of the H8/300 CPU are listed below.
• Two-way register configuration
— Sixteen 8-bit general registers, or
— Eight 16-bit general registers
• Instruction set with 57 basic instructions, including:
— Multiply and divide instructions
— Powerful bit-manipulation instructions
• Eight addressing modes
— Register direct (Rn)
— Register indirect (@Rn)
— Register indirect with displacement (@(d:16, Rn))
— Register indirect with post-increment or pre-decrement (@Rn+ or @–Rn)
— Absolute address (@aa:8 or @aa:16)
— Immediate (#xx:8 or #xx:16)
— PC-relative (@(d:8, PC))
— Memory indirect (@@aa:8)
• Maximum 64K-byte address space
• High-speed operation
— All frequently-used instructions are executed two to four states
— The maximum clock rate is 10MHz
— 8- or 16-bit register-register add or subtract: 0.2µs
— 8 × 8-bit multiply:
1.4µs
1.4µs
— 16 ÷ 8-bit divide:
• Power-down mode
— SLEEP instruction
23
3.2 Register Configuration
Figure 3-1 shows the register structure of the CPU. There are two groups of registers: the general
registers and control registers.
7
07
0
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
(SP)
SP: Stack Pointer
15
0
PC
PC: Program Counter
7 6 5 4 3 2 1 0
I U H U N Z V C
CCR: Condition Code Register
Carryflag
CCR
Overflow flag
Zero flag
Negative flag
Half-carryflag
Interrupt mask bit
User bit
User bit
Figure 3-1. CPU Registers
3.2.1 General Registers
All the general registers can be used as both data registers and address registers. When used as
address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as
data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed
separately as 8-bit registers (R0H to R7H and R0L to R7L).
R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and
subroutine calls. In assembly-language coding, R7 can also be denoted by the letters SP. As
indicated in figure 3-2, R7 (SP) points to the top of the stack.
24
Unused area
Stack area
SP
(R7)
Figure 3-2. Stack Pointer
3.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
(1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the
CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit of the
PC is ignored (always regarded as 0).
(2) Condition Code Register (CCR): This 8-bit register contains internal status information,
including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the interrupt
mask bit (I).
Bit 7—Interrupt Mask Bit (I): When this bit is set to “1,” all interrupts except NMI are masked.
This bit is set to “1” automatically by a reset and at the start of interrupt handling.
Bit 6—User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC,
ORC, and XORC instructions).
Bit 5—Half-Carry Flag (H): This flag is set to “1” when the ADD.B, ADDX.B, SUB.B,
SUBX.B, NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to “0”
otherwise. Similarly, it is set to “1” when the ADD.W, SUB.W, or CMP.W instruction causes a
carry or borrow out of bit 11, and cleared to “0” otherwise. It is used implicitly in the DAA and
DAS instructions.
Bit 4—User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC,
ORC, and XORC instructions).
25
Bit 3—Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): This flag is set to “1” to indicate a zero result and cleared to “0” to indicate
a nonzero result.
Bit 1—Overflow Flag (V): This flag is set to “1” when an arithmetic overflow occurs, and cleared
to “0” at other times.
Bit 0—Carry Flag (C): This flag is used by:
• Add and subtract instructions, to indicate a carry or borrow at the most significant bit of the
result
• Shift and rotate instructions, to store the value shifted out of the most significant or least
significant bit
• Bit manipulation and bit load instructions, as a bit accumulator
The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR,
and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used in
conditional branching instructions (BCC).
For the action of each instruction on the flag bits, see the H8/300 Series Programming Manual.
3.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt
mask bit (I) in the CCR is set to “1.” The other CCR bits and the general registers are not
initialized.
In particular, the stack pointer (R7) is not initialized. To prevent program crashes the stack pointer
should be initialized by software, by the first instruction executed after a reset.
26
3.3 Addressing Modes
3.3.1 Addressing Mode
The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these
addressing modes.
Table 3-1. Addressing Modes
No.
(1)
(2)
(3)
(4)
Addressing mode
Symbol
Register direct
Rn
Register indirect
@Rn
Register indirect with displacement
Register indirect with post-increment
Register indirect with pre-decrement
Absolute address
@(d:16, Rn)
@Rn+
@–Rn
(5)
(6)
(7)
(8)
@aa:8 or @aa:16
#xx:8 or #xx:16
@(d:8, PC)
@@aa:8
Immediate
Program-counter-relative
Memory indirect
(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand. In most cases the general register is accessed as an 8-bit register.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
(2) Register indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in MOV
instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4)
which is added to the contents of the specified general register to obtain the operand address. For
the MOV.W instruction, the resulting address must be even.
(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
•
Register indirect with Post-Increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is incremented after the operand is accessed. The size of the increment is
27
1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the
original contents of the 16-bit general register must be even.
•
Register Indirect with Pre-Decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is decremented before the operand is accessed. The size of the
decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For
MOV.W, the original contents of the 16-bit general register must be even.
(5) Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H'FFxx.
The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to
65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses.
(6) Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or
a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit
immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit
manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the
instruction, specifying a bit number.
(7) Program-Counter-Relative—@(d:8, PC): This mode is used to generate branch addresses in
the Bcc and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a sign-
extended value to the program counter contents. The result must be an even number. The possible
branching range is –126 to +128 bytes (–63 to +64 words) from the current address.
(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0 to
255). The word located at this address contains the branch address. Note that addresses H'0000 to
H'0047 (0 to 71) are located in the vector table.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as “0,” causing word access to be performed at the
address preceding the specified address. See section 3.4.2, “Memory Data Formats,” for further
information.
28
3.3.2 How to Calculate Where the Execution Starts
Table 3-2 shows how to calculate the Effective Address (EA: Effective Address) for each
addressing mode.
In the operation instruction, 1) register direct, as well as 6) immediate (for each instruction,
ADD.B, ADDX, SUBX, CMP.B, AND, OR, XOR) are used.
In the move instruction, 7) program counter relative and 8) all addressing mode to delete the
memory indirect can be used.
In the bit manipulation instruction for the operand specifications, 1) register direct, 2) register
indirect, as well as 5) absolute address (8 bit) can be used. Furthermore, to specify the bit number
within the operand, 1) register direct (for each instruction, BSET, BCLR, BNOT, BTST) as well as
6) immediate (3 bit) can be used independently.
29
Table 3-2. Effective Address Calculation (1)
Addressing mode and
No. instruction format
Effective address calculation
Effective address
3
0
3
0
1
Register direct, Rn
regm
regn
15 8 7
4 3
0
op
regm
regn
Operands are contained in registers regm
and regn
15
0
0
2
3
Register indirect, @Rn
16-bit register contents
15
0
15
7 6 4 3
reg
0
0
op
15
Register indirect with displacement,
@(d:16, Rn)
16-bit register contents
15
0
15
7 6 4 3
op
reg
disp
disp
15
0
15
0
4
Register indirect with
post-increment, @Rn+
16-bit register contents
15
7 6 4 3
0
op
reg
1 or 2 *
15
0
Register indirect with pre-decrement,
@–Rn
16-bit register contents
15
0
15
7 6 4 3
reg
0
op
*
1 or 2
Note: * 1 for a byte operand, 2 for a word operand
Table 3-2. Effective Address Calculation (2)
Addressing mode and
No. instruction format
Effective address calculation
Effective address
15
8 7
0
0
5
6
7
Absolute address
H'FF
@aa:8
15
8 7
0
0
op
abs
@aa:16
15
15
op
abs
Immediate
#xx:8
15
8 7
0
0
op
IMM
Operand is 1- or 2-byte immediate data
#xx:16
15
op
IMM
15
0
PC-relative
@(d:8, PC)
PC contents
15
0
Sign extension
disp
15
8 7
0
op
disp
Table 3-2. Effective Address Calculation (3)
Addressing mode and
No. instruction format
Effective address calculation
Effective address
8
Memory indirect, @@aa:8
15
8 7
0
op
abs
15
8 7
0
H'00
15
0
Memory contents (16 bits)
Notation
reg: General register
op: Operation code
disp: Displacement
IMM: Immediate data
abs: Absolute address
3.4 Data Formats
The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte
operand.
• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
• The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed
BCD form. Each nibble of the byte is treated as a decimal digit.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU
(16 bits ÷ 8 bits) instructions operate on word data.
33
3.4.1 Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 3-3.
Data type
Register No.
Data format
7
0
RnH
7 6 5 4 3 2 1 0
Don't-care
1-Bit data
7
0
Don't-care
1-Bit data
Byte data
Byte data
RnL
RnH
7 6 5 4 3 2 1 0
7
0
M
S
B
L
S
B
Don't-care
7
M
S
0
L
S
RnL
Rn
Don't-care
B
B
15
0
M
S
B
L
S
B
Word data
7
0
4 3
Upper digit Lower digit
RnH
RnL
Don't-care
4 3
4-Bit BCD data
4-Bit BCD data
7
0
Upper digit Lower digit
Don't-care
Figure 3-3. Register Data Formats
Note: RnH: Upper digit of general register
RnL: Lower digit of general register
MSB: Most significant bit
LSB: Least significant bit
34
3.4.2 Memory Data Formats
Figure 3-4 indicates the data formats in memory.
Word data stored in memory must always begin at an even address. In word access the least
significant bit of the address is regarded as “0.” If an odd address is specified, no address error
occurs but the access is performed at the preceding even address. This rule affects MOV.W
instructions and branching instructions, and implies that only even addresses should be stored in the
vector table.
Data type
Address
Data format
7
0
7 6 5 4 3 2 1 0
Address n
Address n
1-Bit data
Byte data
M
S
B
L
S
B
M
S
B
Upper 8 bits
Lower 8 bits
Even address
Odd address
L
S
B
Word data
M
S
B
M
S
B
L
S
B
L
S
B
CCR
Even address
Odd address
Byte data (CCR) on stack
CCR*
M
S
B
Even address
Odd address
L
S
B
Word data on stack
CCR: Condition Code Register
Note: * Ignored when returned
Figure 3-4. Memory Data Formats
When the stack is addressed using R7, it must always be accessed a word at a time. When the CCR
is pushed on the stack, two identical copies of the CCR are pushed to make a complete word.
When they are returned, the lower byte is ignored.
35
3.5 Instruction Set
Table 3-3 lists the H8/300 instruction set.
Table 3-3. Instruction Classification
Function
Instructions
Types
Data transfer
MOV, MOVTPE*3, MOVFPE*3, PUSH*1, POP*1
3
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, 14
DAA, DAS, MULXU, DIVXU, CMP, NEG
Logic operations
Shift
AND, OR, XOR, NOT
4
8
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
Bit manipulation
BSET, BCLR, BNOT, BTST,BAND, BIAND, BOR,
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST
Bcc*2, JMP, BSR, JSR, RTS
14
Branch
5
8
1
System control
Block data transfer
RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
EEPMOV
Total 57
Notes: *1 PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn.
*2 Bcc is a conditional branch instruction in which cc represents a condition code.
*3 Not supported by the H8/329 Series.
The following sections give a concise summary of the instructions in each category, and indicate
the bit patterns of their object code. The notation used is defined next.
36
Operation Notation
Rd
General register (destination)
#xx:3
#xx:8
3-Bit immediate data
8-Bit immediate data
Rs
General register (source)
General register
Rn
#xx:16 16-Bit immediate data
(EAd)
(EAs)
SP
Destination operand
Source operand
disp
+
Displacement
Addition
Stack pointer
–
Subtraction
Multiplication
Division
PC
Program counter
×
CCR
N
Condition code register
N (negative) flag of CCR
Z (zero) flag of CCR
V (overflow) flag of CCR
C (carry) flag of CCR
Immediate data
÷
AND logical
OR logical
Exclusive OR logical
Move
Z
V
C
→
#imm
¬
Not
37
3.5.1 Data Transfer Instructions
Table 3-4 describes the data transfer instructions. Figure 3-5 shows their object code formats.
Table 3-4. Data Transfer Instructions
Instruction
Size* Function
MOV
B/W (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @–Rn, and
@Rn+ addressing modes are available for byte or word data. The
@aa:8 addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not specify
byte size for these two modes.
MOVTPE
MOVFPE
PUSH
B
Not supported by the H8/329 Series.
B
Not supported by the H8/329 Series.
W
Rn → @–SP
Pushes a 16-bit general register onto the stack. Equivalent to MOV.W
Rn, @–SP.
POP
W
@SP+ → Rn
Pops a 16-bit general register from the stack. Equivalent to MOV.W
@SP+, Rn.
Note: * Size: operand size
B: Byte
W: Word
38
15
8
7
0
MOV
r
r
→
Rn
Op
Op
Rm
m
n
r
r
→
→
Rn
@Rm, or @Rm
Rn
m
n
r
r
→
@(d:16, Rm)
Op
Rn, or
m
n
disp.
→
Rn
@(d:16, Rm)
r
r
→
→
@–Rm
Op
@Rm+
@aa:8
Rn, or Rn
→
Rn, or Rn @aa:8
m
n
r
→
Op
Op
abs.
n
r
→
Op
@aa:16
Rn, or
n
abs.
→
Rn
@aa:16
r
→
Rn
#imm.
#xx:8
n
r
→
Rn
Op
#xx:16
n
#imm.
r
Op
Op
MOVFPE, MOVTPE
PUSH, POP
n
abs.
r
n
Op:
Operation field
Register field
r , r :
m n
disp.:
abs.:
#imm.:
Displacement
Absolute address
Immediate data
Figure 3-5. Data Transfer Instruction Codes
39
3.5.2 Arithmetic Operations
Table 3-5 describes the arithmetic instructions. See figure 3-6 in section 3.5.4, “Shift Operations”
for their object codes.
Table 3-5. Arithmetic Instructions
Instruction
ADD
Size* Function
B/W Rd ± Rs → Rd, Rd + #imm → Rd
SUB
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data can
be added or subtracted only when both words are in general registers.
Rd ± Rs ± C → Rd, Rd ± #imm ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data and
data in a general register.
ADDX
SUBX
B
INC
B
Rd ± #1 → Rd
DEC
ADDS
SUBS
Increments or decrements a general register.
Rd ± #imm → Rd
Adds or subtracts immediate data to or from data in a general register.
The immediate data must be 1 or 2.
W
DAA
DAS
B
Rd decimal adjust → Rd
Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR.
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result.
MULXU
DIVXU
CMP
B
B
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.
Rd – Rs, Rd – #imm
B/W
Compares data in a general register with data in another general register
or with immediate data. Word data can be compared only between two
general registers.
NEG
B
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register.
Note: * Size: operand size
B: Byte
W: Word
40
3.5.3 Logic Operations
Table 3-6 describes the four instructions that perform logic operations. See figure 3-6 in
section 3.5.4, “Shift Operations,” for their object codes.
Table 3-6. Logic Operation Instructions
Instruction
Size* Function
AND
B
B
B
B
Rd
Rs → Rd,
Rd
#imm → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
Rd
Rs → Rd,
Rd
#imm → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
NOT
Rd
Rs → Rd,
Rd #imm → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
¬ (Rd) → (Rd)
Obtains the one’s complement (logical complement) of general register
contents.
Note: * Size: operand size
B: Byte
3.5.4 Shift Operations
Table 3-7 describes the eight shift instructions. Figure 3-6 shows the object code formats of the
arithmetic, logic, and shift instructions.
Table 3-7. Shift Instructions
Instruction
SHAL
Size* Function
B
B
B
B
Rd shift → Rd
SHAR
Performs an arithmetic shift operation on general register contents.
Rd shift → Rd
SHLL
SHLR
Performs a logical shift operation on general register contents.
Rd rotate → Rd
ROTL
ROTR
Rotates general register contents.
ROTXL
ROTXR
Rd rotate through carry → Rd
Rotates general register contents through the C (carry) bit.
Note: * Size: operand size
B: Byte
41
15
8
7
0
Op
r
r
ADD, SUB, CMP
m
n
ADDX, SUBX(Rm), MULXU, DIVXU
Op
r
ADDS, SUBS, INC, DEC, DAA,
DAS, NEG, NOT
n
r
Op
#imm.
#imm.
ADD, ADDX, SUBX, CMP
(#xx:8)
n
r
r
Op
AND, OR, XOR (Rm)
m
n
Op
r
AND, OR, XOR (#xx:8)
n
r
Op
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
n
Op:
Operation field
Register field
Immediate data
r , r :
m n
#imm.:
Figure 3-6. Arithmetic, Logic, and Shift Instruction Codes
42
3.5.5 Bit Manipulations
Table 3-8 describes the bit-manipulation instructions. Figure 3-7 shows their object code formats.
Table 3-8. Bit-Manipulation Instructions (1)
Instruction
Size* Function
BSET
B
B
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to “1.” The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register.
BCLR
BNOT
BTST
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to “0.” The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register.
¬(<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register
B
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or clears
the Z flag accordingly. The bit is specified by a bit number, given in
3-bit immediate data or the lower three bits of a general register.
BAND
C
(<bit-No.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or memory.
[¬ (<bit-No.> of <EAd>)] → C
BIAND
C
ANDs the C flag with the inverse of a specified bit in a general register
or memory.
The bit number is specified by 3-bit immediate data.
BOR
B
B
C
(<bit-No.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory.
[¬ (<bit-No.> of <EAd>)] → C
BIOR
C
ORs the C flag with the inverse of a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
BXOR
C
(<bit-No.> of <EAd>) → C
XORs the C flag with a specified bit in a general register or memory.
Note: * Size: operand size
B: Byte
43
Table 3-8. Bit-Manipulation Instructions (2)
Instruction
Size* Function
BIXOR
B
C
¬ [(<bit-No.> of <EAd>)] → C
XORs the C flag with the inverse of a specified bit in a general register
or memory.
The bit number is specified by 3-bit immediate data.
(<bit-No.> of <EAd>) → C
BLD
B
Copies a specified bit in a general register or memory to the C flag.
¬ (<bit-No.> of <EAd>) → C
BILD
Copies the inverse of a specified bit in a general register or memory to
the C flag.
The bit number is specified by 3-bit immediate data.
C → (<bit-No.> of <EAd>)
BST
B
Copies the C flag to a specified bit in a general register or memory.
¬ C → (<bit-No.> of <EAd>)
BIST
Copies the inverse of the C flag to a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
Note: * Size: operand size
B: Byte
Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-modify-
write instructions. They read a byte of data, modify one bit in the byte, then write the byte back.
Care is required when these instructions are applied to registers with write-only bits and to the I/O
port registers.
Step
Description
1
2
3
Read
Read one data byte at the specified address
Modify one bit in the data byte
Modify
Write
Write the modified data byte back to the specified address
Example: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under the
following conditions.
P47:
Input pin, Low
Input pin, High
Output pins, Low
P46:
P45 – P40:
The intended purpose of this BCLR instruction is to switch P40 from output to input.
44
Before Execution of BCLR Instruction
P47
Input
Low
0
P46
P45
P44
P43
P42
P41
P40
Input/output
Pin state
DDR
Input Output Output Output Output Output Output
High
Low
Low
Low
Low
Low
Low
0
0
1
0
1
0
1
0
1
0
1
0
1
0
DR
1
Execution of BCLR Instruction
;clear bit 0 in data direction register
After Execution of BCLR Instruction
BCLR #0, @P4DDR
P47
P46
P45
P44
P43
P42
P41
P40
Input/output
Pin state
DDR
Output Output Output Output Output Output Output Input
Low
High
Low
Low
Low
Low
Low
High
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
DR
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to “0,” making P40 an input pin. In addition, P47DDR and P46DDR
are set to “1,” making P47 and P46 output pins.
45
0
15
8
7
BSET, BCLR, BNOT, BTST
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
r
r
Op
#imm.
n
n
r
Op
Operand: register direct (Rn)
Bit No.: register direct (Rm)
m
Op
Op
r
0
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
n
#imm.
Op
Op
r
r
0
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: register direct (Rm)
n
m
Op
abs.
0
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
Op
#imm.
0
0
0
0
0
0
Op
Op
abs.
0
Operand: absolute (@aa:8)
Bit No.: register direct (Rm)
r
m
BAND, BOR, BXOR, BLD, BST
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
Op
r
n
#imm.
r
0
0
0
0
0 0
Op
Op
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
n
#imm.
0
0
Op
Op
abs.
0
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
#imm.
#imm.
0
0
0
BIAND, BIOR, BIXOR, BILD, BIST
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
Op
r
n
Op
Op
r
0
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
n
#imm.
Op
abs.
0
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
Op
0
0
0
#imm.
Op:
Operation field
Register field
Absolute address
Immediate data
r , r :
m
n
abs.:
#imm.:
Figure 3-7. Bit Manipulation Instruction Codes
46
3.5.6 Branching Instructions
Table 3-9 describes the branching instructions. Figure 3-8 shows their object code formats.
Table 3-9. Branching Instructions
Instruction
Size
Function
Bcc
—
Branches to the specified address if condition cc is true.
Mnemonic
BRA (BT)
BRN (BF)
BHI
cc field
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
Description
Always (True)
Never (False)
High
Condition
Always
Never
C
C
Z = 0
Z = 1
BLS
Low or Same
Carry Clear
(High or Same)
Carry Set (Low)
Not Equal
BCC (BHS)
C = 0
BCS (BLO)
BNE
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
BEQ
Equal
BVC
Overflow Clear
Overflow Set
Plus
BVS
BPL
BMI
Minus
BGE
Greater or Equal
Less Than
N
N
Z
Z
V = 0
BLT
V = 1
BGT
Greater Than
Less or Equal
(N V) = 0
(N V) = 1
BLE
JMP
JSR
BSR
—
—
—
Branches unconditionally to a specified address.
Branches to a subroutine at a specified address.
Branches to a subroutine at a specified displacement from the current
address.
RTS
—
Returns from a subroutine
47
15
8
7
0
0
Op
cc
disp.
Bcc
r
Op
m
0
0
0
JMP(@Rm)
JMP (@aa:16)
Op
abs.
Op
abs.
JMP (@@aa:8)
BSR
Op
disp.
r
Op
0
0
0
0
JSR(@Rm)
JSR (@aa:16)
m
Op
abs.
Op
abs.
JSR (@@aa:8)
RTS
Op
Op:
cc:
Operation field
Condition field
Register field
Displacement
Absolute address
r :
m
disp.:
abs.:
Figure 3-8. Branching Instruction Codes
48
3.5.7 System Control Instructions
Table 3-10 describes the system control instructions. Figure 3-9 shows their object code formats.
Table 3-10. System Control Instructions
Instruction
RTE
Size
—
—
B
Function
Returns from an exception-handling routine.
Causes a transition to the power-down state.
Rs → CCR, #imm → CCR
SLEEP
LDC
Moves immediate data or general register contents to the condition code
register.
STC
B
B
B
B
CCR → Rd
Copies the condition code register to a specified general register.
CCR #imm → CCR
ANDC
ORC
Logically ANDs the condition code register with immediate data.
CCR #imm → CCR
Logically ORs the condition code register with immediate data.
CCR #imm → CCR
XORC
Logically exclusive-ORs the condition code register with immediate
data.
NOP
—
PC + 2 → PC
Only increments the program counter.
Note: * Size: operand size
B: Byte
49
15
8
7
0
Op
RTE, SLEEP, NOP
LDC, STC (Rn)
r
Op
n
Op
#imm.
ANDC, ORC, XORC, LDC
(#xx:8)
Op:
Operation field
Register field
Immediate data
r :
n
#imm.:
Figure 3-9. System Control Instruction Codes
3.5.8 Block Data Transfer Instruction
Table 3-11 describes the EEPMOV instruction. Figure 3-10 shows its object code format.
Table 3-11. Block Data Transfer Instruction/EEPROM Write Operation
Instruction
Size
Function
EEPMOV
—
if R4L ≠ 0 then
repeat @R5+ → @R6+
R4L – 1 → R4L
until
R4L = 0
else next;
Moves a data block according to parameters set in general registers R4L,
R5, and R6.
R4L: size of block (bytes)
R5:
R6:
starting source address
starting destination address
Execution of the next instruction starts as soon as the block transfer is
completed.
50
15
8
7
0
Op
Op
EEPROM
Op: Operation field
Figure 3-10. Block Data Transfer Instruction/EEPROM Write Operation Code
Notes on EEPMOV Instruction
1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
→
R5
←
←
R6
R5 + R4L →
R6 + R4L
2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
R5 →
←
R6
→
R5 + R4L
H'FFFF
Not allowed
← R6 + R4L
3.6 CPU States
The CPU has three states: the program execution state, exception-handling state, and power-down
state. The power-down state is further divided into three modes: the sleep mode, software standby
mode, and hardware standby mode. Figure 3-11 summarizes these states, and figure 3-12 shows a
map of the state transitions.
State
Program execution state
The CPU executes successive program instructions.
Exception-handling state
A transient state triggered by a reset or interrupt. The CPU executes a hardware
sequence that includes loading the program counter from the vector table.
Power-down state
Sleep mode
A state in which some or all of the chip
functions are stopped to conserve power.
Software standby mode
Hardware standby mode
Figure 3-11. Operating States
51
Program
execution state
SLEEP instruction
with SSBY bit set
Exception
handling
request
SLEEP
instruction
Exception
handing
Exception -
handling state
Sleep mode
Interrupt request
NMIorIRQ0
to IRQ2
Software
standby mode
RES = 1
STBY=1, RES=0
Hardware
standby mode
Reset state
Power-down state
Notes: *1 A transition to the reset state occurs when RES goes Low, except when the chip is in the hardware standby mode.
*2 A transition from any state to the hardware standby mode occurs when STBY goes Low.
Figure 3-12. State Transitions
3.6.1 Program Execution State
In this state the CPU executes program instructions.
3.6.2 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or accepts an
interrupt. In this state the CPU carries out a hardware-controlled sequence that prepares it to
execute a user-coded exception-handling routine.
In the hardware exception-handling sequence the CPU does the following:
(1) Saves the program counter and condition code register to the stack (except in the case of a
reset).
(2) Sets the interrupt mask (I) bit in the condition code register to “1.”
(3) Fetches the start address of the exception-handling routine from the vector table.
(4) Branches to that address, returning to the program execution state.
See section 4, “Exception Handling,” for further information on the exception-handling state.
52
3.6.3 Power-Down State
The power-down state includes three modes: the sleep mode, the software standby mode, and the
hardware standby mode.
(1) Sleep Mode: The sleep mode is entered when a SLEEP instruction is executed. The CPU
halts, but CPU register contents remain unchanged and the on-chip supporting modules continue to
function.
(2) Software Standby Mode: The software standby mode is entered if the SLEEP instruction is
executed while the SSBY (Software Standby) bit in the system control register (SYSCR) is set.
The CPU and all on-chip supporting modules halt. The on-chip supporting modules are initialized,
but the contents of the on-chip RAM and CPU registers remain unchanged. I/O port outputs also
remain unchanged.
(3) Hardware Standby Mode: The hardware standby mode is entered when the input at the
STBY pin goes Low. All chip functions halt, including I/O port output. The on-chip supporting
modules are initialized, but on-chip RAM contents are held.
See section 12, “Power-Down State,” for further information.
3.7 Access Timing and Bus Cycle
The CPU is driven by the system clock (Ø). The period from one rising edge of the system clock to
the next is referred to as a “state.”
Memory access is performed in a two- or three-state bus cycle. On-chip memory, on-chip
supporting modules, and external devices are accessed in different bus cycles as described below.
3.7.1 Access to On-Chip Memory (RAM and ROM)
On-chip ROM and RAM are accessed in a cycle of two states designated T1 and T2. Either byte or
word data can be accessed, via a 16-bit data bus. Figure 3-13 shows the on-chip memory access
cycle. Figure 3-14 shows the associated pin states.
53
Bus cycle
T2 state
T1 state
Ø
Internal address bus
Internal Read signal
Internal data bus (read)
Address
Read data
Write data
Internal Write signal
Internal data bus (write)
Figure 3-13. On-Chip Memory Access Cycle
Bus cycle
T1 state
T2 state
Ø
Address bus
Address
AS: High
RD: High
WR: High
Data bus: high impedance state
Figure 3-14. Pin States during On-Chip Memory Access Cycle
54
3.7.2 Access to On-Chip Register Field and External Devices
The on-chip register field (I/O ports, on-chip supporting module registers, etc.) and external devices
are accessed in a cycle consisting of three states: T1, T2, and T3. Only one byte of data can be
accessed per cycle, via an 8-bit data bus. Access to word data or instruction codes requires two
consecutive cycles (six states).
Figure 3-15 shows the access cycle for the on-chip register field. Figure 3-16 shows the associated
pin states. Figures 3-17 (a) and (b) show the read and write access timing for external devices.
Bus cycle
T1 state
T2 state
T3 state
Ø
Internal address bus
Internal Read signal
Internal data bus (read)
Address
Read data
Internal Write signal
Write data
Internal data bus (write)
Figure 3-15. On-Chip Register Field Access Cycle
55
Bus cycle
T2 state
T1 state
T3 state
Ø
Address bus
AS: High
Address
RD: High
WR: High
Data bus: high impedance state
Figure 3-16. Pin States during On-Chip Register Field Access Cycle
Read cycle
T1 state
T2 state
T3 state
Ø
Address bus
Address
AS
RD
WR: High
Data bus
Read data
Figure 3-17 (a). External Device Access Timing (Read)
56
Write cycle
T2 state
T1 state
T3 state
Ø
Address bus
AS
Address
RD: High
WR
Data bus
Write data
Figure 3-17 (b). External Device Access Timing (Write)
57
Section 4. Exception Handling
4.1 Overview
The H8/329 Series recognizes only two kinds of exceptions: interrupts and the reset. Table 4-1
indicates their priority and the timing of their hardware exception-handling sequences.
Table 4-1. Hardware Exception-Handling Sequences and Priority
Type of
Priority
exception
Timing of exception-handling sequence
High
Reset
The hardware exception-handling sequence begins as soon as RES
changes from Low to High.
Interrupt
When an interrupt is requested, the hardware exception-handling
sequence begins at the end of the current instruction, or at the end of
the current hardware exception-handling sequence.
Low
4.2 Reset
4.2.1 Overview
A reset has the highest exception-handling priority. When the RES pin goes Low, all current
processing stops and the chip enters the reset state. The internal state of the CPU and the registers
of the on-chip supporting modules are initialized. When RES returns from Low to High, the reset
exception-handling sequence starts.
4.2.2 Reset Sequence
The reset state begins when RES goes Low. To ensure correct resetting, at power-on the RES pin
should be held Low for at least 20ms. In a reset during operation, the RES pin should be held Low
for at least 10 system clock cycles. For the pin states during a reset, see appendix C, “Pin States.”
When RES returns from Low to High, hardware carries out the following reset exception-handling
sequence.
59
(1) The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit in the condition code register (CCR) is set to “1.”
(2) The CPU loads the program counter with the first word in the vector table (stored at addresses
H'0000 and H'0001) and starts program execution.
The RES pin should be held Low when power is switched off, as well as when power is switched
on.
Figure 4-1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4-2 indicates the
timing in mode 1.
Vector
fetch
Internal
processing prefetch
Instruction
RES
Ø
Internal address
bus
(1)
(2)
Internal Read
signal
Internal Write
signal
Internal data bus
(16 bits)
(2)
(3)
(1) Reset vector address (H'0000)
(2) Starting address of program (contents of H'0000–H'0001)
(3) First instruction of program
Figure 4-1. Reset Sequence (Mode 2 or 3, Program Stored in On-Chip ROM)
60
Internal
process-
ing
Instruction prefetch
Vector fetch
RES
Ø
(3)
(5)
(7)
A15 to A0
(1)
RD
WR
D7 to D0
(8 bits)
(8)
(2)
(4)
(6)
(1),(3) Reset vector address: (1)=H'0000, (3)=H'0001
(2),(4) Starting address of program (contents of reset vector): (2)=upper byte, (4)=lower byte
(5),(7) Starting address of program: (5)=(2)(4), (7)=(2)(4)+1
(6),(8) First instruction of program: (6)=first byte, (8)=second byte
Figure 4-2. Reset Sequence (Mode 1)
4.2.3 Disabling of Interrupts after Reset
After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP: R7),
the program counter and condition code register might not be saved correctly, leading to a program
crash. To prevent this, all interrupts, including NMI, are disabled immediately after a reset. The
first program instruction is therefore always executed. This instruction should initialize the stack
pointer (example: MOV.W #xx:16, SP).
4.3 Interrupts
4.3.1 Overview
The interrupt sources include four input pins for external interrupts (NMI, IRQ0 to IRQ2) and 18
internal sources in the on-chip supporting modules. Table 4-2 lists the interrupt sources in priority
order and gives their vector addresses. When two or more interrupts are requested, the interrupt
with highest priority is served first.
The features of these interrupts are:
• NMI has the highest priority and is always accepted. All internal and external interrupts except
NMI can be masked by the I bit in the CCR. When the I bit is set to “1,” interrupts other than
NMI are not accepted.
• IRQ0 to IRQ2 can be sensed on the falling edge of the input signal, or level-sensed. The type of
sensing can be selected for each interrupt individually. NMI is edge-sensed, and either the
rising or falling edge can be selected.
• All interrupts are individually vectored. The software interrupt-handling routine does not have
to determine what type of interrupt has occurred.
62
Table 4-2. Interrupts
Address of entry
in vector table
Interrupt source
NMI
No.
3
Priority
H'0006
H'0008
–
–
H'0007
H'0009
High
IRQ0
4
IRQ1
5
H'000A – H'000B
IRQ2
6
H'000C
H'000E
H'0010
H'0012
H'0014
H'0016
H'0018
–
–
–
–
–
–
–
H'000D
H'000F
H'0011
H'0013
H'0015
H'0017
H'0019
Reserved
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
16-Bit free-
ICIA (Input capture A)
running timer
ICIB (Input capture B)
ICIC (Input capture C)
ICID (Input capture D)
OCIA (Output compare A)
OCIB (Output compare B)
FOVI (Overflow)
H'001A – H'001B
H'001C
H'001E
H'0020
H'0022
H'0024
H'0026
H'0028
–
–
–
–
–
–
–
H'001D
H'001F
H'0021
H'0023
H'0025
H'0027
H'0029
8-Bit timer 0
8-Bit timer 1
Reserved
CMI0A (Compare-match A)
CMI0B (Compare-match B)
OVI0 (Overflow)
H'002A – H'002B
CMI1A (Compare-match A)
CMI1B (Compare-match B)
OVI1 (Overflow)
H'002C
H'002E
H'0030
H'0032
H'0034
H'0036
H'0038
–
–
–
–
–
–
–
H'002D
H'002F
H'0031
H'0033
H'0035
H'0037
H'0039
Serial
ERI (Receive error)
RXI (Receive end)
TXI (TDR empty)
TEI (TSR empty)
communication
interface
H'003A – H'003B
H'003C
H'003E
H'0040
H'0042
H'0044
H'0046
–
–
–
–
–
–
H'003D
H'003F
H'0041
H'0043
H'0045
H'0047
Reserved
A/D converter
ADI (Conversion end)
Low
Notes: 1. H'0000 and H'0001 contain the reset vector.
2. H'0002 to H'0005 are reserved in the H8/329 Series and are not available to the user.
63
4.3.2 Interrupt-Related Registers
The interrupt-related registers are the system control register (SYSCR), IRQ sense control register
(ISCR), and IRQ enable register (IER).
Table 4-3. Registers Read by Interrupt Controller
Name
Abbreviation
SYSCR
ISCR
Read/Write
R/W
Address
H'FFC4
H'FFC6
H'FFC7
System control register
IRQ sense control register
IRQ enable register
R/W
IER
R/W
System Control Register (SYSCR)—H'FFC4
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
3
2
1
—
1
0
RAME
1
STS0
0
—
1
NMIEG
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
—
R/W
—
R/W
The valid edge on the NMI line is controlled by bit 2 (NMIEG) in the system control register.
Bit 2—NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the
falling or rising edge of the NMI input signal.
Bit 2
NMIEG Description
0
1
An interrupt is generated on the falling edge of NMI.
An interrupt is generated on the rising edge of NMI.
(Initial state)
See section 2.2, “System Control Register,” for information on the other SYSCR bits.
IRQ Sense Control Register (ISCR)—H'FFC6
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
IRQ2SC IRQ1SC IRQ0SC
Initial value
Read/Write
0
0
0
—
—
—
—
—
R/W
R/W
R/W
Bits 3 to 7—Reserved: These bits cannot be modified and are always read as “1.”
64
Bits 0 to 2—IRQ0 to IRQ2 Sense Control (IRQ0SC to IRQ2SC): These bits determine whether
IRQ0 to IRQ2 are level-sensed or sensed on the falling edge.
Bits 0 to 2
IRQ0SC to IRQ2SC
Description
0
An interrupt is generated when IRQ0 to IRQ2
inputs are Low.
(Initial state)
1
An interrupt is generated by the falling edge of the IRQ0 to IRQ2 inputs.
IRQ Enable Register (IER)—H'FFC7
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
IRQ2E IRQ1E IRQ0E
Initial value
Read/Write
0
0
0
—
—
—
—
—
R/W
R/W
R/W
Bits 3 to 7—Reserved: These bits cannot be modified and are always read as “1.”
Bits 0 to 2—IRQ0 to IRQ2 Enable (IRQ0E to IRQ2E): These bits enable or disable the IRQ0 to
IRQ2 interrupts individually.
Bits 0 to 2
IRQ0E to IRQ2E
Description
0
1
IRQ0 to IRQ2 interrupt requests are disabled.
IRQ0 to IRQ2 interrupt requests are enabled.
(Initial state)
When edge sensing is selected (by setting bits IRQ0SC to IRQ7SC to “1”), it is possible for an
interrupt-handling routine to be executed even though the corresponding enable bit (IRQ0E to
IRQ7E) is cleared to “0” and the interrupt is disabled. If an interrupt is requested while the
enable bit (IRQ0E to IRQ7E) is set to “1,” the request will be held pending until served. If the
enable bit is cleared to “0” while the request is still pending, the request will remain pending,
although new requests will not be recognized. If the interrupt mask bit (I) in the CCR is
cleared to “0,” the interrupt-handling routine can be executed even though the enable bit is
now “0.”
65
If execution of interrupt-handling routines under these conditions is not desired, it can be
avoided by using the following procedure to disable and clear interrupt requests.
1. Set the I bit to “1” in the CCR, masking interrupts. Note that the I bit is set to 1 automatically
when execution jumps to an interrupt vector.
2. Clear the desired bits from IRQ0E to IRQ7E to “0” to disable new interrupt requests.
3. Clear the corresponding IRQ0SC to IRQ7SC bits to “0,” then set them to “1” again. Pending
IRQn interrupt requests are cleared when I = “1” in the CCR, IRQnSC = “0,” and IRQnE = “0.”
4.3.3 External Interrupts
The external interrupts are NMI and IRQ0 to IRQ2. These four interrupts can be used to recover
from software standby mode.
(1) NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input
signal regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected
by the NMIEG bit in the system control register. The NMI vector number is 3. In the NMI
hardware exception-handling sequence the I bit in the CCR is set to “1.”
(2) IRQ0 to IRQ2: These interrupt signals are level-sensed or sensed on the falling edge of the
input, as selected by ISCR bits IRQ0SC to IRQ2SC. These interrupts can be masked collectively by
the I bit in the CCR, and can be enabled and disabled individually by setting and clearing bits
IRQ0E to IRQ2E in the IRQ enable register.
When one of these interrupts is accepted, the I bit is set to “1.” IRQ0 to IRQ2 have interrupt vector
numbers 4 to 6. They are prioritized in order from IRQ2 (Low) to IRQ0 (High). For details, see
table 4-2.
Interrupts IRQ0 to IRQ2 do not depend on whether pins IRQ0 to IRQ2 are input or output pins.
When using external interrupts IRQ0 to IRQ2, clear the corresponding DDR bits to “0” to set these
pins to the input state, and do not use these pins for input to the A/D converter.
66
4.3.4 Internal Interrupts
Eighteen internal interrupts can be requested by the on-chip supporting modules. Each interrupt
source has its own vector number, so the interrupt-handling routine does not have to determine
which interrupt has occurred. All internal interrupts are masked when the I bit in the CCR is set to
“1.” When one of these interrupts is accepted, the I bit is set to 1 to mask further interrupts (except
NMI). The vector numbers are 12 to 35. For the priority order, see table 4-2.
4.3.5 Interrupt Handling
Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt
requests, commands the CPU to start the hardware interrupt exception-handling sequence, and
furnishes the necessary vector number. Figure 4-3 shows a block diagram of the interrupt
controller.
Interrupt
CPU
controller
NMI interrupt
*
IRQ0 flag
IRQ0E
Interrupt request
IRQ0
interrupt
Priority
decision
Vector number
ADF
ADIE
ADI
interrupt
Note: * For edge-sensed
interrupts, these
I (CCR)
AND gates change
to the circuit shown below.
IRQ0 flag
S Q
IRQ0 edge
IRQ0E
IRQ0 interrupt
Figure 4-3. Block Diagram of Interrupt Controller
67
The IRQ interrupts and interrupts from the on-chip supporting modules all have corresponding
enable bits. When the enable bit is cleared to “0,” the interrupt signal is not sent to the interrupt
controller, so the interrupt is ignored. These interrupts can also all be masked by setting the CPU’s
interrupt mask bit (I) to “1.” Accordingly, these interrupts are accepted only when their enable bit
is set to “1” and the I bit is cleared to “0.”
The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware
standby mode.
When an NMI or another enabled interrupt is requested, the interrupt controller transfers the
interrupt request to the CPU and indicates the corresponding vector number. (When two or more
interrupts are requested, the interrupt controller selects the vector number of the interrupt with the
highest priority.) When notified of an interrupt request, at the end of the current instruction or
current hardware exception-handling sequence, the CPU starts the hardware exception-handling
sequence for the interrupt and latches the vector number.
Figure 4-4 is a flowchart of the interrupt (and reset) operations. Figure 4-6 shows the interrupt
timing sequence for the case in which the software interrupt-handling routine is in on-chip ROM
and the stack is in on-chip RAM.
(1) An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and when
an interrupt occurs on an IRQ input line or in an on-chip supporting module provided the
enable bit of that interrupt is set to “1.”
(2) The interrupt controller checks the I bit in the CCR and accepts the interrupt request if the I bit
is cleared to “0.” If the I bit is set to “1” only NMI requests are accepted; other interrupt
requests remain pending.
(3) Among all accepted interrupt requests, the interrupt controller selects the request with the
highest priority and passes it to the CPU. Other interrupt requests remain pending.
(4) When it receives the interrupt request, the CPU waits until completion of the current instruction
or hardware exception-handling sequence, then starts the hardware exception-handling
sequence for the interrupt and latches the interrupt vector number.
(5) In the hardware exception-handling sequence, the CPU first pushes the PC and CCR onto the
stack. See figure 4-5. The stacked PC indicates the address of the first instruction that will be
executed on return from the software interrupt-handling routine.
(6) Next the I bit in the CCR is set to “1,” masking all further interrupts except NMI.
(7) The vector address corresponding to the vector number is generated, the vector table entry at
this vector address is loaded into the program counter, and execution branches to the software
interrupt-handling routine at the address indicated by that entry.
68
Program execution
No
Interrupt
requested?
Yes
NMI?
No
Yes
No
Pending
I = 0?
Yes
No
IRQ0?
Yes
No
IRQ1?
Yes
ADI?
Yes
Latch vector No.
Save PC
Save CCR
Reset
I ← 1
Read vector address
Branch to software
interrupt-handling
routine
Figure 4-4. Hardware Interrupt-Handling Sequence
69
SP-4
SP-3
SP-2
SP(R7)
SP+1
SP+2
CCR
CCR*
PC (upper byte)
SP-1
SP+3
SP+4
PC (lower byte)
SP(R7)
Even address
Stack area
Before interrupt
is accepted
After interrupt
is accepted
Pushed onto stack
PC: Program counter
CCR: Condition code register
SP: Stack pointer
Notes: 1. The PC contains the address of the first instruction
executed after return.
2. Registers must be saved and restored by word
access at an even address.
* Ignored on return.
Figure 4-5. Usage of Stack in Interrupt Handling
70
Interrupt
accepted
Instruction fetch
(first instruction of
Vector Internal interrupt-handling
Interrupt priority
decision. Wait for Instruction Internal
end of instruction. fetch
process-
ing
Stack
fetch
process- routine)
ing
Interrupt request
signal
Ø
Internal address
bus
(1)
(3)
(5)
(6)
(8)
(9)
Internal Read
signal
Internal Write
signal
Internal 16-bit
data bus
(2)
(4)
(1)
(7)
(9)
(10)
(1)
Instruction prefetch address (Pushed on stack. Instruction is executed on return from
interrupt-handling routine.)
(2) (4)Instructioncode(Not executed)
(3)
Instruction prefetch address (Not executed)
(5)
SP–2
(6)
SP–4
(7)
(8)
(9)
(10)
CCR
Address of vector table entry
Vector table entry (address of first instruction of interrupt-handling routine)
First instruction of interrupt-handling routine
Figure 4-6. Timing of Interrupt Sequence
71
4.3.6 Interrupt Response Time
Table 4-4 indicates the number of states that elapse from an interrupt request signal until the first
instruction of the software interrupt-handling routine is executed. Since the H8/329 Series accesses
its on-chip memory 16 bits at a time, very fast interrupt service can be obtained by placing
interrupt-handling routines in on-chip ROM and the stack in on-chip RAM.
Table 4-4. Number of States before Interrupt Service
Number of states
No.
1
Reason for wait
Interrupt priority decision
Wait for completion of
current instruction*1
Save PC and CCR
Fetch vector
On-chip memory
2*3
External memory
2*3
5 to 17*2
2
1 to 13
3
4
5
6
4
12*2
6*2
12*2
2
Fetch instruction
Internal processing
Total
4
4
4
17 to 29
41 to 53 *2
Notes: *1 These values do not apply if the current instruction is EEPMOV.
*2 If wait states are inserted in external memory access, add the number of wait states.
*3 1 for internal interrupts.
4.3.7 Precaution
Note that the following type of contention can occur in interrupt handling.
Contention between Interrupt Request and Disable: When software clears the enable bit of an
interrupt to “0” to disable the interrupt, the interrupt becomes disabled after execution of the
clearing instruction. If an enable bit is cleared by a BCLR or MOV instruction, for example, and
the interrupt is requested during execution of that instruction, at the instant when the instruction
ends the interrupt is still enabled, so after execution of the instruction, the hardware exception-
handling sequence is executed for the interrupt. If a higher-priority interrupt is requested at the
same time, however, the hardware exception-handling sequence is executed for the higher-priority
interrupt and the interrupt that was disabled is ignored.
Similar considerations apply when an interrupt request flag is cleared to “0.”
72
Figure 4-7 shows an example in which the OCIAE bit is cleared to “0.”
CPU write
cycle to TIER
TIER address
OCIA interrupt handling
Ø
Internal address bus
Internal write signal
OCIAE
OCFA
OCIA interrupt signal
Figure 4-7. Contention between Interrupt and Disabling Instruction
The above contention does not occur if the enable bit or flag is cleared to “0” while the interrupt
mask bit (I) is set to “1.”
4.4 Note on Stack Handling
In word access, the least significant bit of the address is always assumed to be 0. The stack is
always accessed by word access. Care should be taken to keep an even value in the stack pointer
(general register R7). Use the PUSH and POP (or MOV.W Rn, @–SP and MOV.W @SP+, Rn)
instructions to push and pop registers on the stack.
Setting the stack pointer to an odd value can cause programs to crash. Figure 4-8 shows an
example of damage caused when the stack pointer contains an odd address.
73
SP
H'FECC
H'FECD
PC
PC
R1
PC
L
L
H
L
SP
H'FECF
SP
BSR instruction
MOV.B R1L, @–R7
PC is improperly stored
beyond top of stack
PC is lost
H
H'FECF set in SP
PC : Upper byte of program counter
H
PC : Lower byte of program counter
L
R1 : General register
L
SP : Stack pointer
Figure 4-8. Example of Damage Caused by Setting an Odd Address in R7
Although the CCR consists of only one byte, it is treated as word data when pushed on the stack.
In the hardware interrupt exception-handling sequence, two identical CCR bytes are pushed onto
the stack to make a complete word. When popped from the stack by an RTE instruction, the CCR
is loaded from the byte stored at the even address. The byte stored at the odd address is ignored.
74
Section 5. I/O Ports
5.1 Overview
The H8/329 Series has seven parallel I/O ports, including:
• Five 8-bit input/output ports—ports 1, 2, 3, 4, and 6
• One 8-bit input port—port 7
• One 3-bit input/output port—port 5
Ports 1, 2, and 3 have programmable input pull-up transistors. Ports 1 to 6 can drive a Darlington
pair. Ports 1 to 4, and 6 can drive one TTL load and a 90pF capacitive load. Port 5 can drive one
TTL load and a 30pF capacitive load. Ports 1 and 2 can drive LEDs (10mA current sink).
Input and output are memory-mapped. The CPU views each port as a data register (DR) located in
the register field at the high end of the address space. Each port (except port 7) also has a data
direction register (DDR) which determines which pins are used for input and which for output.
Output: To send data to an output port, the CPU selects output in the data direction register and
writes the desired data in the data register, causing the data to be held in a latch. The latch output
drives the pin through a buffer amplifier. If the CPU reads the data register of an output port, it
obtains the data held in the latch rather than the actual level of the pin.
Input: To read data from an I/O port, the CPU selects input in the data direction register and reads
the data register. This causes the input logic level at the pin to be placed directly on the internal
data bus. There is no intervening input latch.
The data direction registers are write-only registers; their contents are invisible to the CPU. If the
CPU reads a data direction register all bits are read as “1,” regardless of their true values. Care is
required if bit manipulation instructions are used to set and clear the data direction bits. See the
note on bit manipulation instructions in section 3.5.5, “Bit Manipulations.”
Auxiliary Functions: In addition to their general-purpose input/output functions, all of the I/O
ports have auxiliary functions. Most of the auxiliary functions are software-selectable and must be
enabled by setting bits in control registers. When selected, an auxiliary function usually replaces
the general-purpose input/output function, but in some cases both functions can operate
simultaneously. Table 5-1 summarizes the functions of the ports.
75
Table 5-1. Port Functions
Port Description
Expanded modes
Mode 1 Mode 2
Single-chip mode
Mode 3
Pins
Port 1 • 8-bit input-output P17 to P10/
Address output General input
General input/
port
A7 to A0
(low) when DDR = “0” output
• Can drive LEDs
• Input pull-ups
(initial state)
Address output
(low) when
DDR = “1”
Port 2 • 8-bit input-output P27 to P20/
Address output General input
General input/
port
A15 to A8
(high)
when DDR = “0” output
• Can drive LEDs
• Input pull-ups
(initial state)
Address output
(high) when
DDR = “1”
Data bus
Port 3 • 8-bit input-output P37 to P30/
Data bus
General input/
output
port
D7 to D0
• Input pull-ups
Port 4 • 8-bit input/output P47/WAIT
WAIT input
General input/
output
P46/Ø
System clock
output
General input
when DDR = “0”
(initial state)
System clock
output when
DDR = “1”
General input/
output
P45/AS
AS output
WR output
RD output
P44/WR
P43/RD
P42/IRQ0
General input/output or external interrupt input
(IRQ0, IRQ1)
P41/IRQ1
P40/ADTRG/
General input/output, A/D converter trigger input
(ADTRG), or external interrupt input (IRQ2)
General input/output or serial communication interface
input/output (TxD, RxD, SCK)
IRQ2
Port 5 • 3-bit input-output P52 to P50
port
Port 6 • 8-bit input-output P67 to P60
port
General input/output, 16-bit free-running timer
input/output (FTCI, FTOA, FTOB, FTIA, FTIB, FTIC,
FTID), or 8-bit timer 0/1 input/output (TMCI0, TMO0,
TMRI0, TMCI1, TMO1, TMRI1)
Port 7 • 8-bit input port
P77 to P70
General input, or analog input to A/D converter
76
5.2 Port 1
Port 1 is an 8-bit input/output port that also provides the low bits of the address bus. The function
of port 1 depends on the MCU mode as indicated in table 5-2.
Table 5-2. Functions of Port 1
Mode 1
Mode 2
Mode 3
Address bus (Low)
(A7 to A0)
Input port or
Address bus (Low)
(A7 to A0)*
Input/output port
Note: * Depending on the bit settings in the data direction register: 0—input pin; 1—address pin
Pins of port 1 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive light-emitting diodes and a Darlington pair. When they are used as input
pins, they have programmable MOS transistor pull-ups.
Table 5-3 details the port 1 registers.
Table 5-3. Port 1 Registers
Name
Abbreviation Read/Write Initial value
Address
Port 1 data direction register P1DDR
W
H'FF (mode 1)
H'00 (modes 2 and 3)
H'00
H'FFB0
Port 1 data register
P1DR
R/W
R/W
H'FFB2
H'FFAC
Port 1 input pull-up control P1PCR
register
H'00
Port 1 Data Direction Register (P1DDR)—H'FFB0
Bit
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
77
P1DDR is an 8-bit register that selects the direction of each pin in port 1. A pin functions as an
output pin if the corresponding bit in P1DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Port 1 Data Register (P1DR)—H'FFB2
Bit
7
P17
0
6
P16
0
5
P15
0
4
P14
0
3
P13
0
2
P12
0
1
P11
0
0
P10
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1DR is an 8-bit register containing the data for pins P17 to P10. When the CPU reads P1DR, for
output pins it reads the value in the P1DR latch, but for input pins, it obtains the logic level directly
from the pin, bypassing the P1DR latch.
Port 1 Input Pull-Up Control Register (P1PCR)—H'FFAC
Bit
7
6
5
4
3
2
1
0
P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 1. If a
bit in P1DDR is cleared to “0” (designating input) and the corresponding bit in P1PCR is set to “1,”
the input pull-up transistor for that bit is turned on.
Mode 1: In mode 1 (expanded mode without on-chip ROM), port 1 is automatically used for
address output. The port 1 data direction register is unwritable. All bits in P1DDR are
automatically set to “1” and cannot be cleared to “0.”
Mode 2: In mode 2 (expanded mode with on-chip ROM), the usage of port 1 can be selected on a
pin-by-pin basis. A pin is used for general-purpose input if its data direction bit is cleared to “0,”
or for address output if its data direction bit is set to “1.”
Mode 3: In the single-chip mode port 1 is a general-purpose input/output port.
78
Reset: A reset clears P1DDR, P1DR, and P1PCR to all “0,” placing all pins in the input state with
the pull-up transistors off. In mode 1, when the chip comes out of reset, P1DDR is set to all “1.”
Hardware Standby Mode: All pins are placed in the high-impedance state with the pull-up
transistors off. P1DR and P1PCR are initialized to H'00. In modes 2 and 3, P1DDR is initialized to
H'00.
Software Standby Mode: In the software standby mode, P1DDR, P1DR, and P1PCR remain in
their previous state. Address output pins are Low. General-purpose output pins continue to output
the data in P1DR.
Input Pull-Up Transistors: Port 1 has built-in programmable input pull-up transistors that are
available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn
on an input pull-up in mode 2 or 3, set the corresponding P1PCR bit to “1” and clear the
corresponding P1DDR bit to “0.” P1PCR is cleared to H'00 by a reset and in the hardware standby
mode, turning all input pull-ups off. In software standby mode, the previous state is maintained.
Table 5-4 indicates the states of the input pull-up transistors in each operating mode.
Table 5-4. States of Input Pull-Up Transistors (Port 1)
Mode
Reset
Off
Hardware standby
Software standby
Other operating modes
1
2
3
Off
Off
Off
Off
Off
Off
On/off
On/off
On/off
On/off
Off
Notes: Off:
The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P1PCR = “1” and P1DDR = “0,” but off
otherwise.
Figure 5-1 shows a schematic diagram of port 1.
79
Reset
R
D
Q
P1n PCR
C
WP1P
RP1P
Mode 1 Reset
Hardware standby
S
Q
R
D
P1n DDR
C
*
WP1D
Reset
Mode 3
R
D
Q
P1n
P1n DR
C
Mode 1 or 2
WP1
RP1
WP1P: Write Port 1 PCR
WP1D: Write Port 1 DDR
WP1: Write Port 1
RP1P : Read Port 1 PCR
RP1:
Read Port 1
n = 0 to 7
Note: * Set-priority
Figure 5-1. Port 1 Schematic Diagram
5.3 Port 2
Port 2 is an 8-bit input/output port that also provides the high bits of the address bus. The function
of port 2 depends on the MCU mode as indicated in table 5-5.
Table 5-5. Functions of Port 2
Mode 1
Mode 2
Mode 3
Address bus (High)
(A15 to A8)
Input port or
Address bus (High)
(A15 to A8)*
Input/output port
Note: * Depending on the bit settings in the data direction register: 0—input pin; 1—address pin
80
Pins of port 2 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive light-emitting diodes and a Darlington pair. When they are used as input
pins, they have programmable MOS transistor pull-ups.
Table 5-6 details the port 2 registers.
Table 5-6. Port 2 Registers
Name
Abbreviation Read/Write
Initial value
H'FF (mode 1)
H'00 (modes 2 and 3)
H'00
Address
Port 2 data direction
register
P2DDR
W
H'FFB1
Port 2 data register
Port 2 input pull-up
control register
P2DR
R/W
R/W
H'FFB3
H'FFAD
P2PCR
H'00
Port 2 Data Direction Register (P2DDR)—H'FFB1
Bit
7
6
5
4
3
2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P2DDR is an 8-bit register that selects the direction of each pin in port 2. A pin functions as an
output pin if the corresponding bit in P2DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Port 2 Data Register (P2DR)—H'FFB3
Bit
7
P27
0
6
P26
0
5
P25
0
4
P24
0
3
P23
0
2
P22
0
1
P21
0
0
P20
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P2DR is an 8-bit register containing the data for pins P27 to P20. When the CPU reads P2DR, for
output pins it reads the value in the P2DR latch, but for input pins, it obtains the logic level directly
from the pin, bypassing the P2DR latch.
81
Port 2 Input Pull-Up Control Register (P2PCR)—H'FFAD
Bit
7
6
5
4
3
2
1
0
P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P2PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 2. If a
bit in P2DDR is cleared to “0” (designating input) and the corresponding bit in P2PCR is set to “1,”
the input pull-up transistor for that bit is turned on.
Mode 1: In mode 1 (expanded mode without on-chip ROM), port 2 is automatically used for
address output. The port 2 data direction register is unwritable. All bits in P2DDR are
automatically set to “1” and cannot be cleared to “0.”
Mode 2: In mode 2 (expanded mode with on-chip ROM), the usage of port 2 can be selected on a
pin-by-pin basis. A pin is used for general-purpose input if its data direction bit is cleared to “0,”
or for address output if its data direction bit is set to “1.”
Mode 3: In the single-chip mode port 2 is a general-purpose input/output port.
Reset: A reset clears P2DDR, P2DR, and P2PCR to all “0,” placing all pins in the input state with
the pull-up transistors off. In mode 1, when the chip comes out of reset, P2DDR is set to all “1.”
Hardware Standby Mode: All pins are placed in the high-impedance state with the pull-up
transistors off. P2DR and P2PCR are initialized to H'00. In modes 2 and 3, P2DDR is initialized to
H'00.
Software Standby Mode: In the software standby mode, P2DDR, P2DR, and P2PCR remain in
their previous state. Address output pins are Low. General-purpose output pins continue to output
the data in P2DR.
Input Pull-Up Transistors: Port 2 has built-in programmable input pull-up transistors that are
available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn
on an input pull-up in mode 2 or 3, set the corresponding P2PCR bit to “1” and clear the
corresponding P2DDR bit to “0.” P2PCR is cleared to H'00 by a reset and in the hardware standby
mode, turning all input pull-ups off. In software standby mode, the previous state is maintained.
82
Table 5-7 indicates the states of the input pull-up transistors in each operating mode.
Table 5-7. States of Input Pull-Up Transistors (Port 2)
Mode
Reset
Off
Hardware standby
Software standby
Other operating modes
1
2
3
Off
Off
Off
Off
Off
Off
On/off
On/off
On/off
On/off
Off
Notes: Off:
The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P2PCR = “1” and P2DDR = “0,” but off
otherwise.
Figure 5-2 shows a schematic diagram of port 2.
Reset
R
Q
D
P2n PCR
C
WP2P
RP2P
Hardware
standby
Mode 1 Reset
S
Q
R
D
P2n DDR
C
*
WP2D
Reset
Mode 3
R
D
Q
P2n
P2n DR
C
Mode 1 or 2
WP2
RP2
WP2P: Write Port 2 PCR
WP2D: Write Port 2 DDR
WP2: Write Port 2
RP2P : Read Port 2 PCR
RP2:
Read Port 2
n = 0 to 7
Note: * Set-priority
Figure 5-2. Port 2 Schematic Diagram
83
5.4 Port 3
Port 3 is an 8-bit input/output port that also provides the external data bus. The function of port 3
depends on the MCU mode as indicated in table 5-8.
Table 5-8. Functions of Port 3
Mode 1
Mode 2
Mode 3
Data bus
Data bus
Input/output port
Pins of port 3 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive a Darlington pair. When they are used as input pins, they have program-
mable MOS transistor pull-ups.
Table 5-9 details the port 3 registers.
Table 5-9. Port 3 Registers
Name
Abbreviation
P3DDR
Read/Write
W
Initial value
H'00
Address
H'FFB4
H'FFB6
H'FFAE
Port 3 data direction register
Port 3 data register
Port 3 input pull-up control
register
P3DR
R/W
H'00
P3PCR
R/W
H'00
Port 3 Data Direction Register (P3DDR)—H'FFB4
Bit
7
6
5
4
3
2
1
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P3DDR is an 8-bit register that selects the direction of each pin in port 3. A pin functions as an
output pin if the corresponding bit in P3DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
84
Port 3 Data Register (P3DR)—H'FFB6
Bit
7
P37
0
6
P36
0
5
P35
0
4
P34
0
3
P33
0
2
P32
0
1
P31
0
0
P30
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3DR is an 8-bit register containing the data for pins P37 to P30. When the CPU reads P3DR, for
output pins it reads the value in the P3DR latch, but for input pins, it obtains the logic level directly
from the pin, bypassing the P3DR latch.
Port 3 Input Pull-Up Control Register (P3PCR)—H'FFAE
Bit
7
6
5
4
3
2
1
0
P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 3. If a
bit in P3DDR is cleared to “0” (designating input) and the corresponding bit in P3PCR is set to “1,”
the input pull-up transistor for that bit is turned on.
Modes 1 and 2: In the expanded modes, port 3 is automatically used as the data bus. The values
in P3DDR, P3DR, and P3PCR are ignored.
Mode 3: In the single-chip mode, port 3 can be used as a general-purpose input/output port.
85
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P3DDR, P3DR, and P3PCR to all “0.” All pins are placed in the high-impedance state with the
pull-up transistors off.
Software Standby Mode: In the software standby mode, P3DDR, P3DR, and P3PCR remain in
their previous state. In modes 1 and 2, all pins are placed in the data input (high-impedance) state.
In mode 3, all pins remain in their previous input or output state.
Input Pull-Up Transistors: Port 3 has built-in programmable input pull-up transistors that are
available in mode 3. The pull-up for each bit can be turned on and off individually. To turn on an
input pull-up in mode 3, set the corresponding P3PCR bit to “1” and clear the corresponding
P3DDR bit to “0.” P3PCR is cleared to H'00 by a reset and in the hardware standby mode, turning
all input pull-ups off. In software standby mode, the previous state is maintained.
Table 5-10 indicates the states of the input pull-up transistors in each operating mode.
Table 5-10. States of Input Pull-Up Transistors (Port 3)
Mode
Reset
Off
Hardware standby
Software standby
Other operating modes
1
2
3
Off
Off
Off
Off
Off
Off
Off
Off
Off
On/off
On/off
Notes: Off:
The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P3PCR = “1” and P3DDR = “0,” but off
otherwise.
Figure 5-3 shows a schematic diagram of port 3.
86
Reset
Mode 3
R
D
Q
P3n PCR
C
RP3P
WP3P
Mode 3
Reset
R
D
Q
External
address
write
P3n DDR
C
WP3D
Mode 3
Reset
R
Q
D
P3n
P3n DR
C
Mode 1 or 2
WP3
RP3
External address
read
WP3P: Write Port 3 PCR
WP3D: Write Port 3 DDR
WP3: Write Port 3
RP3P : Read Port 3 PCR
RP3:
Read Port 3
n = 0 to 7
Figure 5-3. Port 3 Schematic Diagram
87
5.5 Port 4
Port 4 is an 8-bit input/output port that also provides pins for interrupt input (IRQ0 to IRQ2), A/D
trigger input, system clock (Ø) output, and bus control signals (in the expanded modes).
Pins P47 to P43 have different functions in different modes. Pins P42 to P40 have the same
functions in all modes. Table 5-11 lists the pin functions.
Table 5-11. Port 4 Pin Functions
Pin
P40
P41
P42
P43
P44
P45
P46
P47
Expanded modes
Single-chip mode
P40 input/output , IRQ2 input, and ADTRG input (simultaneously)
P41 input/output and IRQ1 input (simultaneously)
P42 input/output and IRQ0 input (simultaneously)
RD output
WR output
AS output
Ø output
P43 input/output
P44 input/output
P45 input/output
P46 input or Ø output
P47 input/output
WAIT input
Pins of port 4 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins.
Table 5-12 details the port 4 registers.
Table 5-12. Port 4 Registers
Name
Abbreviation Read/Write Initial value
Address
H'40 (modes 1 and 2) H'FFB5
H'00 (mode 3)
Port 4 data direction register P4DDR
W
Port 4 data register
P4DR
R/W*1
Undetermined*2
H'FFB7
Notes: *1 Bit 6 is read-only.
*2 Bit 6 is undetermined. Other bits are initially “0.”
88
Port 4 Data Direction Register (P4DDR)—H'FFB5
Bit
7
6
5
4
3
2
1
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Modes 1 and 2
Initial value
Read/Write
Mode 3
0
1
0
0
0
0
0
0
W
—
W
W
W
W
W
W
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P4DDR is an 8-bit register that selects the direction of each pin in port 4. A pin functions as an
output pin if the corresponding bit in P4DDR is set to “1,” and as in input pin if the bit is cleared to
“0.”
Port 4 Data Register (P4DR)—H'FFB7
Bit
7
P47
0
6
P46
*
5
P45
0
4
P44
0
3
P43
0
2
P42
0
1
P41
0
0
P40
0
Initial value
Read/Write
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Determined by the level at pin P46.
P4DR is an 8-bit register containing the data for pins P47 to P40. When the CPU reads P4DR, for
output pins (P4DDR = “1”) it reads the value in the P4DR latch, but for input pins (P4DDR = “0”),
it obtains the logic level directly from the pin, bypassing the P4DR latch. This also applies to pins
used for interrupt input, A/D trigger input, clock output, and control signal input or output.
Pins P40, P41, and P42: Can be used for general-purpose input or output, interrupt request input,
or A/D trigger input. See table 5-11. If a pin is used for interrupt or A/D trigger input, its data
direction bit should be cleared to “0,” so that the output from P4DR will not generate an interrupt
request or A/D trigger signal.
Pins P43, P44 and P45: In modes 1 and 2 (the expanded modes), these pins are used for output of
the RD, WR, and AS bus control signals. They are unaffected by the values in P4DDR and P4DR.
89
In mode 3 (single-chip mode), these pins can be used for general-purpose input or output.
Pin P46: In modes 1 and 2, this pin is used for system clock (Ø) output.
In mode 3, this pin is used for general-purpose input if P46DDR is cleared to “0,” or system clock
output if P46DDR is set to “1.”
Pin P47: In modes 1 and 2, this pin is used for input of the WAIT bus control signal. It is
unaffected by the values in P4DDR and P4DR.
In mode 3 (single-chip mode), this pin can be used for general-purpose input or output.
Reset: In the single-chip mode (mode 3), a reset initializes all pins of port 4 to the general-purpose
input function. In the expanded modes (modes 1 and 2), P40 to P42 are initialized as input port
pins, and P43 to P47 are initialized to their bus control and system clock output functions.
Hardware Standby Mode: All pins are placed in the high-impedance state.
90
Software Standby Mode: All pins remain in their previous state. For RD, WR, AS, and Ø this
means the High output state.
Figures 5-4 to 5-8 show schematic diagrams of port 4.
Reset
R
Q
D
P4.0 DDR
C
WP4D
Reset
R
D
P40
Q
P40 DR
C
WP4
RP4
A/D converter
module
ADTRG
IRQ2 input
WP4D: Write Port 4 DDR
WP4: Write Port 4
IRQ enable
register
RP4:
Read Port 4
IRQ2 enable
Figure 5-4. Port 4 Schematic Diagram (Pin P40)
91
Reset
R
D
Q
P4n DDR
C
WP4D
Reset
R
D
P4n
Q
P4n DR
C
WP4
RP4
IRQ0 input
IRQ1 input
WP4D: Write Port 4 DDR
WP4: Write Port 4
IRQ enable
register
RP4:
Read Port 4
n = 1, 2
IRQ0 enable
IRQ1 enable
Figure 5-5. Port 4 Schematic Diagram (Pins P41 and P42)
92
Hardware standby
Mode 1 or 2
Reset
R
D
Q
P4n DDR
C
WP4D
Mode 3
Reset
R
D
Q
P4 n
P4n DR
C
Mode 1 or 2
WP4
RD output
WR output
AS ouput
RP4
WP4D: Write Port 4 DDR
WP4: Write Port 4
RP4:
Read Port 4
n = 3, 4, 5
Figure 5-6. Port 4 Schematic Diagram (Pins P43, P44 and P45)
93
Mode 1, 2 Reset
Hardware standby
S
Q
R
D
P46 DDR
C
*
WP4D
P46
Ø
RP9
WP4D: Write Port 4 DDR
WP4: Write Port 4
RP4: Read Port 4
Note: * Set-priority
Figure 5-7. Port 4 Schematic Diagram (Pin P46)
94
Reset
Mode 1 or 2
R
D
Q
P47 DDR
C
WP4D
Reset
R
D
P47
Q
P47 DR
C
WP4
RP4
WAIT
input
WP4D: Write Port 4 DDR
WP4: Write Port 4
RP4:
Read Port 4
Figure 5-8. Port 4 Schematic Diagram (Pin P47)
95
5.6 Port 5
Port 5 is a 3-bit input/output port that also provides input and output pins for the serial communi-
cation interface (SCI). The pin functions depend on control bits in the serial control register (SCR).
Pins not used for serial communication are available for general-purpose input/output. Table 5-13
lists the pin functions, which are the same in both the expanded and single-chip modes.
Table 5-13. Port 5 Pin Functions (Modes 1 to 3)
Usage
Pin functions
I/O port
P50
P51
P52
Serial communication interface
TxD
RxD
SCK
See section 8, “Serial Communication Interface” for details of the serial control bits. Pins used by
the serial communication interface are switched between input and output without regard to the
values in the data direction register.
Pins of port 5 can drive a single TTL load and a 30pF capacitive load when they are used as output
pins. They can also drive a Darlington pair.
Table 5-14 details the port 5 registers.
Table 5-14. Port 5 Registers
Name
Abbreviation
P5DDR
Read/Write
Initial value
H'F8
Address
H'FFB8
H'FFBA
Port 5 data direction register
Port 5 data register
W
P5DR
R/W
H'F8
Port 5 Data Direction Register (P5DDR)—H'FFB8
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
P52DDR P51DDR P50DDR
Initial value
Read/Write
0
0
0
—
—
—
—
—
W
W
W
P5DDR is an 8-bit register that selects the direction of each pin in port 5. A pin functions as an
output pin if the corresponding bit in P5DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
96
Port 5 Data Register (P5DR)—H'FFBA
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
P52
0
1
P51
0
0
P50
0
Initial value
Read/Write
—
—
—
—
—
R/W
R/W
R/W
P5DR is an 8-bit register containing the data for pins P52 to P50. When the CPU reads P5DR, for
output pins (P5DDR = “1”) it reads the value in the P5DR latch, but for input pins (P5DDR = “0”),
it obtains the logic level directly from the pin, bypassing the P5DR latch. This also applies to pins
used for serial communication.
Pin P50: This pin can be used for general-purpose input or output, or for output of serial transmit
data (TxD). When used for TxD output, this pin is unaffected by the values in P5DDR and P5DR.
Pin P51: This pin can be used for general-purpose input or output, or for input of serial receive
data (RxD). When used for RxD input, this pin is unaffected by P5DDR and P5DR.
Pin P52: This pin can be used for general-purpose input or output, or for serial clock input or
output (SCK). When used for SCK input or output, this pin is unaffected by P5DDR and P5DR.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode makes all
pins of port 5 into input port pins.
Software Standby Mode: In the software standby mode, the serial control register is initialized
but P5DDR and P5DR remain in their previous states. All pins become input or output port pins
depending on the setting of P5DDR. Output pins output the values in P5DR.
Figures 5-9 to 5-11 show schematic diagrams of port 5.
97
Reset
R
D
Q
P50 DDR
C
WP5D
Reset
R
D
Q
P50
P50 DR
C
SCI module
WP5
Serial transmit enable
Serial transmit data
RP5
WP5D: Write Port 5 DDR
WP5: Write Port 5
RP5:
Read Port 5
Figure 5-9. Port 5 Schematic Diagram (Pin P50)
98
Reset
R
D
Q
P51 DDR
C
SCI module
WP5D
Serial receive
enable
Reset
R
D
P51
Q
P51 DR
C
WP5
RP5
Serial receive
data
WP5D: Write Port 5 DDR
WP5: Write Port 5
RP5:
Read Port 5
Figure 5-10. Port 5 Schematic Diagram (Pin P51)
99
Reset
R
D
Q
P52 DDR
C
SCI module
WP5D
Serial clock
input enable
Reset
R
D
Q
P52
P52 DR
C
WP5
Serial clock
output enble
Serial clock
output enable
RP5
Serial clock
input
WP5D: Write Port 5 DDR
WP5: Write Port 5
RP5:
Read Port 5
Figure 5-11. Port 5 Schematic Diagram (Pin P52)
100
5.7 Port 6
Port 6 is an 8-bit input/output port that also provides input and output pins for the 16-bit free-
running timer and 8-bit timers. The pin functions depend on control bits in the control registers of
the timers. Pins not used by the timers are available for general-purpose input/output. Table 5-15
lists the pin functions, which are the same in both the expanded and single-chip modes.
Table 5-15. Port 6 Pin Functions (Modes 1 to 3)
Usage
Pin functions (Modes 1 to 3)
I/O port
P60
P61
P62
P63
P64
P65
P66
P67
—
16-bit timer
8-bit timer
FTCI
FTOA FTIA
FTIB
FTIC
FTID
FTOB
TMCI0 —
—
TMRI0 TMO0 TMCI1 TMRI1 TMO1
See section 6, “16-Bit Free-Running Timer,” and section 7, “8-Bit Timers” for details of the timer
control bits.
Pins of port 6 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive a Darlington pair.
Table 5-16 details the port 6 registers.
Table 5-16. Port 6 Registers
Name
Abbreviation
P6DDR
Read/Write
Initial value
H'00
Address
H'FFB9
H'FFBB
Port 6 data direction register
Port 6 data register
W
P6DR
R/W
H'00
Port 6 Data Direction Register (P6DDR)—H'FFB9
Bit
7
6
5
4
3
2
1
0
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P6DDR is an 8-bit register that selects the direction of each pin in port 6. A pin functions as an
output pin if the corresponding bit in P6DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
101
Port 6 Data Register (P6DR)—H'FFBB
Bit
7
P67
0
6
P66
0
5
P65
0
4
P64
0
3
P63
0
2
P62
0
1
P61
0
0
P60
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P6DR is an 8-bit register containing the data for pins P67 to P60. When the CPU reads P6DR, for
output pins (P6DDR = “1”) it reads the value in the P6DR latch, but for input pins (P6DDR = “0”),
it obtains the logic level directly from the pin, bypassing the P6DR latch. This also applies to pins
used for timer input and output.
Pin P60: This pin can be used for general-purpose input or output, and input of external clock
signals to the 16-bit free-running timer and 8-bit timer 0. External clock input is selected by the
CKS bits of the timers. When this pin is used for timer clock input, its P6DDR bit should normally
be cleared to “0;” otherwise the timer will receive the value in P6DR.
Pin P61: This pin can be used for general-purpose input or output, or for 16-bit free-running timer
output (FTOA). When timer output is selected by the OEA bit of the 16-bit free-running timer, this
pin is unaffected by the values in P6DDR and P6DR.
Pin P62: This pin can be used for general-purpose input or output, and input of the FTIA input
capture signal to the 16-bit free-running timer. FTIA input can operate simultaneously with
general-purpose input or output.
Pin P63: This pin can be used for general-purpose input or output, input of the FTIB input capture
signal to the 16-bit free-running timer, and input of the timer reset signal to 8-bit timer 0. FTIB
input operates simultaneously with the other functions. Reset signal input is selected by the CCLR
bits of 8-bit timer 0. When this pin is used for timer reset signal input, its P6DDR bit should
normally be cleared to “0;” otherwise the timer will receive the value in P6DR.
Pin P64: This pin can be used for general-purpose input or output, input of the FTIC input capture
signal to the 16-bit free-running timer, or output from 8-bit timer 0. FTIC input operates
simultaneously with the other functions. When 8-bit timer output is selected by the OS bits of 8-bit
timer 0, this pin is unaffected by the values in P6DDR and P6DR.
102
Pin P65: This pin can be used for general-purpose input or output, input of the FTID input capture
signal to the 16-bit free-running timer, or input of an external clock signal to 8-bit timer 1. FTID
input operates simultaneously with the other functions. When external clock input is selected by
the CKS bits of 8-bit timer 1, the P6DDR bit of this pin should normally be cleared to “0,”
otherwise the timer will receive the value in P6DR.
Pin P66: This pin can be used for general-purpose input or output, 16-bit free-running timer output
(FTOB), and input of the timer reset signal to 8-bit timer 1. Reset signal input is selected by the
CCLR bits of 8-bit timer 1, and can operate simultaneously with general-purpose input or output or
16-bit timer output. When 16-bit timer output is selected by the OEB bit of the 16-bit free-running
timer, this pin is unaffected by the values in P6DDR and P6DR.
Pin P67: This pin can be used for general-purpose input or output, or output from 8-bit timer 1.
When 8-bit timer output is selected by the OS bits of 8-bit timer 1, this pin is unaffected by the
values in P6DDR and P6DR.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P6DDR and P6DR to all “0” and initializes the control registers of both the 8-bit and 16-bit timers.
All pins become input port pins.
Software Standby Mode: In the software standby mode, the control registers of the 8-bit and 16-
bit timers are initialized but P6DDR and P6DR remain in their previous states. All pins become
input or output port pins depending on the setting of P6DDR. Output pins output the values in
P6DR.
Figures 5-12 to 5-18 show schematic diagrams of port 6.
103
Reset
R
D
Q
P60 DDR
C
WP6D
Reset
R
D
P60
Q
P60 DR
C
WP6
RP6
Free-running timer
module
Counter clock input
8-bit timer module
Counter clock input
WP6D: Write Port 6 DDR
WP6: Write Port 6
RP6:
Read Port 6
Figure 5-12. Port 6 Schematic Diagram (Pin P60)
104
Reset
R
D
Q
P61 DDR
C
WP6D
Reset
R
D
Q
P61
P61 DR
C
Free-running timer
module
WP6
Output enable
Output-compare
output
RP6
WP6D: Write Port 6 DDR
WP6: Write Port 6
RP6:
Read Port 6
Figure 5-13. Port 6 Schematic Diagram (Pin P61)
105
Reset
R
D
Q
P62 DDR
C
WP6D
Reset
R
D
P62
Q
P62 DR
C
WP6
RP6
Free-running timer
module
Input-capture input
WP6D: Write Port 6 DDR
WP6: Write Port 6
RP6:
Read Port 6
Figure 5-14. Port 6 Schematic Diagram (Pin P62)
106
Reset
R
D
Q
P6n DDR
C
WP6D
Reset
R
D
P6n
Q
P6n DR
C
WP6
RP6
Free-running timer
module
Input-capture input
8-bit timer module
Counter clock input
Counter reset input
WP6D: Write Port 6 DDR
WP6: Write Port 6
RP6:
Read Port 6
n = 3, 5
Figure 5-15. Port 6 Schematic Diagram (Pins P63 and P65)
107
Reset
R
D
Q
P64 DDR
C
WP6D
Reset
R
D
Q
P64
P64 DR
C
8-bit timer module
WP6
Output enable
8-bit timer output
RP6
Free-running timer
module
Input-capture input
WP6D: Write Port 6 DDR
WP6: Write Port 6
RP6:
Read Port 6
Figure 5-16. Port 6 Schematic Diagram (Pin P64)
108
Reset
R
D
Q
P66 DDR
C
WP6D
Reset
R
D
Q
P66
P66 DR
C
Free-running timer
module
WP6
Output enable
Output-compare
output
RP6
8-bit timer module
Counter reset input
WP6D: Write Port 6 DDR
WP6: Write Port 6
RP6:
Read Port 6
Figure 5-17. Port 6 Schematic Diagram (Pin P66)
109
Reset
R
D
Q
P67 DDR
C
WP6D
Reset
R
D
Q
P67
P67 DR
C
8-bit timer module
WP6
Output enable
8-bit timer output
RP6
WP6D: Write Port 6 DDR
WP6: Write Port 6
RP6:
Read Port 6
Figure 5-18. Port 6 Schematic Diagram (Pin P67)
110
5.8 Port 7
Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter module.
The pin functions are the same in both the expanded and single-chip modes.
Table 5-17 lists the pin functions. Table 5-18 describes the port 7 data register, which simply
consists of connections of the port 7 pins to the internal data bus. Figure 5-19 shows a schematic
diagram of port 7.
Table 5-17. Port 7 Pin Functions (Modes 1 to 3)
Usage
Pin functions
I/O port
P70
P71
P72
P73
P74
P75
P76
P77
Analog input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Table 5-18. Port 7 Register
Name
Abbreviation
Read/Write
Initial value
Address
Port 7 data register
P7DR
R
Undetermined
H'FFBE
Port 7 Data Register (P7DR)—H'FFBE
Bit
7
P77
*
6
P76
*
5
P75
*
4
P74
*
3
P73
*
2
P72
*
1
P71
*
0
P70
*
Initial value
Read/Write
R
R
R
R
R
R
R
R
Note: * Depends on the levels of pins P77 to P70.
RP7
A/D converter
module
P7n
Analog input
RP7: Read port 7
n = 0 to 7
Figure 5-19. Port 7 Schematic Diagram
111
Section 6. 16-Bit Free-Running Timer
6.1 Overview
The H8/329 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free-
running counter as a time base. Applications of the FRT module include rectangular-wave output
(up to two independent waveforms), input pulse width measurement, and measurement of external
clock periods.
6.1.1 Features
The features of the free-running timer module are listed below.
• Selection of four clock sources
The free-running counter can be driven by an internal clock source (Ø/2, Ø/8, or Ø/32), or an
external clock input (enabling use as an external event counter).
• Two independent comparators
Each comparator can generate an independent waveform.
• Four input capture channels
The current count can be captured on the rising or falling edge (selectable) of an input signal.
The four input capture registers can be used separately, or in a buffer mode.
• Counter can be cleared under program control
The free-running counters can be cleared on compare-match A.
• Seven independent interrupts
Compare-match A and B, input capture A to D, and overflow interrupts are requested
independently.
113
6.1.2 Block Diagram
Figure 6-1 shows a block diagram of the free-running timer.
Internal
clock sources
Ø/2
External
Ø/8
Ø/32
clock source
FTCI
Clock
OCRA (H/L)
Comparator A
FRC(H/L)
Clock select
Compare-
match A
FTOA
FTOB
Overflow
Clear
Internal
data bus
Comparator B
OCRB (H/L)
Compare-
match B
Control
logic
Capture
ICRA (H/L)
ICRB (H/L)
FTIA
FTIB
ICRC (H/L)
ICRD (H/L)
FTIC
FTID
TCSR
TIER
TCR
TOCR
ICIA
ICIB
ICIC
ICID
OCIA
OCIB
Interrupt signals
FOVI
FRC:
OCRA, B:
Free-Running Counter (16 bits)
Output Compare Register A, B (16 bits)
TIER: Timer Interrupt Enable Register (8 bits)
TCR: Timer Control Register (8 bits)
TOCR: Timer Output Compare Control
Register (8 bits)
ICRA, B, C, D: Input Capture Register A, B, C, D (16 bits)
TCSR: Timer Control/Status Register (8 bits)
Figure 6-1. Block Diagram of 16-Bit Free-Running Timer
114
6.1.3 Input and Output Pins
Table 6-1 lists the input and output pins of the free-running timer module.
Table 6-1. Input and Output Pins of Free-Running Timer Module
Name
Abbreviation
I/O
Function
Counter clock input FTCI
Input
Input of external free-running counter clock
signal
Output compare A
Output compare B
Input capture A
FTOA
FTOB
FTIA
Output
Output
Input
Output controlled by comparator A
Output controlled by comparator B
Trigger for capturing current count into input
capture register A
Input capture B
Input capture C
Input capture D
FTIB
FTIC
FTID
Input
Input
Input
Trigger for capturing current count into input
capture register B
Trigger for capturing current count into input
capture register C
Trigger for capturing current count into input
capture register D
6.1.4 Register Configuration
Table 6-2 lists the registers of the free-running timer module.
Table 6-2. Register Configuration
Initial
value
H'01
Name
Abbreviation R/W
Address
H'FF90
H'FF91
H'FF92
H'FF93
H'FF94*2
H'FF95*2
H'FF96
H'FF97
H'FF98
H'FF99
Timer interrupt enable register
Timer control/status register
Free-running counter (High)
Free-running counter (Low)
Output compare register A/B (High)*2
Output compare register A/B (Low)*2
Timer control register
TIER
R/W
TCSR
R/(W)*1 H'00
FRC (H)
FRC (L)
OCRA/B (H)
OCRA/B (L)
TCR
R/W
R/W
R/W
R/W
R/W
R/W
R
H'00
H'00
H'FF
H'FF
H'00
H'E0
H'00
H'00
Timer output compare control register
Input capture register A (High)
Input capture register A (Low)
TOCR
ICRA (H)
ICRA (L)
R
Notes: *1 Software can write a “0” to clear bits 7 to 1, but cannot write a “1” in these bits.
*2 OCRA and OCRB share the same addresses. Access is controlled by the OCRS
bit in TOCR.
115
Table 6-2. Register Configuration (cont.)
Initial
value
H'00
H'00
H'00
H'00
H'00
H'00
Name
Abbreviation R/W
Address
H'FF9A
H'FF9B
H'FF9C
H'FF9D
H'FF9E
H'FF9F
Input capture register B (High)
Input capture register B (Low)
Input capture register C (High)
Input capture register C (Low)
Input capture register D (High)
Input capture register D (Low)
ICRB (H)
ICRB (L)
ICRC (H)
ICRC (L)
ICRD (H)
ICRD (L)
R
R
R
R
R
R
6.2 Register Descriptions
6.2.1 Free-Running Counter (FRC)—H'FF92
Bit
15 14 13
12 11 10
9
0
8
0
7
0
6
5
0
4
0
3
0
2
0
1
0
0
0
Initial 0
value
0
0
0
0
0
0
Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Write
The FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated
from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and
CKS0) of the timer control register (TCR).
When the FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to “1.”
Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is written
or read. See section 6.3, “CPU Interface,” for details.
The FRC is initialized to H'0000 at a reset and in the standby modes. It can also be cleared by
compare-match A.
116
6.2.2 Output Compare Registers A and B (OCRA and OCRB)—H'FF94
Bit
15 14 13
12 11 10
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Initial 1
value
1
1
1
1
1
Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Write
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually
compared with the value in the FRC. When a match is detected, the corresponding output compare
flag (OCFA or OCFB) is set in the timer control/status register (TCSR).
In addition, if the output enable bit (OEA or OEB) in the timer output compare control register
(TOCR) is set to “1,” when the output compare register and FRC values match, the logic level
selected by the output level bit (OLVLA or OLVLB) in the TOCR is output at the output compare
pin (FTOA or FTOB).
OCRA and OCRB share the same address. They are differentiated by the OCRS bit in the TOCR.
A temporary register (TEMP) is used for write access, as explained in section 6.3, “CPU Interface.”
OCRA and OCRB are initialized to H'FFFF at a reset and in the standby modes.
6.2.3 Input Capture Registers A to D (ICRA to ICRD)—H'FF98, H'FF9A, H'FF9C, H'FF9E
Bit
15 14 13
12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Initial 0
value
0
0
0
0
0
Read/ R
Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Each input capture register is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected, the
current value of the FRC is copied to the corresponding input capture register (ICRA to ICRD).*
At the same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status
register (TCSR) is set to “1.” The input capture edge is selected by the input edge select bits
(IEDGA to IEDGD) in the timer control register (TCR).
117
Note: * The FRC contents are transferred to the input capture register regardless of the value of
the input capture flag (ICFA/B/C/D).
Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in
the timer control register (TCR) is set to “1,” ICRC is used as a buffer register for ICRA as shown
in figure 6-2. When an FTIA input is received, the old ICRA contents are moved into ICRC, and
the new FRC count is copied into ICRA.
BUFEA
IEDGA IEDGC
Edge detect and
capture signal
FTIA
generating circuit
FRC
ICRC
ICRA
BUFEA: Buffer Enable A
IEDGA: Input Edge Select A
IEDGC: Input Edge Select C
ICRC:
ICRA:
FRC:
Input Capture Register C
Input Capture Register A
Free-Running Counter
Figure 6-2. Input Capture Buffering
Similarly, when the BUFEB bit in TIER is set to “1,” ICRD is used as a buffer register for ICRB.
When input capture is buffered, if the two input edge bits are set to different values (IEDGA ≠
IEDGC or IEDGB ≠ IEDGD), then input capture is triggered on both the rising and falling edges of
the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA =
IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge.
118
Table 6-3. Buffered Input Capture Edge Selection (Example)
IEDGA
IEDGC
Input Capture Edge
0
0
1
1
0
1
0
1
Captured on falling edge of input capture A (FTIA)
(Initial value)
Captured on both rising and falling edges of input capture A (FTIA)
Captured on rising edge of input capture A (FTIA)
Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when
they are read. See section 6.3, “CPU Interface,” for details.
To ensure input capture, the width of the input capture pulse (FTIA, FTIB, FTIC, FTID) should be
at least 1.5 system clock periods (1.5·Ø). When triggering is enabled on both edges, the input
capture pulse width should be at least 2.5 system clock periods.
Ø
FTIA, FTIB,
FTIC, orFTID
Figure 6-3. Minimum Input Capture Pulse Width
119
The input capture registers are initialized to H'0000 at a reset and in the standby modes.
Note: When input capture is detected, the FRC value is transferred to the input capture register
even if the input capture flag is already set.
6.2.4 Timer Interrupt Enable Register (TIER)—H'FF90
Bit
7
6
5
4
3
2
1
0
—
1
ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE
Initial value
Read/Write
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
The TIER is an 8-bit readable/writable register that enables and disables interrupts.
The TIER is initialized to H'01 (all interrupts disabled) at a reset and in the standby modes.
Bit 7—Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input
capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register
(TCSR) is set to “1.”
Bit 7
ICIAE
Description
0
1
Input capture interrupt request A (ICIA) is disabled.
Input capture interrupt request A (ICIA) is enabled.
(Initial value)
Bit 6—Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input
capture interrupt B (ICIB) when input capture flag B (ICFB) in the timer status/control register
(TCSR) is set to “1.”
Bit 6
ICIBE
Description
0
1
Input capture interrupt request B (ICIB) is disabled.
Input capture interrupt request B (ICIB) is enabled.
(Initial value)
Bit 5—Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input
capture interrupt C (ICIC) when input capture flag C (ICFC) in the timer status/control register
(TCSR) is set to “1.”
120
Bit 5
ICICE
Description
0
1
Input capture interrupt request C (ICIC) is disabled.
Input capture interrupt request C (ICIC) is enabled.
(Initial value)
Bit 4—Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input
capture interrupt D (ICID) when input capture flag D (ICFD) in the timer status/control register
(TCSR) is set to “1.”
Bit 4
ICIDE
Description
0
1
Input capture interrupt request D (ICID) is disabled.
Input capture interrupt request D (ICID) is enabled.
(Initial value)
Bit 3—Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request
output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer status/control
register (TCSR) is set to “1.”
Bit 3
OCIAE Description
0
1
Output compare interrupt request A (OCIA) is disabled.
Output compare interrupt request A (OCIA) is enabled.
(Initial value)
Bit 2—Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request
output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer status/control
register (TCSR) is set to “1.”
Bit 2
OCIBE Description
0
1
Output compare interrupt request B (OCIB) is disabled.
Output compare interrupt request B (OCIB) is enabled.
(Initial value)
Bit 1—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a free-
running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer
status/control register (TCSR) is set to “1.”
121
Bit 1
OVIE
Description
0
1
Timer overflow interrupt request (FOVI) is disabled.
Timer overflow interrupt request (FOVI) is enabled.
(Initial value)
Bit 0—Reserved: This bit cannot be modified and is always read as “1.”
6.2.5 Timer Control/Status Register (TCSR)—H'FF91
Bit
7
ICFA
0
6
ICFB
0
5
ICFC
0
4
ICFD
0
3
2
1
0
OCFA OCFB
OVF CCLRA
Initial value
Read/Write
0
0
0
0
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
R/W
The TCSR is an 8-bit readable and partially writable* register that contains the seven interrupt flags
and specifies whether to clear the counter on compare-match A (when the FRC and OCRA values
match).
Note: * Software can write a “0” in bits 7 to 1 to clear the flags, but cannot write a “1” in these
bits.
The TCSR is initialized to H'00 at a reset and in the standby modes.
Bit 7—Input Capture Flag A (ICFA): This status bit is set to “1” to flag an input capture A
event. If BUFEA = “0,” ICFA indicates that the FRC value has been copied to ICRA. If BUFEA =
“1,” ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value
has been copied to ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 7
ICFA
Description
0
To clear ICFA, the CPU must read ICFA after it
has been set to “1,” then write a “0” in this bit.
This bit is set to 1 when an FTIA input signal causes the FRC
value to be copied to ICRA.
(Initial value)
1
122
Bit 6—Input Capture Flag B (ICFB): This status bit is set to “1” to flag an input capture B
event. If BUFEB = “0,” ICFB indicates that the FRC value has been copied to ICRB. If BUFEB =
“1,” ICFB indicates that the old ICRB value has been moved into ICRC and the new FRC value has
been copied to ICRB.
ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6
ICFB
Description
0
To clear ICFB, the CPU must read ICFB after it
has been set to “1,” then write a “0” in this bit.
This bit is set to 1 when an FTIB input signal causes the FRC value
to be copied to ICRB.
(Initial value)
1
Bit 5—Input Capture Flag C (ICFC): This status bit is set to “1” to flag input of a rising or
falling edge of FTIC as selected by the IEDGC bit. When BUFEA = “0,” this indicates capture of
the FRC count in ICRC. When BUFEA = “1,” however, the FRC count is not captured, so ICFC
becomes simply an external interrupt flag. In other words, the buffer mode frees FTIC for use as a
general-purpose interrupt signal (which can be enabled or disabled by the ICICE bit).
ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 5
ICFC
Description
0
To clear ICFC, the CPU must read ICFC after it
has been set to “1,” then write a “0” in this bit.
This bit is set to 1 when an FTIC input signal is received.
(Initial value)
1
Bit 4—Input Capture Flag D (ICFD): This status bit is set to “1” to flag input of a rising or
falling edge of FTID as selected by the IEDGD bit. When BUFEB = “0,” this indicates capture of
the FRC count in ICRD. When BUFEB = “1,” however, the FRC count is not captured, so ICFD
becomes simply an external interrupt flag. In other words, the buffer mode frees FTID for use as a
general-purpose interrupt signal (which can be enabled or disabled by the ICIDE bit).
ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software.
123
Bit 4
ICFD
0
Description
To clear ICFD, the CPU must read ICFD after it
has been set to “1,” then write a “0” in this bit.
This bit is set to 1 when an FTID input signal is received.
(Initial value)
1
Bit 3—Output Compare Flag A (OCFA): This status flag is set to “1” when the FRC value
matches the OCRA value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 3
OCFA
Description
0
To clear OCFA, the CPU must read OCFA after
it has been set to “1,” then write a “0” in this bit.
This bit is set to 1 when FRC = OCRA.
(Initial value)
1
Bit 2—Output Compare Flag B (OCFB): This status flag is set to “1” when the FRC value
matches the OCRB value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 2
OCFB
Description
0
To clear OCFB, the CPU must read OCFB after
it has been set to “1,” then write a “0” in this bit.
This bit is set to 1 when FRC = OCRB.
(Initial value)
1
Bit 1—Timer Overflow Flag (OVF): This status flag is set to “1” when the FRC overflows
(changes from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 1
OVF
Description
0
To clear OVF, the CPU must read OVF after
it has been set to “1,” then write a “0” in this bit.
This bit is set to 1 when FRC changes from H'FFFF to H'0000.
(Initial value)
1
124
Bit 0—Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match
A (when the FRC and OCRA values match).
Bit 0
CCLRA Description
0
1
The FRC is not cleared.
(Initial value)
The FRC is cleared at compare-match A.
6.2.6 Timer Control Register (TCR)—H'FF96
Bit
7
6
5
4
3
2
1
0
IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1
CKS0
0
Initial value
Read/Write
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input
capture signals, enables the input capture buffer mode, and selects the FRC clock source.
The TCR is initialized to H'00 at a reset and in the standby modes.
Bit 7—Input Edge Select A (IEDGA): This bit causes input capture A events to be recognized on
the selected edge of the input capture A signal (FTIA).
Bit 7
IEDGA Description
0
1
Input capture A events are recognized on the falling edge of FTIA.
Input capture A events are recognized on the rising edge of FTIA.
(Initial value)
Bit 6—Input Edge Select B (IEDGB): This bit causes input capture B events to be recognized on
the selected edge of the input capture B signal (FTIB).
Bit 6
IEDGB Description
0
1
Input capture B events are recognized on the falling edge of FTIB.
Input capture B events are recognized on the rising edge of FTIB.
(Initial value)
125
Bit 5—Input Edge Select C (IEDGC): This bit causes input capture C events to be recognized on
the selected edge of the input capture C signal (FTIC).
Bit 5
IEDGC Description
0
1
Input capture C events are recognized on the falling edge of FTIC.
Input capture C events are recognized on the rising edge of FTIC.
(Initial value)
Bit 4—Input Edge Select D (IEDGD): This bit causes input capture D events to be recognized on
the selected edge of the input capture D signal (FTID).
Bit 4
IEDGD Description
0
1
Input capture D events are recognized on the falling edge of FTID.
Input capture D events are recognized on the rising edge of FTID.
(Initial value)
Bit 3—Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for
ICRA.
Bit 3
BUFEA Description
0
1
ICRC is used for input capture C.
(Initial value)
ICRC is used as a buffer register for input capture A. Input C is not captured.
Bit 2—Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for
ICRB.
Bit 2
BUFEB Description
0
1
ICRD is used for input capture D.
(Initial value)
ICRD is used as a buffer register for input capture B. Input D is not captured.
Bits 1 and 0—Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
126
Bit 1
Bit 0
CKS1
CKS0
Description
0
0
1
1
0
1
0
1
Ø/2 Internal clock source
Ø/8 Internal clock source
Ø/32 Internal clock source
External clock source (rising edge)
(Initial value)
6.2.7 Timer Output Compare Control Register (TOCR)—H'FF97
Bit
7
—
1
6
—
1
5
—
1
4
OCRS
0
3
2
1
0
OEA
0
OEB OLVLA OLVLB
Initial value
Read/Write
0
0
0
—
—
—
R/W
R/W
R/W
R/W
R/W
The TOCR is an 8-bit readable/writable register that controls the output compare function.
The TOCR is initialized to H'E0 at a reset and in the standby modes.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as “1.”
Bit 4—Output Compare Register Select (OCRS): When the CPU accesses addresses H'FF94
and H'FF95, this bit directs the access to either OCRA or OCRB. These two registers share the
same addresses as follows:
Upper byte of OCRA and upper byte of OCRB: H'FF94
Lower byte of OCRA and lower byte of OCRB: H'FF95
Bit 4
OCRS
Description
0
1
The CPU can access OCRA.
The CPU can access OCRB.
(Initial value)
Bit 3—Output Enable A (OEA): This bit enables or disables output of the output compare A
signal (FTOA).
Bit 3
OEA
Description
0
1
Output compare A output is disabled.
Output compare A output is enabled.
(Initial value)
127
Bit 2—Output Enable B (OEB): This bit enables or disables output of the output compare B
signal (FTOB).
Bit 2
OEB Description
0
1
Output compare B output is disabled.
Output compare B output is enabled.
(Initial value)
Bit 1—Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin
when the FRC and OCRA values match.
Bit 1
OLVLA Description
0
1
A “0” logic level (Low) is output for compare-match A.
A “1” logic level (High) is output for compare-match A.
(Initial value)
Bit 0—Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin
when the FRC and OCRB values match.
Bit 0
OLVLB Description
0
1
A “0” logic level (Low) is output for compare-match B.
A “1” logic level (High) is output for compare-match B.
(Initial value)
6.3 CPU Interface
The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture
registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When
the CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the
access is performed using an 8-bit temporary register (TEMP).
These registers are written and read as follows:
• Register Write
When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when
the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16
bits are written in the register simultaneously.
128
• Register Read
When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte
is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP.
(As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower bytes
directly, without using TEMP.)
Programs that access these registers should normally use word access. Equivalently, they may
access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not be
transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed.
Coding Examples
To write the contents of general register R0 to OCRA:
To transfer the contents of ICRA to general register R0:
MOV.W R0, @OCRA
MOV.W @ICRA, R0
Figure 6-4 shows the data flow when the FRC is accessed. The other registers are accessed in the
same way.
(1) Upper byte write
Module data bus
CPU writes
data H'AA
Bus interface
TEMP
[H'AA]
FRCL
FRCH
[
]
[
]
(2) Lower byte write
Module data bus
CPU writes
data H'55
Bus interface
TEMP
[H'AA]
FRCH
[H'AA]
FRCL
[H'55]
Figure 6-4 (a). Write Access to FRC (when CPU Writes H'AA55)
129
(1) Upper byte read
Module data bus
CPU reads
data H'AA
Bus interface
TEMP
[H'55]
FRCH
[H'AA]
FRCL
[H'55]
(2) Lower byte read
Module data bus
CPU reads
data H'55
Bus interface
TEMP
[H'55]
FRCH
FRCL
[
]
[
]
Figure 6-4 (b). Read Access to FRC (when FRC Contains H'AA55)
6.4 Operation
6.4.1 FRC Incrementation Timing
The FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source. The clock source is selected by bits CKS0 and CKS1 in the TCR.
Internal Clock: The internal clock sources (Ø/2, Ø/8, Ø/32) are created from the system clock (Ø)
by a prescaler. The FRC increments on a pulse generated from the falling edge of the prescaler
output. See figure 6-5.
130
Ø
Internal
clock
FRC clock
pulse
FRC
N – 1
N
N + 1
Figure 6-5. Increment Timing for Internal Clock Source
External Clock: If external clock input is selected, the FRC increments on the rising edge of the
FTCI clock signal. Figure 6-6 shows the increment timing.
The pulse width of the external clock signal must be at least 1.5 system clock (Ø) periods. The
counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods.
Ø
FTCI
FRC clock pulse
FRC
N
N + 1
Figure 6-6. Increment Timing for External Clock Source
Ø
FTCI
Figure 6-7. Minimum External Clock Pulse Width
131
6.4.2 Output Compare Timing
(1) Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags
are set to “1” by an internal compare-match signal generated when the FRC value matches the
OCRA or OCRB value. This compare-match signal is generated at the last state in which the two
values match, just before the FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 6-8 shows the timing of the setting of the output
compare flags.
Ø
N
N
N + 1
FRC
OCRA or OCRB
Internal compare-
match signal
OCFAorOCFB
Figure 6-8. Setting of Output Compare Flags
132
(2) Output Timing: When a compare-match occurs, the logic level selected by the output level
bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB).
Figure 6-9 shows the timing of this operation for compare-match A.
Ø
FRC
N
N
N + 1
N
N
N + 1
OCRA
Internal compare-
match A signal
Clear*
OLVLA
FTOA
Note: * Cleared by software
Figure 6-9. Timing of Output Compare A
(3) FRC Clear Timing: If the CCLRA bit in the TCSR is set to “1,” the FRC is cleared when
compare-match A occurs. Figure 6-10 shows the timing of this operation.
Ø
Internal compare-
match A signal
FRC
N
H'0000
Figure 6-10. Clearing of FRC by Compare-Match A
6.4.3 Input Capture Timing
(1) Input Capture Timing: An internal input capture signal is generated from the rising or falling
edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the corresponding
IEDGx bit in TCR. Figure 6-11 shows the usual input capture timing when the rising edge is
selected (IEDGx = “1”).
133
Ø
Input at FTI pin
Internal input
capture signal
Figure 6-11. Input Capture Timing (Usual Case)
If the upper byte of ICRx is being read when the input capture signal arrives, the internal input
capture signal is delayed by one state. Figure 6-12 shows the timing for this case.
Read cycle: CPU reads upper byte of ICR
T 1
T 2
T 3
Ø
Input at FTI pin
Internal input
capture signal
Figure 6-12. Input Capture Timing (1-State Delay)
In buffer mode, this delay occurs if the CPU is reading either of the two registers concerned. When
ICRA and ICRC are used in buffer mode, for example, if the upper byte of either ICRA or ICRC is
being read when the FTIA input arrives, the internal input capture signal is delayed by one state.
Figure 6-13 shows the timing for this case. The case of ICRB and ICRD is similar.
Read cycle: CPU reads upper byte of ICRA or ICRC
T 1
T 2
T 3
Ø
Input at
FTIA pin
Internal input
capture signal
Figure 6-13. Input Capture Timing (1-State Delay, Buffer Mode)
134
Figure 6-14 shows how input capture operates when ICRA and ICRC are used in buffer mode and
IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and
IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
Ø
FTIA
Internal input
capture signal
n
n + 1
N
N + 1
FRC
ICRA
M
n
n
N
n
M
ICRC
m
M
Figure 6-14. Buffered Input Capture with Both Edges Selected
In this mode, FTIC does not cause the FRC contents to be copied to ICRC. However, input capture
flag C still sets on the edge of FTIC selected by IEDGC, and if the interrupt enable bit (ICICE) is
set, a CPU interrupt is requested.
The situation when ICRB and ICRD are used in buffer mode is similar.
135
(2) Timing of Input Capture Flag (ICF) Setting: The input capture flag ICFx (x = A, B, C, D) is
set to “1” by the internal input capture signal. Figure 6-15 shows the timing of this operation.
Ø
Internal input
capture signal
ICFA/B/C/D
FRC
N
N
ICRA/B/C/D
Figure 6-15. Setting of Input Capture Flag
6.4.4 Setting of FRC Overflow Flag (OVF)
The FRC overflow flag (OVF) is set to “1” when the FRC overflows (changes from H'FFFF to
H'0000). Figure 6-16 shows the timing of this operation.
Ø
FRC
H'FFFF
H'0000
Internal overflow
signal
OVF
Figure 6-16. Setting of Overflow Flag (OVF)
136
6.5 Interrupts
The free-running timer can request seven types of interrupts: input capture A to D (ICIA, ICIB,
ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt is
requested when the corresponding enable and flag bits are set. Independent signals are sent to the
interrupt controller for each type of interrupt. Table 6-4 lists information about these interrupts.
Table 6-4. Free-Running Timer Interrupts
Interrupt
ICIA
Description
Priority
Requested when ICFA and ICIAE are set
Requested when ICFB and ICIBE are set
Requested when ICFC and ICICE are set
Requested when ICFD and ICIDE are set
Requested when OCFA and OCIAE are set
Requested when OCFB and OCIBE are set
Requested when OVF and OVIE are set
High
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
Low
6.6 Sample Application
In the example below, the free-running timer is used to generate two square-wave outputs with a
50% duty cycle and arbitrary phase relationship. The programming is as follows:
(1) The CCLRA bit in the TCSR is set to “1.”
(2) Each time a compare-match interrupt occurs, software inverts the corresponding output level
bit in TOCR (OLVLA or OLVLB).
FRC
H'FFFF
Clear counter
OCRA
OCRB
H'0000
FTOA
FTOB
Figure 6-17. Square-Wave Output (Example)
137
6.7 Application Notes
Application programmers should note that the following types of contention can occur in the free-
running timers.
(1) Contention between FRC Write and Clear: If an internal counter clear signal is generated
during the T3 state of a write cycle to the lower byte of the free-running counter, the clear signal
takes priority and the write is not performed.
Figure 6-18 shows this type of contention.
Write cycle: CPU write to lower byte of FRC
T1
T2
T3
Ø
Internal address bus
FRC address
Internal write signal
FRC clear signal
FRC
N
H'0000
Figure 6-18. FRC Write-Clear Contention
138
(2) Contention between FRC Write and Increment: If an FRC increment pulse is generated
during the T3 state of a write cycle to the lower byte of the free-running counter, the write takes
priority and the FRC is not incremented.
Figure 6-19 shows this type of contention.
Write cycle: CPU write to lower byte of FRC
T 1
T 2
T 3
Ø
Internal address bus
FRC address
Internal write signal
FRC clock pulse
FRC
N
M
Write data
Figure 6-19. FRC Write-Increment Contention
139
(3) Contention between OCR Write and Compare-Match: If a compare-match occurs during
the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the
compare-match signal is inhibited.
Figure 6-20 shows this type of contention.
Write cycle: CPU write to lower byte of OCRA or OCRB
T1
T2
T3
Ø
Internal address bus
OCR address
Internal write signal
FRC
N
N
N + 1
M
OCRAorOCRB
Write data
Compare-match
A or B signal
Inhibited
Figure 6-20. Contention between OCR Write and Compare-Match
140
(4) Incrementation Caused by Changing of Internal Clock Source: When an internal clock
source is changed, the changeover may cause the FRC to increment. This depends on the time at
which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 6-5.
The pulse that increments the FRC is generated at the falling edge of the internal clock source. If
clock sources are changed when the old source is High and the new source is Low, as in case No. 3
in table 6-5, the changeover generates a falling edge that triggers the FRC increment clock pulse.
Switching between an internal and external clock source can also cause the FRC to increment.
Table 6-5. Effect of Changing Internal Clock Sources
No.
Description
Timing chart
Low → Low:
Old clock
source
CKS1 and CKS0 are
rewritten while both
clock sources are Low.
1
New clock
source
FRC clock
pulse
N
N + 1
FRC
CKS rewrite
Low → High:
Old clock
source
CKS1 and CKS0 are
rewritten while old
clock source is Low and
new clock source is High.
2
New clock
source
FRC clock
pulse
N
N + 1
N + 2
FRC
CKS rewrite
141
Table 6-5. Effect of Changing Internal Clock Sources (cont.)
No.
Description
Timing chart
High → Low:
Old clock
source
CKS1 and CKS0 are
rewritten while old
clock source is High and
new clock source is Low.
3
New clock
source
*
FRC clock
pulse
FRC
N
N + 1
N + 2
CKS rewrite
High → High:
Old clock
source
CKS1 and CKS0 are
rewritten while both
clock sources are High.
4
New clock
source
FRC clock
pulse
N
N + 1
N + 2
FRC
CKS rewrite
Note: * The switching of clock sources is regarded as a falling edge that increments the FRC.
142
Section 7. 8-Bit Timers
7.1 Overview
The H8/329 Series includes an 8-bit timer module with two channels (TMR0 and TMR1). Each
channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that
are constantly compared with the TCNT value to detect compare-match events. One application of
the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty cycle.
7.1.1 Features
The features of the 8-bit timer module are listed below.
• Selection of seven clock sources
The counters can be driven by one of six internal clock signals or an external clock input
(enabling use as an external event counter).
• Selection of three ways to clear the counters
The counters can be cleared on compare-match A or B, or by an external reset signal.
• Timer output controlled by two time constants
The timer output signal in each channel is controlled by two independent time constants,
enabling the timer to generate output waveforms with an arbitrary duty factor.
• Three independent interrupts
Compare-match A and B and overflow interrupts can be requested independently.
7.1.2 Block Diagram
Figure 7-1 shows a block diagram of one channel in the 8-bit timer module. The other channel is
identical.
143
Internal
clock sources
External
clock source
Channel 0
Ø/2
Ø/8
Ø/32
Ø/64
Ø/256
Ø/1024
Channel 1
Ø/2
Ø/8
TMCI
Ø/64
Ø/128
Ø/1024
Ø/2048
Clock
Clock select
TCORA
Compare-match A
Comparator A
TCNT
TMO
TMRI
Internal
data bus
Overflow
Clear
Comparator B
TCORB
Control
logic
Compare-match B
TCSR
TCR
CMIA
CMIB
OVI
Interrupt signals
TCR:
Timer Control Register (8 bits)
TCSR: Timer Control Status Register (8 bits)
TCORA: Time Constant Register A (8 bits)
TCORB: Time Constant Register B (8 bits)
TCNT: Timer Counter
Figure 7-1. Block Diagram of 8-Bit Timer
7.1.3 Input and Output Pins
Table 7-1 lists the input and output pins of the 8-bit timer.
Table 7-1. Input and Output Pins of 8-Bit Timer
Abbreviation
Name
TMR0
TMR1
TMO1
TMCI1
TMRI1
I/O
Function
Timer output
TMO0
Output
Input
Input
Output controlled by compare-match
External clock source for the counter
External reset signal for the counter
Timer clock input TMCI0
Timer reset input TMRI0
144
7.1.4 Register Configuration
Table 7-2 lists the registers of the 8-bit timer module. Each channel has an independent set of
registers.
Table 7-2. 8-Bit Timer Registers
Address
Name
Abbreviation R/W
Initial value TMR0
TMR1
Timer control register
Timer control/status register
Timer constant register A
Timer constant register B
Timer counter
TCR
R/W
H'00
H'10
H'FF
H'FF
H'00
H'F8
H'FFC8 H'FFD0
H'FFC9 H'FFD1
H'FFCA H'FFD2
H'FFCB H'FFD3
H'FFCC H'FFD4
H'FFC3 H'FFC3
TCSR
TCORA
TCORB
TCNT
STCR
R/(W)*
R/W
R/W
R/W
Serial/timer control register
R/W
Note: * Software can write a “0” to clear bits 7 to 5, but cannot write a “1” in these bits.
7.2 Register Descriptions
7.2.1 Timer Counter (TCNT)—H'FFCC (TMR0), H'FFD4 (TMR1)
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from an
internal or external clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer
control register (TCR). The CPU can always read or write the timer counter.
The timer counter can be cleared by an external reset input or by an internal compare-match signal
generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer
control register select the method of clearing.
When a timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to “1.”
145
The timer counters are initialized to H'00 at a reset and in the standby modes.
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
CKS1
0
0
CKS0
0
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
146
Bit 7
CMIEB Description
0
1
Compare-match interrupt request B (CMIB) is disabled.
Compare-match interrupt request B (CMIB) is enabled.
(Initial value)
7.2.2 Time Constant Registers A and B (TCORA and TCORB)—H'FFCA and H'FFCB
(TMR0), H'FFD2 and H'FFD3 (TMR1)
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually
Bit 6
CMIEA Description
0
1
Compare-match interrupt request A (CMIA) is disabled.
Compare-match interrupt request A (CMIA) is enabled.
(Initial value)
compared with the constants written in these registers. When a match is detected, the
corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register
(TCSR).
The timer output signal (TMO0 or TMO1) is controlled by these compare-match signals as
Bit 5
OVIE
Description
0
1
The timer overflow interrupt request (OVI) is disabled.
The timer overflow interrupt request (OVI) is enabled.
(Initial value)
specified by output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR).
TCORA and TCORB are initialized to H'FF at a reset and in the standby modes.
Bit 4
Bit 3
CCLR1 CCLR0 Description
0
0
1
1
0
1
0
1
Not cleared.
(Initial value)
Cleared on compare-match A.
Cleared on compare-match B.
Cleared on rising edge of external reset input signal.
Compare-match is not detected during the T3 state of a write cycle to TCORA or TCORB. See
item (3) in section 7.6, “Application Notes.”
7.2.3 Timer Control Register (TCR)—H'FFC8 (TMR0), H'FFD0 (TMR1)
Each TCR is an 8-bit readable/writable register that selects the clock source and the time at which
147
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and
ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for the
timer counter. Six internal clock sources, derived by prescaling the system clock, are available for
each timer channel. For internal clock sources the counter is incremented on the falling edge of the
internal clock. For an external clock source, these bits can select whether to increment the counter
on the rising or falling edge of the clock input, or on both edges.
TCR
STCR
Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
0
No clock source (timer stopped) (Initial value)
Ø/8 internal clock, counted on falling edge
Ø/2 internal clock, counted on falling edge
Ø/64 internal clock, counted on falling edge
Ø/32 internal clock, counted on falling edge
Ø/1024 internal clock, counted on falling edge
Ø/256 internal clock, counted on falling edge
No clock source (timer stopped)
1
0
1
0
1
—
—
—
—
External clock source, counted on rising edge
External clock source, counted on falling edge
External clock source, counted on both rising
and falling edges
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
—
0
—
—
—
—
—
—
—
—
—
—
—
No clock source (timer stopped) (Initial value)
Ø/8 internal clock, counted on falling edge
Ø/2 internal clock, counted on falling edge
Ø/64 internal clock, counted on falling edge
Ø/128 internal clock, counted on falling edge
Ø/1024 internal clock, counted on falling edge
Ø/2048 internal clock, counted on falling edge
No clock source (timer stopped)
1
0
1
0
1
—
—
—
—
External clock source, counted on rising edge
External clock source, counted on falling edge
External clock source, counted on both rising
and falling edges
148
the timer counter is cleared, and enables interrupts.
Bit
7
6
5
OVF
0
4
—
1
3
2
1
0
CMFB CMFA
OS3
0
OS2
0
OS1
0
OS0
0
Initial value
Read/Write
0
0
R/(W)* R/(W)* R/(W)*
—
R/W
R/W
R/W
R/W
The TCRs are initialized to H'00 at a reset and in the standby modes.
For timing diagrams, see section 7.3, “Operation.”
Bit 7—Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request
compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer
control/status register (TCSR) is set to “1.”
Bit 7
CMFB
Description
0
To clear CMFB, the CPU must read CMFB after
it has been set to “1,” then write a “0” in this bit.
This bit is set to 1 when TCNT = TCORB.
(Initial value)
1
Bit 6
CMFA
0
Description
To clear CMFA, the CPU must read CMFA after
it has been set to “1,” then write a “0” in this bit.
This bit is set to 1 when TCNT = TCORA.
(Initial value)
1
149
Bit 6—Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request
compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer
control/status register (TCSR) is set to “1.”
Bit 5
OVF
Description
0
To clear OVF, the CPU must read OVF after
it has been set to “1,” then write a “0” in this bit.
This bit is set to 1 when TCNT changes from H'FF to H'00.
(Initial value)
1
Bit 5—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer
overflow interrupt (OVI) when the overflow flag (OVF) in the timer control/status register (TCSR)
is set to “1.”
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer
counter is cleared: by compare-match A or B or by an external reset input.
Bit 3
Bit 2
OS3
OS2
Description
0
0
1
1
0
1
0
1
No change when compare-match B occurs.
Output changes to “0” when compare-match B occurs.
Output changes to “1” when compare-match B occurs.
Output inverts (toggles) when compare-match B occurs.
(Initial value)
Bit 1
Bit 0
OS1
OS0
Description
0
0
1
1
0
1
0
1
No change when compare-match A occurs.
Output changes to “0” when compare-match A occurs.
Output changes to “1” when compare-match A occurs.
Output inverts (toggles) when compare-match A occurs.
(Initial value)
150
7.2.5 Serial/Timer Control Register (STCR)—H'FFC3
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
MPE
0
ICKS1 ICKS0
Initial value
Read/Write
0
0
—
—
—
—
—
R/W
R/W
R/W
The STCR is an 8-bit readable/writable register that controls the serial communication interface
and selects internal clock sources for the timer counters.
The STCR is initialized to H'F8 at a reset.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as “1.”
Bit 2—Multiprocessor Enable (MPE): Controls the operating mode of the serial communication
interface. For details, see section 8, “Serial Communication Interface.”
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1 and ICKS0): These bits and bits
CKS2 to CKS0 in the TCR select clock sources for the timer counters. For details, see
section 7.2.3, “Timer Control Register.”
151
7.2.4 Timer Control/Status Register (TCSR)—H'FFC9 (TMR0), H'FFD1 (TMR1)
Note: * Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these
bits.
The TCSR is an 8-bit readable and partially writable register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal.
The TCSR is initialized to H'10 at a reset and in the standby modes.
Bit 7—Compare-Match Flag B (CMFB): This status flag is set to “1” when the timer count
Ø
Internal
clock
TCNT clock
pulse
TCNT
N–1
N
N+1
matches the time constant set in TCORB. CMFB must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 6—Compare-Match Flag A (CMFA): This status flag is set to “1” when the timer count
matches the time constant set in TCORA. CMFA must be cleared by software. It is set by
hardware, however, and cannot be set by software.
152
Ø
External clock
source
TCNT clock
pulse
TCNT
N – 1
N
N + 1
Bit 5—Timer Overflow Flag (OVF): This status flag is set to “1” when the timer count overflows
(changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however,
Ø
TMCI
Minimum TMCI Pulse Width
(Single-Edge Incrementation)
Ø
TMCI
Minimum TMCI Pulse Width
(Double-Edge Incrementation)
and cannot be set by software.
Bit 4—Reserved: This bit cannot be modified and is always read as “1.”
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of compare-match
events on the timer output signal (TCOR or TCNT). Bits OS3 and OS2 control the effect of
compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on
the output level.
153
If compare-match A and B occur simultaneously, any conflict is resolved as explained in item (4) in
section 7.6, “Application Notes.”
Ø
N
N
N + 1
TCNT
TCOR
Internal
compare-match
signal
CMF
After a reset, the timer output is “0” until the first compare-match event.
When all four output select bits are cleared to “0” the timer output signal is disabled.
Ø
Internal
compare-match
A signal
Timer output
(TMO)
154
7.3 Operation
7.3.1 TCNT Incrementation Timing
Ø
Internal
compare-match
signal
TCNT
N
H'00
The timer counter increments on a pulse generated once for each period of the selected (internal or
external) clock source.
Internal Clock: Internal clock sources are created from the system clock by a prescaler. The
counter increments on an internal TCNT clock pulse generated from the falling edge of the
prescaler output, as shown in figure 7-2. Bits CKS2 to CKS0 of the TCR and bits ICKS1 and
ICKS0 of the STCR can select one of the six internal clocks.
Ø
External reset
input (TMRI)
Internal clear
pulse
N – 1
N
H'00
TCNT
Figure 7-2. Count Timing for Internal Clock Input
External Clock: If external clock input (TMCI) is selected, the timer counter can increment on the
rising edge, the falling edge, or both edges of the external clock signal. Figure 7-3 shows
incrementation on both edges of the external clock signal.
The external clock pulse width must be at least 1.5 system clock periods for incrementation on a
155
single edge, and at least 2.5 system clock periods for incrementation on both edges. See
figure 7-4. The counter will not increment correctly if the pulse width is shorter than these values.
Ø
TCNT
H'FF
H'00
Internal overflow
signal
OVF
156
Figure 7-3. Count Timing for External Clock Input
Figure 7-4. Minimum External Clock Pulse Widths (Example)
7.3.2 Compare Match Timing
(1) Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags
are set to “1” by an internal compare-match signal generated when the timer count matches the time
Interrupt
CMIA
CMIB
OVI
Description
Priority
Requested when CMFA and CMIEA are set
Requested when CMFB and CMIEB are set
Requested when OVF and OVIE are set
High
Low
constant in TCNT or TCOR. The compare-match signal is generated at the last state in which the
match is true, just before the timer counter increments to a new value.
TCNT
H'FF
Clear counter
TCORA
TCORB
H'00
TMO pin
157
Accordingly, when the timer count matches one of the time constants, the compare-match signal is
not generated until the next period of the clock source. Figure 7-5 shows the timing of the setting
of the compare-match flags.
Figure 7-5. Setting of Compare-Match Flags
(2) Output Timing: When a compare-match event occurs, the timer output (TMO0 or TMO1)
changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits,
the output can remain the same, change to “0,” change to “1,” or toggle.
Figure 7-6 shows the timing when the output is set to toggle on compare-match A.
Write cycle: CPU writes to TCNT
T1
T2
T3
Ø
Internal Address
bus
TCNT address
Internal write
signal
Counter clear
signal
TCNT
N
H'00
Figure 7-6. Timing of Timer Output
158
(3) Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR,
the timer counter can be cleared when compare-match A or B occurs. Figure 7-7 shows the timing
of this operation.
Figure 7-7. Timing of Compare-Match Clear
Write cycle: CPU writes to TCNT
T1
T2
T3
Ø
Internal Address
bus
TCNT address
Internal write
signal
TCNT clock
pulse
TCNT
N
M
Write data
7.3.3 External Reset of TCNT
When the CCLR1 and CCLR0 bits in the TCR are both set to “1,” the timer counter is cleared on
the rising edge of an external reset input. Figure 7-8 shows the timing of this operation. The timer
reset pulse width must be at least 1.5 system clock periods.
Figure 7-8. Timing of External Reset
159
7.3.4 Setting of TCSR Overflow Flag (OVF)
The overflow flag (OVF) is set to “1” when the timer count overflows (changes from H'FF to
H'00). Figure 7-9 shows the timing of this operation.
Write cycle: CPU writes to TCORA or TCORB
T1
T2
T3
Ø
Internal address
bus
TCOR address
Internal write
signal
N + 1
TCNT
N
TCORAor
TCORB
N
M
TCOR write data
Compare-match
A or B signal
Inhibited
Figure 7-9. Setting of Overflow Flag (OVF)
Output selection
Toggle
Priority
High
“1” Output
“0” Output
No change
Low
160
7.4 Interrupts
Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B
(CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding
enable bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller
for each interrupt. Table 7-3 lists information about these interrupts.
Table 7-3. 8-Bit Timer Interrupts
7.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle.
No.
Description
Timing chart
Low → Low*1:
Old clock
source
Clock select bits are
rewritten while both
clock sources are Low.
1
New clock
source
TCNT clock
pulse
N + 1
TCNT
N
CKS rewrite
Low → High*2:
Old clock
source
Clock select bits are
rewritten while old
2
New clock
source
clock source is Low and
new clock source is High.
TCNT clock
pulse
TCNT
N
N + 1
N + 2
CKS rewrite
The control bits are set as follows:
(1) In the TCR, CCLR1 is cleared to “0” and CCLR0 is set to “1” so that the timer counter is
cleared when its value matches the constant in TCORA.
161
(2) In the TCSR, bits OS3 to OS0 are set to “0110,” causing the output to change to “1” on
No.
Description
Timing chart
High → Low*1:
Old clock
source
Clock select bits are
rewritten while old
clock source is High and
new clock source is Low.
3
New clock
source
*32
*
TCNT clock
pulse
TCNT
N
N + 1
N + 2
CKS rewrite
High → High:
Old clock
source
Clock select bits are
rewritten while both
clock sources are High.
4
New clock
source
TCNT clock
pulse
TCNT
N
N + 1
N + 2
CKS rewrite
compare-match A and to “0” on compare-match B.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a
pulse width determined by TCORB. No software intervention is required.
Figure 7-10. Example of Pulse Output
7.6 Application Notes
Application programmers should note that the following types of contention can occur in the 8-bit
timer.
(1) Contention between TCNT Write and Clear: If an internal counter clear signal is generated
during the T3 state of a write cycle to the timer counter, the clear signal takes priority and the write
is not performed.
Figure 7-11 shows this type of contention.
162
Section 8. Serial Communication Interface
8.1 Overview
The H8/329 Series includes a serial communication interface (SCI) for transferring serial data to
and from other chips. Either synchronous or asynchronous communication can be selected.
8.1.1 Features
The features of the on-chip serial communication interface are:
• Asynchronous mode
The H8/329 Series can communicate with a UART (Universal Asynchronous
Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other chip
that employs standard asynchronous serial communication. It also has a multiprocessor
communication function for communication with other processors. Twelve data formats are
available.
— Data length: 7 or 8 bits
— Stop bit length: 1 or 2 bits
— Parity: Even, odd, or none
— Multiprocessor bit: “1” or “0”
— Error detection: Parity, overrun, and framing errors
— Break detection: When a framing error occurs, the break condition can be detected by
reading the level of the RxD line directly.
• Synchronous mode
The SCI can communicate with chips able to perform clocked synchronous data transfer.
— Data length: 8 bits
— Error detection: Overrun errors
• Full duplex communication
The transmitting and receiving sections are independent, so each channel can transmit and
receive simultaneously. Both the transmit and receive sections use double buffering, so
continuous data transfer is possible in either direction.
• Built-in baud rate generator
Any specified baud rate can be generated.
• Internal or external clock source
The SCI can operate on an internal clock signal from baud rate generator, or an external clock
signal input at the SCK pin.
• Four interrupts
TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested independently.
163
8.1.2 Block Diagram
Figure 8-1 shows a block diagram of the serial communication interface.
Internal
data bus
Module data bus
RDR
RSR
TDR
TSR
SSR
SCR
SMR
BRR
Internal
clock
RxD
TxD
Ø
Communi-
cation
control
Ø/4
Ø/16
Ø/64
Baud rate
generator
Parity
generate
Clock
Parity check
External clock source
SCK
TEI
TXI
RXI
ERI
RSR: Receive Shift Register (8 bits)
RDR: Receive Data Register (8 bits)
TSR:
TDR:
Transmit Shift Register (8 bits)
Transmit Data Register (8 bits)
Interrupt signals
SMR: Serial Mode Register (8 bits)
SCR: Serial Control Register (8 bits)
SSR: Serial Status Register (8 bits)
BRR: Bit Rate Register (8 bits)
Figure 8-1. Block Diagram of Serial Communication Interface
164
8.1.3 Input and Output Pins
Table 8-1 lists the input and output pins used by the SCI module.
Table 8-1. SCI Input/Output Pins
Name
Abbr.
SCK
RxD
TxD
I/O
Function
Serial clock
Receive data
Transmit data
Input/output
Input
Serial clock input and output.
Receive data input.
Transmit data output.
Output
8.1.4 Register Configuration
Table 8-2 lists the SCI registers. These registers specify the operating mode (synchronous or
asynchronous), data format and bit rate, and control the transmit and receive sections.
Table 8-2. SCI Registers
Name
Abbr.
RSR
RDR
TSR
R/W
—
Value
—
Address
—
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
R
H'00
—
H'FFDD
—
—
TDR
SMR
SCR
SSR
R/W
R/W
R/W
R/(W)*
R/W
R/W
H'FF
H'00
H'00
H'84
H'FF
H'F8
H'FFDB
H'FFD8
H'FFDA
H'FFDC
H'FFD9
H'FFC3
BRR
STCR
Serial/timer control register
Note: * Software can write a “0” to clear the flags in bits 7 to 3, but cannot write “1” in these bits.
165
8.2 Register Descriptions
8.2.1 Receive Shift Register (RSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
The RSR receives incoming data bits. When one data character has been received, it is transferred
to the receive data register (RDR).
The CPU cannot read or write the RSR directly.
8.2.2 Receive Data Register (RDR)—H'FFDD
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
The RDR stores received data. As each character is received, it is transferred from the RSR to the
RDR, enabling the RSR to receive the next character. This double-buffering allows the SCI to
receive data continuously.
The CPU can read but not write the RDR. The RDR is initialized to H'00 at a reset and in the
standby modes.
8.2.3 Transmit Shift Register (TSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
The TSR holds the character currently being transmitted. When transmission of this character is
completed, the next character is moved from the transmit data register (TDR) to the TSR and
transmission of that character begins. If the TDRE bit is still set to “1,” however, nothing is
transferred to the TSR.
The CPU cannot read or write the TSR directly.
166
8.2.4 Transmit Data Register (TDR)—H'FFDB
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The TDR is an 8-bit readable/writable register that holds the next character to be transmitted.
When the TSR becomes empty, the character written in the TDR is transferred to the TSR.
Continuous data transmission is possible by writing the next byte in the TDR while the current byte
is being transmitted from the TSR.
The TDR is initialized to H'FF at a reset and in the standby modes.
8.2.5 Serial Mode Register (SMR)—H'FFD8
Bit
7
C/A
0
6
5
PE
0
4
O/E
0
3
STOP
0
2
MP
0
1
CKS1
0
0
CKS0
0
CHR
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The SMR is an 8-bit readable/writable register that controls the communication format and selects
the clock rate for the internal clock source. It is initialized to H'00 at a reset and in the standby
modes. For further information on the SMR settings and communication formats, see tables 8-5
and 8-7 in section 8.3, “Operation.”
Bit 7—Communication Mode (C/A): This bit selects the asynchronous or clocked synchronous
communication mode.
Bit 7
C/A Description
0
1
Asynchronous communication.
(Initial value)
Clocked synchronous communication.
167
Bit 6—Character Length (CHR): This bit selects the character length in asynchronous mode.
It is ignored in synchronous mode. The character length is always eight bits in synchronous mode.
Bit 6
CHR
Description
0
1
8 bits per character.
(Initial value)
7 bits per character. (Bits 0 to 6 in TDR and RDR are sent and received.)
Bit 5—Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode.
It is ignored in synchronous mode, and when a multiprocessor format is used.
Bit 5
PE
Description
0
Transmit: No parity bit is added.
Receive: Parity is not checked.
Transmit: A parity bit is added.
Receive: Parity is checked.
(Initial value)
1
Bit 4—Parity Mode (O/E ): In asynchronous mode, when parity is enabled (PE = “1”), this bit
selects even or odd parity.
Even parity means that a parity bit is added to the data bits for each character to make the total
number of 1’s even. Odd parity means that the total number of 1’s is made odd.
This bit is ignored when PE = “0,” or when a multiprocessor format is used. It is also ignored in
the synchronous mode.
Bit 4
O/E
0
Description
Even parity.
Odd parity.
(Initial value)
1
168
Bit 3—Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in the
synchronous mode.
Bit 3
STOP
Description
0
One stop bit
(Initial value)
Transmit: one stop bit is added.
Receive: one stop bit is checked to detect framing errors.
Two stop bits
1
Transmit: two stop bits are added.
Receive: the first stop bit is checked to detect framing errors; if the second bit is a space
(0), it is regarded as the next start bit.
Bit 2—Multiprocessor Mode (MP): This bit selects the multiprocessor format in asynchronous
communication. When multiprocessor format is selected, the parity settings of the parity enable bit
(PE) and parity mode bit (O/E) are ignored. The MP bit is ignored in synchronous communication.
The MP bit is valid only when the MPE bit in the serial/timer control register (STCR) is set to “1.”
When the MPE bit is cleared to “0,” the multiprocessor communication function is disabled
regardless of the setting of the MP bit.
Bit 2
MP
0
Description
Multiprocessor communication function is disabled.
Multiprocessor communication function is enabled.
(Initial value)
1
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source when the baud rate generator is clocked from within the chip.
Bit 1
Bit 0
CKS1
CKS0
Description
Ø clock
0
0
1
1
0
1
0
1
(Initial value)
Ø/4 clock
Ø/16 clock
Ø/64 clock
169
8.2.6 Serial Control Register (SCR)—H'FFDA
Bit
7
TIE
0
6
RIE
0
5
TE
0
4
RE
0
3
MPIE
0
2
1
CKE1
0
0
CKE0
0
TEIE
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The SCR is an 8-bit readable/writable register that enables or disables various SCI functions.
It is initialized to H'00 at a reset and in the standby modes.
Bit 7—Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty interrupt
(TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR)
is set to “1.”
Bit 7
TIE
0
Description
The TDR-empty interrupt request (TXI) is disabled.
The TDR-empty interrupt request (TXI) is enabled.
(Initial value)
1
Bit 6—Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt
(RxI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is
set to “1.” It also enables or disables the receive-error interrupt (ERI) requested when the overrun
error (ORER), framing error (FER), or parity error (PER) bit is set to “1.”
Bit 6
RIE
Description
0
The receive-end interrupt (RxI) and receive-error interrupt (ERI)
requests are disabled.
(Initial value)
1
The receive-end interrupt (RxI) and receive-error interrupt (ERI)
requests are enabled.
170
Bit 5—Transmit Enable (TE): This bit enables or disables the transmit function. When the
transmit function is enabled, the TxD pin is automatically used for output. When the transmit
function is disabled, the TxD pin can be used as a general-purpose I/O port.
Bit 5
TE
Description
0
The transmit function is disabled.
(Initial value)
The TxD pin can be used for general-purpose I/O.
The transmit function is enabled. The TxD pin is used for output.
1
Bit 4—Receive Enable (RE): This bit enables or disables the receive function. When the receive
function is enabled, the RxD pin is automatically used for input. When the receive function is
disabled, the RxD pin is available as a general-purpose I/O port.
Bit 4
RE
Description
0
The receive function is disabled. The RxD pin can be
used for general-purpose I/O.
(Initial value)
1
The receive function is enabled. The RxD pin is used for input.
171
Bit 3—Multiprocessor Interrupt Enable (MPIE): When serial data are received in a
multiprocessor format, this bit enables or disables the receive-end interrupt (RxI) and receive-error
interrupt (ERI) until data with the multiprocessor bit set to “1” are received. It also enables or
disables the transfer of received data from the RSR to the RDR, and enables or disables setting of
the RDRF, FER, PER, and ORER bits in the serial status register (SSR).
The MPIE bit is ignored when a multiprocessor format is not used, and in synchronous mode.
Clearing the MPIE bit to “0” disables the multiprocessor receive interrupt function. In this
condition data are received regardless of the value of the multiprocessor bit in the receive data.
Setting the MPIE bit to “1” enables the multiprocessor receive interrupt function. In this condition,
if the multiprocessor bit in the receive data is “0,” the receive-end interrupt (RxI) and receive-error
interrupt (ERI) are disabled, the receive data are not transferred from the RSR to the RDR, and the
RDRF, FER, PER, and ORER bits in the serial status register (SSR) are not set. If the
multiprocessor bit is “1,” however, the MPB bit in the SSR is set to “1,” the MPIE bit is cleared to
“0,” the FER, PER, and ORER bits can be set, and the receive-end and receive-error interrupts are
enabled.
Bit 3
MPIE
Description
0
The multiprocessor receive interrupt function is disabled.
(Normal receive operation)
(Initial value)
1
The multiprocessor receive interrupt function is enabled. During the
interval before data with the multiprocessor bit set to “1” are received,
the receive interrupt request (RxI) and receive-error interrupt request
(ERI) are disabled, the RDRF, FER, PER, and ORER bits are not set in
the serial status register (SSR), and no data are transferred from the RSR
to the RDR. The MPIE bit is cleared at the following times:
(1) When “0” is written in MPIE.
(2) When data with the multiprocessor bit set to “1” are received.
172
Bit 2—Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty
interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is set
to “1.”
Bit 2
TEIE
Description
0
1
The TSR-empty interrupt request (TEI) is disabled.
The TSR-empty interrupt request (TEI) is enabled.
(Initial value)
Bit 1—Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud
rate generator. When the external clock source is selected, the SCK pin is automatically used for
input of the external clock signal.
Bit 1
CKE1
Description
0
Internal clock source.
(Initial value)
When C/A = “1,” the serial clock signal is output at the SCK pin.
When C/A = “0,” output depends on the CKE0 bit.
External clock source. The SCK pin is used for input.
1
Bit 0—Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode,
this bit enables or disables serial clock output at the SCK pin.
This bit is ignored when the external clock is selected, or when synchronous mode is selected.
For further information on the communication format and clock source selection, see table 8-7 in
section 8.3, “Operation.”
Bit 0
CKE0
Description
0
The SCK pin is not used by the SCI (and is available as
a general-purpose I/O port).
(Initial value)
1
The SCK pin is used for serial clock output.
173
8.2.7 Serial Status Register (SSR)—H'FFDC
Bit
7
6
5
4
FER
0
3
PER
0
2
TEND
1
1
MPB
0
0
MPBT
0
TDRE RDRF ORER
Initial value
Read/Write
1
0
0
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
R
R
R/W
Note: * Software can write a “0” to clear the flags, but cannot write a “1” in these bits.
The SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 at a
reset and in the standby modes.
Bit 7—Transmit Data Register Empty (TDRE): This bit indicates when the TDR contents have
been transferred to the TSR and the next character can safely be written in the TDR.
Bit 7
TDRE
Description
0
To clear TDRE, the CPU must read TDRE after it has been set to “1,”
then write a “0” in this bit.
1
This bit is set to 1 at the following times:
(1) When TDR contents are transferred to the TSR.
(2) When the TE bit in the SCR is cleared to “0.”
(Initial value)
Bit 6—Receive Data Register Full (RDRF): This bit indicates when one character has been
received and transferred to the RDR.
Bit 6
RDRF
Description
0
To clear RDRF, the CPU must read RDRF after
it has been set to “1,” then write a “0” in this bit.
This bit is set to 1 when one character is received without error and
transferred from the RSR to the RDR.
(Initial value)
1
174
Bit 5—Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5
ORER
Description
0
To clear ORER, the CPU must read ORER after
it has been set to “1,” then write a “0” in this bit.
This bit is set to 1 if reception of the next character ends while
the receive data register is still full (RDRF = “1”).
(Initial value)
1
Bit 4—Framing Error (FER): This bit indicates a framing error during data reception in
asynchronous mode. It has no meaning in synchronous mode.
Bit 4
FER
Description
0
To clear FER, the CPU must read FER after
it has been set to “1,” then write a “0” in this bit.
This bit is set to 1 if a framing error occurs (stop bit = “0”).
(Initial value)
1
Bit 3—Parity Error (PER): This bit indicates a parity error during data reception in the
asynchronous mode, when a communication format with parity bits is used.
This bit has no meaning in the synchronous mode, or when a communication format without parity
bits is used.
Bit 3
PER
Description
0
To clear PER, the CPU must read PER after
(Initial value)
it has been set to “1,” then write a “0” in this bit.
This bit is set to “1” when a parity error occurs (the parity of the received
data does not match the parity selected by the O/E bit in SMR).
1
175
Bit 2—Transmit End (TEND): This bit indicates that transmission of a character has ended and
the serial communication interface has stopped transmitting because there is no valid data in the
TDR. The TEND bit is also set to “1” when the TE bit in the serial control register (SCR) is
cleared to “0.”
The TEND bit can be read but not written. To use the TEI interrupt, after TEND is cleared to “0”
at the start of data transmission, set TEIE to “1” to enable the interrupt.
Bit 2
TEND
Description
0
To clear TEND, the CPU must read TDRE after
it has been set to “1,” then write a “0” in TDRE.
This bit is set to “1” when:
(Initial value)
1
(1) TE = “0”
(2) TDRE = “1” at the end of transmission of a character
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received in a
multiprocessor format in asynchronous communication mode. In synchronous mode, when a
multiprocessor format is not used, or if the RE bit is cleared to “0” when a multiprocessor format is
used, the MPB bit retains its previous value.
MPB can be read but not written.
Bit 1
MPB
Description
0
1
Multiprocessor bit = “0” in receive data.
Multiprocessor bit = “1” in receive data.
(Initial value)
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit inserted
in transmit data when a multiprocessor format is used in asynchronous communication mode. The
MPBT bit is double-buffered, in the same way that TSR and TDR are double-buffered. The MPBT
bit has no effect in synchronous mode, or when a multiprocessor format is not used.
Bit 0
MPBT
Description
0
1
Multiprocessor bit = “0” in transmit data.
Multiprocessor bit = “1” in transmit data.
(Initial value)
176
8.2.8 Bit Rate Register (BRR)—H'FFD9
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines
the baud rate output by the baud rate generator.
The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes.
Tables 8-3 and 8-4 show examples of BRR (N) and CKS (n) settings for commonly used bit rates.
Table 8-3. Examples of BRR Settings in Asynchronous Mode (1)
XTAL frequency (MHz)
2
2.4576
4
4.194304
Error
(%)
Bit
Error
(%)
Error
(%)
Error
(%)
rate
110
n
N
n
1
0
0
0
0
0
0
0
0
—
0
N
n
N
n
N
1
70 +0.03
207 +0.16
103 +0.16
51 +0.16
25 +0.16
12 +0.16
86 +0.31
255 0
1
141
103
207
103
51
+0.03
+0.16
+0.16
+0.16
+0.16
+0.16
+0.16
—
1
148 –0.04
108 +0.21
217 +0.21
108 +0.21
150
0
1
1
300
0
127 0
0
0
600
0
63
31
15
7
0
0
0
1200
2400
4800
9600
0
0
0
0
54
26
13
6
–0.70
+1.14
–2.48
–2.48
—
0
0
0
25
0
—
—
—
—
—
0
—
—
—
0
0
0
12
0
3
0
—
—
0
—
0
19200 —
31250 0
38400 —
1
0
—
—
—
—
—
—
—
—
—
0
—
0
1
0
—
—
—
—
—
—
—
177
Table 8-3. Examples of BRR Settings in Asynchronous Mode (2)
XTAL frequency (MHz)
4.9152
Error
(%)
6
7.3728
8
Bit
Error
(%)
Error
Error
(%)
rate
110
n
1
1
0
0
0
0
0
0
N
n
2
1
1
0
0
0
0
0
0
0
—
N
n
2
1
1
0
0
0
0
0
0
—
0
N
(%)
n
2
N
174 –0.26
127 0
52 +0.50
155 +0.16
77 +0.16
155 +0.16
77 +0.16
38 +0.16
19 –2.34
64
191
95
191
95
47
23
11
5
+0.70
70
+0.03
150
0
0
0
0
0
0
0
0
—
0
1
207 +0.16
103 +0.16
207 +0.16
103 +0.16
300
255 0
1
600
127 0
0
1200
2400
4800
9600
63
31
15
7
0
0
0
0
51
25
12
—
3
+0.16
+0.16
+0.16
—
0
0
0
9
–2.34
–2.34
0
0
19200 0
31250 —
38400 0
3
0
4
—
0
—
1
—
0
2
—
2
0
—
—
—
—
—
Table 8-3. Examples of BRR Settings in Asynchronous Mode (3)
XTAL frequency (MHz)
9.8304
10
12
12.288
N
Bit
Error
(%)
Error
(%)
Error
(%)
–0.44
0
Error
(%)
rate
110
n
2
1
1
0
0
0
0
0
N
n
2
2
1
1
0
0
0
0
0
0
0
N
n
2
N
n
2
2
1
1
0
0
0
0
0
0
—
86 +0.31
255 0
88 –0.25
64 +0.16
129 +0.16
64 +0.16
129 +0.16
64 +0.16
32 –1.36
15 +1.73
106
77
155
77
155
77
38
19
—
5
108 +0.08
150
2
79
159
79
159
79
39
19
4
0
300
127 0
1
0
0
600
255 0
1
0
0
1200
2400
4800
9600
127 0
0
+0.16
+0.16
+0.16
–2.34
—
0
63
31
15
7
0
0
0
0
0
0
0
0
0
19200 0
31250 0
38400 0
0
7
4
3
+1.73
0
—
0
0
4
–1.70
0
0
5
+2.40
—
3
+1.73
—
—
—
—
178
Table 8-3. Examples of BRR Settings in Asynchronous Mode (4)
XTAL frequency (MHz)
14.7456
Error
(%)
130 –0.07
95
191 0
95
191 0
16
19.6608
20
Bit
Error
(%)
Error
Error
(%)
rate
110
n
2
2
1
1
0
0
0
0
N
n
2
2
1
1
0
0
0
0
0
0
—
N
n
2
2
1
1
0
0
0
0
0
0
0
N
(%)
n
3
2
2
1
1
0
0
0
0
0
0
N
141 +0.03
103 +0.16
207 +0.16
103 +0.16
207 +0.16
103 +0.16
51 +0.16
25 +0.16
12 +0.16
174
127
255
127
255
127
63
–0.26
43
+0.88
150
0
0
129 +0.16
64 +0.16
129 +0.16
64 +0.16
129 +0.16
300
0
600
0
0
1200
2400
4800
9600
0
95
47
23
11
—
5
0
0
0
0
64
32
15
9
+0.16
–1.36
+1.73
0
0
31
0
19200 0
31250 —
38400 0
0
15
0
—
0
7
0
9
–1.70
0
—
—
7
7
+1.73
Note: If possible, the error should be within 1%.
6
2n
B = OSC × 10 /[64 × 2
× (N + 1)]
N: BRR value (0 ≤ N ≤ 255)
OSC: Crystal oscillator frequency in MHz
B: Bit rate (bits/second)
n: Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n
0
1
2
3
CKS1
CKS0
Clock
Ø
0
0
1
1
0
1
0
1
Ø/4
Ø/16
Ø/64
179
Table 8-4. Examples of BRR Settings in Synchronous Mode
XTAL frequency (MHz)
Bit
2
4
8
10
16
20
rate
100
250
500
1k
n
—
1
N
n
—
2
1
1
0
0
0
0
0
0
0
0
N
n
—
2
2
1
1
0
0
0
0
0
0
0
0
N
n
N
n
—
3
2
2
1
1
0
0
0
0
0
0
0
N
n
N
—
249
124
249
99
49
24
9
—
124
249
124
199
99
49
19
9
—
249
124
249
99
199
99
39
19
9
—
—
—
—
1
—
—
—
—
124
249
124
49
24
—
4
—
124
249
124
199
99
199
79
39
19
7
—
—
—
—
1
—
—
—
—
249
124
249
99
49
24
9
1
0
2.5k
5k
0
0
0
1
10k
25k
50k
100k
250k
500k
1M
0
0
0
0
0
0
0
4
0
0
—
0
—
0*
4
—
0
0
1
3
0
0*
1
—
—
—
—
3
0
4
0*
1
—
0
—
0*
2.5M
Notes: Blank: No setting is available.
—: A setting is available, but the bit rate is inaccurate.
* Continuous transfer is not possible.
6
2n
B = OSC × 10 /[8 × 2
× (N + 1)]
N: BRR value (0 ≤ N ≤ 255)
OSC: Crystal oscillator frequency in MHz
B: Bit rate (bits/second)
n: Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n
0
1
2
3
CKS1
CKS0
Clock
Ø
0
0
1
1
0
1
0
1
Ø/4
Ø/16
Ø/64
180
8.2.9 Serial/Timer Control Register (STCR)—H'FFC3
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
MPE
0
ICKS1 ICKS0
Initial value
Read/Write
0
0
—
—
—
—
—
R/W
R/W
R/W
The STCR is an 8-bit readable/writable register that controls the operating mode of the serial
communication interface and selects input clock sources for the 8-bit timer counters (TCNT).
The STCR is initialized to H'F8 by a reset.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as “1.”
Bit 2—Multiprocessor Enable (MPE): Enables or disables the SCI’s multiprocessor
communication function.
Bit 2
MPE
Description
0
The multiprocessor communication function is disabled,
regardless of the setting of the MP bit in SMR.
The multiprocessor communication function is enabled. The multi-
processor format can be selected by setting the MP bit in SMR to “1.”
(Initial value)
1
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICKS0): These bits select the
clock input to the timer counters (TCNT) in the 8-bit timers. For further information see
section 7.2.3, “Timer Control Register.”
181
8.3 Operation
8.3.1 Overview
The SCI supports serial data transfer in two modes. In asynchronous mode each character is
synchronized individually. In synchronous mode communication is synchronized with a clock
signal.
The selection of asynchronous or synchronous mode and the communication format depend on
settings in the SMR as indicated in table 8-5. The clock source depends on the settings of the C/A
bit in the SMR and the CKE1 and CKE0 bits in the SCR as indicated in table 8-6.
(1) Asynchronous Mode:
•
Data lengths of seven or eight bits can be selected.
•
A parity bit or multiprocessor bit can be added, and stop bit lengths of one or two bits can be
selected. These selections determine the communication format and character length.
Framing errors (FER), parity errors (PER) and overrun errors (ORER) can be detected in
receive data, and the line-break condition can be detected.
•
•
•
An internal or external clock source can be selected for the serial clock.
When an internal clock source is selected, the SCI is clocked by the on-chip baud rate generator
and can output a clock signal at the bit-rate frequency.
•
When the external clock source is selected, the on-chip baud rate generator is not used. The
external clock frequency must be 16 times the bit rate.
(2) Synchronous Mode:
•
•
•
•
The transmit data length is eight bits.
Overrun errors (ORER) can be detected in receive data.
An internal or external clock source can be selected for the serial clock.
When an internal clock source is selected, the SCI is clocked by the on-chip baud rate generator
and outputs a serial clock signal.
•
When the external clock source is selected, the on-chip baud rate generator is not used and the
SCI operates on the input serial clock.
182
Table 8-5. Communication Formats Used by SCI
SMR settings
Communication format
Bit 7 Bit 6 Bit 2 Bit 5 Bit 3
C/A CHR MP PE STOP Mode
Data
Multipro- Parity Stop-bit
length cessor bit bit
length
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
—
Asynchronous mode 8 bits
None
None 1 bit
2 bits
1
Present 1 bit
2 bits
None 1 bit
2 bits
1
0
7 bits
1
Present 1 bit
2 bits
0
1
—
Asynchronous mode 8 bits
(multiprocessor
Present
None
None 1 bit
2 bits
1
format)
7 bits
1 bit
2 bits
1
—
—
—
Synchronous mode 8 bits
None
Table 8-6. SCI Clock Source Selection
SMR
Bit 7
C/A
0
SCR
Bit 0
Bit 1
Serial transmit/receive clock
CKE1 CKE0 Mode Clock source SCK pin function
0
1
0
1
0
1
0
1
0
1
0
1
Async Internal
Input/output port (not used by SCI)
Serial clock output at bit rate
External
Serial clock input at 16 × bit rate
1
Sync
Internal
External
Serial clock output
Serial clock input
183
8.3.2 Asynchronous Mode
In asynchronous mode, each transmitted or received character is individually synchronized by
framing it with a start bit and stop bit.
Full duplex data transfer is possible because the SCI has independent transmit and receive sections.
Double buffering in both sections enables data to be written and read during serial communication,
for continuous data transfer.
Figure 8-2 shows the general format of one character sent or received in asynchronous mode. The
communication channel is normally held in the mark state (High). Character transmission or
reception starts with a transition to the space state (Low).
The first bit transmitted or received is the start bit (Low). It is followed by the data bits, in which
the least significant bit (LSB) comes first. The data bits are followed by the parity or
multiprocessor bit, if present, then the stop bit or bits (High) confirming the end of the frame.
In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the
center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate).
(LSB)
D0
(MSB)
D7
Idle state
(mark)
Parity or
multipro-
cessor bit
Start bit
1 bit
D1
Stop bit
Serial data
7 or 8 bits
0 or 1 bit
1 or 2 bits
One unit of data (one character or frame)
Figure 8-2. Data Format in Asynchronous Mode
(1) Data Format: Table 8-7 lists the data formats that can be sent and received in asynchronous
mode. Twelve formats can be selected by bits in the SMR.
184
Table 8-7. Data Formats in Asynchronous Mode
SMR Bits
CHR PE
MP
STOP
1
S
S
S
S
S
S
S
S
S
S
S
S
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
8-Bit data
STOP
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
8-Bit data
8-Bit data
8-Bit data
7-Bit data
7-Bit data
7-Bit data
7-Bit data
8-Bit data
8-Bit data
7-Bit data
7-Bit data
STOP STOP
1
P
P
STOP
STOP STOP
1
0
STOP
0
STOP STOP
1
P
P
STOP
1
STOP STOP
—
—
—
—
MPB STOP
MPB STOP STOP
MPB STOP
MPB STOP STOP
Notes: SMR: Serial mode register
START: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
(2) Clock: In asynchronous mode it is possible to select either an internal clock created by the on-
chip baud rate generator, or an external clock input at the SCK pin. The clock selection depends on
the C/A bit in the serial mode register (SMR) and the CKE0 and CKE1 bits in the serial control
register (SCR). Refer to table 8-6.
If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate.
If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is used
for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the
center of the transmit data bits. Figure 8-3 shows the phase relationship between the output clock
and transmit data.
185
“0”
D0
D1
D2
D3
D4
D5
D6
D7
0/1
“1”
“1”
One frame
Figure 8-3. Phase Relationship between Clock Output and Transmit Data
(Asynchronous Mode)
(3) Transmitting and Receiving Data
• SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to
“0” in the serial control register (SCR), then initialize the SCI as follows.
Note: When changing the communication mode or format, always clear the TE and RE bits to “0”
before following the procedure given below. Clearing TE to “0” sets TDRE to “1” and
initializes the transmit shift register (TSR). Clearing RE to “0,” however, does not initialize
the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their
previous contents.
When an external clock is used, the clock should not be stopped during initialization or
subsequent operation. SCI operation becomes unreliable if the clock is stopped.
186
Initialization
1. Select the communication format in the serial mode register (SMR).
2. Write the value corresponding to the bit rate in the bit rate register
(BRR). This step is not necessary when an external clock is used.
Clear TE and RE bits to
“0” in SCR
3. Select interrupts and the clock source in the serial control register
(SCR). Leave TE and RE cleared to “0.” If clock output is selected,
in asynchronous mode, clock output starts immediately after the
setting is made in SCR.
1
2
3
Select communication
format in SMR
4. Wait for at least the interval required to transmit or receive one bit,
then set TE or RE in the serial control register (SCR).
Set value in BRR
Setting TE or RE enables the SCI to use the TxD or RxD pin.
Also set the RIE, TIE, TEIE, and MPIE bits as necessary to enable
interrupts. The initial states are the mark transmit state, and the
idle receive state (waiting for a start bit).
Set CKE1 and CKE0 bits in
SCR (leaving TE and RE
cleared to “0”)
No
1 bit interval
elapsed?
Yes
4
Set TE or RE to “1” in SCR,
and set RIE, TIE, TEIE, and
MPIE as necessary
Start transmitting or receiving
Figure 8-4. Sample Flowchart for SCI Initialization
187
• Transmitting Serial Data: Follow the procedure below for transmitting serial data.
1.
2.
SCI initialization: the transmit data output function of the TxD pin is
selected automatically.
1
2
Initialize
SCI status check and transmit data write: read the serial status
register (SSR), check that the TDRE bit is “1,” then write transmit
data in the transmit data register (TDR) and clear TDRE to “0.”
If a multiprocessor format is selected, after writing the transmit
data write “0” or “1” in the multiprocessor bit transfer (MPBT) in
SSR. Transition of the TDRE bit from “0” to “1” can be reported
by an interrupt.
Start transmitting
Read TDRE bit in SSR
No
TDRE = “1”?
Yes
3. (a) To continue transmitting serial data: read the TDRE bit to check
whether it is safe to write; if TDRE = “1,” write data in TDR, then
clear TDRE to “0.”
(b) To end serial transmission: end of transmission can be
confirmed by checking transition of the TEND bit from “0” to “1.”
This can be reported by a TEI interrupt.
Write transmit data in TDR
If using multiprocessor format,
select MPBT value in SSR
4.
To output a break signal at the end of serial transmission: set the
DDR bit to “1” and clear the DR bit to “0” (DDR and DR are I/O
port registers), then clear TE to “0” in SCR.
Clear TDRE bit to “0” in SSR
Serial transmission
End of
transmission?
No
3
Yes
Read TEND bit in SSR
No
No
TEND = “1”?
Yes
Output break
signal?
4
Yes
Set DR = “0,” DDR = “1”
Clear TE bit in SCR to “0”
End
Figure 8-5. Sample Flowchart for Transmitting Serial Data
188
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to “0” the SCI recognizes that
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to “1” and starts
transmitting. If the TIE bit (TDR-empty interrupt enable) is set to “1” in SCR, the SCI requests
a TXI interrupt (TDR-empty interrupt) at this time.
Serial transmit data are transmitted in the following order from the TxD pin:
(a) Start bit: one “0” bit is output.
(b) Transmit data: seven or eight bits are output, LSB first.
(c) Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit
is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also
be selected.
(d) Stop bit: one or two “1” bits (stop bits) are output.
(e) Mark state: output of “1” bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is “0,” the SCI loads new
data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame.
If TDRE is “1,” the SCI sets the TEND bit to “1” in SSR, outputs the stop bit, then continues
output of “1” bits in the mark state. If the TEIE bit (TSR-empty interrupt enable) in SCR is set
to “1,” a TEI interrupt (TSR-empty interrupt) is requested.
189
Figure 8-6 shows an example of SCI transmit operation in asynchronous mode.
Start
bit
Parity Stop Start
bit bit bit
Parity Stop
bit bit
Data
Data
“1”
“1”
“0”
D0
D1
D7
0/1 “1” “0”
D0
D1
D7
0/1 “1”
Mark (idle)
state
TDRE
TEND
TXI
request
TXI interrupt handler
writes data in TDR and
clears TDRE to “0”
TXI
request
TEI request
1 frame
Figure 8-6. Example of SCI Transmit Operation (8-Bit Data with Parity and One Stop Bit)
190
• Receiving Serial Data: Follow the procedure below for receiving serial data.
1
2
Initialize
1. SCI initialization: the receive data function of the RxD pin is
selected automatically.
Start receiving
2. SCI status check and receive data read: read the serial status
register (SSR), check that RDRF is set to “1,” then read receive
data from the receive data register (RDR) and clear RDRF to “0.”
Transition of the RDRF bit from “0” to “1” can be reported by an
RXI interrupt.
Read RDRF bit in SSR
No
RDRF = “1”?
Yes
3. To continue receiving serial data: read RDR and clear RDRF to
“0” before the stop bit of the current frame is received.
Read receive data from RDR,
and clear RDRF bit to “0”
in SSR
4. Receive error handling and break detection: if a receive error
occurs, read the ORER, PER, and FER bits in SSR to identify
the error. After executing the necessary error handling, clear
ORER, PER, and FER all to “0.” Transmitting and receiving
cannot resume if ORER, PER, or FER remains set to “1.”
When a framing error occurs, the RxD pin can be read to detect
the break state.
Read ORER, PER, and
FER in SSR
3
Yes
PER RER
ORER = “1”?
No
4
No
Finished
receiving?
Error handling
Yes
Clear RE to “0” in SCR
End
Start error handling
Yes
Yes
FER = “1”?
No
Break?
No
Clear RE to “0”
Clear error flags to
“0” in SCR
in SCR
End
Return
Figure 8-7. Sample Flowchart for Receiving Serial Data
191
In receiving, the SCI operates as follows.
1. The SCI monitors the receive data line and synchronizes internally when it detects a start bit.
2. Receive data are shifted into RSR in order from LSB to MSB.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI makes the following checks:
(a) Parity check: the number of 1s in the receive data must match the even or odd parity setting
of the O/E bit in SMR.
(b) Stop bit check: the stop bit value must be “1.” If there are two stop bits, only the first stop
bit is checked.
(c) Status check: RDRF must be “0” so that receive data can be loaded from RSR into RDR.
If these checks all pass, the SCI sets RDRF to “1” and stores the received data in RDR. If one of
the checks fails (receive error), the SCI operates as indicated in table 8-8.
Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to “1.”
Be sure to clear the error flags.
4. After setting RDRF to “1,” if the RIE bit (receive-end interrupt enable) is set to “1” in SCR, the
SCI requests an RXI (receive-end) interrupt. If one of the error flags (ORER, PER, or FER) is
set to “1” and the RIE bit in SCR is also set to “1,” the SCI requests an ERI (receive-error)
interrupt.
192
Figure 8-8 shows an example of SCI receive operation in asynchronous mode.
Table 8-8. Receive Error Conditions and SCI Operation
Receive error
Abbreviation Condition
Data transfer
Overrun error
ORER
Receiving of next data ends
Receive data not loaded from
while RDRF is still set to “1” RSR into RDR
in SSR
Framing error
Parity error
FER
PER
Stop bit is “0”
Receive data loaded from RSR
into RDR
Parity of receive data differs
from even/odd parity setting
in SMR
Receive data loaded from RSR
into RDR
Start
bit
Parity Stop Start
Parity Stop
Data
bit
bit
bit
Data
bit
bit
“1”
“1”
“0”
D0
D1
D7
0/1
“1”
“0”
D0
D1
D7
0/1
“0”
Mark (idle)
state
RDRF
FER
RXI
request
RXI interrupt handler
reads data in RDR and
clears RDRF to “0”
Framing error,
ERI request
1 frame
Figure 8-8. Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
193
(4) Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID.
A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the
receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending
cycles from data-sending cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to “1.” Next the transmitting processor
sends transmit data with the multiprocessor bit cleared to “0.”
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
“1.”
After receiving data with the multiprocessor bit set to “1,” the receiving processor with an ID
matching the received data continues to receive further incoming data. Multiple processors can
send and receive data in this way.
Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected.
For details see table 8-7.
Transmitting
processor
Serial communication line
Receiving
processor A
Receiving
processor B
Receiving
processor C
Receiving
processor D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial data
H'01
H'AA
(MPB = 0)
(MPB = 1)
ID-sending cycle:
receiving processor address
Data-sending cycle:
data sent to receiving
processor specified by ID
MPB: multiprocessor bit
Figure 8-9. Example of Communication among Processors Using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
194
• Transmitting Multiprocessor Serial Data: See figures 8-5 and 8-6.
• Receiving Multiprocessor Serial Data: Follow the procedure below for receiving
multiprocessor serial data.
1
Initialize
1. SCI initialization: the receive data function of the RxD pin is
selected automatically.
2. ID receive cycle: Set the MPIE bit in the serial control register
(SCR) to “1.”
Start receiving
3. SCI status check and ID check: read the serial status register
(SSR), check that RDRF is set to “1,” then read receive data
from the receive data register (RDR) and compare with the
processor’s own ID. Transition of the RDRF bit from “0” to
“1” can be reported by an RXI interrupt. If the ID does not match
the receive data, set MPIE to “1” again and clear RDRF to “0.”
If the ID matches the receive data, clear RDRF to “0.”
2
3
Set MPIE bit to “1” in SCR
Read RDRF bit in SSR
No
RDRF = “1”?
Yes
4. SCI status check and data receiving: read SSR, check that
RDRF is set to “1,” then read data from the receive data register
(RDR) and write “0” in the RDRF bit. Transition of the RDRF bit
from “0” to “1” can be reported by an RXI interrupt.
Read receive data from RDR
5. Receive error handling and break detection: if a receive error
occurs, read the ORER and FER bits in SSR to identify the error.
After executing the necessary error handling, clear both ORER
and FER to “0.” Receiving cannot resume while ORER or FER
remains set to “1.” When a framing error occurs, the RxD pin
can be read to detect the break state.
No
Own ID?
Yes
Read ORER and FER
bits in SSR
FER
Yes
ORER = “1”?
No
4
Read RDRF bit in SSR
No
RDRF = “1”?
Yes
Read ORER and FER
bits in SSR
Read receive data from RDR
Start error handling
Yes
FER +
ORER = “1”?
5
No
Error handling
Yes
Yes
FER = “1”?
No
Break?
No
No
Finished
receiving?
Yes
Clear RE bit to
“0” in SCR
Clear error flags
Return
Clear RE to “0” in SCR
End
End
Figure 8-10. Sample Flowchart for Receiving Multiprocessor Serial Data
195
Figure 8-11 shows an example of SCI receive operation using a multiprocessor format.
Start
bit
Stop Start
MPB bit bit
Stop
MPB bit
Data (ID1)
D1
Data (Data2)
D1
“1”
“1”
“0”
D0
D7
“1”
“1”
“0”
D0
D7
“0”
“1”
Mark (idle)
state
MPIE
RDRF
RDR value
ID1
RXI request,
MPIE = “0”
RXI handler reads
RDR data and clears
RDRF to “0”
Not own ID, so
MPIE is set to
“1” again
No RXI request,
RDR not updated
(Multiprocessor interrupt)
(a) Own ID does not match data
Start
bit
Stop Start
Stop
MPB bit
Data (ID2)
D1
MPB bit
“1” “1”
bit
“0”
Data (Data2)
D1
“1”
“1”
“0”
D0
D7
D0
D7
“0” “1”
Mark (idle)
state
MPIE
RDRF
RDR value
ID1
ID2
Data 2
RXI request,
MPIE = “0”
RXI handler reads
RDR data and clears
RDRF to “0”
Own ID, so receiving
continues, with data
received at each RXI
MPIE set to
“1” again
(Multiprocessor interrupt)
(b) Own ID matches data
Figure 8-11. Example of SCI Receive Operation
(Eight-Bit Data with Multiprocessor Bit and One Stop Bit)
196
8.3.3 Clocked Synchronous Operation
(1) Overview: In clocked synchronous mode, the SCI transmits and receives data in
synchronization with clock pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex
communication is possible. The transmitter and receiver are also double buffered, so continuous
transmitting or receiving is possible by reading or writing data while transmitting or receiving is in
progress.
Figure 8-12 shows the general format in clocked synchronous serial communication.
One unit (character or frame) of serial data
*
*
Serial clock
Data
LSB
Bit 0
MSB
Bit 7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Don’t care
Don’t care
Note: * High except in continuous transmitting or receiving
Figure 8-12. Data Format in Clocked Synchronous Communication
In clocked synchronous serial communication, each data bit is sent on the communication line from
one falling edge of the serial clock to the next. Data are received in synchronization with the rising
edge of the serial clock.
In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After
output of the MSB, the communication line remains in the state of the MSB until the next falling
edge of the serial clock.
197
• Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor
bit can be added.
• Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected by clearing or setting the CKE1 bit in the serial control register
(SCR). See table 8-5.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock
pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains at the high level.
(2) Transmitting and Receiving Data
• SCI Initialization: The SCI must be initialized in the same way as in asynchronous mode. See
figure 8-4. When switching from asynchronous mode to clocked synchronous mode, check that the
ORER, FER, and PER bits are cleared to “0.” Transmitting and receiving cannot begin if ORER,
FER, or PER is set to “1.”
198
• Transmitting Serial Data: Follow the procedure below for transmitting serial data.
1.
2.
SCI initialization: the transmit data output function of the TxD pin is
selected automatically.
1
2
Initialize
SCI status check and transmit data write: read the serial status
register (SSR), check that the TDRE bit is “1,” then write transmit
data in the transmit data register (TDR) and clear TDRE to “0.”
Transition of the TDRE bit from “0” to “1” can be reported by a
TXI interrupt.
Start transmitting
Read TDRE bit in SSR
3. (a) To continue transmitting serial data: read the TDRE bit to check
whether it is safe to write; if TDRE = “1,” write data in TDR, then
clear TDRE to “0.”
No
TDRE = “1”?
Yes
(b) To end serial transmission: end of transmission can be confirmed
by checking transition of the TEND bit from “0” to “1.” This can be
reported by a TEI interrupt.
Write transmit data in
TDR and clear TDRE bit to
“0” in SSR
Serial transmission
End of
transmission?
No
3
Yes
Read TEND bit in SSR
No
TEND = “1”?
Yes
Clear TE bit to “0” in SCR
End
Figure 8-13. Sample Flowchart for Serial Transmitting
199
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to “0” the SCI recognizes that
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to “1” and starts
transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to “1,” the SCI requests
a TXI interrupt (TDR-empty interrupt) at this time.
If clock output is selected the SCI outputs eight serial clock pulses, triggered by the clearing of
the TDRE bit to “0.” If an external clock source is selected, the SCI outputs data in
synchronization with the input clock.
Data are output from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is “0,” the SCI loads
data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is “1,” the
SCI sets the TEND bit in SSR to “1,” transmits the MSB, then holds the output in the MSB
state. If the TEIE bit (transmit-end interrupt enable) in SCR is set to “1,” a TEI interrupt (TSR-
empty interrupt) is requested at this time.
4. After the end of serial transmission, the SCK pin is held at the high level.
200
Figure 8-14 shows an example of SCI transmit operation.
Serial clock
Data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI
TXI interrupt
TXI
request
request handler writes
data in TDR and
TEI
request
clears TDRE to “0”
1 frame
Figure 8-14. Example of SCI Transmit Operation
201
• Receiving Serial Data: Follow the procedure below for receiving serial data. When switching
from asynchronous mode to clocked synchronous mode, be sure to check that PER and FER are
cleared to “0.” If PER or FER is set to “1” the RDRF bit will not be set and both transmitting and
receiving will be disabled.
1
2
Initialize
1. SCI initialization: the receive data function of the RxD pin is
selected automatically.
Start receiving
2. SCI status check and receive data read: read the serial status
register (SSR), check that RDRF is set to “1,” then read receive
data from the receive data register (RDR) and clear RDRF to “0.”
Transition of the RDRF bit from “0” to “1” can be reported by an
RXI interrupt.
Read RDRF bit in SSR
No
3. To continue receiving serial data: read RDR and clear RDRF to
“0” before the MSB (bit 7) of the current frame is received.
RDRF = “1”?
Yes
4. Receive error handling: if a receive error occurs, read the ORER
bit in SSR then, after executing the necessary error handling,
clear ORER to “0.” Neither transmitting nor receiving can
resume while ORER remains set to “1.” When clock output
mode is selected, receiving can be halted temporarily by
receiving one dummy byte and causing an overrun error.
When preparations to receive the next data are completed, clear
the ORER bit to “0.” This causes receiving to resume, so
return to the step marked 2 in the flowchart.
3
Read receive data
from RDR, and clear
RDRF bit to “0” in SSR
Read ORER in SSR
Yes
No
ORER = “1”?
No
4
Error handling
Finished
receiving?
Yes
Clear RE to “0” in SCR
End
Start error handling
Overrun error handling
Clear ORER to “0” in SSR
Return
Figure 8-15. Sample Flowchart for Serial Receiving
202
In receiving, the SCI operates as follows.
1. If an external clock is selected, data are input in synchronization with the input clock. If clock
output is selected, as soon as the RE bit is set to “1” the SCI begins outputting the serial clock
and inputting data. If clock output is stopped because the ORER bit is set to “1,” output of the
serial clock and input of data resume as soon as the ORER bit is cleared to “0.”
2. Receive data are shifted into RSR in order from LSB to MSB.
After receiving the data, the SCI checks that RDRF is “0” so that receive data can be loaded
from RSR into RDR. If this check passes, the SCI sets RDRF to “1” and stores the received
data in RDR. If the check does not pass (receive error), the SCI operates as indicated in
table 8-8.
Note: Both transmitting and receiving are disabled while a receive error flag is set. The RDRF bit
is not set to “1.” Be sure to clear the error flag.
3. After setting RDRF to “1,” if the RIE bit (receive-end interrupt enable) is set to “1” in SCR, the
SCI requests an RXI (receive-end) interrupt. If the ORER bit is set to “1” and the RIE bit in
SCR is set to “1,” the SCI requests an ERI (receive-error) interrupt.
When clock output mode is selected, clock output stops when the RE bit is cleared to “0” or the
ORER bit is set to “1.” To prevent clock count errors, it is safest to receive one dummy byte
and generate an overrun error.
203
Figure 8-16 shows an example of SCI receive operation.
Serial clock
Data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI
request
RXI interrupt
handler reads
data in RDR and
clears RDRF to “0”
RXI
request
Overrun error,
ERI request
1 frame
Figure 8-16. Example of SCI Receive Operation
204
• Transmitting and Receiving Serial Data Simultaneously: Follow the procedure below for
transmitting and receiving serial data simultaneously. If clock output mode is selected, output of
the serial clock begins simultaneously with serial transmission.
1
2
Initialize
Start
1. SCI initialization: the transmit data output function of the TxD pin
and receive data input function of the RxD pin are selected,
enabling simultaneous transmitting and receiving.
2. SCI status check and transmit data write: read the serial status
register (SSR), check that the TDRE bit is “1,” then write transmit
data in the transmit data register (TDR) and clear TDRE to “0.”
Transition of the TDRE bit from “0” to “1” can be reported by a
TXI interrupt.
Read TDRE bit in SSR
No
TDRE = “1”?
Yes
3. SCI status check and receive data read: read the serial status
register (SSR), check that the RDRF bit is “1,” then read receive
data from the receive data register (RDR) and clear RDRF to “0.”
Transition of the RDRF bit from “0” to “1” can be reported by an
RXI interrupt.
3
Write transmit data
in TDR and clear TDRE
bit to “0” in SSR
4. To continue transmitting and receiving serial data: read RDR
and clear RDRF to “0” before the MSB (bit 7) of the current
frame is received. Also read the TDRE bit and check that it is
set to “1,” indicating that it is safe to write; then write data
in TDR and clear TDRE to “0” before the MSB (bit 7) of the
current frame is transmitted.
Read RDRF bit in SSR
No
RDRF = “1”?
Yes
5. Receive error handling: if a receive error occurs, read the ORER
bit in SSR then, after executing the necessary error handling,
clear ORER to “0.” Neither transmitting nor receiving can resume
while ORER remains set to “1.”
4
Read receive data
from RDR and clear
RDRF bit to “0” in SSR
Read ORER bit in SSR
Yes
No
ORER = “1”?
No
5
Error handling
End of
transmitting and receiv-
ing?
Yes
Clear TE and RE bits
to “0” in SCR
End
Figure 8-17. Sample Flowchart for Serial Transmitting and Receiving
Note: In switching from transmitting or receiving to simultaneous transmitting and receiving,
clear both TE and RE to “0,” then set both TE and RE to “1.”
205
8.4 SCI Interrupts
The SCI can request four types of interrupts: ERI, RXI, TXI, and TEI. Table 8-9 indicates the
source and priority of these interrupts. The interrupt sources can be enabled or disabled by the TIE,
RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for each
interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three sources:
overrun error, framing error, and parity error.
The TXI interrupt indicates that the next transmit data can be written. The TEI interrupt indicates
that the SCI has stopped transmitting data.
Table 8-9. SCI Interrupt Sources
Interrupt
ERI
Description
Priority
Receive-error interrupt (ORER, FER, or PER) High
Receive-end interrupt (RDRF)
RXI
TXI
TDR-empty interrupt (TDRE)
TEI
TSR-empty interrupt (TEND)
Low
8.5 Application Notes
Application programmers should note the following features of the SCI.
(1) TDR Write: The TDRE bit in the SSR is simply a flag that indicates that the TDR contents
have been transferred to the TSR. The TDR contents can be rewritten regardless of the TDRE
value. If a new byte is written in the TDR while the TDRE bit is “0,” before the old TDR contents
have been moved into the TSR, the old byte will be lost. Software should check that the TDRE bit
is set to “1” before writing to the TDR.
206
(2) Multiple Receive Errors: Table 8-10 lists the values of flag bits in the SSR when multiple
receive errors occur, and indicates whether the RSR contents are transferred to the RDR.
Table 8-10. SSR Bit States and Data Transfer When Multiple Receive Errors Occur
SSR bits
RSR →
RDR*2
No
Receive error
RDRF ORER FER
PER
Overrun error
1*1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
1
Framing error
0
Yes
Parity error
0
Yes
Overrun and framing errors
Overrun and parity errors
Framing and parity errors
Overrun, framing, and parity errors
1*1
1*1
0
No
No
Yes
1*1
No
Notes: *1 Set to “1” before the overrun error occurs.
*2 Yes: The RSR contents are transferred to the RDR.
No: The RSR contents are not transferred to the RDR.
(3) Line Break Detection: When the RxD pin receives a continuous stream of 0’s in asynchronous
mode (line-break state), a framing error occurs because the SCI detects a “0” stop bit. The value
H'00 is transferred from the RSR to the RDR. Software can detect the line-break state as a framing
error accompanied by H'00 data in the RDR.
The SCI continues to receive data, so if the FER bit is cleared to “0” another framing error will
occur.
(4) Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by
the SCI in asynchronous mode runs at 16 times the baud rate. The falling edge of the start bit is
detected by sampling the RxD input on the falling edge of this clock. After the start bit is detected,
each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is
sampled on the rising edge of the serial clock pulse at the center of the bit. See figure 8-18.
It follows that the receive margin can be calculated as in equation (1).
When the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5, data
can theoretically be received with distortion up to the margin given by equation (2). This is a
theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%.
207
0 1 2 3 4 5 6 7 89 10111213141516 1 2 3 4 5 6 7 8 9101112131415161 2 3 4 5
Basic clock
–7.5 pulses
+7.5 pulses
Receive data
D0
D1
Start bit
Sync sampling
Data sampling
Figure 8-18. Sampling Timing (Asynchronous Mode)
M = {(0.5 – 1/2N) – (D – 0.5)/N – (L – 0.5)F} × 100 [%]
(1)
M: Receive margin
N: Ratio of basic clock to baud rate (N=16)
D: Duty factor of clock—ratio of High pulse width to Low width (0.5 to 1.0)
L: Frame length (9 to 12)
F: Absolute clock frequency deviation
When D = 0.5 and F = 0
M=(0.5 –1/2 × 16) × 100 [%] = 46.875%
(2)
208
Section 9. A/D Converter
9.1 Overview
The H8/329 Series includes an analog-to-digital converter module with eight input channels. A/D
conversion is performed by the successive approximations method with 8-bit resolution.
9.1.1 Features
The features of the on-chip A/D module are:
• 8-bit resolution
• Eight analog input channels
• Rapid conversion
Conversion time is 12.2µs per channel (minimum) with a 10MHz system clock
• External triggering can be selected
• Single and scan modes
— Single mode: A/D conversion is performed once.
— Scan mode: A/D conversion is performed in a repeated cycle on one to four channels.
• Sample-and-hold function
• Four 8-bit data registers
These registers store A/D conversion results for up to four channels.
• A CPU interrupt (ADI) can be requested at the completion of each A/D conversion cycle.
209
9.1.2 Block Diagram
Internal
data bus
Module data bus
AVCC
A
D
D
R
A
A
D
D
R
B
A
D
D
R
C
A
D
D
R
D
A
D
C
S
R
A
D
C
R
8 Bit
D/A
AVSS
AN0
Ø/8
Ø/16
AN1
AN2
+
–
Analog
multi-
plexer
AN3
AN4
AN5
Control circuit
Comparator
AN6
AN7
Sample and
hold circuit
ADI
Interrupt signal
ADTRG
ADCR: A/D Control Register (8 bits)
ADCSR: A/D Control/Status Register (8 bits)
ADDRA: A/D Data Register A (8 bits)
ADDRB: A/D Data Register B (8 bits)
ADDRC: A/D Data Register C (8 bits)
ADDRD: A/D Data Register D (8 bits)
Figure 9-1. Block Diagram of A/D Converter
210
9.1.3 Input Pins
Table 9-1 lists the input pins used by the A/D converter module.
The eight analog input pins are divided into two groups, consisting of analog inputs 0 to 3 (AN0 to
AN3) and analog inputs 4 to 7 (AN4 to AN7), respectively.
Table 9-1. A/D Input Pins
Name
Abbreviation I/O
Function
Analog supply voltage
AVCC
Input
Power supply and reference voltage for the
analog circuits.
Analog ground
AVSS
Input
Ground and reference voltage for the
analog circuits.
Analog input 0
Analog input 1
Analog input 2
Analog input 3
Analog input 4
Analog input 5
Analog input 6
Analog input 7
A/D external trigger
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADTRG
Input
Input
Input
Input
Input
Input
Input
Input
Input
Analog input pins, group 0
Analog input pins, group 1
External trigger for starting A/D conversion
9.1.4 Register Configuration
Table 9-2 lists the registers of the A/D converter module.
Table 9-2. A/D Registers
Name
Abbreviation R/W
Initial value Address
A/D data register A
A/D data register B
A/D data register C
A/D data register D
A/D control/status register
A/D control register
ADDRA
ADDRB
ADDRC
ADDRD
ADCSR
ADCR
R
R
R
R
H'00
H'00
H'00
H'00
H'FFE0
H'FFE2
H'FFE4
H'FFE6
H'FFE8
H'FFEA
R/(W)* H'00
R/W H'7E
Note: * Software can write a “0” to clear bit 7, but cannot write a “1” in this bit.
211
9.2 Register Descriptions
9.2.1 A/D Data Registers (ADDR)—H'FFE0 to H'FFE6
Bit
7
6
5
4
3
2
1
0
ADDRn
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 8-bit read-only registers that store the results
of A/D conversion. Each data register is assigned to two analog input channels as indicated in
table 9-3.
The A/D data registers are always readable by the CPU.
The A/D data registers are initialized to H'00 at a reset and in the standby modes.
Table 9-3. Assignment of Data Registers to Analog Input Channels
Analog input channel
Group 0 Group 1 A/D data register
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADDRA
ADDRB
ADDRC
ADDRD
9.2.2 A/D Control/Status Register (ADCSR)—H'FFE8
Bit
7
ADF
0
6
ADIE
0
5
4
3
2
1
0
ADST SCAN
CKS
0
CH2
0
CH1
0
CH0
0
Initial value
Read/Write
0
0
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Software can write a “0” in bit 7 to clear the flag, but cannot write a “1” in this bit.
The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the
operation of the A/D converter module.
212
The ADCSR is initialized to H'00 at a reset and in the standby modes.
Bit 7—A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion.
Bit 7
ADF
Description
0
To clear ADF, the CPU must read ADF after
it has been set to “1,” then write a “0” in this bit.
This bit is set to 1 at the following times:
(1) Single mode: when one A/D conversion is completed.
(2) Scan mode: when inputs on all selected channels have been
converted.
(Initial value)
1
Bit 6—A/D Interrupt Enable (ADIE): This bit selects whether to request an A/D interrupt (ADI)
when A/D conversion is completed.
Bit 6
ADIE
Description
0
1
The A/D interrupt request (ADI) is disabled.
The A/D interrupt request (ADI) is enabled.
(Initial value)
Bit 5—A/D Start (ADST): The A/D converter operates while this bit is set to “1.” This bit can be
set to “1” by the external trigger signal ADTRG.
Bit 5
ADST
Description
0
1
A/D conversion is halted.
(Initial value)
(1) Single mode: One A/D conversion is performed. The ADST bit is
automatically cleared to “0” at the end of the conversion.
(2) Scan mode: A/D conversion starts and continues cyclically on the
selected channels until the ADST bit is cleared to “0” by software (or
a reset, or by entry to a standby mode).
213
Bit 4—Scan Mode (SCAN): This bit selects the scan mode or single mode of operation.
See section 9.3, “Operation” for descriptions of these modes.
The mode should be changed only when the ADST bit is cleared to “0.”
Bit 4
SCAN
Description
Single mode
Scan mode
0
1
(Initial value)
Bit 3—Clock Select (CKS): This bit controls the A/D conversion time.
The conversion time should be changed only when the ADST bit is cleared to “0.”
Bit 3
CKS
Description
0
1
Conversion time = 242 states (max)
Conversion time = 122 states (max)
(Initial value)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit combine to select
one or more analog input channels.
The channel selection should be changed only when the ADST bit is cleared to “0.”
Group select
Channel select
Selected channels
Single mode Scan mode
CH2
CH1
CH0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AN0 (Initial value)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN0, AN1
AN0 to AN2
AN0 to AN3
AN4
1
AN4, AN5
AN4 to AN6
AN4 to AN7
214
9.2.3 A/D Control Register (ADCR)—H'FFEA
Bit
7
TRGE
0
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
CHS
0
Initial value
Read/Write
R/W
—
—
—
—
—
—
R/W
The A/D control register (ADCR) is an 8-bit readable/writable register that enables or disables the
A/D external trigger signal.
The ADCR is initialized to H'7E at a reset and in the standby modes.
Bit 7—Trigger Enable (TRGE): This bit enables the ADTRG (A/D external trigger) signal to set
the ADST bit and start A/D conversion.
Bit 7
TRGE
Description
0
A/D external trigger is disabled. ADTRG does not set
the ADST bit.
(Initial value)
1
A/D external trigger is enabled. ADTRG sets the ADST bit.
(The ADST bit can also be set by software.)
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as “1.”
Bit 0—Channel Set Select (CHS): This bit is reserved. It does not affect the operation of the
chip.
215
9.3 Operation
The A/D converter performs 8 successive approximations to obtain a result ranging from H'00
(corresponding to AVSS) to H'FF (corresponding to AVCC).
The A/D converter module can be programmed to operate in single mode or scan mode as
explained below.
9.3.1 Single Mode (SCAN = 0)
The single mode is suitable for obtaining a single data value from a single channel. A/D
conversion starts when the ADST bit is set to “1,” either by software or by a High-to-Low
transition of the ADTRG signal (if enabled). During the conversion process the ADST bit remains
set to “1.” When conversion is completed, the ADST bit is automatically cleared to “0.”
When the conversion is completed, the ADF bit is set to “1.” If the interrupt enable bit (ADIE) is
also set to “1,” an A/D conversion end interrupt (ADI) is requested, so that the converted data can
be processed by an interrupt-handling routine. The ADF bit is cleared when software reads the
A/D control/status register (ADCSR), then writes a “0” in this bit.
Before selecting the single mode, clock, and analog input channel, software should clear the ADST
bit to “0” to make sure the A/D converter is stopped. Changing the mode, clock, or channel
selection while A/D conversion is in progress can lead to conversion errors. A/D conversion begins
when the ADST bit is set to “1” again. The same instruction can be used to alter the mode and
channel selection and set ADST to “1.”
216
The following example explains the A/D conversion process in single mode when channel 1 (AN1)
is selected and the external trigger is disabled. Figure 9-2 shows the corresponding timing chart.
(1) Software clears the ADST bit to “0,” then selects the single mode (SCAN = “0”) and channel 1
(CH2 to CH0 = “001”), enables the A/D interrupt request (ADIE = “1”), and sets the ADST bit
to “1” to start A/D conversion.
Coding Example: (when using the slow clock, CKS = “0”)
BCLR #5, @H'FFE8
MOV.B #H'7F, ROL
;Clear ADST
MOV.B ROL, @H'FFEA;Disable external trigger
MOV.B #H'61, ROL
MOV.B ROL, @H'FFE8;Select mode and channel and set ADST to “1”
Value set in ADCSR:
ADF
0
ADIE
1
ADST SCAN
CKS
0
CH2
0
CH1
0
CH0
1
1
0
(2) The A/D converter converts the voltage level at the AN1 input pin to a digital value. At the end
of the conversion process the A/D converter transfers the result to register ADDRB, sets the
ADF bit to “1,” clears the ADST bit to “0,” and halts.
(3) ADF = “1” and ADIE = “1,” so an A/D interrupt is requested.
(4) The user-coded A/D interrupt-handling routine is started.
(5) The interrupt-handling routine reads the ADCSR value, then writes a “0” in the ADF bit to
clear this bit to “0.”
(6) The interrupt-handling routine reads ADDRB and processes the A/D conversion result.
(7) The routine ends.
Steps (2) to (7) can now be repeated by setting the ADST bit to “1” again.
217
Interrupt (ADI)
ADIE
Set*
Set*
Set*
A/D conversion starts
ADST
ADF
Clear*
Clear*
Channel 0 (AN 0)
Waiting
Waiting
Waiting
Waiting
Channel 1 (AN 1)
A/D conver-
sion
Waiting
Waiting
A/D conver-
sion ➁
➀
Channel 2 (AN 2)
Channel 3 (AN 3)
ADDRA
ADDRB
ADDRC
ADDRD
Read result
Read result
A/D conversion result
A/D conversion result
➀
➁
Note: * indicates execution of a software instruction
Figure 9-2. A/D Operation in Single Mode (when Channel 1 is Selected)
9.3.2 Scan Mode (SCAN = 1)
The scan mode can be used to monitor analog inputs on one or more channels. When the ADST bit
is set to “1,” either by software or by a High-to-Low transition of the ADTRG signal (if enabled),
A/D conversion starts from the first channel selected by the CH bits. When CH2 = “0” the first
channel is AN0. When CH2 = “1” the first channel is AN4.
If the scan group includes more than one channel (i.e., if bit CH1 or CH0 is set), conversion of the
next channel (AN1 or AN5)begins as soon as conversion of the first channel ends.
Conversion of the selected channels continues cyclically until the ADST bit is cleared to “0.” The
conversion results are placed in the data registers corresponding to the selected channels. The A/D
data registers are readable by the CPU.
Before selecting the scan mode, clock, and analog input channels, software should clear the ADST
bit to “0” to make sure the A/D converter is stopped. Changing the mode, clock, or channel
selection while A/D conversion is in progress can lead to conversion errors. A/D conversion begins
from the first selected channel when the ADST bit is set to “1” again. The same instruction can be
used to alter the mode and channel selection and set ADST to “1.”
The following example explains the A/D conversion process when three channels in group 0 are
selected (AN0, AN1, and AN2) and the external trigger is disabled. Figure 9-3 shows the
corresponding timing chart.
(1) Software clears the ADST bit to “0,” then selects the scan mode (SCAN = “1”), scan group 0
(CH2 = “0”), and analog input channels AN0 to AN2 (CH1 = “1”, CH0 = “0”) and sets the
ADST bit to “1” to start A/D conversion.
Coding Example: (with slow clock and ADI interrupt enabled)
BCLR #5, @H'FFE8
MOV.B #H'7F, ROL
;Clear ADST
MOV.B ROL, @H'FFEA;Disable external trigger
MOV.B #H'72, ROL
MOV.B ROL, @H'FFE8;Select mode and channels and set ADST to “1”
Value set in ADCSR
ADF
0
ADIE
1
ADST SCAN
CKS
0
CH2
0
CH1
1
CH0
0
1
1
219
(2) The A/D converter converts the voltage level at the AN0 input pin to a digital value, and
transfers the result to register ADDRA.
(3) Next the A/D converter converts AN1 and transfers the result to ADDRB. Then it converts
AN2 and transfers the result to ADDRC.
(4) After all selected channels (AN0 to AN2) have been converted, the AD converter sets the ADF
bit to “1.” If the ADIE bit is set to “1,” an A/D interrupt (ADI) is requested. Then the A/D
converter begins converting AN0 again.
(5) Steps (2) to (4) are repeated cyclically as long as the ADST bit remains set to “1.”
To stop the A/D converter, software must clear the ADST bit to “0.”
Regardless of which channel is being converted when the ADST bit is cleared to “0,” when the
ADST bit is set to “1” again, conversion begins from the the first selected channel (AN0).
220
Continuous A/D conversion
1
Clear *
Set*
1
ADST
1
*
Clear
ADF
A/D conversion
time
Channel 0 (AN 0)
A/D conver-
A/D conver-
Waiting
Waiting
Waiting
Waiting
Waiting
sion
sion
➀
➃
Waiting
Waiting
A/D conver- * 2
sion ➄
Channel 1 (AN 1)
A/D conver-
sion ➁
Channel 2 (AN 2)
Channel 3 (AN 3)
ADDRA
Waiting
A/D conver-
➂
sion
Waiting
Transfer
A/D conversion result
A/D conver-
➃
➀
sion result
ADDRB
ADDRC
A/D conversion result
➁
A/D conversion result
➂
ADDRD
Notes: *1 indicates execution of a software instruction
*2 Data undergoing conversion when ADST bit is cleared are ignored.
Figure 9-3. A/D Operation in Scan Mode (when Channels 0 to 2 are Selected)
9.3.3 Input Sampling Time and A/D Conversion Time
The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a
time tD after the ADST bit is set to “1.” The sampling process lasts for a time tSPL. The actual A/D
conversion begins after sampling is completed. Figure 9-4 shows the timing of these steps.
Table 9-4 (a) lists the conversion times for the single mode. Table 9-4 (b) lists the conversion times
for the scan mode.
The total conversion time (tCONV) includes tD and tSPL. The purpose of tD is to synchronize the
ADCSR write time with the A/D conversion process, so the length of tD is variable. The total
conversion time therefore varies within the minimum to maximum ranges indicated in table 9-4 (a)
and (b).
In the scan mode, the ranges given in table 9-4 (b) apply to the first conversion. The length of the
second and subsequent conversion processes is fixed at 256 states (when CKS = “0”) or 128 states
(when CKS = “1”).
(1)
Ø
Internal address bus
(2)
Write signal
Input sampling timing
ADF
tD
tSPL
tCONV
(1):
(2):
tD:
ADCSR write cycle
ADCSR address
Synchronization delay
Input sampling time
tSPL:
tCONV: Total A/D conversion time
Figure 9-4. A/D Conversion Timing
222
Table 9-4 (a). A/D Conversion Time (Single Mode)
CKS = “0”
Typ
CKS = “1”
Item
Symbol Min
Max
33
Min
10
Typ
—
Max
17
Synchronization delay
Input sampling time
tD
18
—
63
—
tSPL
—
—
—
31
—
Total A/D conversion time tCONV
227
242
115
—
122
Table 9-4 (b). A/D Conversion Time (Scan Mode)
CKS = “0”
Typ
CKS = “1”
Item
Symbol Min
Max
33
Min
10
Typ
—
Max
17
Synchronization delay
Input sampling time
tD
18
—
63
—
tSPL
—
—
—
31
—
Total A/D conversion time tCONV
259
274
131
—
138
Note: Values in the tables above are numbers of states.
9.3.4 External Trigger Input Timing
A/D conversion can be started by external trigger input at the ADTRG pin. This input is enabled or
disabled by the TRGE bit in the A/D control register (ADCR). If the TRGE bit is set to “1,” when
a falling edge of ADTRG is detected the ADST bit is set to “1” and A/D conversion begins.
Subsequent operation in both single and scan modes is the same as when the ADST bit is set to “1”
by software.
Figure 9-5 shows the trigger timing.
223
Ø
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 9-5. External Trigger Input Timing
9.4 Interrupts
The A/D conversion module generates an A/D-end interrupt request (ADI) at the end of A/D
conversion.
The ADI interrupt request can be enabled or disabled by the ADIE bit in the A/D control/status
register (ADCSR).
224
Section 10. RAM
10.1 Overview
The H8/329 and H8/328 include 1k byte of on-chip static RAM. The H8/327 has 512 bytes. The
H8/326 has 256 bytes. The on-chip RAM is connected to the CPU by a 16-bit data bus. Both byte
and word access to the on-chip RAM are performed in two states, enabling rapid data transfer and
instruction execution.
The on-chip RAM is assigned to addresses H'FB80 to H'FF7F in the H8/329 and H8/328, addresses
H'FD80 to H'FF7F in the H8/327, and addresses H'FE80 to H'FF7F in the H8/326. The RAME bit
in the system control register (SYSCR) can enable or disable the on-chip RAM, permitting these
addresses to be allocated to external memory instead, if so desired.
10.2 Block Diagram
Figure 10-1 is a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FB80
H'FB82
H'FB81
H'FB83
On-chip RAM
H'FF7E
H'FF7F
Even address
Odd address
Figure 10-1. Block Diagram of On-Chip RAM (H8/329 and H8/328)
225
10.3 RAM Enable Bit (RAME) in System Control Register (SYSCR)
The on-chip RAM is enabled or disabled by the RAME (RAM Enable) bit in the system control
register (SYSCR).
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
—
1
2
NMIEG
0
1
—
1
0
RAME
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
—
R/W
—
R/W
The only bit in the system control register that concerns the on-chip RAM is the RAME bit. See
section 2.2, “System Control Register” for the other bits.
Bit 0—RAM Enable (RAME): This bit enables or disables the on-chip RAM.
The RAME bit is initialized to “1” on the rising edge of the RES signal, so a reset enables the on-
chip RAM. The RAME bit is not initialized in the software standby mode.
Bit 7
RAME
Description
0
1
On-chip RAM is disabled.
On-chip RAM is enabled.
(Initial value)
10.4 Operation
10.4.1 Expanded Modes (Modes 1 and 2)
If the RAME bit is set to “1,” accesses to addresses H'FB80 to H'FF7F in the H8/329 and H8/328,
addresses H'FD80 to H'FF7F in the H8/327, and addresses H'FE80 to H'FF7F in the H8/326 are
directed to the on-chip RAM. If the RAME bit is cleared to “0,” accesses to these addresses are
directed to the external data bus.
10.4.2 Single-Chip Mode (Mode 3)
If the RAME bit is set to “1,” accesses to addresses H'FB80 to H'FF7F in the H8/329 and H8/328,
addresses H'FD80 to H'FF7F in the H8/327, and addresses H'FE80 to H'FF7F in the H8/326 are
directed to the on-chip RAM.
If the RAME bit is cleared to “0,” the on-chip RAM data cannot be accessed. Attempted write
access has no effect. Attempted read access always results in H'FF data being read.
226
Section 11. ROM
11.1 Overview
The H8/329 includes 32k bytes of high-speed, on-chip ROM. The H8/328 has 24k bytes. The
H8/327 has 16k bytes. The H8/326 has 8k bytes. The on-chip ROM is connected to the CPU via a
16-bit data bus. Both byte data and word data are accessed in two states, enabling rapid data
transfer and instruction fetching.
The H8/329 and H8/327 are available with electrically programmable ROM (PROM). The PROM
version has a PROM mode in which the chip can be programmed with a standard PROM writer.
The on-chip ROM is enabled or disabled depending on the MCU operating mode, which is
determined by the inputs at the mode pins (MD1 and MD0). See table 11-1.
Table 11-1. On-Chip ROM Usage in Each MCU Mode
Mode pins
Mode
MD1
MD0
On-Chip ROM
Disabled (external addresses)
Enabled
Mode 1 (expanded mode)
Mode 2 (expanded mode)
Mode 3 (single-chip mode)
0
1
1
1
0
1
Enabled
227
11.1.1 Block Diagram
Figure 11-1 is a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000
H'0002
H'0001
H'0003
On-chip ROM
H'7FFE
H'7FFF
Even addresses Odd addresses
Figure 11-1. Block Diagram of On-Chip ROM (H8/329)
11.2 PROM Mode (H8/329, H8/327)
11.2.1 PROM Mode Setup
In the PROM mode of the PROM version of the H8/329 and H8/327, the usual microcomputer
functions are halted to allow the on-chip PROM to be programmed. The programming method is
the same as for the HN27C256.
To select the PROM mode, apply the signal inputs listed in table 11-2.
Table 11-2. Selection of PROM Mode
Pin
Input
Low
Low
Low
High
Mode pin MD1
Mode pin MD0
STBY pin
Pins P63 and P64
228
11.2.2 Socket Adapter Pin Assignments and Memory Map
The H8/329 and H8/327 can be programmed with a general-purpose PROM writer. Since the
package has more than 32 pins, a socket adapter is necessary. Table 11-3 lists recommended socket
adapters. Figure 11-2 shows the socket adapter pin assignments by giving the correspondence
between H8/329 or H8/327 pins and HN27C256 pin functions. The same socket adapter can be
used for both the H8/329 and H8/327.
Figures 11-3 and 11-4 show memory maps in the PROM mode. Since the H8/329 has only 32k
bytes of on-chip PROM, its address range should be specified as H'0000 to H'7FFF. Since the
H8/327 has only 16k bytes of on-chip PROM, its address range should be specified as H'0000 to
H'3FFF. H'FF data should be specified for unused address areas.
It is important to limit the program address range to H'0000 to H'7FFF for the H8/329, and to
H'0000 to H'3FFF for the H8/327, and specify H'FF data for H'8000 or H'4000 and higher
addresses. If data (other than H'FF) are written by mistake in addresses equal to or greater than
H'8000 in the H8/329, or H'4000 in the H8/327, it may become impossible to program or verify the
PROM data. With a windowed package, it is possible to erase the data and reprogram, but this
cannot be done with a plastic package, so particular care is required.
Table 11-3. Recommended Socket Adapters
Package
Recommended socket adapter
64-pin windowed shrink DIP (DC-64S)
64-pin shrink DIP (DP-64S)
64-pin QFP (FP-64A)
HS328ESS02H
HS328ESH02H
HS328ESC02H
68-pin PLCC (DP-68)
229
H8/329 or H8/327
DC-64S
EPROM Socket
HN27C256
CP-68
13
14
61
62
63
64
65
66
67
68
60
59
58
57
56
55
54
53
50
49
48
47
46
45
44
43
37
38
32
15
42
22
21
16
23
17
51
1
FP-64A
DP-64S Pin
Pin
(28 pins)
4
12
13
57
58
59
60
61
62
63
64
56
55
54
53
52
51
50
49
47
46
45
44
43
42
41
40
34
35
30
14
39
20
19
15
21
16
48
—
RES
NMI
P30
P31
P32
P33
P34
P35
P36
P37
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P63
P64
AVCC
VCC
VCC
MD0
MD1
STBY
AVSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
1
5
EA9
EO0
EO1
EO2
EO3
EO4
EO5
EO6
EO7
EA0
EA1
EA2
EA3
EA4
EA5
EA6
EA7
EA8
OE
24
11
12
13
15
16
17
18
19
10
9
49
50
51
52
53
54
55
56
48
47
46
45
44
43
42
41
39
38
37
36
35
34
33
32
26
27
22
8
8
7
6
5
4
3
25
22
21
23
2
EA10
EA11
EA12
EA13
EA14
CE
26
27
20
28
VCC
31
12
11
7
VSS
14
13
8
40
—
—
—
—
PP
V
:
Program voltage (12.5 V)
EO 7 to EO0: Data input/output
EA 14 to EA0: Address input
18
35
52
—
—
OE:
CE:
Output enable
Chip enable
—
Note: All pins not listed in this figure should be left open.
Figure 11-2. Socket Adapter Pin Assignments
230
Address in MCU mode
H'0000
Address in PROM mode
H'0000
On-chip
PROM
H'7FFF
H'7FFF
Figure 11-3. Memory Map of H8/329 in PROM Mode
Address in MCU mode
Address in PROM mode
H'0000
H'0000
On-chip
PROM
H'3FFF
H'3FFF
Note: * If this area is read in PROM mode,
“1” output *
the output data are H'FF.
H'7FFF
Figure 11-4. Memory Map of H8/327 in PROM Mode
231
11.3 Programming
The write, verify, and other sub-modes of the PROM mode are selected as shown in table 11-4.
Table 11-4. Selection of Sub-Modes in PROM Mode
Sub-Mode
Write
CE
Low High VPP
High Low
OE
VPP
VCC
VCC
VCC
VCC
EO7 to EO0
Data input
EA14 to EA0
Address input
Address input
Address input
Verify
VPP
Data output
High impedance
Programming High High VPP
inhibited
Note: The VPP and VCC pins must be held at the VPP and VCC voltage levels.
The H8/329 and H8/327 PROM has the same standard read/write specifications as the HN27C256
and HN27256 EPROM.
11.3.1 Writing and Verifying
An efficient, high-speed programming procedure can be used to write and verify PROM data. This
procedure writes data quickly without subjecting the chip to voltage stress and without sacrificing
data reliability. It leaves the data H'FF written in unused addresses. Figure 11-5 shows the basic
high-speed programming flowchart. Tables 11-5 and 11-6 list the electrical characteristics of the
chip in the PROM mode. Figure 11-6 shows a write/verify timing chart.
232
START
Set program/verify mode
VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V
Address = 0
n = 0
n + 1 → n
Write time tPW = 1 ms ±5%
Yes
n < 25?
No
No
Verify OK?
Yes
Write tOPW = 3n ms
→
Address + 1
Address
No
Last address?
Yes
Set read mode
VCC = 5.0V ±0.5V, VPP = VCC
No
Error
All addresses read?
Yes
END
Figure 11-5. High-Speed Programming Flowchart
233
Table 11-5. DC Characteristics
(when VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, VSS = 0V, Ta = 25˚C ±5˚C)
Measurement
Unit conditions
VCC + 0.3 V
Item
Symbol Min Typ Max
Input High voltage
EO7 – EO0,
EA14 – EA0,
OE, CE
VIH
2.4
—
Input Low voltage
EO7 – EO0,
EA14 – EA0,
OE, CE
VIL
–0.3
—
0.8
V
Output High voltage EO7 – EO0
Output Low voltage EO7 – EO0
VOH
VOL
|ILI|
2.4
—
—
—
—
—
—
0.45
2
V
V
IOH = –200µA
IOL = 1.6mA
Input leakage
current
EO7 – EO0,
EA14 – EA0,
OE, CE
µA Vin = 5.25V/
0.5V
VCC current
VPP current
ICC
IPP
—
—
—
—
40
40
mA
mA
Table 11-6. AC Characteristics
(when VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, Ta = 25˚C ±5˚C)
Measurement
Max Unit conditions
Item
Symbol Min
Typ
—
Address setup time
OE setup time
tAS
2
—
µs
µs
µs
µs
µs
ns
See figure 11-6*
tOES
tDS
2
—
—
Data setup time
Address hold time
Data hold time
2
—
—
tAH
tDH
tDF
0
—
—
2
—
—
Data output disable time
Vpp setup time
Program pulse width
—
2
—
130
—
tVPS
tPW
—
µs
ms
0.95
1.0
1.05
Note: * Input pulse level: 0.8V to 2.2V
Input rise/fall time ≤ 20ns
Timing reference levels: input—1.0V, 2.0V; output—0.8V, 2.0V
234
Table 11-6. AC Characteristics (cont.)
(when VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, Ta = 25˚C ±5˚C)
Measurement
Max Unit conditions
78.75 ms See figure 11-6*
Item
Symbol Min
Typ
OE pulse width for
overwrite-programming
VCC setup time
tOPW
2.85
—
tVCS
tOE
2
0
—
—
—
µs
ns
Data output delay time
500
Note: * Input pulse level: 0.8V to 2.2V
Input rise/fall time ≤ 20ns
Timing reference levels: input—1.0V, 2.0V; output—0.8V, 2.0V
Write
Verify
Address
Data
tAS
tAH
tDF
Input data
Output data
tDS
tDH
VPP
VPP
VCC
tVPS
VCC
tVCS
GND
CE
OE
tPW
tOES
tOE
tOPW
Figure 11-6. PROM Write/Verify Timing
235
11.3.2 Notes on Writing
(1) Write with the specified voltages and timing. The programming voltage (VPP) is 12.5V.
Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be
particularly careful about the PROM writer’s overshoot characteristics.
If the PROM writer is set to Hitachi HN27256 or HN27C256 specifications, or to Intel
specifications, VPP will be 12.5V.
(2) Before writing data, check that the socket adapter and chip are correctly mounted in the
PROM writer. Overcurrent damage to the chip can result if the index marks on the PROM writer,
socket adapter, and chip are not correctly aligned.
(3) Don’t touch the socket adapter or chip while writing. Touching either of these can cause
contact faults and write errors.
11.3.3 Reliability of Written Data
An effective way to assure the data holding characteristics of the programmed chips is to bake them
at 150˚C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 11-7 shows the recommended screening procedure.
236
Write and verify program
Bake with power off
+ 8 Hr *
– 0 Hr
150°± 10°C, 48 Hr
Read and check program
VCC = 4.5V and 5.5V
Install
Note: * Baking time should be measured from the point when the baking oven reaches 150°C.
Figure 11-7. Recommended Screening Procedure
If a series of write errors occurs while the same PROM writer is in use, stop programming and
check the PROM writer and socket adapter for defects, using a microcomputer chip with a
windowed package and on-chip EPROM.
Please inform Hitachi of any abnormal conditions noted during programming or in screening of
program data after high-temperature baking.
11.3.4 Erasing of Data
The windowed package enables data to be erased by illuminating the window with ultraviolet light.
Table 11-7 lists the erasing conditions.
Table 11-7. Erasing Conditions
Item
Value
Ultraviolet wavelength
Minimum illumination
253.7 nm
15W·s/cm2
The conditions in table 11-7 can be satisfied by placing a 12000µW/cm2 ultraviolet lamp 2 or 3
centimeters directly above the chip and leaving it on for about 20 minutes.
237
11.4 Handling of Windowed Packages
(1) Glass Erasing Window: Rubbing the glass erasing window of a windowed package with a
plastic material or touching it with an electrically charged object can create a static charge on the
window surface which may cause the chip to malfunction.
If the erasing window becomes charged, the charge can be neutralized by a short exposure to
ultraviolet light. This returns the chip to its normal condition, but it also reduces the charge stored
in the floating gates of the PROM, so it is recommended that the chip be reprogrammed afterward.
Accumulation of static charge on the window surface can be prevented by the following
precautions:
① When handling the package, ground yourself. Don’t wear gloves. Avoid other possible
sources of static charge.
② Avoid friction between the glass window and plastic or other materials that tend to accumulate
static charge.
③ Be careful when using cooling sprays, since they may have a slight ion content.
④ Cover the window with an ultraviolet-shield label, preferably a label including a conductive
material. Besides protecting the PROM contents from ultraviolet light, the label protects the
chip by distributing static charge uniformly.
(2) Handling after Programming: Fluorescent light and sunlight contain small amounts of
ultraviolet, so prolonged exposure to these types of light can cause programmed data to invert. In
addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip
malfunction. It is recommended that after programming the chip, you cover the erasing window
with a light-proof label (such as an ultraviolet-shield label).
238
Section 12. Power-Down State
12.1 Overview
The H8/329 Series has a power-down state that greatly reduces power consumption by stopping
some or all of the chip functions. The power-down state includes three modes:
(1) Sleep mode – a software-triggered mode in which the CPU halts but the rest of the chip
remains active
(2) Software standby mode – a software-triggered mode in which the entire chip is inactive
(3) Hardware standby mode – a hardware-triggered mode in which the entire chip is inactive
Table 12-1 lists the conditions for entering and leaving the power-down modes. It also indicates the
status of the CPU, on-chip supporting modules, etc. in each power-down mode.
Table 12-1. Power-Down State
Entering
procedure
Execute
CPU Sup.
I/O
Exiting
Mode
Sleep
mode
Clock CPU Reg’s. Mod. RAM ports methods
Run
Halt
Halt
Halt
Held
Held
Run
Held
Held
Held
Held
• Interrupt
• RES
SLEEP
instruction
Set SSBY bit
in SYSCR to
“1,” then
• STBY
• NMI
Soft-
Halt
and
ware
• IRQ0 – IRQ2
• STBY
• RES
standby
mode
initial-
ized
execute SLEEP
instruction
Set STBY
pin to Low
level
Hard-
ware
Halt
Halt
Not
Halt
and
Held
High
impe-
dance
state
• STBY High,
then RES
held
standby
mode
initialized
Low → High
Notes: 1. SYSCR: System control register
2. SSBY: Software standby bit
239
12.2 System Control Register: Power-Down Control Bits
Bits 7 to 4 of the system control register (SYSCR) concern the power-down state. Specifically,
they concern the software standby mode.
Table 12-2 lists the attributes of the system control register.
Table 12-2. System Control Register
Name
Abbreviation R/W
Initial value Address
System control register
SYSCR
R/W
H'0B
H'FFC4
Bit
7
SSBY
0
6
5
STS1
0
4
STS0
0
3
—
1
2
1
0
RAME
1
STS2
NMIEG
0
—
1
Initial value
Read/Write
0
R/W
R/W
R/W
R/W
—
R/W
—
R/W
Bit 7—Software Standby (SSBY): This bit enables or disables the transition to the software
standby mode.
On recovery from the software standby mode by an external interrupt, SSBY remains set to “1.”
To clear this bit, software must write a “0.”
Bit 7
SSBY
Description
0
1
The SLEEP instruction causes a transition to the sleep mode.
The SLEEP instruction causes a transition to the software
standby mode.
(Initial value)
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from the software standby mode by an external interrupt. During the
selected time, the clock oscillator runs but clock pulses are not supplied to the CPU or the on-chip
supporting modules.
240
Bit 6
Bit 5
Bit 4
STS2
STS1
STS0
Description
0
0
0
0
1
0
0
Settling time = 8192 states
Settling time = 16384 states
Settling time = 32768 states
Settling time = 65536 states
Settling time = 131072 states
(Initial value)
0
1
1
0
1
1
—
—
When the on-chip clock generator is used, the STS bits should be set to allow a settling time of at
least 10ms. Table 12-3 lists the settling times selected by these bits at several clock frequencies and
indicates the recommended settings.
When the chip is externally clocked, the STS bits can be set to any value. The minimum value
(STS2 = STS1 = STS0 = “0”) is recommended.
Table 12-3. Times Set by Standby Timer Select Bits (Unit: ms)
Settling
time
System clock frequency (MHz)
STS2 STS1 STS0
(states) 10
8
6
4
2
1
0.5
0
0
0
0
1
0
0
8192
0.8
1.0
2.0
4.1
8.2
16.4
1.3
2.7
5.5
10.9
21.8
2.0
4.1
8.2
16.4
32.8
4.1
8.2
16.4
32.8
65.5
8.2
16.4
32.8
65.5
131.1
0
1
16384 1.6
32768 3.3
65536 6.6
131072 13.1
16.4
32.8
65.5
1
0
1
1
—
—
131.1 262.1
Notes: 1. All times are in milliseconds.
2. Recommended values are printed in boldface.
241
12.3 Sleep Mode
The sleep mode provides an effective way to conserve power while the CPU is waiting for an
external interrupt or an interrupt from an on-chip supporting module.
12.3.1 Transition to Sleep Mode
When the SSBY bit in the system control register is cleared to “0,” execution of the SLEEP
instruction causes a transition from the program execution state to the sleep mode. After executing
the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged.
The on-chip supporting modules continue to operate normally.
12.3.2 Exit from Sleep Mode
The chip wakes up from the sleep mode when it receives an internal or external interrupt request, or
a Low input at the RES or STBY pin.
(1) Wake-Up by Interrupt: An interrupt releases the sleep mode and starts the CPU’s interrupt-
handling sequence.
If an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable
bit in the module’s control register, the interrupt cannot be requested, so it cannot wake the chip up.
Similarly, the CPU cannot be awoken by an interrupt other than NMI if the I (interrupt mask) bit in
the CCR (condition code register) is set when the SLEEP instruction is executed.
(2) Wake-Up by RES pin: When the RES pin goes Low, the chip exits from the sleep mode to
the reset state.
(3) Wake-Up by STBY pin: When the STBY pin goes Low, the chip exits from the sleep mode to
the hardware standby mode.
242
12.4 Software Standby Mode
In the software standby mode, the system clock stops and chip functions halt, including both CPU
functions and the functions of the on-chip supporting modules. Power consumption is reduced to
an extremely low level. The on-chip supporting modules and their registers are reset to their initial
states, but as long as a minimum necessary voltage supply is maintained (at least 2V), the contents
of the CPU registers and on-chip RAM remain unchanged.
12.4.1 Transition to Software Standby Mode
To enter the software standby mode, set the standby bit (SSBY) in the system control register
(SYSCR) to “1,” then execute the SLEEP instruction.
12.4.2 Exit from Software Standby Mode
The chip can be brought out of the software standby mode by an input at one of six pins: NMI,
IRQ0, IRQ1, IRQ2, RES, or STBY.
(1) Recovery by External Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 request signal is
received, the clock oscillator begins operating. After the waiting time set in the system control
register (bits STS2 to STS0), clock pulses are supplied to the CPU and on-chip supporting modules.
The CPU executes the interrupt-handling sequence for the requested interrupt, then returns to the
instruction after the SLEEP instruction. The SSBY bit is not cleared.
See section 12.2, “System Control Register: Power-Down Control Bits,” for information about the
STS bits.
(2) Recovery by RES Pin: When the RES pin goes Low, the clock oscillator starts and clock
pulses are supplied to the entire chip. Next, when the RES pin goes High, the CPU begins
executing the reset sequence. The SSBY bit is cleared to “0.”
The RES pin must be held Low long enough for the clock to stabilize.
(3) Recovery by STBY Pin: When the STBY pin goes Low, the chip exits from the software
standby mode to the hardware standby mode.
243
12.4.3 Sample Application of Software Standby Mode
In this example the chip enters the software standby mode when NMI goes Low and exits when
NMI goes High, as shown in figure 12-1.
The NMI edge bit (NMIEG) in the system control register is originally cleared to “0,” selecting the
falling edge. When NMI goes Low, the NMI interrupt handling routine sets NMIEG to “1,” sets
SSBY to “1” (selecting the rising edge), then executes the SLEEP instruction. The chip enters the
software standby mode. It recovers from the software standby mode on the next rising edge of
NMI.
Clock
generator
Ø
NMI
NMIEG
SSBY
Settling time
Software standby mode
(power-down state)
NMI interrupt handler
NMI interrupt handler
NMIEG = “1”
SSBY = “1”
SLEEP
Figure 12-1. Software Standby Mode (when) NMI Timing
12.4.4 Application Note
The I/O ports retain their current states in the software standby mode. If a port is in the High
output state, the current dissipation caused by the High output current is not reduced.
244
12.5 Hardware Standby Mode
12.5.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters the hardware standby mode whenever the STBY pin
goes Low.
The hardware standby mode reduces power consumption drastically by halting the CPU, stopping
all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance
state. The registers of the on-chip supporting modules are reset to their initial values. Only the on-
chip RAM is held unchanged, provided the minimum necessary voltage supply is maintained (at
least 2V).
Notes: 1. The RAME bit in the system control register should be cleared to “0” before the STBY
pin goes Low, to disable the on-chip RAM during the hardware standby mode.
2. Do not change the inputs at the mode pins (MD1, MD0) during hardware standby
mode. Be particularly careful not to let both mode pins go Low in hardware standby
mode, since that places the chip in PROM mode and increases current dissipation.
12.5.2 Recovery from Hardware Standby Mode
Recovery from the hardware standby mode requires inputs at both the STBY and RES pins.
When the STBY pin goes High, the clock oscillator begins running. The RES pin should be Low at
this time and should be held Low long enough for the clock to stabilize. When the RES pin
changes from Low to High, the reset sequence is executed and the chip returns to the program
execution state.
245
12.5.3 Timing Relationships
Figure 12-2 shows the timing relationships in the hardware standby mode.
In the sequence shown, first RES goes Low, then STBY goes Low, at which point the chip enters
the hardware standby mode. To recover, first STBY goes High, then after the clock settling time,
RES goes High.
Clock pulse
generator
RES
STBY
Clock settling
time
Restart
Figure 12-2. Hardware Standby Mode Timing
246
Section 13. Clock Pulse Generator
13.1 Overview
The H8/329 Series has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a
system (Ø) clock divider, and a prescaler. The prescaler generates clock signals for the on-chip
supporting modules.
13.1.1 Block Diagram
CPG
XTAL
Oscillator
circuit
Divider
÷ 2
Prescaler
EXTAL
ø
ø/2 to ø/4096
Figure 13-1. Block Diagram of Clock Pulse Generator
13.2 Oscillator Circuit
If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit
generates a clock signal for the system clock divider. Alternatively, an external clock signal can be
applied to the EXTAL pin.
(1) Connecting an External Crystal
① Circuit Configuration: An external crystal can be connected as in the example in figure 13-2.
An AT-cut parallel resonating crystal should be used.
247
CL1
CL2
EXTAL
XTAL
CL1 = CL2 = 10 to 22pF
Figure 13-2. Connection of Crystal Oscillator (Example)
② Crystal Oscillator: Figure 15-3 shows an equivalent circuit of the external crystal. The
external crystal should have the characteristics listed in table 13-1.
Table 13-1. External Crystal Parameters
Frequency (MHz)
Rs max (Ω)
C0 (pF)
2
4
8
12
40
16
30
20
20
500
120
60
7 pF max
CL
L
RS
XTAL
EXTAL
C0
AT-cut parallel resonating crystal
Figure 13-3. Equivalent Circuit of External Crystal
③ Note on Board Design: When an external crystal is connected, other signal lines should be
kept away from the crystal circuit to prevent induction from interfering with correct oscillation.
See figure 13-4. The crystal and its load capacitors should be placed as close as possible to the
XTAL and EXTAL pins.
248
Not allowed
Signal A
Signal B
H8/327
CL2
XTAL
EXTAL
CL1
Figure 13-4. Notes on Board Design around External Crystal
(2) Input of External Clock Signal
① Circuit Configuration: An external clock signal can be input as shown in the examples in
figure 13-5. In example (b), the external clock should be held high during standby.
EXTAL
External clock input
XTAL
Open
(a)
EXTAL
XTAL
External clock input
74HC04
(b)
Figure 13-5. External Clock Input (Example)
249
② External Clock Input
Frequency
Duty factor
Double the system clock (Ø) frequency
45% to 55%
13.3 System Clock Divider
The system clock divider divides the crystal oscillator or external clock frequency by 2 to create the
system clock (Ø).
250
Section 14. Electrical Specifications
14.1 Absolute Maximum Ratings
Table 14-1 lists the absolute maximum ratings.
Table 14-1. Absolute Maximum Ratings
Item
Symbol
VCC
VPP
Rating
Unit
V
Supply voltage
–0.3 to +7.0
Programming voltage
Input voltage Ports 1 – 6
Port 7
–0.3 to +13.5
V
Vin
–0.3 to VCC + 0.3
–0.3 to AVCC + 0.3
–0.3 to +7.0
V
Vin
V
Analog supply voltage
Analog input voltage
Operating temperature
AVCC
VAN
Topr
V
–0.3 to AVCC + 0.3
Regular specifications: –20 to +75
V
˚C
Wide-range specifications: – 40 to +85 ˚C
–55 to +125 ˚C
Storage temperature
Tstg
Note: Exceeding the absolute maximum ratings shown in table 14-1 can permanently destroy
the chip.
14.2 Electrical Characteristics
14.2.1 DC Characteristics
Table 14-2 lists the DC characteristics of the 5V versions of the H8/329 Series. Table 14-3 lists the
DC characteristics of the 3V versions. Table 14-4 gives the allowable current output values of the
5V versions. Table 14-5 gives the allowable current output values of the 3V versions.
251
Table 14-2. DC Characteristics (5V Versions)
Conditions: VCC = 5.0V ±10%, AVCC = 5.0V ±10%*, VSS = AVSS = 0V,
Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications)
Measurement
Item
Symbol Min
Typ Max
Unit conditions
-
Schmitt trigger
input voltage
(1)
P67 – P62, P60, VT
1.0
–
–
–
V
+
P47, P44 – P40 VT
–
–
VCC × 0.7 V
-
+
VT –VT 0.4
–
V
Input High voltage RES, STBY, NMI VIH
VCC – 0.7 –
VCC + 0.3 V
(2)
MD1, MD0
EXTAL
P77 – P70
2.0
2.0
–
–
AVCC + 0.3 V
VCC + 0.3 V
Input High voltage Input pins
other than (1)
VIH
and (2) above
Input Low voltage RES, STBY
VIL
VIL
–0.3
–0.3
–
–
0.5
0.8
V
V
(3)
Input Low voltage Input pins
other than (1)
and (3) above
MD1, MD0
Output High
voltage
All output pins VOH
VCC – 0.5 –
–
V
V
V
V
IOH = –200µA
IOH = –1.0mA
IOL = 1.6mA
IOL = 10.0mA
3.5
–
–
–
–
–
–
–
Output Low
voltage
All output pins VOL
Ports 1 and 2
0.4
1.0
10.0
1.0
–
Input leakage
current
RES
|Iin|
–
µA Vin = 0.5V to
µA VCC – 0.5V
STBY, NMI,
MD1, MD0
P77 – P70
–
–
–
–
–
1.0
1.0
250
µA Vin = 0.5V to
AVCC – 0.5V
Leakage current
Ports 1, 2, 3
|ITSI|
–
µA Vin = 0.5V to
VCC – 0.5V
in 3-state (off state) 4, 5, 6
Input pull-up
MOS current
Ports 1, 2, 3
–Ip
30
µA Vin = 0V
Note: * Connect AVCC to the power supply (VCC) even when the A/D converter is not used.
252
Table 14-2. DC Characteristics (5V Versions) (cont.)
Conditions: VCC = 5.0V ±10%, AVCC = 5.0V ±10%*1, VSS = AVSS = 0V, Ta = –20 to 75˚C (regular
specifications), Ta = –40 to 85˚C (wide-range specifications)
Measurement
Item
Symbol Min
Typ
Max
60
Unit conditions
Input capacitance RES
NMI
Cin
–
–
–
–
–
–
pF
pF
pF
Vin = 0V
f = 1MHz
Ta = 25˚C
30
All input pins
15
except RES
and NMI
Normal
Current
dissipation*2
ICC
–
–
–
–
–
–
–
–
12
16
20
8
25
30
40
15
20
25
5.0
1.5
mA
mA
mA
mA
mA
mA
µA
f = 6MHz
f = 8MHz
f = 10MHz
f = 6MHz
f = 8MHz
f = 10MHz
operation
Sleep mode
10
12
0.01
0.6
Standby modes*3
During A/D
conversion
Waiting
Analog supply
current
AICC
mA
–
0.01
–
5.0
–
µA
V
RAM standby
voltage
VRAM
2.0
Notes: *1 Connect AVCC to the power supply (+5V) even when the A/D converter is not used.
*2 Current dissipation values assume that VIH min = VCC – 0.5V, VIL max = 0.5V, all output
pins are in the no-load state, and all input pull-up transistors are off.
*3 For these values it is assumed that VRAM ≤ VCC < 4.5V and VIH min = VCC × 0.9,
VIL max = 0.3V.
253
Table 14-3. DC Characteristics (3V Versions)
Conditions: VCC = 3.0V ±10%, AVCC = 5.0V ±10%*1, VSS = AVSS = 0V, Ta = –20 to 75˚C
Measurement
Unit conditions
Item
Symbol Min
Typ
Max
–
Schmitt
P67 – P62, P60, VT
VCC × 0.15 –
–
V
+
+
trigger input P47, P44 – P40 VT
–
–
–
VCC × 0.7 V
voltage*2
VT –VT 0.2
–
V
–
(1)
Input High RES, STBY
VIH
VCC × 0.9
–
VCC + 0.3 V
voltage*2
MD1, MD0
(2)
EXTAL, NMI
P77 – P70
VCC × 0.7
VCC × 0.7
–
–
AVCC + 0.3 V
VCC + 0.3 V
Input pins
other than (1)
and (2) above
Input Low RES, STBY
VIL
–0.3
–0.3
–
–
VCC × 0.1 V
VCC × 0.15 V
voltage*2
MD1, MD0
(3)
Input pins
other than (1)
and (3) above
Output High All output pins VOH
voltage
VCC – 0.4
–
–
–
–
–
–
–
V
V
V
V
IOH = –200µA
IOH = –1mA
IOL = 0.8mA
IOL = 1.6mA
VCC – 0.9
–
Output Low All output pins VOL
–
–
–
–
0.4
0.4
10.0
1.0
voltage
Input
Ports 1 and 2
RES
|Iin|
µA Vin = 0.5 to
µA VCC – 0.5V
leakage
current
STBY, NMI,
MD1, MD0
P77 – P70
–
–
–
–
1.0
1.0
µA Vin = 0.5 to
AVCC – 0.5V
Leakage
current in
3-state
Ports 1, 2, 3
4, 5, 6
|ITSI|
–Ip
µA Vin = 0.5 to
VCC – 0.5V
(off state)
Input
Ports 1, 2, 3
3
–
120
µA Vin = 0V
pull-up MOS
current
Notes: *1 Connect AVCC to the power supply (VCC) even when the A/D converter is not used.
*2 In the range 3.3V < VCC < 4.5V, for the input levels of VIH and VT, apply the higher of
–
the values given for the 5V and 3V versions. For VIL and VT , apply the lower of the
values given for the 5V and 3V versions.
254
Table 14.3. DC Characteristics (3V Versions) (cont.)
Conditions: VCC = 3.0V ±10%, AVCC = 5.0V ±10%*1, VSS = AVSS = 0V, Ta = –20 to 70˚C
Measurement
Max Unit conditions
Item
Symbol
Min
Typ
–
Input
RES
Cin
–
–
–
60
30
15
pF
pF
pF
Vin = 0V
f = 1MHz
Ta = 25˚C
capacitance
NMI
–
All input pins
except RES
and NMI
Normal
–
Current
dissipation*2
ICC
–
–
–
–
–
–
4
–
mA
mA
mA
mA
µA
f = 3MHz
f = 5MHz
f = 3MHz
f = 5MHz
operation
Sleep mode
6
12
–
3
4
8
Standby modes*3
During A/D
conversion
Waiting
0.01
0.6
5.0
1.5
Analog
supply
current
AICC
mA
–
0.01
–
5.0
–
µA
V
RAM backup voltage
(in standby modes)
VRAM
2.0
Notes: *1 Connect AVCC to the power supply (+3V) even when the A/D converter is not used.
*2 Current dissipation values assume that VIH min. = VCC – 0.5V, VIL max. = 0.5V, all
output pins are in the no-load state, and all input pull-up transistors are off.
*3 For these values it is assumed that VRAM ≤ VCC < 2.7V and VIH min = VCC × 0.9,
VIL max = 0.3V.
255
Table 14-4. Allowable Output Current Values (5V Versions)
Conditions: VCC = 5.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ta = –20 to 75˚C (regular
specifications), Ta = –40 to 85˚C (wide-range specifications)
Item
Symbol
Min
Typ
–
Max
10
Unit
mA
mA
mA
mA
mA
Allowable output Low
current (per pin)
Allowable output Low
current (total)
Ports 1 and 2
IOL
–
–
–
–
–
Other output pins
Ports 1 and 2, total
Total of all output
–
2.0
80
ΣIOL
–IOH
–
–
120
2.0
Allowable output High All output pins
current (per pin)
–
Allowable output High Total of all output
Σ–IOH
–
–
40
mA
current (total)
Table 14-5. Allowable Output Current Values (3V Versions)
Conditions: VCC = 3.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ta = –20 to 75˚C
pins
Item
Symbol
Min
Typ
–
Max
2
Unit
mA
mA
mA
mA
mA
Allowable output Low
current (per pin)
Allowable output Low
current (total)
Ports 1 and 2
IOL
–
–
–
–
–
Other output pins
Ports 1 and 2, total
All output pins
–
1
ΣIOL
–IOH
–
40
60
2
–
Allowable output High All output pins
current (per pin)
–
Allowable output High Total of all output
Σ–IOH
–
–
30
mA
current (total)
pins
Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current
values in tables 14-4 and 14-5. In particular, when driving a Darlington transistor pair or
LED directly, be sure to insert a current-limiting resistor in the output path. See figures 14-1
and 14-2.
256
H8/329
Series
2 kΩ
Port
Darlington
pair
Figure 14-1. Example of Circuit for Driving a Darlington Pair (5V Versions)
H8/329
Series
Vcc
600 Ω
Port 1 or 2
LED
Figure 14-2. Example of Circuit for Driving an LED (5V Versions)
14.2.2 AC Characteristics
The AC characteristics of the H8/329 Series are listed in three tables. Bus timing parameters are
given in table 14-6, control signal timing parameters in table 14-7, and timing parameters of the on-
chip supporting modules in table 14-8.
257
Table 14-6. Bus Timing
Condition A: VCC = 5.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C (regular specifications),
Ta = –40 to 85˚C (wide-range specifications)
Condition B: VCC = 3.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C
Condition B
5MHz
Condition A
8MHz
6MHz
10MHz
Measurement
Item
Symbol Min Max Min Max Min Max Min Max Unit conditions
Clock cycle time
tcyc
200 2000 166.7 2000 125 2000 100 2000 ns
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-4
Fig. 14-5
Fig. 14-5
Clock pulse width Low
Clock pulse width High
Clock rise time
tCL
70
70
–
–
65
65
–
–
45
45
–
–
35
35
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCH
–
–
–
–
tCr
25
25
90
–
15
15
70
–
15
15
60
–
15
15
50
–
Clock fall time
tCf
–
–
–
–
Address delay time
Address hold time
Address strobe delay time
Write strobe delay time
Strobe delay time
tAD
–
–
–
–
tAH
30
–
30
–
25
–
20
–
tASD
tWSD
tSD
80
80
90
–
70
70
70
–
60
60
60
–
40
50
50
–
–
–
–
–
–
–
–
–
Write strobe pulse width*
Address setup time 1*
Address setup time 2*
Read data setup time
Read data hold time
Read data access time*
Write data delay time
Write data setup time
Write data hold time
Wait setup time
tWSW
tAS1
tAS2
tRDS
tRDH
tACC
tWDD
tWDS
tWDH
tWTS
tWTH
200
25
105
90
0
200
25
105
70
0
150
20
80
50
0
120
15
65
35
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
300
125
–
–
270
85
–
–
210
75
–
–
170 ns
–
–
–
–
75
–
ns
ns
ns
ns
ns
10
30
60
20
20
30
40
10
10
25
40
10
5
–
–
–
20
40
10
–
–
–
–
–
Wait hold time
–
–
–
–
Note: * Values at maximum operating frequency
258
Table 14-7. Control Signal Timing
Condition A: VCC = 5.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C (regular specifications),
Ta = –40 to 85˚C (wide-range specifications)
Condition B: VCC = 3.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C
Condition B
5MHz
Condition A
8MHz
6MHz
10MHz
Measurement
Item
Symbol Min Max Min Max Min Max Min Max Unit conditions
RES setup time
tRESS
tRESW
tNMIS
300
10
–
–
–
200
10
–
–
–
200
10
–
–
–
200
10
–
–
–
ns
Fig. 14-6
RES pulse width
tcyc Fig. 14-6
NMI setup time
300
150
150
150
ns
ns
ns
Fig. 14-7
Fig. 14-7
Fig. 14-7
(NMI, IRQ0 to IRQ2)
NMI hold time
tNMIH
tNMIW
10
–
–
10
–
–
10
–
–
10
–
–
(NMI, IRQ0 to IRQ2)
Interrupt pulse width
for recovery from soft-
ware standby mode
(NMI, IRQ0 to IRQ2)
Crystal oscillator settling
time (reset)
300
200
200
200
tOSC1
tOSC2
20
10
–
–
20
10
–
–
20
10
–
–
20
10
–
–
ms Fig. 14-8
ms Fig. 14-9
Crystal oscillator settling
time (software standby)
259
Table 14-8. Timing Conditions of On-Chip Supporting Modules
Condition A: VCC = 5.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C (regular specifications),
Ta = –40 to 85˚C (wide-range specifications)
Condition B: VCC = 3.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C
Condition B
5MHz
Condition A
8MHz
6MHz
10MHz
Measurement
Item
Symbol Min Max Min Max Min Max Min Max Unit conditions
FRT Timer output delay time tFTOD
Timer input setup time tFTIS
–
150
–
–
100
–
–
100
–
–
100 ns
Fig. 14-10
Fig. 14-10
Fig. 14-11
80
80
50
50
50
50
50
50
–
–
ns
ns
Timer clock input
setup time
tFTCS
–
–
–
Timer clock pulse width tFTCWH 1.5
–
1.5
–
1.5
–
1.5
–
tcyc Fig. 14-11
tFTCWL
TMR Timer output delay time tTMOD
–
150
–
–
100
–
–
100
–
–
100 ns
Fig. 14-12
Fig. 14-14
Timer reset input
setup time
tTMRS
80
50
50
50
–
–
–
–
ns
Timer clock input
setup time
tTMCS
80
–
–
–
50
–
–
–
50
–
–
–
50
ns
Fig. 14-13
Timer clock pulse width tTMCWH 1.5
(single edge)
1.5
2.5
1.5
2.5
1.5
2.5
tcyc Fig. 14-13
tcyc Fig. 14-13
Timer clock pulse width tTMCWL 2.5
(both edges)
SCI Input clock (Async) tscyc
4
6
–
–
4
6
–
–
4
6
–
–
4
6
–
–
–
tcyc Fig. 14-15
tcyc Fig. 14-15
cycle
(Sync)
tscyc
–
–
–
Transmit data delay
time (Sync)
tTXD
200
100
100
100 ns
Fig. 14-15
Fig. 14-15
Fig. 14-15
Receive data setup time tRXS
(Sync)
150
150
–
–
100
100
–
–
100
100
–
–
100
100
–
–
ns
ns
Receive data hold time tRXH
(Sync)
Input clock pulse width tSCKW
Ports Output data delay time tPWD
0.4 0.6
0.4
–
0.6 0.4
0.6
100
–
0.4
–
0.6 tscyc Fig. 14-16
–
150
–
100
–
–
100 ns
Fig. 14-17
Fig. 14-17
Fig. 14-17
Input data setup time
Input data hold time
tPRS
tPRH
80
80
50
50
50
50
50
50
–
–
ns
ns
–
–
–
260
• Measurement Conditions for AC Characteristics
5 V
RL
LSI
output pin
C = 90 pF: Ports 1 – 4, 6
30 pF: Port 5
RL = 2.4 kΩ
RH
C
RH = 12 kΩ
Input/output timing reference levels
Low: 0.8 V
High: 2.0 V
Figure 14-3. Output Load Circuit
14.2.3 A/D Converter Characteristics
Table 14-9 lists the characteristics of the on-chip A/D converter.
Table 14-9. A/D Converter Characteristics
Condition A: VCC = AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ø = 0.5MHz to maximum operating
frequency, Ta = –20 to 75˚C (regular specifications),
Ta = –40 to 85˚C (wide-range specifications)
Condition B: VCC = 3.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ø = 0.5MHz to maximum
operating frequency, Ta = –20 to 75˚C
Condition B
5MHz
Condition A
8MHz
6MHz
10MHz
Item
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
Resolution
8
8
8
8
8
8
8
8
8
8
8
8
Bits
Conversion time (single mode)*
Analog input capacitance
Allowable signal
source impedance
Nonlinearity error
Offset error
—
—
—
—
—
—
24.4 —
—
—
—
20.4 —
—
—
—
15.25 —
—
—
—
12.2 µs
20
10
—
—
20
10
—
—
20
10
—
—
20
10
pF
kΩ
—
—
—
—
—
—
—
—
—
—
±1
±1
±1
—
—
—
—
—
—
—
—
±1
±1
±1
—
—
—
—
—
—
—
—
±1
±1
±1
—
—
—
—
—
—
—
—
±1
±1
±1
LSB
LSB
LSB
Full-scale error
Quantizing error
Absolute accuracy
±0.5 —
±1.5 —
±0.5 —
±1.5 —
±0.5 —
±1.5 —
±0.5 LSB
±1.5 LSB
Note: * At maximum operating frequency.
261
14.3 MCU Operational Timing
This section provides the following timing charts:
14.3.1 Bus Timing
Figures 14-4 to 14-5
14.3.2 Control Signal Timing
14.3.3 16-Bit Free-Running Timer Timing
14.3.4 8-Bit Timer Timing
14.3.5 SCI Timing
Figures 14-6 to 14-9
Figures 14-10 to 14-11
Figures 14-12 to 14-14
Figures 14-15 to 14-16
Figure 14-17
14.3.6 I/O Port Timing
14.3.1 Bus Timing
(1) Basic Bus Cycle (without Wait States) in Expanded Modes
T
1
T
2
T
3
tcyc
tCH
tCL
Ø
tCf
tAD
tCr
A15 to A0
tASD
tSD
tAH
tASI
AS, RD
tRDH
tRDS
tACC
D7 to D0
(Read)
tWSD
tSD
tAS2
tWSW
tAH
WR
tWDH
tWDD
tWDS
D7 to D0
(Write)
Figure 14-4. Basic Bus Cycle (without Wait States) in Expanded Modes
262
(2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes
T
T
T
T
3
2
1
W
Ø
A15 to A0
AS, RD
D7 to D0
(Read)
WR
D7 to D0
(Write)
tWTS tWTH
tWTS tWTH
WAIT
Figure 14-5. Basic Bus Cycle (with 1 Wait State) in Expanded Modes (Modes 1 and 2)
14.3.2 Control Signal Timing
(1) Reset Input Timing
Ø
tRESS
tRESS
RES
tRESW
Figure 14-6. Reset Input Timing
263
(2) Interrupt Input Timing
Ø
tNMIS tNMIH
NMI
IRQE (Edge)
tNMIS
IRQL (Level)
tNMIW
NMI
IRQi
Note: i = 0 to 2; IRQE: IRQi when edge-sensed; IRQL: IRQi when level-sensed
Figure 14-7. Interrupt Input Timing
264
Ø
VCC
STBY
RES
tOSC1
tOSC1
Figure 14-8. Clock Setting Timing
(4) Clock Settling Timing for Recovery from Software Standby Mode
Ø
NMI
IRQi
tOSC2
(i = 0, 1, 2)
Figure 14-9. Clock Settling Timing for Recovery from Software Standby Mode
14.3.3 16-Bit Free-Running Timer Timing
(1) Free-Running Timer Input/Output Timing
Ø
Free-running
Compare-match
timer counter
tFTOD
FTOA , FTOB
tFTIS
FTIA, FTIB,
FTIC, FTID
Figure 14-10. Free-Running Timer Input/Output Timing
266
(2) External Clock Input Timing for Free-Running Timer
Ø
t
FTCS
FTCI
t
FTCWL
tFTCWH
Figure 14-11. External Clock Input Timing for Free-Running Timer
14.3.4 8-Bit Timer Timing
(1) 8-Bit Timer Output Timing
Ø
Timer
Compare-match
counter
tTMOD
TMO0,
TMO1
Figure 14-12. 8-Bit Timer Output Timing
(2) 8-Bit Timer Clock Input Timing
Ø
tTMCS
tTMCS
TMCI0,
TMCI1
tTMCWL
tTMCWH
Figure 14-13. 8-Bit Timer Clock Input Timing
267
(3) 8-Bit Timer Reset Input Timing
Ø
tTMRS
TMRI0,
TMRI1
Timer
counter
N
H'00
Figure 14-14. 8-Bit Timer Reset Input Timing
14.3.5 Serial Communication Interface Timing
(1) SCI Input/Output Timing
tScyc
Serial clock
(SCK)
tTXD
Transmit
data
(TxD)
tRXS tRXH
Receive
data
(RxD)
Figure 14-15. SCI Input/Output Timing (Synchronous Mode)
268
(2) SCI Input Clock Timing
tSCKW
SCK
tScyc
Figure 14-16. SCI Input Clock Timing
14.3.6 I/O Port Timing
T1
T2
T3
Ø
tPRS
tPRH
Port 1
to (Input)
Port 7
tPWD
*
Port 1
to (Output)
Port 6
Note: * Except P46.
Figure 14-17. I/O Port Input/Output Timing
269
Appendix A. CPU Instruction Set
A.1 Instruction Set List
Operation Notation
Rd8/16
General register (destination) (8 or 16 bits)
Rs8/16
General register (source) (8 or 16 bits)
General register (8 or 16 bits)
Condition code register
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Program counter
Rn8/16
CCR
N
Z
V
C
PC
SP
Stack pointer
#xx:3/8/16
Immediate data (3, 8, or 16 bits)
Displacement (8 or 16 bits)
Absolute address (8 or 16 bits)
Addition
d:8/16
@aa:8/16
+
–
×
÷
Subtraction
Multiplication
Division
AND logical
OR logical
Exclusive OR logical
Move
→
—
Not
Condition Code Notation
↕
*
Modified according to the instruction result
Undetermined (unpredictable)
Always cleared to “0”
0
—
Not affected by the instruction result
271
A.2 Operation Code Map
Table A-2 is a map of the operation codes contained in the first byte of the instruction code (bits 15
to 8 of the first instruction word).
Some pairs of instructions have identical first bytes. These instructions are differentiated by the
first bit of the second byte (bit 7 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is “0.”
Instruction when first bit of byte 2 (bit 7 of first instruction word) is “1.”
278
Table A-2. Operation Code Map
LO
0
1
2
3
4
5
6
8
9
A
B
C
E
7
D
F
HI
ADDS
0
NOP
SLEEP
STC
LDC
ORC
OR
XORC
XOR
ANDC
AND
ADD
SUB
INC
DEC
MOV
CMP
ADDX
SUBX
DAA
DAS
LDC
SHLL
SHLR
SHAR
ROTXL
ROTL
ROTXR
ROTR
NOT
SUBS
1
2
3
4
5
6
SHAL
NEG
MOV
BRA*2
MULXU DIVXU
BRN *2
BHI
BLS
BCC*2
RTS
BCS*2
BSR
BVS
BMI
BNE
RTE
BEQ
BVC
BPL
JMP
BGE
BLT
BGT
JSR
BLE
BST
BLD
MOV *1
BIST
BNOT
BTST
BSET
BCLR
BOR
BXOR
BIXOR
BAND
BIAND
EEPMOV
Bit manipulation instruction
7
MOV
BIOR
BILD
ADD
8
ADDX
9
CMP
SUBX
OR
A
B
C
D
E
F
XOR
AND
MOV
Notes: *1 The MOVFPE and MOVTPE instructions are identical to MOV instructions in the first byte and first bit of the second byte (bits 15 to 7 of the instruction word).
The PUSH and POP instructions are identical in machine language to MOV instructions.
*2 The BT, BF, BHS, and BLO instructions are identical in machine language to BRA, BRN, BCC, and BCS, respectively.
A.3 Number of States Required for Execution
The tables below can be used to calculate the number of states required for instruction execution.
Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates
the number of cycles of each type occurring in each instruction. The total number of states required
for execution of an instruction can be calculated from these two tables as follows:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state
inserted in external memory access.
1. BSET #0, @FFC7
From table A-4: I = L = 2, J = K = M = N= 0
From table A-3: SI = 8, SL = 3
Number of states required for execution: 2 × 8 + 2 × 3 =22
2. JSR @@30
From table A-4: I = 2, J = K = 1, L = M = N = 0
From table A-3: SI = SJ = SK = 8
Number of states required for execution: 2 × 8 + 1 × 8 + 1 × 8 = 32
Table A-3. Number of States Taken by Each Cycle in Instruction Execution
Execution status
(instruction cycle)
Instruction fetch
Access location
On-chip memory On-chip reg. field External memory
SI
Branch address read SJ
6
6 + 2m
Stack operation
Byte data access
Word data access
Internal operation
SK
SL
SM
SN
2
3
6
1
3 + m
6 + 2m
Note: m: Number of wait states inserted in access to external device.
280
Table A-4. Number of Cycles in Each Instruction
Instruction Branch
Stack
Byte data Word data Internal
fetch
I
addr. read operation access
access
M
operation
N
Instruction Mnemonic
J
K
L
ADD
ADD.B #xx:8, Rd
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
2
2
ADD.B Rs, Rd
ADD.W Rs, Rd
ADDS.W #1/2, Rd
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
AND.B #xx:8, Rd
AND.B Rs, Rd
ANDC#xx:8, CCR
BAND#xx:3, Rd
BAND#xx:3, @Rd
BAND#xx:3, @aa:8
BRAd:8 (BT d:8)
BRNd:8 (BF d:8)
BHId:8
ADDS
ADDX
AND
ANDC
BAND
1
1
Bcc
BLSd:8
BCCd:8 (BHS d:8)
BCSd:8 (BLO d:8)
BNEd:8
BEQd:8
BVCd:8
BVSd:8
BPLd:8
BMId:8
BGEd:8
BLTd:8
BGTd:8
BLEd:8
BCLR
BCLR#xx:3, Rd
BCLR#xx:3, @Rd
BCLR#xx:3, @aa:8
BCLRRn, Rd
BCLRRn, @Rd
BCLRRn, @aa:8
2
2
2
2
Note: All values left blank are zero.
281
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch
Stack
Byte data Word data Internal
fetch
I
addr. read operation access
access
M
operation
N
Instruction Mnemonic
BIAND#xx:3, Rd
J
K
L
BIAND
BILD
BIOR
BIST
BIXOR
BLD
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
BIAND#xx:3, @Rd
BIAND#xx:3, @aa:8
BILD#xx:3, Rd
1
1
BILD#xx:3, @Rd
BILD#xx:3, @aa:8
BIOR#xx:3 Rd
1
1
BIOR#xx:3 @Rd
BIOR#xx:3 @aa:8
BIST#xx:3, Rd
1
1
BIST#xx:3, @Rd
BIST#xx:3, @aa:8
BIXOR#xx:3, Rd
BIXOR#xx:3, @Rd
BIXOR#xx:3, @aa:8
BLD #xx:3, Rd
2
2
1
1
BLD #xx:3, @Rd
BLD #xx:3, @aa:8
BNOT #xx:3, Rd
BNOT #xx:3, @Rd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
1
1
BNOT
2
2
BNOT Rn, @Rd
BNOT Rn, @aa:8
BOR #xx:3, Rd
2
2
BOR
BOR #xx:3, @Rd
BOR #xx:3, @aa:8
BSET #xx:3, Rd
BSET #xx:3, @Rd
BSET #xx:3, @aa:8
BSET Rn, Rd
1
1
BSET
2
2
BSET Rn, @Rd
BSET Rn, @aa:8
2
2
Note: All values left blank are zero.
282
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch
Stack
Byte data Word data Internal
fetch
I
addr. read operation access
access
M
operation
N
Instruction Mnemonic
J
K
L
BSR
BST
BSR d:8
2
1
2
2
1
2
2
1
2
2
1
2
2
1
1
1
1
1
1
1
2
1
2
2
2
2
2
2
1
1
1
1
1
2
1
BST #xx:3, Rd
BST #xx:3, @Rd
BST #xx:3, @aa:8
BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
2
2
BTST
1
1
BTST Rn, @Rd
BTST Rn, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W Rs, Rd
DAA.B Rd
1
1
BXOR
CMP
1
1
DAA
DAS
DAS.B Rd
DEC
DEC.B Rd
DIVXU
DIVXU.B Rs, Rd
12
1
EEPMOV EEPMOV
2n+2*
INC
JMP
INC.B Rd
JMP @Rn
JMP @aa:16
2
2
JMP @@aa:8
JSR @Rn
1
1
JSR
1
1
1
JSR @aa:16
2
JSR @@aa:8
LDC #xx:8, CCR
LDC Rs, CCR
MOV.B#xx:8, Rd
MOV.BRs, Rd
MOV.B@Rs, Rd
MOV.B@(d:16,Rs), Rd
LDC
MOV
1
1
Notes: All values left blank are zero.
* n: Initial value in R4L. Source and destination are accessed n + 1 times each.
283
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch
Stack
Byte data Word data Internal
fetch
I
addr. read operation access
access
M
operation
N
Instruction Mnemonic
MOV MOV.B @Rs+, Rd
J
K
L
1
1
1
1
1
1
1
1
1
1
2
1
2
1
1
2
2
1
1
2
1
2
1
2
1
2
2
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @–Rd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
2
MOV.W @Rs, Rd
1
1
1
1
1
1
1
1
MOV.W @(d:16, Rs), Rd
MOV.W @Rs+, Rd
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
2
MOV.W Rs, @(d:16, Rd)
MOV.W Rs, @–Rd
MOV.W Rs, @aa:16
2
MOVFPE MOVFPE @aa:16, Rd
MOVTPE MOVTPE.Rs, @aa:16
Not supported
MULXU
NEG
NOP
NOT
OR
MULXU.Rs, Rd
NEG.B Rd
NOP
1
1
1
1
1
1
1
1
1
1
1
1
1
12
NOT.B Rd
OR.B #xx:8, Rd
OR.B Rs, Rd
ORC #xx:8, CCR
POP Rd
ORC
POP
1
1
2
2
PUSH
ROTL
ROTR
ROTXL
ROTXR
PUSH Rd
ROTL.B Rd
ROTR.B Rd
ROTXL.B Rd
ROTXR.B Rd
Note: All values left blank are zero.
284
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch
Stack
Byte data Word data Internal
fetch
I
addr. read operation access
access
M
operation
N
Instruction Mnemonic
J
K
2
L
RTE
RTE
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
RTS
RTS
1
SHAL
SHAR
SHLL
SHLR
SLEEP
STC
SHAL.B Rd
SHAR.B Rd
SHLL.B Rd
SHLR.B Rd
SLEEP
STC CCR, Rd
SUB.B Rs, Rd
SUB.W Rs, Rd
SUBS.W#1/2, Rd
SUBX.B#xx:8, Rd
SUBX.BRs, Rd
XOR.B#xx:8, Rd
XOR.B Rs, Rd
XORC#xx:8, CCR
SUB
SUBS
SUBX
XOR
XORC
Note: All values left blank are zero.
285
Appendix B. Register Field
B.1 Register Addresses and Bit Names
Addr.
(last Register
Bit names
Bit 4 Bit 3
byte) name Bit 7
Bit 6
Bit 5
Bit 2 Bit 1
Bit 0
Module
External
addresses
(in
H'80
H'81
H'82
H'83
H'84
H'85
H'86
H'87
expanded
modes)
H'88
H'89
H'8A
H'8B
H'8C
H'8D
H'8E
H'8F
H'90
H'91
H'92
H'93
H'94
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TIER
TCSR
FRC (H)
FRC (L)
ICIAE
ICFA
ICIBE
ICFB
ICICE
ICFC
ICIDE
ICFD
OCIAE OCIBE OVIE
OCFA OCFB OVF
—
FRT
CCLRA
OCRA (H)
OCRB (H)
OCRA (L)
OCRB (L)
TCR
H'95
H'96
H'97
H'98
H'99
H'9A
H'9B
H'9C
H'9D
H'9E
H'9F
IEDGA IEDGB IEDGC IEDGD
OCRS
BUFEA BUFEB CKS1
CKS0
TOCR
—
—
—
OEA OEB OLVLA OLVLB
ICRA (H)
ICRA (L)
ICRB (H)
ICRB (L)
ICRC (H)
ICRC (L)
ICRD (H)
ICRD (L)
(Continued on next page)
Notes: FRT: Free-Running Timer
286
(Continued from previous page)
Addr.
(last Register
Bit names
Bit 4 Bit 3
byte) name Bit 7
Bit 6
—
Bit 5
—
Bit 2 Bit 1
Bit 0
—
Module
H'A0
H'A1
H'A2
H'A3
H'A4
H'A5
H'A6
H'A7
H'A8
H'A9
H'AA
H'AB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H'AC P1PCR P17PCR P16PCR P15PCR P14PCR
H'AD P2PCR P27PCR P26PCR P25PCR P24PCR
H'AE P3PCR P37PCR P36PCR P35PCR P34PCR
P13PCR P12PCR P11PCR P10PCR
P23PCR P22PCR P21PCR P20PCR
P33PCR P32PCR P31PCR P30PCR
Port 1
Port 2
Port 3
—
H'AF
H'B0
H'B1
H'B2
H'B3
H'B4
H'B5
H'B6
H'B7
H'B8
H'B9
—
—
—
—
—
—
—
—
—
P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDRP11DDR P10DDR
P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDRP21DDR P20DDR
Port 1
Port 2
Port 1
Port 2
Port 3
Port 4
Port 3
Port 4
Port 5
Port 6
Port 5
Port 6
—
P1DR
P2DR
P17
P27
P16
P26
P15
P25
P14
P24
P13
P23
P12
P22
P11
P21
P10
P20
P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDRP31DDR P30DDR
P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDRP41DDR P40DDR
P3DR
P4DR
P5DDR
P37
P47
—
P36
P46
—
P35
P45
—
P34
P44
—
P33
P43
—
P32
P42
P31
P41
P30
P40
P52DDRP51DDR P50DDR
P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDRP61DDR P60DDR
H'BA P5DR
H'BB P6DR
—
—
—
—
—
P52
P62
—
P51
P61
—
P50
P60
—
P67
—
P66
—
P65
—
P64
—
P63
—
H'BC
H'BD
H'BE
H'BF
—
—
—
—
—
—
—
—
—
—
—
P7DR
—
P77
—
P76
—
P75
—
P74
—
P73
—
P72
—
P71
—
P70
—
Port 7
—
(Continued on next page)
287
(Continued from preceding page)
Addr.
(last Register
Bit names
Bit 4 Bit 3
byte) name Bit 7
Bit 6
—
Bit 5
—
Bit 2 Bit 1
Bit 0
—
Module
H'C0
H'C1
H'C2
H'C3
H'C4
H'C5
H'C6
H'C7
H'C8
H'C9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STCR
—
—
—
MPE
ICKS1 ICKS0
SYSCR SSBY
STS2
—
STS1
—
STS0
—
NMIEG —
— MDS1
RAME
MDS0
MDCR
ISCR
IER
—
—
—
—
—
—
IRQ2SC IRQ1SC IRQ0SC
—
—
—
IRQ2E IRQ1E
IRQ0E
CKS0
OS0
TCR
CMIEB CMIEA OVIE
CCLR1
—
CCLR0 CKS2 CKS1
TMR0
TMR1
SCI
TCSR
CMFB
CMFA OVF
OS3
OS2
OS1
H'CA TCORA
H'CB TCORB
H'CC TCNT
H'CD
H'CE
H'CF
H'D0
H'D1
H'D2
H'D3
H'D4
H'D5
H'D6
H'D7
H'D8
H'D9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TCR
TCSR
TCORA
TCORB
TCNT
—
CMIEB CMIEA OVIE
CCLR1
—
CCLR0 CKS2 CKS1
CKS0
OS0
CMFB
CMFA OVF
OS3
OS2
OS1
—
—
—
—
—
PE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SMR
BRR
C/A
CHR
O/E
STOP
MP
CKS1
CKS0
H'DA SCR
H'DB TDR
H'DC SSR
H'DD RDR
TIE
RIE
TE
RE
MPIE
PER
TEIE
CKE1
CKE0
MPBT
TDRE
RDRF
ORER
FER
TEND MPB
H'DE
H'DF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Continued on next page)
Notes: TMR0: 8-Bit Timer channel 0
TMR1: 8-Bit Timer channel 1
SCI: Serial Communication Interface
288
(Continued from preceding page)
Addr.
(last Register
Bit names
byte) name Bit 7
Bit 6
—
Bit 5
—
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
—
Module
H'E0
H'E1
H'E2
H'E3
H'E4
H'E5
H'E6
H'E7
H'E8
H'E9
ADDRA
—
A/D
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADDRB
—
—
—
—
—
ADDRC
—
—
—
—
—
ADDRD
—
—
ADIE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCAN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CKS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CH2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CH1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CH0
—
CHS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCSR ADF
—
—
H'EA ADCR TRGE
H'EB
H'EC
H'ED
H'EE
H'EF
H'F0
H'F1
H'F2
H'F3
H'F4
H'F5
H'F6
H'F7
H'F8
H'F9
H'FA
H'FB
H'FC
H'FD
H'FE
H'FF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Note: A/D: Analog-to-Digital converter
289
B.2 Register Descriptions
Register name
Address onto which
register is mapped
Abbreviation of
register name
TIER—Timer Interrupt Enable Register
H'FF90
FRT
Name of on-chip
supporting module
Bit No.
Bit
7
6
5
4
3
2
1
0
—
1
ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE
Initial value
Initial value
Read/Write
0
0
0
0
0
0
0
Bit names (abbreviations).
Bits marked “—”
are reserved.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Overflow Interrupt Enable
Type of access permitted
0
1
Overflow interrupt request is disabled.
Overflow interrupt request is enabled.
R
Read only
Write only
W
R/W Read or write
Output Compare Interrupt B Enable
0
1
Output compare interrupt request B is disabled.
Output compare interrupt request B is enabled.
Full name of bit
Output Compare Interrupt A Enable
0
1
Output compare interrupt request A is disabled.
Output compare interrupt request A is enabled.
Description of bit function
Input Capture Interrupt D Enable
0
1
Input capture interrupt request D is disabled.
Input capture interrupt request D is enabled.
290
TIER—Timer Interrupt Enable Register
H'FF90
FRT
Bit
7
6
5
ICICE
0
4
3
2
1
0
—
1
ICIAE ICIBE
ICIDE OCIAE OCIBE OVIE
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Overflow Interrupt Enable
0 Overflow interrupt request is disabled.
1 Overflow interrupt request is enabled.
Output Compare Interrupt B Enable
0 Output compare interrupt request B is disabled.
1 Output compare interrupt request B is enabled.
Output Compare Interrupt A Enable
0 Output compare interrupt request A is disabled.
1 Output compare interrupt request A is enabled.
Input Capture Interrupt D Enable
0 Input capture interrupt request D is disabled.
1 Input capture interrupt request D is enabled.
Input Capture Interrupt C Enable
0 Input capture interrupt request C is disabled.
1 Input capture interrupt request C is enabled.
Input Capture Interrupt B Enable
0 Input capture interrupt request B is disabled.
1 Input capture interrupt request B is enabled.
Input Capture Interrupt A Enable
0 Input capture interrupt request A is disabled.
1 Input capture interrupt request A is enabled.
291
TCSR—Timer Control/Status Register
H'FF91
FRT
Bit
7
ICFA
0
6
ICFB
0
5
ICFC
0
4
3
2
1
0
ICFD OCFA OCFB
OVF CCLRA
Initial value
0
0
0
0
0
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W
Counter Clear A
0 FRC count is not cleared.
1 FRC count is cleared by compare-match A.
Timer Overflow Flag
0 Cleared when CPU reads OVF = “1,” then writes “0” in OVF.
1 Set when FRC changes from H'FFFF to H'0000.
Output Compare Flag B
0 Cleared when CPU reads OCFB = “1”, then writes “0” in OCFB.
1 Set when FRC = OCRB.
Output Compare Flag A
0 Cleared when CPU reads OCFA = “1”, then writes “0” in OCFA.
1 Set when FRC = OCRA.
Input Capture Flag D
0 Cleared when CPU reads ICFD = “1”, then writes “0” in ICFD.
1 Set by FTID input.
Input Capture Flag C
0 Cleared when CPU reads ICFC = “1”, then writes “0” in ICFC.
1 Set by FTIC input.
Input Capture Flag B
0 Cleared when CPU reads ICFB = “1”, then writes “0” in ICFB.
1 Set when FTIB input causes FRC to be copied to ICRB.
Input Capture Flag A
0 Cleared when CPU reads ICFA = “1”, then writes “0” in ICFA.
1 Set when FTIA input causes FRC to be copied to ICRA.
Note: * Software can write a “0” in bits 7 to 1 to clear the flags, but cannot write a “1” in these bits.
292
FRC (H and L)—Free-Running Counter
H'FF92, H'FF93
FRT
Bit
7
6
5
4
3
2
1
0
0
Initial value
Read/Write
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
OCRA (H and L)—Output Compare Register A
H'FF94, H'FF95
FRT
Bit
7
6
5
4
3
2
1
0
1
Initial value
Read/Write
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Continually compared with FRC. OCFA is set to “1” when OCRA = FRC.
OCRB (H and L)—Output Compare Register B
H'FF94, H'FF95
FRT
Bit
7
6
5
4
3
2
1
0
1
Initial value
Read/Write
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Continually compared with FRC. OCFB is set to “1” when OCRB = FRC.
293
TCR—Timer Control Register
H'FF96
FRT
Bit
7
6
5
4
3
2
1
0
IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select
0 0 Internal clock source: Ø/2
0 1 Internal clock source: Ø/8
1 0 Internal clock source: Ø/32
1 1 External clock source: counted on rising edge
Buffer Enable B
0 ICRD is used for input capture D.
1 ICRD is buffer register for input capture B.
Buffer Enable A
0 ICRC is used for input capture C.
1 ICRC is buffer register for input capture A.
Input Edge Select D
0 Falling edge of FTID is valid.
1 Rising edge of FTID is valid.
Input Edge Select C
0 Falling edge of FTIC is valid.
1 Rising edge of FTIC is valid.
Input Edge Select B
0 Falling edge of FTIB is valid.
1 Rising edge of FTIB is valid.
Input Edge Select A
0 Falling edge of FTIA is valid.
1 Rising edge of FTIA is valid.
294
TOCR—Timer Output Compare Control Register
H'FF97
FRT
Bit
7
—
1
6
—
1
5
—
1
4
3
2
1
0
OCRS OEA
OEB OLVLA OLVLB
Initial value
Read/Write
0
0
0
0
0
—
—
—
R/W
R/W
R/W
R/W
R/W
Output Level B
0 Compare-match B causes “0” output.
1 Compare-match B causes “1” output.
Output Level A
0 Compare-match A causes “0” output.
1 Compare-match A causes “1” output.
Output Enable B
0 Output compare B output is disabled.
1 Output compare B output is enabled.
Output Enable A
0 Output compare A output is disabled.
1 Output compare A output is enabled.
Output Compare Register Select
0 The CPU can access OCRA.
1 The CPU can access OCRB.
ICRA (H and L)—Input Capture Register A
H'FF98, H'FF99
FRT
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Contains FRC count captured on FTIA input.
295
ICRB (H and L)—Input Capture Register B
H'FF9A, H'FF9B
FRT
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Contains FRC count captured on FTIB input.
ICRC (H and L)—Input Capture Register C
H'FF9C, H'FF9D
FRT
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Contains FRC count captured on FTIC input, or old ICRA value in buffer mode.
ICRD (H and L)—Input Capture Register D
H'FF9E, H'FF9F
FRT
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Contains FRC count captured on FTID input, or old ICRB value in buffer mode.
296
P1PCR—Port 1 Input Pull-Up Control Register
H'FFAC
Port 1
Bit
7
6
5
4
3
2
1
0
P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 1 Input Pull-Up Control
0 Input pull-up transistor is off.
1 Input pull-up transistor is on.
P2PCR—Port 2 Input Pull-Up Control Register
H'FFAD
Port 2
Bit
7
6
5
4
3
2
1
0
P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 2 Input Pull-Up Control
0 Input pull-up transistor is off.
1 Input pull-up transistor is on.
P3PCR—Port 3 Input Pull-Up Control Register
H'FFAE
Port 3
Bit
7
6
5
4
3
2
1
0
P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 3 Input Pull-Up Control
0 Input pull-up transistor is off.
1 Input pull-up transistor is on.
297
P1DDR—Port 1 Data Direction Register
H'FFB0
Port 1
Bit
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 1 Input/Output Control
0 Input port
1 Output port
P1DR—Port 1 Data Register
H'FFB2
Port 1
Bit
7
P17
0
6
P16
0
5
P15
0
4
P14
0
3
P13
0
2
P12
0
1
P11
0
0
P10
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
298
P2DDR—Port 2 Data Direction Register
H'FFB1
Port 2
Bit
7
6
5
4
3
2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 2 Input/Output Control
0 Input port
1 Output port
P2DR—Port 2 Data Register
H'FFB3
Port 2
Bit
7
P27
0
6
P26
0
5
P25
0
4
P24
0
3
P23
0
2
P22
0
1
P21
0
0
P20
0
Initial value
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3DDR—Port 3 Data Direction Register
H'FFB4
Port 3
Bit
7
6
5
4
3
2
1
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 3 Input/Output Control
0 Input port
1 Output port
299
P3DR—Port 3 Data Register
H'FFB6
Port 3
Bit
7
P37
0
6
P36
0
5
P35
0
4
P34
0
3
P33
0
2
1
P31
0
0
P30
0
P32
Initial value
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P4DDR—Port 4 Data Direction Register
H'FFB5
Port 4
Bit
7
6
5
4
3
2
1
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 4 Input/Output Control
0 Input port
1 Output port
P4DR—Port 4 Data Register
H'FFB7
Port 4
Bit
7
P47
0
6
P46
*
5
P45
0
4
P44
0
3
P43
0
2
P42
0
1
P41
0
0
P40
0
Initial value
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Determined by the level at pin P46.
P5DDR—Port 5 Data Direction Register
H'FFB8
Port 5
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
P52DDR P51DDR P50DDR
Initial value
Read/Write
0
0
0
—
—
—
—
—
W
W
W
Port 5 Input/Output Control
0 Input port
1 Output port
300
P5DR—Port 5 Data Register
H'FFBA
Port 5
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
P52
0
1
P51
0
0
P50
0
Initial value
Read/Write
—
—
—
—
—
R/W
R/W
R/W
P6DDR—Port 6 Data Direction Register
H'FFB9
Port 6
Bit
7
6
5
4
3
2
1
0
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 6 Input/Output Control
0 Input port
1 Output port
P6DR—Port 6 Data Register
H'FFBB
Port 6
Bit
7
P67
0
6
P66
0
5
P65
0
4
P64
0
3
P63
0
2
P62
0
1
P61
0
0
P60
0
Initial value
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P7DR—Port 7 Data Register
H'FFBE
Port 7
Bit
7
P77
*
6
P76
*
5
P75
*
4
P74
*
3
P73
*
2
P72
*
1
P71
*
0
P70
*
Initial value
Read/Write
R
R
R
R
R
R
R
R
Note: * Depends on the levels of pins P77 to P70.
301
STCR—Serial/Timer Control Register
H'FFC3
TMR0/1
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
MPE
ICKS1 ICKS0
Initial value
Read/Write
0
0
0
—
—
—
—
—
R/W
R/W
R/W
Multiprocessor Enable
0 Multiprocessor communication function is disabled.
1 Multiprocessor communication function is enabled.
Internal Clock Source Select
See TCR under TMR0 and TMR1.
SYSCR—System Control Register
H'FFC4
System Control
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
—
1
2
NMIEG
0
1
—
1
0
RAME
1
Initial value
Read/Write R/W
R/W
R/W
R/W
—
R/W
—
R/W
RAM Enable
0 On-chip RAM is disabled.
1 On-chip RAM is enabled.
NMI Edge
0 Falling edge of NMI is detected.
1 Rising edge of NMI is detected.
Standby Timer Select
0 0 0 Clock settling time = 8192 states
0 0 1 Clock settling time = 16384 states
0 1 0 Clock settling time = 32768 states
0 1 1 Clock settling time = 65536 states
1 – – Clock settling time = 131072 states
Software Standby
0 SLEEP instruction causes transition to sleep mode.
1 SLEEP instruction causes transition to software standby mode.
302
MDCR—Mode Control Register
H'FFC5
System Control
Bit
7
—
1
6
—
1
5
—
1
4
—
0
3
—
0
2
—
1
1
0
MDS1 MDS0
Initial value
Read/Write
*
*
—
—
—
—
—
—
R
R
Mode Select Bits
Value at mode pins.
Note: * Determined by inputs at pins MD1 and MD0.
ISCR—IRQ Sense Control Register
H'FFC6
System Control
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
IRQ2SC IRQ1SC IRQ0SC
Initial value
Read/Write
0
0
0
—
—
—
—
—
R/W
R/W
R/W
IRQ0 to IRQ2 Sense Control
0 IRQi is level-sensed (active Low).
1 IRQi is edge-sensed (falling edge).
IER—IRQ Enable Register
H'FFC7
System Control
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
IRQ2E IRQ1E IRQ0E
Initial value
Read/Write
0
0
0
—
—
—
—
—
R/W
R/W
R/W
IRQ0 to IRQ2 Enable
0 IRQi is disabled.
1 IRQi is enabled.
303
TCR—Timer Control Register
H'FFC8
TMR0
Bit
7
6
5
4
3
2
1
0
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2
CKS1 CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select
TCR
STCR
CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
0
Timer stopped
Ø/8 internal clock, falling edge
Ø/2 internal clock, falling edge
Ø/64 internal clock, falling edge
Ø/32 internal clock, falling edge
Ø/1024 internal clock, falling edge
Ø/256 internal clock, falling edge
Timer stopped
1
0
1
0
1
—
—
—
—
External clock, rising edge
External clock, falling edge
External clock, rising and falling
edges
Counter Clear
0 0 Counter is not cleared.
0 1 Cleared by compare-match A.
1 0 Cleared by compare-match B.
1 1 Cleared on rising edge of external reset input.
Timer Overflow Interrupt Enable
0 Overflow interrupt request is disabled.
1 Overflow interrupt request is enabled.
Compare-Match Interrupt Enable A
0 Compare-match A interrupt request is disabled.
1 Compare-match A interrupt request is enabled.
Compare-Match Interrupt Enable B
0 Compare-match B interrupt request is disabled.
1 Compare-match B interrupt request is enabled.
304
TCSR—Timer Control/Status Register
H'FFC9
TMR0
Bit
7
6
5
OVF
0
4
—
1
3
2
1
0
CMFB CMFA
OS3*2 OS2*2
OS1*2 OS0*2
Initial value
0
0
0
0
0
0
Read/Write R/(W)*1 R/(W)*1 R/(W)*1
—
R/W
R/W
R/W
R/W
Output Select
0 0 No change on compare-match A.
0 1 Output “0” on compare-match A.
1 0 Output “1” on compare-match A.
1 1 Invert (toggle) output on compare-match A.
Output Select
0 0 No change on compare-match B.
0 1 Output “0” on compare-match B.
1 0 Output “1” on compare-match B.
1 1 Invert (toggle) output on compare-match B.
Timer Overflow Flag
0 Cleared when CPU reads OVF = “1,” then writes “0” in OVF.
1 Set when TCNT changes from H'FF to H'00.
Compare-Match Flag A
0 Cleared when CPU reads CMFA = “1,” then writes “0” in CMFA.
1 Set when TCNT = TCORA.
Compare-Match Flag B
0 Cleared from when CPU reads CMFB = “1,” then writes “0” in CMFB.
1 Set when TCNT = TCORB.
Notes: *1 Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these
bits.
*2 When all four bits (OS3 to OS0) are cleared to “0,” output is disabled.
305
TCORA—Time Constant Register A
H'FFCA
TMR0
Bit
7
1
6
5
4
3
1
2
1
1
0
Initial value
1
1
1
1
1
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The CMFA bit is set to “1” when TCORA = TCNT.
TCORB—Time Constant Register B
H'FFCB
TMR0
Bit
7
1
6
5
4
3
1
2
1
1
0
Initial value
1
1
1
1
1
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The CMFB bit is set to “1” when TCORB = TCNT.
TCNT—Timer Counter
H'FFCC
TMR0
Bit
7
0
6
5
4
3
0
2
0
1
0
Initial value
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
306
TCR—Timer Conrol Register
H'FFD0
TMR1
Bit
7
6
5
4
3
2
1
0
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2
CKS1 CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select
TCR
STCR
CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
—
0
—
—
—
—
—
—
—
—
—
—
—
Timer stopped
Ø/8 internal clock, falling edge
Ø/2 internal clock, falling edge
Ø/64 internal clock, falling edge
Ø/128 internal clock, falling edge
Ø/1024 internal clock, falling edge
Ø/2048 internal clock, falling edge
Timer stopped
1
0
1
0
1
—
—
—
—
External clock, rising edge
External clock, falling edge
External clock, rising and falling
edges
Counter Clear
0 0 Counter is not cleared.
0 1 Cleared by compare-match A.
1 0 Cleared by compare-match B.
1 1 Cleared on rising edge of external reset input.
Timer Overflow Interrupt Enable
0 Overflow interrupt request is disabled.
1 Overflow interrupt request is enabled.
Compare-Match Interrupt Enable A
0 Compare-match A interrupt request is disabled.
1 Compare-match A interrupt request is enabled.
Compare-Match Interrupt Enable B
0 Compare-match B interrupt request is disabled.
1 Compare-match B interrupt request is enabled.
307
TCSR—Timer Control/Status Register
H'FFD1
TMR1
Bit
7
6
5
OVF
0
4
—
1
3
2
1
0
CMFB CMFA
OS3*2 OS2*2
OS1*2 OS0*2
Initial value
0
0
0
0
0
0
Read/Write R/(W)*1 R/(W)*1 R/(W)*1
—
R/W
R/W
R/W
R/W
Notes: Bit functions are the same as for TMR0.
*1 Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these
bits.
*2 When all four bits (OS3 to OS0) are cleared to “0,” output is disabled.
TCORA—Time Constant Register A
H'FFD2
TMR1
Bit
7
6
5
4
3
1
2
1
0
Initial value
1
1
1
1
1
1
1
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for TMR0.
TCORB—Time Constant Register B
H'FFD3
2
TMR1
Bit
7
6
5
4
3
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for TMR0.
TCNT—Timer Counter
H'FFD4
TMR1
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for TMR0.
308
SMR—Serial Mode Register
H'FFD8
SCI
Bit
7
C/A
0
6
5
PE
0
4
O/E
0
3
2
1
0
CHR
0
STOP
0
MP
0
CKS1 CKS0
Initial value
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select
0
0
1
1
0
1
0
1
Ø clock
Ø/4 clock
Ø/16 clock
Ø/64 clock
Multiprocessor Mode
0
1
Multiprocessor function disabled
Multiprocessor format selected
Stop Bit Length
0
1
One stop bit
Two stop bits
Parity Mode
0
1
Even parity
Odd parity
Parity Enable
0
Transmit: No parity bit added.
Receive: Parity bit not checked.
Transmit: Parity bit added.
1
Receive: Parity bit checked.
Character Length
0
1
8-Bit data length
7-Bit data length
Communication Mode
0
1
Asynchronous
Synchronous
309
BRR—Bit Rate Register
H'FFD9
SCI
Bit
7
1
6
5
4
3
1
2
1
1
0
Initial value
1
1
1
1
1
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Constant that determines the bit rate
310
SCR—Serial Control Register
H'FFDA
SCI
Bit
7
TIE
0
6
RIE
0
5
TE
0
4
RE
0
3
2
1
0
MPIE
0
TEIE
0
CKE1 CKE0
Initial value
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Enable 0
0
1
Serial clock not output
Serial clock output at SCK pin
Clock Enable 1
0
1
Internal clock
External clock
Transmit End Interrupt Enable
0
1
TSR-empty interrupt request is disabled.
TSR-empty interrupt request is enabled.
Multiprocessor Interrupt Enable
0
1
Multiprocessor receive interrupt function is disabled.
Multiprocessor receive interrupt function is enabled.
Receive Enable
0
1
Receive disabled
Receive enabled
Transmit Enable
0
1
Transmit disabled
Transmit enabled
Receive Interrupt Enable
0
1
Receive interrupt and receive error interrupt requests are disabled.
Receive interrupt and receive error interrupt requests are enabled.
Transmit Interrupt Enable
0
1
TDR-empty interrupt request is disabled.
TDR-empty interrupt request is enabled.
311
TDR—Transmit Data Register
H’FFDB
SCI
Bit
7
1
6
5
4
3
1
2
1
1
0
Initial value
1
1
1
1
1
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Transmit data
312
SSR—Serial Status Register
H'FFDC
SCI
Bit
7
6
5
4
FER
0
3
PER
0
2
1
0
TDRE RDRF ORER
TEND
MPB MPBT
Initial value
1
0
0
0
0
0
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
R
R
R/W
Multiprocessor Bit Transfer
0 Multiprocessor bit = “0” in transmit data.
1 Multiprocessor bit = “1” in transmit data.
Multiprocessor Bit
0 Multiprocessor bit = “0” in receive data.
1 Multiprocessor bit = “1” in receive data.
Transmit End
0 Cleared when CPU reads TDRE = “1,” then writes “0” in TDRE.
1 Set to “1” when TE = “0,” or when TDRE = “1” at the end of
character transmission.
Parity Error
0 Cleared when CPU reads PER = “1,” then writes “0” in PER.
1 Set when a parity error occurs (parity of receive data does not match
parity selected by O/E bit in SMR).
Framing Error
0 Cleared when CPU reads FER = “1,” then writes “0” in FER.
1 Set when a framing error occurs (stop bit is “0”).
Overrun Error
0 Cleared when CPU reads ORER = “1,” then writes “0” in ORER.
1 Set when an overrun error occurs (next data is completely received while
RDRF bit is set to “1”).
Receive Data Register Full
0 Cleared when CPU reads RDRF = “1,” then writes “0” in RDRF.
1 Set when one character is received normally and transferred from RSR to RDR.
Transmit Data Register Empty
0 Cleared when CPU reads TDRE = “1,” then writes “0” in TDRE
1 Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = “0.”
Note: * Software can write a “0” in bits 7 to 3 to clear the flags, but cannot write a “1” in these bits.
313
RDR—Receive Data Register
H'FFDD
SCI
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Receive data
ADDRn—A/D Data Register n (n = A, B, C, D) H'FFE0, H'FFE2,
H'FFE4, H'FFE6
A/D
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
A/D conversion result
314
ADCSR—A/D Control/Status Register
H'FFE8
A/D
Bit
7
ADF
0
6
ADIE
0
5
4
3
2
1
0
ADST SCAN
CKS
0
CH2
0
CH1
0
CH0
0
Initial value
0
0
Read/Write R/(W)* R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel Select
CH2 CH1 CH0 Single mode Scan mode
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN0
AN0, AN1
AN0 to AN2
AN0 to AN3
AN4
AN4, AN5
AN4 to AN6
AN4 to AN7
1
Clock Select
0 Conversion time = 242 states (max)
1 Conversion time = 122 states (max)
Scan Mode
0 Single mode
1 Scan mode
A/D Start
0 A/D conversion is halted.
1 1. Single mode: One A/D conversion is performed, then this bit is automatically cleared to “0.”
2. Scan mode: A/D conversion starts and continues cyclically on all selected channels until “0”
is written in this bit.
A/D Interrupt Enable
0 The A/D interrupt request (ADI) is disabled.
1 The A/D interrupt request (ADI) is enabled.
A/D End Flag
0 Cleared from “1” to “0” when CPU reads ADF = “1,” then writes “0” in ADF.
1 Set to “1” at the following times:
1. Single mode: at the completion of A/D conversion
2. Scan mode: when all selected channels have been converted.
Note: * Software can write a “0” in bit 7 to clear the flag, but cannot write a “1” in this bit.
315
ADCR—A/D Control Register
H'FFEA
A/D
Bit
7
TRGE
0
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
CHS
0
Initial value
Read/Write R/W
—
—
—
—
—
—
R/W
Channel Select
Reserved bit.
Trigger Enable
0 ADTRG is disabled.
1 ADTRG is enabled. A/D conversion can be started by external trigger,
or by software.
316
Appendix C. Pin States
C.1 Pin States in Each Mode
Table C-1. Pin States
Pin
MCU
mode Reset
Hardware
standby
3-State
Software Sleep
Normal
name
standby
Low
mode
operation
A7 – A0
P17 – P10
A7 – A0
1
2
Low
Prev. state
(Addr.
3-State
Low if
Addr. output
DDR = 1, output pins: or input port
Prev. state last address
if DDR = 0 accessed)
3
1
2
Prev. state
Low
I/O port
P27 – P20
A15 – A8
Low
3-State
Prev. state
(Addr.
A15–A8 output
Addr. output
3-State
Low if
DDR = 1, output pins: or input port
Prev. state last address
if DDR = 0 accessed)
3
1
2
3
1
2
3
1
2
3
Prev. state
3-State
I/O port
D7 – D0
P37 – P30
D7 – D0
3-State
3-State
3-State
3-State
3-State
3-State
Prev. state Prev. state
3-State 3-State
I/O port
WAIT
P47/WAIT
P46/Ø
Prev. state Prev. state
I/O port
Clock
Clock
output
3-State
High
Clock
output
output
High if
Clock output Clock output
DDR = 1, if DDR = 1, if DDR = 1,
3-state if
3-state if
input port if
DDR = 0
DDR = 0 DDR = 0
Notes: 1. 3-State: High-impedance state
2. Prev. state: Previous state. Input ports are in the high-impedance state (with the MOS
pull-up on if PCR = 1). Output ports hold their previous output level.
3. I/O port: Direction depends on the data direction (DDR) bit. Note that these pins may
also be used by the on-chip supporting modules.
See section 5, “I/O Ports,” for further information.
317
Table C-1. Pin States (cont.)
Pin
MCU
Hardware
standby
3-State
Software Sleep
Normal
operation
AS, WR,
RD
name
mode Reset
standby
mode
P45 – P43,
AS, WR, RD
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
High
High
High
3-State
3-State
Prev. state Prev. state
Prev. state Prev. state
I/O port
I/O port
P42 – P40
P52 – P50
P67 – P60
P77 – P70
3-State
3-State
3-State
3-State
3-State
3-State
3-State
Prev. state* Prev. state
Prev. state* Prev. state
I/O port
I/O port
Input port
3-State
3-State
Notes: 1. 3-State: High-impedance state
2. Prev. state: Previous state. Input ports are in the high-impedance state (with the MOS
pull-up on if PCR = 1). Output ports hold their previous output level.
3. I/O port: Direction depends on the data direction (DDR) bit. Note that these pins may
also be used by the on-chip supporting modules.
See section 5, “I/O Ports,” for further information.
*
On-chip supporting modules are initialized, so these pins revert to I/O ports according
to the DDR and DR bits.
318
Appendix D. Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit cleared to “0” in SYSCR, drive the RES signal
low 10 system clock cycles before the STBY signal goes low, as shown below. RES must
remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
STBY
t1 ≥ 10 tcyc
t2 ≥ 0 ns
RES
(2) When the RAME bit in SYSCR is set to “1” or it is not necessary to retain RAM contents, RES
does not have to be driven low as in (1).
Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately
100 ns before STBY goes high.
STBY
t
100 ns
tOSC
≥
RES
319
Appendix E. Package Dimensions
Figure E-1 shows the dimensions of the DC-64S package. Figure E-2 shows the dimensions of the
DP-64S package. Figure E-3 shows the dimensions of the FP-64A package. Figure E-4 shows the
dimensions of the CP-68 package.
Unit: mm
57.30
64
1
33
32
0.9
19.05
+ 0.11
– 0.05
0.25
1.778 ± 0.250
0.48 ± 0.10
Figure E-1. Package Dimensions (DC-64S)
Unit: mm
57.6
58.50 Max
33
64
1
32
1.0
19.05
+ 0.11
– 0.05
0.25
1.78 ± 0.25
0.48 ± 0.10
0° – 15°
Figure E-2. Package Dimensions (DP-64S)
320
Unit: mm
17.2 ± 0.3
14
33
48
32
17
49
64
1
16
M
0.35 ± 0.10
0.15
1.6
0 – 5 °
0.8 – 0.3
0.1
Figure E-3. Package Dimensions (FP-64A)
Unit: mm
25.15 ± 0.12
24.20
60
44
61
43
68
1
9
27
26
10
0.75
1.27
0.42 ± 0.10
23.12 ± 0.50
23.12 ± 0.50
0.10
Figure E-4. Package Dimensions (CP-68)
321
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