HD6473714PV [RENESAS]
OTPROM, 4.19MHz, MICROCONTROLLER, PDIP64, SDIP-64;
| 型号： | HD6473714PV |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | OTPROM, 4.19MHz, MICROCONTROLLER, PDIP64, SDIP-64 微控制器 |
| 文件： | 总324页 (文件大小：780K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 1, 2003
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H8/3714 Series
HD6433712
HD6433713
HD6433714, HD6473714
Hardware Manual
Preface
The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core,
with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is
compatible with the H8/300 CPU, and is ideal for realtime control.
The H8/3714 Series has a system-on-a-chip architecture that includes such peripheral functions as
a vacuum fluorescent display controller/driver, five timers, a 14-bit PWM, a two-channel serial
communication interface, and an A/D converter. It also has high-voltage pins capable of directly
driving a vacuum fluorescent display, making it ideal for use in systems employing this type of
display.
This manual describes the hardware of the H8/3714 Series. For details on the instruction set, refer
to the H8/300L Series Programming Manual.
Contents
Section 1 Overview..........................................................................................................
1
1
5
6
6
8
1.1
1.2
1.3
Overview.........................................................................................................................
Internal Block Diagram ..................................................................................................
Pin Arrangement and Functions .....................................................................................
1.3.1 Pin Arrangement.................................................................................................
1.3.2 Pin Functions ......................................................................................................
Section 2 CPU................................................................................................................... 15
2.1
Overview......................................................................................................................... 15
2.1.1 Features............................................................................................................... 15
2.1.2 Address Space..................................................................................................... 16
2.1.3 Register Configuration........................................................................................ 17
Register Descriptions...................................................................................................... 18
2.2.1 General Registers................................................................................................ 18
2.2.2 Control Registers ................................................................................................ 18
2.2.3 Initial Register Values......................................................................................... 20
Data Formats................................................................................................................... 20
2.3.1 Data Formats in General Registers ..................................................................... 21
2.3.2 Memory Data Formats........................................................................................ 22
Addressing Modes .......................................................................................................... 23
2.4.1 Addressing Modes .............................................................................................. 23
2.4.2 Effective Address Calculation ............................................................................ 25
Instruction Set................................................................................................................. 29
2.5.1 Data Transfer Instructions .................................................................................. 31
2.5.2 Arithmetic Operations ........................................................................................ 33
2.5.3 Logic Operations ................................................................................................ 34
2.5.4 Shift Operations.................................................................................................. 34
2.5.5 Bit Manipulations ............................................................................................... 36
2.5.6 Branching Instructions........................................................................................ 40
2.5.7 System Control Instructions ............................................................................... 42
2.5.8 Block Data Transfer Instruction ......................................................................... 43
CPU States...................................................................................................................... 45
2.6.1 Overview............................................................................................................. 45
2.6.2 Program Execution State .................................................................................... 46
2.6.3 Program Halt State.............................................................................................. 46
2.6.4 Exception-Handling State................................................................................... 46
Basic Operation Timing.................................................................................................. 47
2.7.1 Access to On-Chip Memory (RAM, ROM) ....................................................... 47
2.7.2 Access to On-Chip Peripheral Modules ............................................................. 48
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Application Notes........................................................................................................... 49
2.8.1 Notes on Data Access......................................................................................... 49
2.8.2 Notes on Bit Manipulation.................................................................................. 51
Section 3 System Control .............................................................................................. 55
3.1
3.2
Overview......................................................................................................................... 55
Exception Handling ........................................................................................................ 55
3.2.1 Reset ................................................................................................................... 55
3.2.2 Interrupts............................................................................................................. 56
3.2.3 Interrupt Control Registers ................................................................................. 58
3.2.4 External Interrupts .............................................................................................. 66
3.2.5 Internal Interrupts ............................................................................................... 67
3.2.6 Interrupt Operations............................................................................................ 67
3.2.7 Return from an Interrupt..................................................................................... 72
3.2.8 Interrupt Response Time..................................................................................... 72
3.2.9 Valid Interrupts in Each Mode............................................................................ 73
3.2.10 Notes on Stack Area Use.................................................................................... 74
System Modes................................................................................................................. 75
3.3.1 Active Mode ....................................................................................................... 76
3.3.2 Low-Power Operation Mode .............................................................................. 76
3.3.3 Application Notes............................................................................................... 82
System Control Registers ............................................................................................... 83
3.4.1 System Control Register 1 (SYSCR1)................................................................ 83
3.4.2 System Control Register 2 (SYSCR2)................................................................ 85
3.3
3.4
Section 4 ROM.................................................................................................................. 87
4.1
Overview......................................................................................................................... 87
4.1.1 Block Diagram.................................................................................................... 87
PROM Mode................................................................................................................... 88
4.2.1 Selection to PROM Mode................................................................................... 88
4.2.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 88
Programming .................................................................................................................. 91
4.3.1 Writing and Verifying......................................................................................... 91
4.3.2 Programming Precautions................................................................................... 94
4.3.3 Reliability of Written Data ................................................................................. 96
4.2
4.3
Section 5 RAM ................................................................................................................. 97
5.1
Overview......................................................................................................................... 97
5.1.1 Block Diagram.................................................................................................... 97
5.1.2 Display RAM Area............................................................................................. 97
Section 6 Clock Pulse Generators............................................................................... 99
6.1
Overview......................................................................................................................... 99
6.1.1 Block Diagram.................................................................................................... 99
System Clock Generator................................................................................................. 100
Subclock Generator ........................................................................................................ 103
6.2
6.3
Section 7 I/O Ports........................................................................................................... 105
7.1
Overview......................................................................................................................... 105
7.1.1 Port Types and Mask Options............................................................................. 107
7.1.2 MOS Pull-Up...................................................................................................... 108
7.1.3 MOS Pull-Down ................................................................................................. 110
Port 0 ............................................................................................................................ 111
7.2.1 Overview............................................................................................................. 111
7.2.2 Register Configuration and Description ............................................................. 111
7.2.3 Pin Functions ...................................................................................................... 112
7.2.4 Pin States ............................................................................................................ 112
Port 1 ............................................................................................................................ 113
7.3.1 Overview............................................................................................................. 113
7.3.2 Register Configuration and Description ............................................................. 113
7.3.3 Pin Functions ...................................................................................................... 118
7.3.4 Pin States ............................................................................................................ 119
Port 4 ............................................................................................................................ 120
7.4.1 Overview............................................................................................................. 120
7.4.2 Register Configuration and Description ............................................................. 120
7.4.3 Pin Functions ...................................................................................................... 121
7.4.4 Pin States ............................................................................................................ 121
Port 5 ............................................................................................................................ 122
7.5.1 Overview............................................................................................................. 122
7.5.2 Register Configuration and Description ............................................................. 122
7.5.3 Pin Functions ...................................................................................................... 123
7.5.4 Pin States ............................................................................................................ 123
Port 6 ............................................................................................................................ 124
7.6.1 Overview............................................................................................................. 124
7.6.2 Register Configuration and Description ............................................................. 124
7.6.3 Pin Functions ...................................................................................................... 125
7.6.4 Pin States ............................................................................................................ 125
Port 7 ............................................................................................................................ 126
7.7.1 Overview............................................................................................................. 126
7.7.2 Register Configuration and Description ............................................................. 126
7.7.3 Pin Functions ...................................................................................................... 127
7.7.4 Pin States ............................................................................................................ 127
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Port 9 ............................................................................................................................ 128
7.8.1 Overview............................................................................................................. 128
7.8.2 Register Configuration and Description ............................................................. 128
7.8.3 Pin Functions ...................................................................................................... 132
7.8.4 Pin States ............................................................................................................ 134
Section 8 Timers............................................................................................................... 135
8.1
Overview......................................................................................................................... 135
8.1.1 Prescaler Operation............................................................................................. 136
Timer A........................................................................................................................... 138
8.2.1 Overview............................................................................................................. 138
8.2.2 Register Descriptions.......................................................................................... 139
8.2.3 Timer Operation.................................................................................................. 141
Timer B........................................................................................................................... 143
8.3.1 Overview............................................................................................................. 143
8.3.2 Register Descriptions.......................................................................................... 144
8.3.3 Timer Operation.................................................................................................. 146
Timer C........................................................................................................................... 148
8.4.1 Overview............................................................................................................. 148
8.4.2 Register Descriptions.......................................................................................... 149
8.4.3 Timer Operation.................................................................................................. 152
Timer D........................................................................................................................... 154
8.5.1 Overview............................................................................................................. 154
8.5.2 Register Descriptions.......................................................................................... 155
8.5.3 Timer Operation.................................................................................................. 157
Timer E ........................................................................................................................... 158
8.6.1 Overview............................................................................................................. 158
8.6.2 Register Descriptions.......................................................................................... 160
8.6.3 Timer Operation.................................................................................................. 164
Interrupts......................................................................................................................... 167
Application Notes........................................................................................................... 167
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Section 9 14-Bit PWM ................................................................................................... 169
9.1
Overview......................................................................................................................... 169
9.1.1 Features............................................................................................................... 169
9.1.2 Block Diagram.................................................................................................... 169
9.1.3 Pin Configuration................................................................................................ 170
9.1.4 Register Configuration........................................................................................ 170
9.2
9.3
Register Descriptions...................................................................................................... 171
9.2.1 PWM Control Register (PWCR) ........................................................................ 171
9.2.2 PWM Data Registers U and L (PWDRU, PWDRL) .......................................... 172
Operation ........................................................................................................................ 173
Section 10 SCI1 .................................................................................................................. 175
10.1 Overview......................................................................................................................... 175
10.1.1 Features............................................................................................................... 175
10.1.2 Block Diagram.................................................................................................... 175
10.1.3 Pin Configuration................................................................................................ 176
10.1.4 Register Configuration........................................................................................ 176
10.2 Register Descriptions...................................................................................................... 177
10.2.1 Serial Mode Register 1 (SMR1) ......................................................................... 177
10.2.2 Serial Data Register U1 (SDRU1)...................................................................... 178
10.2.3 Serial Data Register L1 (SDRL1)....................................................................... 179
10.2.4 Serial Port Register 1 (SPR1) ............................................................................. 179
10.2.5 Port Mode Register 2 (PMR2)............................................................................ 180
10.2.6 Port Mode Register 3 (PMR3)............................................................................ 181
10.3 Operation ........................................................................................................................ 182
10.3.1 Overview............................................................................................................. 182
10.3.2 Data Transfer Format.......................................................................................... 183
10.3.3 Clock................................................................................................................... 183
10.3.4 Data Transmit/Receive........................................................................................ 183
10.3.5 SCI1 State Transitions ........................................................................................ 186
10.3.6 Serial Clock Error Detection .............................................................................. 187
10.3.7 Interrupts............................................................................................................. 188
Section 11 SCI2 .................................................................................................................. 189
11.1 Overview......................................................................................................................... 189
11.1.1 Features............................................................................................................... 189
11.1.2 Block Diagram.................................................................................................... 189
11.1.3 Pin Configuration................................................................................................ 190
11.1.4 Register Configuration........................................................................................ 190
11.2 Register Descriptions...................................................................................................... 191
11.2.1 Start Address Register (STAR)........................................................................... 191
11.2.2 End Address Register (EDAR)........................................................................... 191
11.2.3 Serial Control Register 2 (SCR2) ....................................................................... 192
11.2.4 Status Register (STSR)....................................................................................... 193
11.2.5 Port Mode Register 3 (PMR3)............................................................................ 195
11.3 Operation ........................................................................................................................ 197
11.3.1 Overview............................................................................................................. 197
11.3.2 Clock................................................................................................................... 198
11.3.3 Data Transfer Format.......................................................................................... 198
11.3.4 Data Transmit/Receive........................................................................................ 200
11.4 Interrupts......................................................................................................................... 202
11.5 Application Notes........................................................................................................... 202
Section 12 VFD Controller/Driver................................................................................ 203
12.1 Overview......................................................................................................................... 203
12.1.1 Features............................................................................................................... 203
12.1.2 Block Diagram.................................................................................................... 203
12.1.3 Pin Configuration................................................................................................ 204
12.1.4 Register Configuration........................................................................................ 204
12.2 Register Descriptions...................................................................................................... 205
12.2.1 VFD Digit Control Register (VFDR) ................................................................. 205
12.2.2 VFD Segment Control Register (VFSR) ............................................................ 208
12.2.3 Digit Beginning Register (DBR) ........................................................................ 210
12.3 Operation ........................................................................................................................ 212
12.3.1 Overview............................................................................................................. 212
12.3.2 Control Section................................................................................................... 212
12.3.3 RAM Bit Correspondence to Digits/Segments................................................... 212
12.3.4 Procedure for Starting Operation........................................................................ 214
12.4 Interrupts......................................................................................................................... 214
12.5 Occurrence of Flicker when VFD Registers are Rewritten ............................................ 214
Section 13 A/D Converter................................................................................................ 215
13.1 Overview......................................................................................................................... 215
13.1.1 Features............................................................................................................... 215
13.1.2 Block Diagram.................................................................................................... 216
13.1.3 Pin Configuration................................................................................................ 217
13.1.4 Register Configuration........................................................................................ 217
13.2 Register Descriptions...................................................................................................... 218
13.2.1 A/D Result Register (ADRR) ............................................................................. 218
13.2.2 A/D Mode Register (AMR)................................................................................ 218
13.2.3 A/D Start Register (ADSR) ................................................................................ 221
13.2.4 Port Mode Register 0 (PMR0)............................................................................ 222
13.3 Operation ........................................................................................................................ 222
13.4 Interrupts......................................................................................................................... 222
13.5 Typical Use ..................................................................................................................... 223
13.6 Application Notes........................................................................................................... 227
Section 14 Electrical Specifications.............................................................................. 229
14.1 Absolute Maximum Ratings........................................................................................... 229
14.2 HD6473714 Electrical Characteristics ........................................................................... 230
14.2.1 HD6473714 DC Characteristics ......................................................................... 230
14.2.2 HD6473714 AC Characteristics ......................................................................... 236
14.2.3 HD6473714 A/D Converter Characteristics ....................................................... 239
14.3 HD6433712, HD6433713 and HD6433714 Electrical Characteristics .......................... 240
14.3.1 HD6433712, HD6433713 and HD6433714 DC Characteristics........................ 240
14.3.2 HD6433712, HD6433713 and HD6433714 AC Characteristics........................ 246
14.3.3 HD6433712, HD6433713 and HD6433714 A/D Converter Characteristics...... 249
14.4 Operational Timing......................................................................................................... 250
14.5 Differences in Electrical Characteristics between HD6473714 and
HD6433712/HD6433713/HD6433714........................................................................... 253
Appendix A CPU Instruction Set................................................................................... 255
A.1
A.2
A.3
Instruction Notation........................................................................................................ 255
Operation Code Map....................................................................................................... 256
Number of States Required for Execution...................................................................... 258
Appendix B On-Chip Registers...................................................................................... 265
B.1
On-Chip Registers (1)..................................................................................................... 265
B.2
On-Chip Registers (2)..................................................................................................... 268
Appendix C I/O Port Block Diagrams ......................................................................... 295
C.1
C.2
C.3
C.4
C.5
C.6
C.7
Port 0 Block Diagram..................................................................................................... 295
Port 1 Block Diagram..................................................................................................... 296
Port 4 Block Diagram..................................................................................................... 299
Port 5 Block Diagram..................................................................................................... 300
Port 6 Block Diagram..................................................................................................... 301
Port 7 Block Diagram..................................................................................................... 302
Port 9 Block Diagram..................................................................................................... 303
Appendix D Port States in Each Processing State.................................................... 309
Appendix E List of Mask Options................................................................................. 311
Appendix F Rise Time and Fall Time of High-Voltage Pins................................. 312
Appendix G Package Dimensions................................................................................. 313
Section 1 Overview
1.1 Overview
The H8/300L Series is a series of single-chip microcontrollers (MCU: microcomputer unit) built
around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.
Within the H8/300L Series, the H8/3714 Series microcontrollers are equipped with high-voltage
pins. On-chip peripheral functions include a vacuum fluorescent display (VFD) controller/driver,
timers, a 14-bit pulse width modulator (digital-to-analog converter), two serial communication
interface channels, and an analog-to-digital converter. Together, these functions make the
H8/3714 Series ideally suited for embedded control of systems requiring a vacuum fluorescent
display. On-chip memory is 16 kbytes of ROM and 384 bytes of RAM in the H8/3712, 24 kbytes
of ROM and 384 bytes of RAM in the H8/3713, or 32 kbytes of ROM and 512 bytes of RAM in
the H8/3714, providing a choice for systems of different sizes. The ZTAT™* versions of the
H8/3714 come with user-programmable PROM.
Table 1 summarizes the features of the H8/3714 Series.
Note: * ZTAT (zero turn-around time) is a trademark of Hitachi, Ltd.
1
Table 1-1 Features
Item
Description
CPU
General-register architecture
• General registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)
Operating speed
• Max. operating speed: 4.19 MHz
• Add/subtract: 0.5 µs (operating at φ = 4 MHz)
• Multiply/divide: 3.5 µs (operating at φ = 4 MHz)
• Can run on 32 kHz subclock
Instruction set compatible with H8/300 CPU
• Instruction length of 2 bytes or 4 bytes
• Basic arithmetic operations between registers
• MOV instruction for data transfer between memory and registers
Instruction features
• Multiply (8 bits × 8 bits)
• Divide (16 bits ÷ 8 bits)
• Bit accumulator
• Register-indirect designation of bit position
• H8/3714: 32 kbyte ROM, 512 byte RAM
• H8/3713: 24 kbyte ROM, 384 byte RAM
• H8/3712: 16 kbyte ROM, 384 byte RAM
Memory
2
Table 1-1 Features (cont)
Item
Description
Timers
• Timer A: 8-bit interval timer
Count-up timer with selection of eight internal clock signals divided from
the system clock (φ)* and four clock signals divided from the subclock
(φSUB
)
• Timer B: 8-bit reload timer
Count-up timer with selection of seven internal clock signals or event input
from pin P10/IRQ0
• Timer C: 8-bit reload timer
Count-up/count-down timer with selection of seven internal clock signals
or event input from pin P11/IRQ1
• Timer D: 8-bit event counter
Up-counter for counting input from pin P16/EVENT
• Timer E: 8-bit reloadable timer
Count-up timer with selection of eight internal clock signals. Square-wave
(50% duty cycle) output with a fixed frequency or variable frequency
controlled by timer E overflow can be selected by pin P15/IRQ5/TMOE
settings.
Note: * φ indicates a clock frequency that is divided in half from the original
oscillator frequency
14-bit PWM
• Pulse-division PWM designed for less ripple
• Can be used as a 14-bit D/A converter by connecting to an external low-
pass filter
VFD
driver/controller
• Up to 24 segment pins and up to 16 digit pins (of which 8 are for both
uses)
• Brightness adjustable in 8 steps (dimmer function)
• Digit and segment pins can be switched to use as general-purpose high-
voltage pins
• Key scan interval can be enabled or disabled
• Interrupt can be requested when key scan interval starts
• 2-channel synchronous SCI1 and SCI2
Serial communica-
tion interface
• Choice of 8-bit or 16-bit data transfer (SCI1)
• Automatic transfer of 32-byte data (SCI2)
• Overrun error detection possible
• Interrupt can be requested when transfer is complete
3
Table 1-1 Features (cont)
Item
Description
A/D converter
• Successive approximations using a resistance ladder
• Resolution: 8 bits
• 8-channel analog input port
• Conversion time: 31/φ or 62/φ per channel
• Interrupt can be requested at completion of A/D conversion
• High-voltage I/O pins: 32
I/O ports
Interrupts
• High-voltage input pin: 1
• Standard-voltage I/O pins: 12
• Standard-voltage input pins: 9
• Four external interrupt pins: IRQ5, IRQ4, IRQ1, IRQ0
• Ten internal interrupt sources
• Sleep mode
Low power operation
modes
• Standby mode
• Watch mode
• Subactive mode
Other
• Built-in pulse generators for system clock and subclock
• Timer A can run on the subclock for use as a time base
Product Code
Product lineup
Mask ROM Version ZTAT Version
Package
ROM/RAM Size
HD6433714H
HD6433714P
HD6433713H
HD6433713P
HD6433712H
HD6433712P
HD6473714H
64 pin GFP
(FP-64A)
ROM: 32 kbytes
RAM: 512 bytes
HD6473714P
64 pin SDIP
(DP-64S)
—
—
—
—
64 pin QFP
(FP-64A)
ROM: 24 kbytes
RAM: 384 bytes
64 pin SDIP
(DP-64S)
64 pin QFP
(FP-64A)
ROM: 16 kbytes
RAM: 384 bytes
64 pin SDIP
(DP-64S)
4
1.2 Internal Block Diagram
Figure 1-1 is an internal block diagram of the H8/3714 Series.
CPU
Subclock
pulse
generator
System
clock pulse
generator
H8/300L
P10 /IRQ0
P11 /IRQ1
P12 /IRQ2
P13 /IRQ3
P14 /IRQ4
P15 /IRQ5 /TMOE
P16 /EVENT
P17 /Vdisp
P90 /PWM
P91 /SCK1
P92 /SI1
P93/SO1
P94 /SCK2
P95 /SI2/CS
P96/SO2
P97 /UD
Data bus (lower)
RAM
P60 /FD0 /FS7
P61 /FD1 /FS6
P62 /FD2 /FS5
P63 /FD3 /FS4
P64 /FD4 /FS3
P65 /FD5 /FS2
P66 /FD6 /FS1
P67 /FD7 /FS0
Timer A
Mask ROM (PROM)
P50 /FS15
P51 /FS14
P52 /FS13
P53 /FS12
P54 /FS11
P55 /FS10
P56 /FS9
P57 /FS8
Timer B
Timer C
Timer D
Timer E
P70 /FD8
P71 /FD9
P72 /FD10
P73 /FD11
P74 /FD12
P75 /FD13
P76 /FD14
P77 /FD15
SCI1
SCI2
P40 /FS16
P41 /FS17
P42 /FS18
P43 /FS19
P44 /FS20
P45 /FS21
P46/FS22
P47/FS23
VFD
controller/driver
14-bit PWM
A/D converter
Port 0
Figure 1-1 Block Diagram
5
1.3 Pin Arrangement and Functions
1.3.1 Pin Arrangement
The pin arrangements for the H8/3714 Series are shown in figure 1-2 (FP-64A) and figure 1-3
(DP-64S).
AVCC
P00/AN0
P01/AN1
P02/AN2
P03/AN3
P04/AN4
P05/AN5
P06/AN6
P07/AN7
AVSS
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P70/FD8
2
P67/FD7/FS0
P66/FD6/FS1
P65/FD5/FS2
P64/FD4/FS3
P63/FD3/FS4
P62/FD2/FS5
P61/FD1/FS6
P60/FD0/FS7
P17/Vdisp
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TEST
P57/FS8
X2
P56/FS9
X1
P55/FS10
VSS
P54/FS11
OSC1
P53/FS12
OSC2
P52/FS13
Figure 1-2 Pin Arrangement (FP-64A: Top View)
6
VCC
P90/PWM
P91/SCK1
P92/SI1
P93/SO1
P94/SCK2
P95/SI2/CS
P96/SO2
P97/UD
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P77/FD15
P76/FD14
P75/FD13
P74/FD12
P73/FD11
P72/FD10
P71/FD9
2
3
4
5
6
7
8
P70/FD8
9
P67/FD7/FS0
P66/FD6/FS1
P65/FD5/FS2
P64/FD4/FS3
P63/FD3/FS4
P62/FD2/FS5
P61/FD1/FS6
P60/FD0/FS7
P17/Vdisp
AVCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P00/AN0
P01/AN1
P02/AN2
P03/AN3
P04/AN4
P05/AN5
P06/AN6
P07/AN7
AVSS
P57/FS8
P56/FS9
TEST
P55/FS10
P54/FS11
P53/FS12
P52/FS13
P51/FS14
P50/FS15
P40/FS16
P41/FS17
P42/FS18
P43/FS19
P44/FS20
P45/FS21
P46/FS22
X2
X1
VSS
OSC1
OSC2
RES
P10/IRQ0
P11/IRQ1
P14/IRQ4
P15/IRQ5 /TMOE
P16/EVENT
P47/FS23
Figure 1-3 Pin Arrangement (DP-64S: Top View)
7
1.3.2 Pin Functions
1. List of pin functions
Table 1-2 lists the pin functions of the LSI.
Table 1-2 List of Pin Functions
Pin No.
FP-64A
6
DP-64S
15
Name and Function
PROM Mode
NC
P04/AN4 (standard input port/analog input channel)
P05/AN5 (standard input port/analog input channel)
P06/AN6 (standard input port/analog input channel)
P07/AN7 (standard input port/analog input channel)
AVSS (reference voltage for A/D converter)
TEST (test pin)
7
16
NC
8
17
NC
9
18
NC
10
11
12
13
14
15
16
17
18
19
VSS
20
VCC
NC
21
X2 (subclock oscillator connection)
X1 (subclock oscillator connection)
VSS (ground)
22
VCC
VSS
23
24
OSC1 (system clock oscillator connection)
OSC2 (system clock oscillator connection)
RES (reset input)
VSS
25
NC
26
VPP
27
P10/IRQ0 (standard I/O port/external interrupt or
timer B event input)
NC
19
28
P11/IRQ1 (standard I/O port/external interrupt or
timer C event input)
NC
20
21
29
30
P14/IRQ4 (standard I/O port/external interrupt)
NC
NC
P15/IRQ5/TMOE (standard I/O port/external
interrupt/warning tone output)
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
P16/EVENT (standard input port/timer D event input)
P47/FS23 (high-voltage I/O port/VFD segment output)
P46/FS22 (high-voltage I/O port/VFD segment output)
P45/FS21 (high-voltage I/O port/VFD segment output)
P44/FS20 (high-voltage I/O port/VFD segment output)
P43/FS19 (high-voltage I/O port/VFD segment output)
P42/FS18 (high-voltage I/O port/VFD segment output)
P41/FS17 (high-voltage I/O port/VFD segment output)
EA9
NC
NC
NC
NC
VCC
VCC
VSS
8
Table 1-2 List of Pin Functions (cont)
Pin No.
FP-64A
30
DP-64S
39
Name and Function
PROM Mode
VSS
P40/FS16 (high-voltage I/O port/VFD segment output)
P50/FS15 (high-voltage I/O port/VFD segment output)
P51/FS14 (high-voltage I/O port/VFD segment output)
P52/FS13 (high-voltage I/O port/VFD segment output)
P53/FS12 (high-voltage I/O port/VFD segment output)
P54/FS11 (high-voltage I/O port/VFD segment output)
P55/FS10 (high-voltage I/O port/VFD segment output)
P56/FS9 (high-voltage I/O port/VFD segment output)
P57/FS8 (high-voltage I/O port/VFD segment output)
P17/Vdisp (high-voltage input port/VFD power source)
31
40
EA0
32
41
EA1
33
42
EA2
34
43
EA3
35
44
EA4
36
45
EA5
37
46
EA6
38
47
EA7
39
48
VCC
40
49
P60/FD0/FS7 (high-voltage I/O port/VFD digit-segment
output)
NC
41
42
43
44
45
46
47
50
51
52
53
54
55
56
P61/FD1/FS6 (high-voltage I/O port/VFD digit-segment
output)
NC
NC
NC
NC
NC
NC
NC
P62/FD2/FS5 (high-voltage I/O port/VFD digit-segment
output)
P63/FD3/FS4 (high-voltage I/O port/VFD digit-segment
output)
P64/FD4/FS3 (high-voltage I/O port/VFD digit-segment
output)
P65/FD5/FS2 (high-voltage I/O port/VFD digit-segment
output)
P66/FD6/FS1 (high-voltage I/O port/VFD digit-segment
output)
P67/FD7/FS0 (high-voltage I/O port/VFD digit-segment
output)
48
49
50
57
58
59
P70/FD8 (high-voltage I/O port/VFD digit output)
P71/FD9 (high-voltage I/O port/VFD digit output)
P72/FD10 (high-voltage I/O port/VFD digit output)
EA8
OE
EA10
9
Table 1-2 List of Pin Functions (cont)
Pin No.
FP-64A
51
DP-64S
Name and Function
PROM Mode
EA11
EA12
EA13
EA14
CE
60
61
62
63
64
1
P73/FD11 (high-voltage I/O port/VFD digit output)
P74/FD12 (high-voltage I/O port/VFD digit output)
P75/FD13 (high-voltage I/O port/VFD digit output)
P76/FD14 (high-voltage I/O port/VFD digit output)
P77/FD15 (high-voltage I/O port/VFD digit output)
VCC (system power source)
52
53
54
55
56
VCC
57
2
P90/PWM (standard I/O port/PWM output)
P91/SCK1 (standard I/O port/clock output)
P92/SI1 (standard I/O port/data input)
EO0
58
3
EO1
59
4
EO2
60
5
P93/SO1 (standard I/O port/data output)
P94/SCK2 (standard I/O port/clock I/O)
EO3
61
6
EO4
62
7
P95/SI2/CS (standard I/O port/data input/chip
select output)
EO5
63
64
1
8
P96/SO2 (standard I/O port/data output)
EO6
EO7
VCC
NC
9
P97/UD (standard I/O port/timer C up-down control)
AVCC (reference power source for A/D converter)
PO0/AN0 (standard input port/analog input channel)
PO1/AN1 (standard input port/analog input channel)
PO2/AN2 (standard input port/analog input channel)
PO3/AN3 (standard input port/analog input channel)
10
11
12
13
14
2
3
NC
4
NC
5
NC
Notes: 1. NC pins should be left unconnected.
2. Details on PROM mode are given in 4.2, PROM Mode.
10
2. Pin functions
Table 1-3 explains the functions of each pin in more detail.
Table 1-3 Pin Functions
Pin No.
Type
Symbol FP-64A DP-64S I/O
Name and Functions
Power
supply pins
VCC
56
14
1
1
Input Power source: Connects to a power
supply (+5 V)
All VCC pins should be connected to the
system power supply (+5 V).
VSS
23
10
Input Ground: Connects to a power supply
(0 V).
All VSS pins should be connected to the
system power supply (0 V).
AVCC
Input Analog power supply: This is the
reference power supply pin for the A/D
converter. When the A/D converter is not
used, connect this pin to the system
power supply (+5 V).
AVSS
10
19
Input Analog ground: This is the A/D
converter ground pin.
It should be connected to the system
power supply (0 V).
Vdisp
39
15
48
24
Input VFD power supply: This pin should be
connected to a VFD driver power supply.
Clock pins
OSC1
Input This pin connects to a crystal or ceramic
oscillator, or can be used to input an
external clock.
See section 6, Clock Pulse Generators,
for a typical connection diagram.
OSC2
X1
16
13
25
22
Output This pin connects to a crystal or ceramic
oscillator.
Input This pin connects to a 32.768 kHz crystal
oscillator.
For a typical connection diagram,
see section 6, Clock Pulse Generators.
X2
12
21
Output This pin connects to a 32.768 kHz crystal
oscillator.
11
Table 1-3 Pin Functions (cont)
Pin No.
Symbol FP-64A DP-64S I/O
Type
Name and Functions
System control
RES
17
26
Input Reset: When this pin goes to low level,
the chip is reset.
TEST
11
20
Input Test: This pin is not for use in
application systems. It should be
connected to VSS
.
Interrupt pins
IRQ0
18
27
Input External interrupt request 0: This is an
input pin for external interrupts for which
there is a choice between rising and
falling edge sensing. It can be used to
exit low-power mode.
This pin can be used as the event input
pin for timer B. A noise cancel function is
also provided.
IRQ1
19
28
Input External interrupt request 1: This is an
input pin for external interrupts for which
there is a choice between rising and
falling edge sensing. It can be used to
exit low-power mode.
This pin can be used as the event input
pin for timer C.
IRQ4
IRQ5
20
21
29
30
Input External interrupt request 4: This is an
input pin for external interrupts for which
there is a choice between rising and
falling edge sensing.
Input External interrupt request 5: This is an
input pin for external interrupts that are
detected at the falling edge.
12
Table 1-3 Pin Functions (cont)
Pin No.
Symbol FP-64A DP-64S I/O
Type
Name and Functions
Timer pins
IRQ0
IRQ1
UD
18
19
64
27
28
9
Input Timer B event counter input: This is
an event input pin for input to the timer B
counter.
Input Timer C event counter input: This is
an event input pin for input to the timer C
counter.
Input Timer C up/down select: This pin
selects whether the timer C counter is
used for up- or down-counting. At high
level it selects down-counting, and at low
level up-counting.
Input to this pin is valid only when bit
TMC6 in timer mode register C (TMC) is
set to 1.
EVENT 22
31
30
2
Input Timer D event counter input: This is
an event input pin for input to the timer D
counter.
TMOE
PWM
21
57
Output Timer E output: This is an output pin for
waveforms generated by the timer E
output circuit.
14-bit PWM pin
Output 14-bit PWM output: This is an output
pin for waveforms generated by the
14-bit PWM.
Serial
SO1
SO2
60
63
5
8
Output Serial transmit data output (channels 1
and 2): These are SCI data output pins.
communication
interface (SCI)
pins
SI1
SI2
59
62
4
7
Input Serial receive data input (channels 1
and 2): These are SCI data input pins.
SCK1
SCK2
58
61
3
6
I/O
Serial clock I/O (channels 1 and 2):
These are SCI clock I/O pins.
CS
62
7
Output Chip select output: When SCI2 is in
transmit mode and the serial clock is an
internal clock, this pin goes low.
This function is valid when bit SI2 in port
mode register 2 (PMR2) is 1 and the CS
bit in PMR3 is 1.
13
Table 1-3 Pin Functions (cont)
Pin No.
Symbol FP-64A DP-64S I/O
Type
Name and Functions
18 to 11 Input Port 0: This is an 8-bit input port.
I/O ports
P07 to
P00
9 to 2
P17
39
48
31
Input Port 1 (bit 7): This is a 1-bit high-
voltage input pin.
P16
22
Input Port 1 (bit 6): This is a 1-bit input pin.
P15, P14, 21 to 18 30 to 27 I/O
P11, P10
Port 1: This is a 4-bit group of I/O pins.
Input or output can be designated for
each bit by means of port control
register 1 (PCR1).
P47 to
P40
23 to 30 32 to 39 I/O
38 to 31 47 to 40 I/O
47 to 40 56 to 49 I/O
55 to 48 64 to 57 I/O
Port 4: This is an 8-bit high-voltage I/O
port.
P57 to
P50
Port 5: This is an 8-bit high-voltage I/O
port.
P67 to
P60
Port 6: This is an 8-bit high-voltage I/O
port.
P77 to
P70
Port 7: This is an 8-bit high-voltage I/O
port.
P97 to
P90
64 to 57 9 to 2
I/O
Port 9: This is an 8-bit I/O port. Input or
output can be designated for each bit by
means of PCR9.
A/D converter
AN7 to
AN0
9 to 2
18 to 11 Input Analog input channels 7 to 0: These
are analog data input channels to the
A/D converter.
VFD controller/
driver
FD15 to 55 to 40 64 to 49 Output VFD digit output: These are digit output
FD0
pins from the VFD controller/driver.
FS23 to
FS8
23 to 38 32 to 47 I/O
40 to 47 49 to 56
VFD segment output: These are
segment output pins from the VFD
controller/driver. When a key scan
interval is set during display operations,
these pins can be used by the CPU
during this interval as general-purpose
I/O ports.
FS7 to
FS0
14
Section 2 CPU
2.1 Overview
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise, optimized instruction set is designed for high-speed operation.
2.1.1 Features
The main features of the H8/300L CPU are listed below.
•
•
General-register architecture
— Sixteen 8-bit general registers, also usable as eight 16-bit general registers
Instruction set with 55 basic instructions, including:
— Multiply and divide instructions
— Powerful bit-manipulation instructions
•
Eight addressing modes
— Register direct
Rn
— Register indirect
@Rn
— Register indirect with displacement
@(d:16, Rn)
— Register indirect with post-increment or pre-decrement @Rn+ or @–Rn
— Absolute address
— Immediate
— Program-counter relative
— Memory indirect
@aa:8 or @aa:16
#xx:8 or #xx:16
@(d:8, PC)
@@aa:8
•
•
64-kbyte address space
High-speed operation
— All frequently used instructions are executed in two to four states
— High-speed arithmetic and logic operations
— 8- or 16-bit register-register add or subtract: 0.5 µs*
— 8 × 8-bit multiply:
— 16 ÷ 8-bit divide:
3.5 µs*
3.5 µs*
•
Low-power operation modes
— SLEEP instruction for transfer to low-power operation
Note: * These values are at φ = 4 MHz.
15
2.1.2 Address Space
The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and
data.
The memory map varies with the ROM size. Figure 2-1 gives memory map.
H8/3712
H8/3713
H8/3714
H'0000
H'002B
Interrupt vectors
(44 bytes)
16 kbytes
(16,384)
24 kbytes
(24,576)
On-chip ROM
32 kbytes
(32,256)
H'3FFF
H'5FFF
H'7DFF
Reserved
H'FD80
H'FE00
On-chip RAM
H'FFC0
512 bytes
Used also for VFD
384 bytes
384 bytes
display RAM (64 bytes)
H'FEFF
H'FF00
On-chip RAM
(128 bytes)
H'FF7F
H'FF80
H'FF9F
H'FFA0
H'FFA3
H'FFA4
H'FFAF
H'FFB0
32-byte data buffer
Internal I/O registers
(4 bytes)
Reserved
Internal I/O registers
(80 bytes)
H'FFFF
Figure 2-1 Memory Map
16
2.1.3 Register Configuration
Figure 2-2 shows the register structure of the H8/300L CPU. There are two groups of registers: the
general registers and control registers.
General registers (Rn)
7
0 7
0
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
SP: Stack pointer
(SP)
PC
Control registers
15
0
PC: Program counter
7 6 5 4 3 2 1 0
CCR I U H U N Z V C
CCR: Condition code register
Carry flag
Overflow flag
Zero flag
Negative flag
Half-carry flag
Interrupt mask bit
User bit
User bit
Figure 2-2 CPU Registers
17
2.2 Register Descriptions
2.2.1 General Registers
All the general registers can be used as both data registers and address registers.
When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing
and subroutine calls. When it functions as the stack pointer, as indicated in figure 2-3, SP (R7)
points to the top of the stack.
Lower address side [H'0000]
Unused area
SP (R7)
Stack area
Upper address side [H'FFFF]
Figure 2-3 Stack Pointer
2.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
1. Program Counter (PC): This 16-bit register indicates the address of the next instruction the
CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least
significant bit of the PC is ignored (always regarded as 0).
2. Condition Code Register (CCR): This 8-bit register contains internal status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V),
and carry (C) flags.
18
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1
automatically at the start of exception handling. The interrupt mask bit may be read and written
by software. For further details, see 3.2.2, Interrupts.
Bit 6—User Bit (U): Can be written and read by software (using the LDC, STC, ANDC, ORC,
and XORC instructions).
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0
otherwise.
The H flag is used implicitly by the DAA and DAS instructions.
When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and is cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software (using the LDC, STC, ANDC, ORC,
and XORC instructions).
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
•
•
•
Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged. The LDC, STC, ANDC, ORC, and
XORC instructions enable the CPU to load and store the CCR, and to set or clear selected bits by
logic operations. The N, Z, V, and C flags are used as branching conditions for conditional
branching (Bcc) instructions.
Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag
bits.
19
2.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is initialized to the value stored at address
H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general
registers are not initialized. In particular, the stack pointer (R7) is not initialized. To prevent
program crashes the stack pointer should be initialized by software, by the first instruction
executed after a reset.
2.3 Data Formats
The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
•
Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand
(n = 0, 1, 2, ..., 7).
•
•
All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
•
The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in
packed BCD form. Each nibble of the byte is treated as a decimal digit.
20
2.3.1 Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 2-4.
Data Type Register No.
Data Format
7
0
1-bit data
RnH
RnL
7
6
5
4
3
2
1
0
Don’t care
7
0
1-bit data
Don’t care
7
6
5
4
3
2
1
0
7
0
Byte data
RnH MSB
LSB
Don’t care
7
0
Byte data
RnL
Don’t care
MSB
LSB
15
0
Word data
4-bit BCD data
Rn
MSB
LSB
7
4
3
0
Upper digit
Lower digit
RnH
RnL
Don’t care
7
4
3
0
Upper digit
Lower digit
4-bit BCD data
Notation:
Don’t care
RnH: Upper digit of general register
RnL: Lower digit of general register
MSB: Most significant bit
LSB: Least significant bit
Figure 2-4 Register Data Formats
21
2.3.2 Memory Data Formats
Figure 2-5 indicates the data formats in memory. For access by the H8/300L CPU, word data
stored in memory must always begin at an even address. In word access the least significant bit of
the address is regarded as 0. If an odd address is specified, the access is performed at the
preceding even address. This rule affects the MOV.W instruction, and also applies to instruction
fetching.
Word access is possible to the ROM and RAM areas. For details, see 2.8.1, Notes on Data Access.
Data Type
Address
Data Format
7
0
1-bit data
Byte data
Address n
Address n
7
6
5
4
3
2
1
0
MSB
MSB
LSB
Upper 8 bits
Lower 8 bits
Even address
Odd address
Word data
Byte data (CCR) on stack
Word data on stack
LSB
MSB
MSB
CCR
LSB
LSB
Even address
Odd address
*
CCR
MSB
Even address
Odd address
LSB
Note: * Ignored on return
Notation:
CCR: Condition code register
Figure 2-5 Memory Data Formats
When the stack is accessed using R7 as an address register, word access should always be
performed. For further details, see 3.2.10, Notes on Stack Area Use. When the CCR is pushed on
the stack, two identical copies of the CCR are pushed to make a complete word. When they are
restored, the lower byte is ignored.
22
2.4 Addressing Modes
2.4.1 Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a
subset of these addressing modes.
Table 2-1 Addressing Modes
No.
1
Address Modes
Symbol
Rn
Register direct
2
Register indirect
@Rn
3
Register indirect with displacement
@(d:16, Rn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@Rn+
@–Rn
5
6
7
8
Absolute address
Immediate
@aa:8 or @aa:16
#xx:8 or #xx:16
@(d:8, PC)
Program-counter relative
Memory indirect
@@aa:8
1. Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
2. Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
3. Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word
(bytes 3 and 4) containing a displacement which is added to the contents of the specified
general register to obtain the operand address.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting
address must be even.
23
4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
•
Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
The register field of the instruction specifies a 16-bit general register containing the
address of the operand. After the operand is accessed, the register is incremented by 1 for
MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register
must be even.
•
Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is decremented
by 1 or 2 to obtain the address of the operand in memory. The register retains the
decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For
MOV.W, the original contents of the register must be even.
5. Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and
bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP,
and JSR instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range
is H'FF00 to H'FFFF (65280 to 65535).
6. Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its
second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W
instructions can contain 16-bit immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data.
Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte
of the instruction, specifying a bit number.
7. Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR
instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to
16 bits and added to the program counter contents to generate a branch destination address.
The possible branching range is –126 to +128 bytes (–63 to +64 words) from the current
address. The displacement should be an even number.
24
8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address. The word located at
this address contains the branch destination address.
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is
from H'0000 to H'00FF (0 to 255). Note that with the H8/3714 Series, addresses H'0000 to
H'002B (0 to 43) are located in the vector table.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at
the address preceding the specified address. See 2.3.2, Memory Data Formats, for further
information.
2.4.2 Effective Address Calculation
Table 2-2 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (5)
to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte.
The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to
specify the bit position.
25
26
27
28
2.5 Instruction Set
The H8/300L CPU can use a total of 55 instructions, which are grouped by function in table 2-3.
Table 2-3 Instruction Set
Function
Instructions
Types
1
Data transfer
MOV, PUSH*1, POP*1
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS,
SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG
14
Logic operations
Shift
AND, OR, XOR, NOT
4
8
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR,
ROTXL, ROTXR
Bit manipulation
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR,
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST
14
Branch
Bcc*2, JMP, BSR, JSR, RTS
RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
EEPMOV
5
8
1
System control
Block data transfer
Total: 55
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn.
2. Bcc is the generic designation of a conditional branch instruction.
The following sections give a concise summary of the instructions in each category, and indicate
the bit patterns of their object code. The notation used is defined next.
29
Notation
Rd
General register (destination)
General register (source)
General register
Destination operand
Source operand
Condition code register
N (negative) flag of CCR
Z (zero) flag of CCR
V (overflow) flag of CCR
C (carry) flag of CCR
Program counter
Stack pointer
Rs
Rn
(EAd) <EAd>
(EAs) <EAs>
CCR
N
Z
V
C
PC
SP
#IMM
disp
+
Immediate data
Displacement
Addition
–
Subtraction
×
Multiplication
÷
Division
AND logical
OR logical
Exclusive OR logical
Move
→
Inverse logic (logical complement)
3-bit length
:3
:8
8-bit length
:16
( ) < >
16-bit length
Contents of operand effective address
30
2.5.1 Data Transfer Instructions
Table 2-4 describes the data transfer instructions. Figure 2-6 shows their object code formats.
Table 2-4 Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @–Rn, and
@Rn+ addressing modes are available for byte or word data. The
@aa:8 addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not specify
byte size for these two modes.
PUSH
POP
W
W
Rn → @–SP
Pushes a 16-bit general register onto the stack. Equivalent to MOV.W
Rn, @–SP.
@SP+ → Rn
Pops a 16-bit general register from the stack. Equivalent to MOV.W
@SP+, Rn.
Notes: * Size: Operand size
B:
Byte
W:
Word
Certain precautions are required in data access. See 2.8.1, Notes on Data Access, for details.
31
15
15
15
8
8
8
7
7
7
0
0
0
MOV
op
rm
rn
rn
rn
Rm→Rn
op
rm
@Rm←→Rn
op
op
rm
rm
@(d:16, Rm)←→Rn
disp
15
15
15
8
8
8
7
7
7
0
0
0
@Rm+→Rn, or
Rn →@–Rm
rn
rn
op
rn
abs
@aa:8←→Rn
@aa:16←→Rn
op
abs
15
15
8
7
0
0
op
rn
IMM
#xx:8→Rn
8
7
op
rn
#xx:16→Rn
IMM
15
8
7
0
PUSH, POP
@SP+→Rn, or
Rn→@–SP
op
1
1
1
rn
Notation:
op: Operation field
rm, rn: Register field
disp: Displacement
abs:
Absolute address
IMM: Immediate data
Figure 2-6 Data Transfer Instruction Codes
32
2.5.2 Arithmetic Operations
Table 2-5 describes the arithmetic instructions. See figure 3-6 in section 3.5.4, Shift Operations
for their object codes.
Table 2-5 Arithmetic Instructions
Instruction
Size*
Function
ADD
SUB
B/W
Rd ± Rs → Rd, Rd + #IMM → Rd
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data
can be added or subtracted only when both words are in general
registers.
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data and
data in a general register.
INC
B
Rd ± 1 → Rd
DEC
Increments or decrements a general register.
ADDS
SUBS
W
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts immediate data to or from data in a general register.
The immediate data must be 1 or 2.
DAA
DAS
B
Rd decimal adjust → Rd
Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR.
MULXU
DIVXU
CMP
B
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result.
B
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.
B/W
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets the CCR according to the
result. Word data can be compared only between two general
registers.
NEG
B
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register.
Notes: * Size: Operand size
B:
Byte
W:
Word
33
2.5.3 Logic Operations
Table 2-6 describes the four instructions that perform logic operations.
Table 2-6 Logic Operation Instructions
Instruction
Size*
Function
AND
B
Rd Rs → Rd,
Rd #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B
B
B
Rd Rs → Rd,
Rd #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
NOT
Rd Rs → Rd,
Rd #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
~ Rd → Rd
Obtains the one’s complement (logical complement) of general register
contents.
Notes: * Size: Operand size
B: Byte
2.5.4 Shift Operations
Table 2-7 describes the eight shift instructions.
Table 2-7 Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B
Rd shift → Rd
Performs an arithmetic shift operation on general register contents.
Rd shift → Rd
SHLL
SHLR
B
B
B
Performs a logical shift operation on general register contents.
Rd rotate → Rd
ROTL
ROTR
Rotates general register contents.
Rd rotate through carry → Rd
ROTXL
ROTXR
Rotates general register contents through the C (carry) bit.
Notes: * Size: Operand size
B: Byte
34
Figure 2-7 shows the instruction code format of arithmetic, logic, and shift instructions.
15
15
15
15
15
15
15
8
8
8
8
8
8
8
7
7
7
7
7
7
7
0
0
0
0
0
0
0
ADD, SUB, CMP,
ADDX, SUBX (Rm)
op
op
op
rm
rm
rm
rn
rn
rn
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
op
rn
MULXU, DIVXU
ADD, ADDX, SUBX,
CMP (#XX:8)
op
IMM
IMM
rn
rn
AND, OR, XOR (Rm)
AND, OR, XOR (#xx:8)
op
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
op
Notation:
op: Operation field
rm, rn: Register field
IMM: Immediate data
Figure 2-7 Arithmetic, Logic, and Shift Instruction Codes
35
2.5.5 Bit Manipulations
Table 2-8 describes the bit-manipulation instructions. Figure 2-8 shows their object code formats.
Table 2-8 Bit-Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
BNOT
BTST
B
B
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit number
is specified by 3-bit immediate data or the lower three bits of a general
register.
~ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or clears
the zero flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
B
C
(<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
and stores the result in the carry flag.
BIAND
C
[~ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
B
B
C
(<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
and stores the result in the carry flag.
BIOR
C
[~ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general
register or memory and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Notes: * Size: Operand size
B: Byte
36
Table 2-8 Bit-Manipulation Instructions (cont)
Instruction
Size*
Function
BXOR
B
C
(<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
and stores the result in the carry flag.
BIXOR
B
C
~ [(<bit-No.> of <EAd>)] → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
(<bit-No.> of <EAd>) → C
BLD
B
B
Copies a specified bit in a general register or memory to the carry flag.
~ (<bit-No.> of <EAd>) → C
BILD
Copies the inverse of a specified bit in a general register or memory to
the carry flag.
The bit number is specified by 3-bit immediate data.
C → (<bit-No.> of <EAd>)
BST
B
B
Copies the carry flag to a specified bit in a general register or memory.
~ C → (<bit-No.> of <EAd>)
BIST
Copies the inverse of the carry flag to a specified bit in a general
register or memory.
The bit number is specified by 3-bit immediate data.
Notes: * Size: Operand size
B: Byte
Certain precautions are required in bit manipulation. See 2.8.2, Notes on Bit Manipulation, for
details.
37
BSET, BCLR, BNOT, BTST
15
15
15
8
8
8
7
7
7
0
0
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
op
IMM
rn
rn
Operand: register direct (Rn)
Bit No.: register direct (Rm)
op
rm
0
op
op
rn
IMM
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
0
15
15
15
8
8
8
7
7
7
0
op
op
rn
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: register direct (Rm)
rm
0
0
op
abs
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
op
IMM
0
0
0
0
0
0
0
op
op
abs
Operand: absolute (@aa:8)
Bit No.: register direct (Rm)
rm
0
0
BAND, BOR, BXOR, BLD, BST
15
15
8
8
7
7
0
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
op
IMM
rn
0
op
op
rn
IMM
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
0
15
8
7
0
op
op
abs
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
IMM
0
0
0
0
Notation:
op:
rm, rn: Register field
abs: Absolute address
IMM: Immediate data
Operation field
Figure 2-8 Bit Manipulation Instruction Codes
38
BIAND, BIOR, BIXOR, BILD, BIST
15
15
8
8
7
7
0
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
op
IMM
rn
0
op
op
rn
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
IMM
0
15
8
7
0
op
op
abs
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
IMM
0
0
0
0
Notation:
op:
rm, rn: Register field
abs: Absolute address
IMM: Immediate data
Operation field
Figure 2-8 Bit Manipulation Instruction Codes (cont)
39
2.5.6 Branching Instructions
Table 2-9 describes the branching instructions.
Table 2-9 Branching Instructions
Instruction
Size
Function
Bcc
—
Branches to the designated address if condition cc is true. The branching
conditions are given below.
Mnemonic
BRA (BT)
BRN (BF)
BHI
Description
Always (true)
Never (false)
High
Condition
Always
Never
C
C
Z = 0
Z = 1
BLS
Low or same
Carry clear (high or same)
Carry set (low)
Not equal
BCC (BHS)
BCS (BLO)
BNE
C = 0
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
BEQ
Equal
BVC
Overflow clear
Overflow set
Plus
BVS
BPL
BMI
Minus
BGE
Greater or equal
Less than
N
N
Z
Z
V = 0
BLT
V = 1
BGT
Greater than
Less or equal
(N V) = 0
(N V) = 1
BLE
JMP
JSR
BSR
—
—
—
Branches unconditionally to a specified address.
Branches to a subroutine at a specified address.
Branches to a subroutine at a specified displacement from the current
address.
RTS
—
Returns from a subroutine.
40
15
15
15
8
8
8
7
7
7
0
op
cc
disp
Bcc
0
op
rm
0
0
0
0
JMP (@Rm)
0
op
abs
JMP (@aa:16)
15
15
15
15
8
7
7
7
7
0
0
op
abs
JMP (@@aa:8)
BSR
8
8
8
op
disp
0
op
rm
0
0
0
0
JSR (@Rm)
0
op
abs
JSR (@aa:16)
15
15
8
7
0
0
op
abs
JSR (@@aa:8)
RTS
8
7
op
Notation:
op: Operation field
cc: Condition field
rm: Register field
disp: Displacement
abs: Absolute address
Figure 2-9 Branching Instruction Codes
41
2.5.7 System Control Instructions
Table 2-10 describes the system control instructions. Figure 2-10 shows their object code formats.
Table 2-10 System Control Instructions
Instruction
RTE
Size*
—
Function
Returns from an exception-handling routine.
SLEEP
—
Causes a transition from active mode to a power-down mode (sleep
mode, standby mode, or watch mode), or from subactive mode to watch
mode, or from subactive mode via watch mode to active mode. For
details, see 3.3, System Modes.
LDC
B
Rs → CCR, #IMM → CCR
Moves immediate data or general register contents to the condition code
register.
STC
B
B
B
B
—
CCR → Rd
Copies the condition code register to a specified general register.
CCR #IMM → CCR
ANDC
ORC
XORC
NOP
Logically ANDs the condition code register with immediate data.
CCR #IMM → CCR
Logically ORs the condition code register with immediate data.
CCR #IMM → CCR
Logically exclusive-ORs the condition code register with immediate data.
PC + 2 → PC
Only increments the program counter.
Notes: * Size: Operand size
B: Byte
42
15
15
15
8
8
8
7
7
7
0
0
0
op
RTE, SLEEP, NOP
LDC, STC (Rn)
op
rn
ANDC, ORC,
XORC, LDC (#xx:8)
op
IMM
Notation:
op: Operation field
rn: Register field
IMM: Immediate data
Figure 2-10 System Control Instruction Codes
2.5.8 Block Data Transfer Instruction
Table 2-11 describes the block data transfer instruction. Figure 2-11 shows its object code format.
Table 2-11 Block Data Transfer Instruction
Instruction
Size
Function
If R4L ≠ 0 then
repeat
EEPMOV
—
@R5+ → @R6+
R4L – 1 → R4L
R4L = 0
until
else next;
Moves a data block according to parameters set in general registers R4L,
R5, and R6.
R4L: Size of block (bytes)
R5: Starting source address
R6: Starting destination address
Execution of the next instruction starts as soon as the block transfer is
completed.
43
15
8
7
0
op
op
Notation:
op: Operation field
Figure 2-11 Block Data Transfer Instruction Code
Notes on EEPMOV Instruction
1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
→
R5
←
←
R6
→
R5 + R4L
R6 + R4L
2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
→
R5
←
←
R6
H'FFFF
Not allowed
→
R5 + R4L
R6 + R4L
44
2.6 CPU States
2.6.1 Overview
There are three CPU states: program execution state, program halt state, and exception-handling
state. Program execution state includes active mode and subactive mode. In program halt state
there are sleep mode, standby mode, and watch mode. These states are shown in figure 2-12.
Figure 2-13 shows the state transitions.
Program
execution state
State
Active mode
The CPU executes successive program
instructions, synchronized by the system clock.
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock.
operation
Low-power
modes
Program halt state
Sleep mode
A state in which CPU
operations are
stopped to conserve
power.
Standby mode
Watch mode
Exception-
handling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt.
Figure 2-12 CPU Operation States
45
Reset cleared
Reset occurs
Reset state
Exception-handling state
Reset
Interrupt
occurs
Reset
Exception- Exception-
occurs
handling
request
handling
ends
Program halt state
Program execution state
SLEEP instruction executed
Note: On the transitions between modes, see 3.3, System Modes.
Figure 2-13 State Transitions
2.6.2 Program Execution State
In the program execution state the CPU executes program instructions in sequence.
There are two modes in this state, active mode and subactive mode. Operation is synchronized
with the system clock in active mode, and with a subclock in subactive mode. For details on these
modes, see 3.3, System Modes.
2.6.3 Program Halt State
In the program halt state there are three modes: sleep mode, standby mode, and watch mode. For
details on these modes, see 3.3, System Modes.
2.6.4 Exception-Handling State
The exception-handling state is a transient state occurring when exception handling is started by a
reset or interrupt, and the CPU changes its normal processing flow. In exception handling caused
by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.
For details on interrupt handling, see 3.2.2, Interrupts.
46
2.7 Basic Operation Timing
CPU operation is synchronized by a clock (φ ). φ is either the system clock (φ) generated by the
i
i
system clock oscillator circuit, or the subclock (φ ) generated by the subclock oscillator circuit.
SUB
φ denotes φ in active mode and φ
in subactive mode. For details, see section 6, Clock Pulse
i
SUB
Generators. The period from the rising edge of φ to the next rising edge is called one state. A
i
memory cycle or bus cycle consists of two states; access to on-chip memory and to on-chip
peripheral modules always takes place in two states.
2.7.1 Access to On-Chip Memory (RAM, ROM)
Two-state access is employed for on-chip memory. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2-14 shows the on-chip memory access cycle.
Bus cycle
T1 state
T2 state
φi
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2-14 On-Chip Memory Access Cycle
47
2.7.2 Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states. The data bus width is 8 bits, so access is
made in byte size only. This means that two instructions must be used for a word size data access.
Figure 2-15 shows the on-chip peripheral module access cycle.
Bus cycle
T1 state
T2 state
φi
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2-15 On-Chip Peripheral Module Access Cycle
48
2.8 Application Notes
The following points are to be observed in using the H8/300L CPU.
2.8.1 Notes on Data Access
1. The address space of the H8/300L CPU includes some empty areas in addition to the RAM,
registers, and ROM areas available to the user. If these empty areas are mistakenly accessed
by an application program, the following results will occur.
Transfer from CPU to empty area:
The transferred data will be lost. This action may also cause the CPU to misoperate.
Transfer from empty area to CPU:
Unpredictiable data is transferred.
2. Internal data transfer to or from on-chip modules other than ROM and RAM areas makes use
of an 8-bit data width. If word access is attempted to these areas, the following results will
occur.
Word access from CPU to I/O register area:
Upper byte: Will be written to I/O register.
Lower byte: Transferred data will be lost.
Word access from I/O register to CPU:
Upper byte: Will be written to upper part of CPU register.
Lower byte: Data written to lower part of CPU register cannot be guaranteed.
Byte size instructions should therefore be used when transferring data to or from I/O registers
outside the on-chip ROM and RAM areas. Figure 2-16 shows the data size in which access
can be made with on-chip peripheral modules.
49
Access
Word Byte
H'0000
H'002B
Interrupt vector area
(44 bytes)
32,256
bytes*1
On-chip ROM
H'7DFF*1
H'FD80*2
On-chip RAM
(320 bytes)
H'FEC0
H'FF00
Used also for VFD
display RAM (64 bytes)
512
bytes*2
On-chip RAM
(128 bytes)
H'FF7F
H'FF80
32-byte data buffer
H'FF9F
H'FFA0
×
Internal I/O registers
(4 bytes)
H'FFA3
H'FFA4
H'FFAF
H'FFB0
×
×
×
Reserved
Internal I/O registers
(80 bytes)
H'FFFF
: Access possible
: Not possible
×
Notes: The above example is a description of the H8/3714.
1. The H8/3713 has 24,576 bytes of on-chip ROM, and its ending address is H'5FFF.
The H8/3712 has 16,384 bytes of on-chip ROM, and its ending address is H'3FFF.
2. The H8/3713 and H8/3712 each have 384 bytes of on-chip RAM, and their ending address
is H'FE00.
Figure 2-16 Data Size for Access to and from On-Chip Peripheral Modules
50
2.8.2 Notes on Bit Manipulation
The H8/300L CPU executes bit manipulation instructions by a read-modify-write operation on
8-bit data. When bit manipulation instructions are executed in the cases illustrated below, care
must be taken since the operation may affect other bits besides those being manipulated.
1. Bit manipulation in two registers assigned to the same address (when the source and
destination are different)
Example 1: Timer load register and timer counter
In this example, a bit manipulation instruction is executed in the timer load register and timer
counter of a reloadable timer. Since the timer load register and timer counter share the same
address, the operations take place as follows.
a. Read: The timer counter value at the time is read.
b. Modify: The CPU modifies (sets or resets) the bit designated with the instruction. (Other bits
remain the same.)
c. Write: The modified data is written to the timer load register.
The timer counter is counting based on the system clock (φ), so the value read is not necessarily
the same as the value in the timer load register. As a result, bits other than the intended bit in the
timer load register may be modified to the timer counter value.
Figure 2-17 shows the reloadable timer configuration.
R
φ
Timer counter
Reload
R: Read
W: Write
W
Timer load register
Figure 2-17 Reloadable Timer Configuration
Example 2: Port data register (pin input and data register)
When a bit manipulation instruction is executed designating a port data register, it may cause
changes in pin I/O states or data register contents other than the intended bit.
51
As noted above, the H8/300L CPU executes bit manipulation instructions by a read-modify-write
operation on 8-bit data. Since the same address is used for the I/O port data register and reading
of pin input, a bit manipulation instruction designating a port functions as follows.
① High-voltage pin: pin other than the modified bit
• When set as an input pin (data register = 0)
First the CPU reads the pin input level (read), then it sets or resets the designated bit
(modify; other bits remain the same), and writes that value to the data register (write). If
the input level is high (read data = 1), a value of 1 is written to the data register, changing
the input pin to an output pin (high-level output). If the input level is low, no change
occurs.
• When set as an output pin (data register = 1, high-level output)
If the output level is higher than the input high level (V ), there is no change.
IH
If the output level is lower than the input low level (V ), a value of 0 is written to the data
IL
register, so that the PMOS buffer transistor is turned off resulting in pull-down (low level)
or high-impedance state.
If the output level is pulled down by the load to an intermediate level, the resulting state is
indeterminate.
② Standard-voltage pin: pin other than the modified bit
•
When set as an input pin
The CPU reads the pin input level and writes that value to the data register, which may or
may not result in a change to the data register contents.
•
When set as an output pin
The data register is read, so no change occurs.
2. Bit manipulation in registers containing write-only bits
Example: PWM data registers, etc.
(Note that read and write characteristics can differ from bit to bit.)
Write-only bits cannot be read. Write-only bits other than the intended bit are set to 1.
52
Table 2-12 lists the registers that share the same address, while table 2-13 lists the registers that
contain write-only bits.
Table 2-12 Registers Assigned to the Same Address
Register Name
Abbreviation
TLB/TCB
TLC/TCC
TLE/TCE
PDR1
Address
H'FFC3
H'FFC5
H'FFC9
H'FFD1
H'FFD4
H'FFD5
H'FFD6
H'FFD7
H'FFD9
Timer load register B/timer counter B
Timer load register C/timer counter C
Timer load register E/timer counter E
Port data register 1*
Port data register 4*
PDR4
Port data register 5*
PDR5
Port data register 6*
PDR6
Port data register 7*
PDR7
Port data register 9*
PDR9
Note: * These port data registers are used also for pin input.
Table 2-13 Registers with Write-Only Bits
Register Name
Abbreviation
Address
H'FFB0
H'FFCC
H'FFCD
H'FFCE
H'FFE1
H'FFE9
H'FFEF
H'FFC6
H'FFF1
Serial mode register 1
PWM control register
SMR1
PWCR
PWDRU
PWDRL
PCR1
PWM data register U
PWM data register L
Port control register 1
Port control register 9
Port mode register 0
PCR9
PMR0
TMD
Timer mode register D*1
System control register 2*2
Notes: 1. Only bit CRL (bit 7) is write-only.
SYSCR2
2. Bit DTON (bit 3) is a write-only bit only in subactive mode. In active mode it cannot be
read or written.
53
54
Section 3 System Control
3.1 Overview
This section explains the reset state, exception handling, and system modes.
3.2 Exception Handling
Exception handling includes processing of reset exceptions and of interrupts. Table 3-1
summarizes the exception sources and their priorities. Reset exception handling has the highest
priority.
Table 3-1 Types of Exception Handling and Priorities
Priority
Exception Source
Timing for Start of Exception Handling
High
Reset
Reset exception handling starts as soon as RES pin changes
from low to high.
Interrupt
When interrupt request is made, interrupt exception handling
starts after execution of present instruction is completed.
Low
3.2.1 Reset
When the RES pin goes low, all processing stops and the chip enters the reset state. The internal
state of the CPU and the registers of on-chip peripheral modules are initialized. The I bit of the
condition code register (CCR) is set, masking all interrupts.
As soon as the RES pin goes from low to high, reset exception handling starts. The contents of
the reset vector address (H'0000 to H'0001) are read and loaded into the program counter (PC).
Then program execution starts from the address indicated in PC. Figure 3-1 shows the reset
sequence.
Notes: 1. To make sure a reset is carried out properly, when power is turned on the RES pin
should be kept low for at least 20 ms after the rise of the power supply.
2. When resetting during operation, keep the RES pin low for at least 10 system clock
cycles.
3. After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was
initialized, PC and CCR would not be pushed onto the stack correctly, resulting in
program runaway. To prevent this, immediately after reset exception handling all
interrupts are masked. Programs should be coded to initialize the stack pointer before
clearing the interrupt mask. An even-numbered address must be set in SP. It is
recommended that programs start with an instruction initializing SP (e.g., MOV.W
#xx:16, SP).
55
Reset state
Reset exception handling and program execution
Prefetch of
first instruction
Vector fetch
of program
Internal
processing
RES
φ
Internal
address bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program starting address
(3) First instruction of program
Figure 3-1 Reset Sequence
3.2.2 Interrupts
The interrupt sources include external interrupts (IRQ , IRQ , IRQ , IRQ ), and internal interrupts
5
4
1
0
requested from on-chip peripheral modules. Table 3-2 shows the interrupt sources, their priorities,
and their vector addresses. When more than one interrupt is requested, the interrupt with the
highest priority is processed.
The interrupts have the following features.
•
•
Both internal interrupts and external interrupts (IRQ , IRQ , IRQ , IRQ ), can be masked by
5 4 1 0
the I bit of CCR. When this bit is set to 1, interrupt request flags are set but interrupts are not
accepted.
External interrupt pins IRQ , IRQ , and IRQ can be set independently for rising-edge or
4
1
0
falling-edge sensing. For external interrupt pin IRQ , the falling edge is sensed.
5
56
Table 3-2 Interrupt Sources
Vector Starting
Address
Priority
Interrupt
Reset
Origin of Interrupt
External pin
—
High
H'0000
H'0002
H'0004
H'0006
H'0008
H'000A
H'000C
H'000E
H'0010
H'0012
H'0014
H'0016
H'0018
H'001A
H'001C
H'001E
H'0020
H'0022
H'0024
H'0026
H'0028
H'002A
(Reserved)*1
IRQ0
External pin
IRQ1
(Reserved)*1
(Reserved)*1
IRQ4
IRQ5
Key scan
VFD
Timer A overflow
Timer B overflow
Timer C overflow
Timer D overflow
Timer E overflow
Direct transfer
(Reserved)*1
Timer A
Timer B
Timer C
Timer D
Timer E
Standby timer activator*2
—
SCI1 transfer complete, error
SCI2 transfer complete, error
A/D conversion end
Serial communication interface 1
Serial communication interface 2
A/D converter
Low
Notes: 1. Vector addresses indicated as “Reserved” cannot be used.
2. This circuit is triggered by a SLEEP instruction and generates an interrupt after a certain
time.
57
3.2.3 Interrupt Control Registers
Table 3-3 lists the registers that are used to control interrupts.
Table 3-3 Interrupt Control Registers
Register Name
Abbreviation
PMR1
IEGR
R/W
R/W
R/W
R/W
R/W
R/W
R/W*
R/W*
R/W*
Initial Value
H'0C
Address
H'FFEB
H'FFF2
H'FFF3
H'FFF4
H'FFF5
H'FFF6
H'FFF7
H'FFF8
Port mode register 1
IRQ edge select register
Interrupt enable register 1
Interrupt enable register 2
Interrupt enable register 3
Interrupt request register 1
Interrupt request register 2
Interrupt request register 3
H'EC
IENR1
IENR2
IENR3
IRR1
H'C0
H'00
H'3C
H'C0
IRR2
H'00
IRR3
H'3C
Note: * Write is enabled only for writing of 0 to clear flag.
1. Port mode register 1 (PMR1)
Bit
7
6
5
4
3
—
1
2
—
1
1
0
NOISE
CANCEL
EVENT IRQC5 IRQC4
IRQC1 IRQC0
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
—
—
R/W
R/W
PMR1 is an 8-bit read/write register that designates whether pins in port 1 are used for general-
purpose I/O or for external interrupt input. It is also used to turn the noise canceller function of
pin IRQ on or off.
0
Note: Before switching a pin function by modifying bit IRQ5, IRQ4, IRQ1, or IRQ0 in PMR1,
first clear the interrupt enable flag to disable the interrupt. After the pin function has been
switched, issue any instruction, then clear the interrupt request flag to 0.
Program example:
MOV. B R0L, @IENR1
MOV. B R0L, @PMR1
NOP
MOV. B R0L, @IRR1
MOV. B R1L, @IENR1
...................... Disable interrupt
...................... Change pin function
...................... Issue any instruction
...................... Clear interrupt request flag
...................... Enable interrupt
58
Bit 7: Noise cancel (NOISE CANCEL)
This bit enables or disables the noise canceller function of pin IRQ .
0
Bit 7
NOISE CANCEL
Description
0
1
Disables the noise canceller function of pin IRQ0.
(initial value)
Enables the noise canceller function of pin IRQ0. Input is sampled at
intervals of 256 states. If two consecutive values do not match, the input is
regarded as noise.
Bit 6: P1 /EVENT pin function switch (EVENT)
6
Bit 6
EVENT
Description
0
1
P16/EVENT pin functions as P16 pin.
P16/EVENT pin functions as EVENT pin.
(initial value)
Bit 5: P1 /IRQ /TMOE pin function switch (IRQC5)
5
5
Bit 5
IRQC5
Description
0
1
P15/IRQ5/TMOE pin functions as P15/TMOE pin.*
P15/IRQ5/TMOE pin functions as IRQ5 pin.
(initial value)
Note: * For the TMOE usage of this pin, see 7.3.2, Port Mode Register 4 .
Bit 4: P1 /IRQ pin function switch (IRQC4)
4
4
Bit 4
IRQC4
Description
0
1
P14/IRQ4 pin functions as P14 pin.
P14/IRQ4 pin functions as IRQ4 pin.
(initial value)
Bits 3 and 2: Reserved bits
Bits 3 and 2 are reserved; they always read 1, and cannot be modified.
59
Bit 1: P1 /IRQ pin function switch (IRQC1)
1
1
Bit 1
IRQC1
Description
0
1
P11/IRQ1 pin functions as P11 pin.
P11/IRQ1 pin functions as IRQ1 pin.
(initial value)
Bit 0: P1 /IRQ pin function switch (IRQC0)
0
0
Bit 0
IRQC0
Description
0
1
P10/IRQ0 pin functions as P10 pin.
P10/IRQ0 pin functions as IRQ0 pin.
(initial value)
2. IRQ edge select register (IEGR)
Bit
7
—
1
6
—
1
5
—
1
4
IEG4
0
3
—
1
2
—
1
1
IEG1
0
0
IEG0
0
Initial value
Read/Write
—
—
—
R/W
—
—
R/W
R/W
IEGR is an 8-bit read/write register, used to designate rising edge sensing or falling edge sensing
for pins IRQ , IRQ , and IRQ .
0
1
4
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved; they always read 1, and cannot be modified.
Bit 4: IRQ pin input edge select (IEG4)
4
Bit 4
IEG4
Description
0
1
Falling edge of IRQ4 pin input is detected.
Rising edge of IRQ4 pin input is detected.
(initial value)
Bits 3 and 2: Reserved bits
Bits 3 and 2 are reserved; they always read 1, and cannot be modified.
60
Bit 1: IRQ pin input edge select (IEG1)
1
Bit 1
IEG1
Description
0
1
Falling edge of IRQ1 pin input is detected.
Rising edge of IRQ1 pin input is detected.
(initial value)
Bit 0: IRQ pin input edge select (IEG0)
0
Bit 0
IEG0
Description
0
1
Falling edge of IRQ0 pin input is detected.
Rising edge of IRQ0 pin input is detected.
(initial value)
3. Interrupt enable register 1 (IENR1)
Bit
7
—
1
6
—
1
5
IEN5
0
4
IEN4
0
3
—
2
—
1
IEN1
0
0
IEN0
0
Initial value
Read/Write
0
0
—
—
R/W
R/W
R/W
R/W
R/W
R/W
IENR1 is an 8-bit read/write register that enables or disables external interrupts.
Bits 7 and 6: Reserved bits
Bits 7 and 6 are reserved; they always read 1, and cannot be modified.
Bits 5 and 4: IRQ and IRQ interrupt enable (IEN5 and IEN4)
5
4
Bits 5 and 4
IEN5, IEN4
Description
0
1
Disables interrupt requests by IRRI5 and IRRI4.
Enables interrupt requests by IRRI5 and IRRI4.
(initial value)
Bits 3 and 2: Reserved bits
Bits 3 and 2 are reserved, but they can be written and read.
Bits 1 and 0: IRQ and IRQ interrupt enable (IEN1 and IEN0)
1
0
Bits 1 and 0
IEN1, IEN0
Description
0
1
Disables interrupt requests by IRRI1 and IRRI0.
Enables interrupt requests by IRRI1 and IRRI0.
(initial value)
61
4. Interrupt enable register 2 (IENR2)
Bit
7
—
6
—
5
4
3
2
1
0
IENDT IENTE IENTD IENTC
IENTB IENTA
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IENR2 is an 8-bit read/write register that enables or disables direct transfer interrupts and timer A
to E overflow interrupts.
Bits 7 and 6: Reserved bits
Bits 7 and 6 are reserved, but they can be written and read.
Bit 5: Direct transfer interrupt enable (IENDT)
Bit 5
IENDT
Description
0
1
Disables direct transfer interrupt requests by IRRDT.
Enables interrupt requests by IRRDT.
(initial value)
Bits 4 to 0: Timer E to A interrupt enable (IENTE to IENTA)
Bits 4 to 0
IENTE to IENTA
Description
0
1
Disables interrupt requests by IRRTE to IRRTA.
Enables interrupt requests by IRRTE to IRRTA.
(initial value)
5. Interrupt enable register 3 (IENR3)
Bit
7
IENAD
0
6
IENKS
0
5
—
1
4
—
1
3
—
1
2
—
1
1
0
IENS2 IENS1
Initial value
Read/Write
0
0
R/W
R/W
—
—
—
—
R/W
R/W
IENR3 is an 8-bit read/write register that enables or disables A/D converter, key scan, and serial
communication interface 1 and 2 interrupts.
62
Bit 7: A/D converter interrupt enable (IENAD)
Bit 7
IENAD
Description
0
1
Disables interrupt requests by IRRAD.
Enables interrupt requests by IRRAD.
(initial value)
Bit 6: Key scan interrupt enable (IENKS)
Bit 6
IENKS
Description
0
1
Disables interrupt requests by IRRKS.
Enables interrupt requests by IRRKS.
(initial value)
Bits 5 to 2: Reserved bits
Bits 5 to 2 are reserved; they always read 1, and cannot be modified.
Bits 1 and 0: Serial communication interface 2 and 1 interrupt enable (IENS2 and IENS1)
Bits 1 and 0
IENS2, IENS1
Description
0
1
Disables interrupt requests by IRRS2 and IRRS1.
Enables interrupt requests by IRRS2 and IRRS1.
(initial value)
6. Interrupt request register 1 (IRR1)
Bit
7
—
1
6
—
1
5
IRRI5
0
4
IRRI4
0
3
—
0
2
—
0
1
IRRI1
0
0
IRRI0
0
Initial value
Read/Write
*
*
*
*
R/W
—
—
R/W
R/W
—
—
R/W
Note: * Only 0 can be written, to clear the flag.
IRR1 is an 8-bit read/write register with flags that are set to 1 when an external interrupt is
requested.
Bits 7 and 6: Reserved bits
Bits 7 and 6 are reserved; they always read 1, and cannot be modified.
63
Bits 5 and 4: IRQ and IRQ interrupt request (IRRI5 and IRRI4)
5
4
Bits 5 and 4
IRRI5, IRRI4
Description
0
1
No interrupt request from the corresponding pin (IRQ5 or IRQ4). (initial value)
Setting condition: Set when the corresponding pin (IRQ5 or IRQ4) is
designated for interrupt input in PMR1 and the designated edge is input.
Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)
Bits 3 and 2: Reserved bits
Bits 3 and 2 are reserved; they always read 0, and cannot be modified.
Bits 1 and 0: IRQ and IRQ interrupt request (IRRI1 and IRRI0)
1
0
Bits 1 and 0
IRRI1, IRRI0
Description
0
1
No interrupt request from the corresponding pin (IRQ1 or IRQ0). (initial value)
Setting condition: Set when the corresponding pin (IRQ1 or IRQ0) is
designated for interrupt input in PMR1 and the designated edge is input.
Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)
7. Interrupt request register 2 (IRR2)
Bit
7
—
0
6
—
0
5
4
3
2
1
0
IRRDT IRRTE IRRTD IRRTC
IRRTB IRRTA
Initial value
Read/Write
0
0
0
0
0
0
*
*
*
*
*
*
R/W
—
—
R/W
R/W
R/W
R/W
R/W
Note: * Only 0 can be written, to clear the flag.
IRR2 is an 8-bit read/write register with flags that are set to 1 when a direct transfer interrupt or
timer A to E overflow interrupt is requested.
Bits 7 and 6: Reserved bits
Bits 7 and 6 are reserved; they always read 0, and only 0 may be written.
64
Bit 5: Direct transfer interrupt request (IRRDT)
Bits 5
IRRDT
Description
0
1
No direct transfer interrupt request.
(initial value)
Setting conditions: In subactive mode, when the system control register 2
(SYSCR2) DTON bit = 1, the system control register 1 (SYSCR1) LSON bit = 0,
and the interrupt enable register 2 (IENR2) IENDT bit = 1, execution of a SLEEP
instruction results in direct transfer to active mode via watch mode. During this
process a direct transfer interrupt is requested and the IRRDT flag is set to 1.
Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)
Bits 4 to 0: Timer E to A interrupt request (IRRTE to IRRTA)
Bits 4 to 0
IRRTE to IRRTA
Description
0
No overflow interrupt request from the corresponding timer
(E to A).
(initial value)
1
Setting conditions: When a timer E to A overflow interrupt is requested, the
corresponding flag (IRRTE to IRRTA ) is set to 1.
Clearing method: Cleared when software writes 0 in the flag. (The flag is
not automatically cleared when an interrupt is accepted.)
8. Interrupt request register 3 (IRR3)
Bit
7
6
5
—
1
4
—
1
3
—
1
2
—
1
1
0
IRRAD IRRKS
IRRS2 IRRS1
Initial value
Read/Write
0
0
0
0
*
*
*
*
R/W
R/W
R/W
—
—
—
—
R/W
Note: * Only 0 can be written, to clear the flag.
Bit 7: A/D conversion complete interrupt request (IRRAD)
Bit 7
IRRAD
Description
0
1
No A/D converter interrupt request.
(initial value)
Setting conditions: When the A/D converter completes A/D conversion, an interrupt
is requested and the IRRAD flag is set to 1.
Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)
65
Bit 6: Key scan interrupt request (IRRKS)
Bit 6
IRRKS
Description
0
1
No key scan interrupt request.
(initial value)
Setting conditions: When the VFD controller/driver requests a key scan interrupt,
the IRRKS flag is set to 1.
Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)
Bits 5 to 2: Reserved bits
Bits 5 to 2 are reserved; they always read 1, and cannot be modified.
Bits 1 and 0: Serial communication interface 2 and 1 interrupt request (IRRS2, IRRS1)
Bits 1, 0
IRRS2, IRRS1
Description
0
No transfer complete or error interrupt request by the
corresponding serial communication interface.
(initial value)
1
Setting conditions: When an interrupt is requested due to transfer complete or
error on serial communication interface 2 or 1, the corresponding flag (IRRS2 or
IRRS1) is set to 1.
Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)
3.2.4 External Interrupts
There are four external interrupts, IRQ , IRQ , IRQ , and IRQ . These interrupts are requested by
5
4
1
0
means of input signals at pins IRQ , IRQ , IRQ , and IRQ .
5
4
1
0
Interrupts IRQ , IRQ , and IRQ are detected by either rising edge sensing or falling edge
4
1
0
sensing, depending on the settings of bits IEG4, IEG1, and IEG0 in the IRQ edge select register
(IEGR). IRQ is detected by falling edge sensing only. In order to enable external interrupt input,
5
it is first necessary to set the corresponding bit in port mode register 1 (PMR1) to 1.
When the designated edge is input at pins IRQ , IRQ , IRQ , and IRQ , the corresponding flag in
5
4
1
0
interrupt request register 1 (IRR1) is set to 1. After the interrupt is accepted, the flag that was set
is not automatically cleared, so the interrupt handling routine must be programmed to clear the
flag to 0. A given interrupt request can be disabled by clearing its interrupt enable bit to 0.
Interrupts IRQ , IRQ , IRQ , and IRQ are enabled by setting bits IEN5, IEN4, IEN1, and IEN0
5
4
1
0
to 1 in interrupt enable register 1. All interrupts can be masked by setting the I bit in CCR to 1.
66
When an IRQ , IRQ , IRQ , or IRQ interrupt request is accepted, the I bit is set to 1. The order
5
4
1
0
of priority is from IRQ (high) to IRQ (low). For details see table 3-2.
0
5
A noise canceller function can be selected for IRQ interrupts, in which case a noise cancellation
0
circuit samples the IRQ input every 256 states. If two consecutive sampling results do not match,
0
noise is assumed and the request is not accepted.
3.2.5 Internal Interrupts
There are ten internal interrupts that can be requested by the on-chip peripheral modules. These
interrupts can be masked (held pending) by setting the I bit in CCR to 1. When an internal
interrupt request is accepted and the interrupt exception handling sequence is executed, the I bit is
set to 1. For the order of priority of interrupts from on-chip peripheral modules, see table 3-2.
3.2.6 Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the
interrupt controller, while figure 3-3 shows the flow up to interrupt acceptance.
Interrupt controller
IRQ5, IQR4, IRQ1, and
IRQ0 interrupt request
flags and internal
interrupt request flags
Interrupt
request
IRQ5, IQR4, IRQ1, and
IRQ0 interrupt enable
bits and internal
interrupt enable bits
I
CCR (CPU)
Figure 3-2 Block Diagram of Interrupt Controller
67
Program execution state
No
Interrupt
request?
Yes
No
IRQ0
Yes
14 interrupts
No
No
IRQ1
Yes
IRQ4
Yes
No
SCI2
Yes
A/D
Yes
No
Pending
I = 0
Yes
PC contents saved
CCR contents saved
I ← 1
Branch to interrupt
handling routine
Notation:
PC: Program counter
CCR: Condition code register
I:
I bit of CCR
Figure 3-3 Flow Up to Interrupt Acceptance
68
The following operations take place when an interrupt occurs.
1. When an interrupt is requested by external interrupt pin input or by a peripheral module, an
interrupt request signal is sent to the interrupt controller.
2. When the interrupt controller receives an interrupt request signal, it sets the interrupt request
flag.
3. From among the interrupts for which the corresponding interrupt enable bit is also set to 1,
the interrupt controller selects the interrupt request with the highest priority and holds the
others pending. (See table 3-2.)
4. The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.
5. If the interrupt is accepted, after processing of the current instruction is completed, both PC
and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4.
The PC value pushed onto the stack is the address of the first instruction to be executed upon
return from interrupt handling.
6. The I bit of CCR is set to 1, masking all further interrupts.
7. A vector address is generated for the accepted interrupt, and the contents of that address are
read and loaded into PC. Program execution then resumes from the address indicated in PC.
Note: No interrupt detection takes place immediately after completion of ORC, ANDC, XORC,
or LDC instructions.
69
SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
CCR
CCR*
PCH
PCL
Even address
Stack area
Prior to start of interrupt
exception handling
After completion of interrupt
exception handling
Contents
saved to stack
Notation:
PCH: Upper 8 bits of program counter (PC)
PCL: Lower 8 bits of program counter (PC)
CCR: Condition code register
SP: Stack pointer
1. PC shows the address of the first instruction to be executed upon
return from the interrupt.
Notes:
2. Saving and restoring of register contents must always be done
in word size, and must start from an even-numbered address.
* Ignored on return from interrupt.
Figure 3-4 Stack State after Completion of Interrupt Exception Handling
Figure 3-5 shows a typical interrupt sequence.
70
Figure 3-5 Interrupt Sequence
71
3.2.7 Return from an Interrupt
After completion of interrupt handling, the handler routine ends by executing an RTE instruction,
to resume the original program from the point the interrupt. When RTE is executed, the values
saved on the stack are restored to CCR and PC as shown in figure 3-6. Instruction execution
resumes from the address indicated in PC.
(Processing of RTE instruction)
(Stack state)
Memory contents of address
indicated in SP are sent to CCR.
CCR
CCR*
PCH
CCR
CCR*
PCH
SP (R7)
SP – 4
SP – 3
SP value +2
SP + 1
SP + 2
SP + 3
SP + 4
Stack
area
SP – 2
SP – 1
SP (R7)
Memory contents of address
indicated in SP are sent to PC.
PCL
PCL
Stack
area
SP value +2
CCR and PC
values restored
Before RTE instruction is executed
Note: Ignored on return from interrupt.
After RTE instruction is executed
Figure 3-6 Stack State When RTE Instruction is Executed
3.2.8 Interrupt Response Time
Table 3-4 shows the number of wait states after an interrupt request flag is set and until the first
instruction of the interrupt handler is executed.
Table 3-4 Interrupt Wait States
No.
1
Item
States
Waiting time for completion of current instruction*
1 to 13
2
Saving of PC and CCR to stack
Vector fetch
4
3
2
4
Instruction fetch
Internal processing
Total
4
5
4
15 to 27
Note: * Not including EEPMOV instruction.
72
3.2.9 Valid Interrupts in Each Mode
Table 3-5 shows the valid interrupts in each mode. For details of the modes, see 3.3, System
Modes.
Table 3-5 Valid Interrupts in Each Mode
Mode
Interrupt
Active
Sleep
Standby
Watch
Subactive
IRQ0
❍
❍
❍
❍
❍
❍
❍
❍
❍
❍
×
❍
❍
×
×
×
❍
×
×
×
×
×
×
×
×
❍
❍
×
×
×
×
×
×
×
×
×
×
×
×
❍
×
×
×
×
❍
×
×
×
×
×
×
×
×
❍
×
×
×
×
❍
×
×
×
×
∆
×
×
×
IRQ1
IRQ4
IRQ5
Key scan
Timer A overflow
Timer B overflow
Timer C overflow
Timer D overflow
Timer E overflow
Direct transfer
SCI1 transfer complete or error
SCI2 transfer complete or error
A/D conversion end
❍
❍
❍
Note: The above table does not include interrupts occurring during a mode transition.
Notation:
❍: When an interrupt request flag is set, interrupt exception handling is started if the I bit = 0 in
CCR and the interrupt enable bit = 1 for that interrupt. In sleep mode, standby mode, and
watch mode, a mode transition takes place before interrupt exception handling starts.
∆: When a SLEEP instruction is executed while the DTON bit = 1 and the LSON bit = 0, first a
transition is made to watch mode and the interrupt request flag is set in synchronization with
the subclock. When the interrupt request flag is set, if the interrupt enable flag = 1 for that
interrupt and the I bit = 0 in CCR, a transition is made to active mode and interrupt exception
handling starts.
×: The interrupt request flag is not set, and no mode transition occurs.
73
3.2.10 Notes on Stack Area Use
When word data is accessed in the H8/300L Series, the least significant bit of the address is
regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7)
should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W
@SP+, Rn) to save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3-7.
PCH
PCL
R1L
PCL
H'FEFC
H'FEFD
SP
SP
H'FEFF
SP
BSR instruction
MOV.B R1L, @–R7
SP set to H'FEFF
Notation:
Stack accessed beyond SP
Contents of PCH are lost
PCH: Upper byte of program counter
PCL: Lower byte of program counter
R1L: General register R1L
SP: Stack pointer
Figure 3-7 CPU Operation When Odd Address is Set in SP
Word access is also performed when the condition code register (CCR) is saved and restored by
the interrupt exception-handling sequence and RTE instruction. When CCR is saved, the CCR
value is saved in both the upper and lower bytes of the word data. When CCR is restored, it is
loaded with the value at the even address. The value at the odd address is ignored.
74
3.3 System Modes
The H8/300L CPU is equipped with power-down modes for minimizing power dissipation. These
and the other system modes are described below. There are five modes altogether, as follows.
•
•
•
•
•
Active mode
Sleep mode
Standby mode
Watch mode
Subactive mode
Low-power operation modes
Figure 3-8 shows the transitions among these modes.
SSBY = 1 and TMA3 = 1
and SLEEP instruction
SSBY = 0
and SLEEP
instruction
Active mode
LSON = 0 and IRQ0,
or LSON = 0 and
time base*
IRQ0 or IRQ1
or timer A
Sleep mode
Watch mode
IRQ0 or IRQ1
DTON = 0
SSBY = 1 and
TMA3 = 0 and
SLEEP
and SLEEP
instruction
LSON = 0 and
DTON = 1 and
LSON = 1 and
SLEEP instruction
instruction
IRQ0, or LSON =
1 and time base*
Subactive
mode
Standby mode
RES
RES
RES
RES
RES
Reset
Note: * Time base: Timer A interrupt during time-base operation running on subclock.
Figure 3-8 System Mode Transition Diagram
75
3.3.1 Active Mode
In active mode, the CPU executes instructions in synchronization with the system clock.
3.3.2 Low-Power Operation Mode
The H8/300L CPU supports four low-power operation modes: sleep mode, standby mode, watch
mode, and subactive mode. These modes are described below.
Sleep mode:
Sleep mode is entered by executing a SLEEP instruction while the SSBY bit
in system control register 1 (SYSCR1) is cleared to 0. As soon as the SLEEP
instruction has been executed, the CPU and on-chip peripheral modules halt
operation, except for timer A. The contents of the internal registers of the
CPU and on-chip peripheral modules, as well as the RAM contents, are
retained.
Standby mode:
Standby mode is entered by executing a SLEEP instruction while the SSBY
bit in system control register 1 (SYSCR1) is set to 1 and timer mode register
A (TMA) bit TMA3 = 0. In this mode, the CPU, system clock, and on-chip
peripheral modules halt all operations. Output from the on-chip peripheral
modules is reset; but as long as a minimum required voltage is applied, the
contents of the internal registers of the CPU and on-chip peripheral modules,
as well as the RAM contents, are retained. Standard I/O ports go to the high-
impedance state. In high-voltage ports, the PMOS buffer transistors are
switched off.
Watch mode:
Watch mode is entered by executing a SLEEP instruction while the SSBY bit
in system control register 1 (SYSCR1) is set to 1 and timer mode register A
(TMA) bit TMA3 = 1. In this mode, the CPU, system clock, and on-chip
peripheral modules halt, except for timer A. Output from the on-chip
peripheral modules is reset; but as long as a minimum required voltage is
applied, the contents of the internal registers of the CPU and on-chip
peripheral modules, as well as the RAM contents, are retained. Standard I/O
ports go to the high-impedance state. In high-voltage ports, the PMOS buffer
transistors are switched off.
Subactive mode: Subactive mode is entered when a time base or IRQ interrupt request is
0
accepted in watch mode while the LSON bit in system control register 1
(SYSCR1) is set to 1. In this mode the CPU operates in synchronization with
the subclock. On-chip peripheral modules halt operation, except for the time-
base function of timer A. Output from the on-chip peripheral modules is
reset; but as long as a minimum required voltage is applied, the contents of the
internal registers of the on-chip peripheral modules are retained. Standard I/O
ports go to the high-impedance state. In high-voltage ports, the PMOS buffer
transistors are switched off.
76
Table 3-6 shows the internal states in each mode.
Table 3-6 Internal States in Operation Modes
Function
Active
Sleep
Standby
Watch
Subactive
System clock
Subclock
Functions Functions Halted
Halted
Halted
Functions Functions Functions Functions Functions
CPU operation
Instructions
RAM
Functions Halted
Halted
Halted
Functions
Functions
Functions
Functions Retained Retained
Functions Retained Retained
Retained
Retained
Registers
I/O
Functions Retained Retained*1 Retained*1 Functions*1, *2
Functions Functions Functions Functions Functions
Peripheral module
interrupts
IRQ0
IRQ1
Functions Functions Functions Retained
Retained
Retained
IRQ4, IRQ5
Timer A
Timer B
Timer C
Timer D
Timer E
SCI1, SCI2
VFD
Functions Retained Retained
Functions Functions Retained
Functions Retained Retained
Functions Retained Retained
Functions Retained Retained
Functions Retained Retained
Functions Retained Retained
Functions Retained Retained
Retained
Functions*3 Functions*3
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
(output is
reset)
(output is (output is (output is
reset)
reset)
reset)
PWM
A/D
Functions Retained Retained
Retained
Retained
(output is
reset)
(output is (output is (output is
reset)
reset)
reset)
Functions Retained Retained
Retained
Retained
Notes: 1. Register contents are retained; output goes to high-impedance state.
2. Input (read) functions.
3. Functions when the time base function is selected.
77
1. Sleep mode
Operation in sleep mode is described below.
•
Transition to sleep mode
The system goes from active mode to sleep mode when a SLEEP instruction is executed while
the SSBY bit in system control register 1 (SYSCR1) is cleared to 0. In this mode CPU
operation is halted but the register, RAM, and port contents are retained. The clock pulse
generator operates, as do external interrupts (IRQ and IRQ ) and timer A.
1
0
•
Clearing sleep mode
Sleep mode is cleared by an interrupt (IRQ , IRQ , or timer A) or by input at the RES pin.
1
0
— Clearing by interrupt (IRQ , IRQ , or timer A)
1
0
When an IRQ , IRQ , or timer A interrupt is requested, sleep mode is cleared and interrupt
1
0
exception handling starts. Sleep mode is not cleared if the I bit in the condition code
register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable
register.
Before transition to sleep mode, other interrupts should be disabled.
— Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
2. Standby mode
Operation in standby mode is described below.
•
Transition to standby mode
The system goes from active mode to standby mode when a SLEEP instruction is executed
while the SSBY bit in system control register 1 (SYSCR1) is set to 1 and bit TMA3 in timer
mode register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so
the CPU and on-chip peripheral modules stop functioning. As long as a minimum required
voltage is applied, the CPU register contents and data in the on-chip RAM will be retained.
Standard I/O ports go to the high-impedance state. In high-voltage ports, the PMOS buffer
transistors are switched off.
78
•
Clearing standby mode
Standby mode is cleared by an external interrupt (IRQ , IRQ ) or by input at the RES pin.
1
0
— Clearing by interrupt (IRQ , IRQ )
1
0
When an IRQ or IRQ interrupt signal is input, the clock pulse generator starts. After the
1
0
time set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed, a stable
clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception
handling starts. Before the transition to standby mode, other interrupts should be disabled.
Standby mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or
the particular interrupt is disabled in the interrupt enable register.
— Clearing by RES input
When the RES pin goes low, the clock pulse generator starts and standby mode is cleared.
After the pulse generator output has stabilized, if the RES pin is driven high, the CPU
starts reset exception handling.
Since clock signals are supplied to the entire chip as soon as the clock pulse generator
starts functioning, the RES pin should be kept at the low level until the pulse generator
output stabilizes.
3. Watch mode
Operation in watch mode is described below.
•
Transition to watch mode
From active mode, watch mode is entered when a SLEEP instruction is executed while the
SSBY bit in system control register 1 (SYSCR1) is set to 1 and bit TMA3 in timer mode
register A (TMA) is set to 1. From subactive mode, watch mode is entered when a SLEEP
instruction is executed while the DTON bit in system control register 2 (SYSCR2) is cleared
to 0.
In watch mode, operation of the system clock pulse generator and of on-chip peripheral
modules is halted, except for the time-base function of timer A. Output from the on-chip
peripheral modules is reset; but as long as a minimum required voltage is applied, the contents
of the internal registers of the CPU and on-chip peripheral modules, and the on-chip RAM
contents, are retained.
79
•
Clearing watch mode
Watch mode is cleared by a time-base interrupt from timer A, by an IRQ interrupt, or by
0
input at the RES pin.
— Clearing by timer A time-base interrupt or IRQ interrupt
0
When timer A overflows or an IRQ interrupt signal is input, if the LSON bit in system
0
control register 1 (SYSCR1) is cleared to 0, the clock pulse generator starts. After the time
set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed, a stable clock
signal is supplied to the entire chip, watch mode is cleared, and interrupt exception
handling starts. If LSON = 1, the system goes to subactive mode.
In watch mode, the subclock (φ ) is prescaled to generate a clock signal which is
SUB
supplied to timer A. Timer A operates as a time base.
Before the transition to watch mode, other external interrupts should be disabled. Watch
mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the
particular interrupt is disabled in the interrupt enable register.
— Clearing by RES input
When the RES pin goes low, the clock pulse generator starts and watch mode is cleared.
After the pulse generator output has stabilized, if the RES pin is driven high, the CPU
starts reset exception handling.
Since clock signals are supplied to the entire chip as soon as the clock pulse generator
starts functioning, the RES pin should be kept at the low level until the pulse generator
output stabilizes.
4. Subactive mode
Operation in subactive mode is described below.
•
Transition to subactive mode
Subactive mode is entered from watch mode if the LSON bit in system control register 1
(SYSCR1) is set to 1 at the time of a timer A time-base interrupt or IRQ interrupt request.
0
In subactive mode, the CPU operates in synchronization with the subclock (φ ). The on-
SUB
chip peripheral modules halt operation, except for the time base function of timer A. Output
from the on-chip peripheral modules is reset; but as long as a minimum required voltage is
applied, the contents of the internal registers of the on-chip peripheral modules are retained.
Standard I/O ports go to the high-impedance state. In high-voltage ports, the PMOS buffer
transistors are switched off.
80
•
Clearing subactive mode
Subactive mode is cleared by a SLEEP instruction or by input at the RES pin.
— Clearing by SLEEP instruction
When a SLEEP instruction is executed in subactive mode, subactive mode is cleared.
If the DTON bit of system control register 2 (SYSCR2) is cleared to 0 when the SLEEP
instruction is executed, the system goes to watch mode. If DTON = 1 and
LSON = 0, a direct transfer interrupt is requested and the clock pulse generator starts.
After the time set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed,
a stable clock signal is supplied to the entire chip, and the system goes to active mode.
Before the transition to active mode, other interrupts should be disabled. The direct
transfer from subactive mode to active mode does not take place if the I bit in the condition
code register (CCR) is set to 1 or the direct transfer interrupt is disabled in the interrupt
enable register.
— Clearing by RES input
When the RES pin goes low, the clock pulse generator starts and subactive mode is
cleared. After the pulse generator output has stabilized, if the RES pin is driven high, the
CPU starts reset exception handling.
Since clock signals are supplied to the entire chip as soon as the clock pulse generator
starts functioning, the RES pin should be kept at the low level until the pulse generator
output stabilizes.
81
3.3.3 Application Notes
1. In order to ensure sufficient time for the clock pulse generator to reach stable operation after
clearing of standby mode or watch mode, or after a direct transfer from subactive to active
mode, bits STS2 to STS0 in system control register 1 (SYSCR1) should be set as follows.
•
When a ceramic oscillator is used
Set bits STS2 to STS0 for a waiting time of at least 10 ms (see figure 3-9). For details, see
3.4.1, System Control Register 1 (SYSCR1).
•
When an external clock is used
Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be
set.
Oscillator waveform
V
t
Waiting time ≥10 ms
Oscillator stabilization time t
r
Power-on
or standby
cleared
Figure 3-9 Waiting Time
2. To make a transition from subactive mode to active mode, the LSON bit in SYSCR1 should
be cleared to 0 and the DTON bit in system control register 2 (SYSCR2) should be set to 1.
Direct transfer is not possible when the LSON bit = 1.
82
3.4 System Control Registers
Table 3-7 shows how the system control registers (SYSCR1 and SYSCR2) are configured.
These two registers are used to control the power-down modes.
Table 3-7 Register Configuration
Name
Abbreviation
SYSCR1
R/W
R/W
R/W
Initial Value
H'00
Address
H'FFF0
H'FFF1
System control register 1
System control register 2
SYSCR2
H'F4
3.4.1 System Control Register 1 (SYSCR1)
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
LSON
0
2
—
1
—
0
0
—
0
Initial value
Read/Write
0
*
R/W
R/W
R/W
R/W
R/W
R/W
—
—
Note: * Write is enabled only in active mode.
SYSCR1 is an 8-bit read/write register for control of power-down modes.
Bit 7: Standby (SSBY)
This bit designates transition to standby mode.
When standby mode is cleared by an external interrupt and the system goes to active mode, this
bit remains set to 1. It must be cleared by writing a 0. Writing is possible only in active mode.
Bit 7
SSBY
Explanation
0
When a SLEEP instruction is executed, a transition is made to sleep
mode.
(initial value)
1
When a SLEEP instruction is executed, a transition is made to standby mode or watch
mode.
83
Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0)
When a mode in which the system clock is stopped (standby, watch, or subactive mode) is cleared,
the system waits for stable clock operation for a time set in these bits. The designation should be
made according to the clock frequency so that the waiting time is at least 10 ms.
Bit 6
Bit 5
Bit 4
STS2
STS1
STS0
Explanation
0
0
0
0
1
0
0
1
1
*
0
1
0
1
*
Wait time = 8,192 states. (initial value)
Wait time = 16,384 states.
Wait time = 32,768 states.
Wait time = 65,536 states.
Wait time = 131,072 states.
Note: * Don’t care.
Bit 3: Low speed on flag (LSON)
This bit chooses the system clock (φ) or subclock (φ ) as the CPU operating clock when watch
SUB
mode is cleared. Since this relates to the transitions between operation modes, this bit functions in
combination with other control bits and interrupt input.
Bit 3
LSON
Explanation
0
1
The CPU operates on the system clock (φ).
(initial value)
The CPU operates on the subclock (φ
).
SUB
Bit 2: Reserved bit
This bit is reserved, but it can be written and read.
Bits 1 and 0: Reserved bits
These bits are reserved; they always read 0, and cannot be modified.
84
3.4.2 System Control Register 2 (SYSCR2)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
DTON
0
2
—
1
1
—
0
—
Initial value
Read/Write
0
0
*
—
—
—
—
W
—
R/W
R/W
Note: * Write is enabled only in subactive mode.
SYSCR2 is an 8-bit read/write register for control of direct transfer from subactive mode to active
mode.
Bits 7 to 4: Reserved bits
These bits are reserved; they always read 1, and cannot be modified.
Bit 3: Direct transfer on flag (DTON)
This bit designates whether a transition is made to active mode or to watch mode when a SLEEP
instruction is executed in subactive mode. When transfer to active mode is designated, the
transition takes place via watch mode to allow time for the clock pulse generator to stabilize.
Bit 3
DTON
Explanation
0
When a SLEEP instruction is executed in subactive mode, a transition is (initial value)
made to watch mode.
1
When a SLEEP instruction is executed in subactive mode while the LSON bit in system
control register 1 (SYSCR1) is cleared to 0, a direct transfer interrupt is requested, and
the system goes to active mode via watch mode.
Bit 2: Reserved bit
This bit is reserved; it always reads 1, and cannot be modified.
Bits 1 and 0: Reserved bits
These bits are reserved, but they can be written and read.
85
86
Section 4 ROM
4.1 Overview
The H8/3714 has 32 kbytes of on-chip mask ROM. The H8/3713 has 24 kbytes, and the H8/3712
has 16 kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-
state access for both byte data and word data. The ZTAT™ version of the H8/3714 has a 32-kbyte
PROM.
4.1.1 Block Diagram
Figure 4-1 gives a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000
H'0002
H'0001
H'0003
H'7DFE
H'7DFF
Even-numbered
addresses
Odd-numbered
addresses
Figure 4-1 ROM Block Diagram (H8/3714)
87
4.2 PROM Mode
4.2.1 Selection of PROM Mode
If the on-chip ROM is a PROM, setting the chip to PROM mode stops operation as a
microcontroller and allows the PROM to be programmed in the same way as the HN27C256H.
Table 4-1 shows how to select PROM mode.
Table 4-1 Selection of PROM Mode
Pin Name
Setting
Test pin TEST
High level
Low level
Mode pin MD0 (P40/FS16
Mode pin MD1 (P41/FS17
)
)
Mode pin MD2 (P17/Vdisp
)
High level
4.2.2 Socket Adapter Pin Arrangement and Memory Map
A standard PROM programmer can be used to program the PROM. A socket adapter is required
for conversion to 28 pins, as listed in table 4-2.
Figure 4-2 shows the pin-to-pin wiring of the socket adapter. Figure 4-3 shows a memory map.
Table 4-2 Socket Adapter
Package
Socket Adapter
HS3714ESH01H
HS3714ESS01H
64-pin (FP-64A)
64-pin (DP-64S)
88
H8/3714
EPROM Socket
FP-64A
17
DP-64S
26
2
Pin
Pin
VPP
HN27C256H
1
RES
P90
57
EO0
EO1
EO2
EO3
EO4
EO5
EO6
EO7
EA0
EA1
EA2
EA3
EA4
EA5
EA6
EA7
EA8
EA9
EA10
EA11
EA12
EA13
EA14
11
12
13
15
16
17
18
19
10
9
58
3
P91
P92
59
4
60
5
P93
61
6
P94
62
7
P95
63
8
P96
64
9
P97
31
40
41
42
43
44
45
46
47
57
31
59
60
61
62
63
64
58
36
37
48
38
39
1, 10
23, 19
20, 22
24
P50
32
P51
33
P52
8
34
P53
7
35
P54
6
36
P55
5
37
P56
4
38
P57
3
48
P70
25
24
21
23
2
22
P16
50
P72
51
P73
52
P74
53
P75
26
27
20
22
54
P76
55
P77
CE
OE
49
P71
27
P43
28
P42
VCC
28
39
P17
29
P41
VSS
14
30
P40
56, 1
14, 10
11
VCC, AVCC
VSS, AVSS
TEST, X1
OSC1
VCC
VSS
VCC
VSS
28
14
28
14
15
Note: Pins not indicated above should be left open.
Figure 4-2 Socket Adapter Pin Correspondence
89
Address in
MCU mode
Address in
PROM mode
H'0000
H'0000
On-chip ROM
H'7DFF
H'7DFF
Figure 4-3 Memory Map in PROM Mode
90
4.3 Programming
The write, verify, and other modes are selected as shown in table 4-3 in PROM mode.
Table 4-3 Mode Selection in PROM Mode
Pin
Mode
CE
L
OE
H
VPP
VPP
VPP
VPP
VCC
VCC
VCC
VCC
EO7 to EO0
Data input
EA14 to EA0
Address input
Address input
Address input
Write
Verify
H
L
Data output
High impedance
Programming disabled
H
H
Notation:
L:
H:
Low level
High level
V
V
PP: VPP level
CC: VCC level
The specifications for writing and reading the on-chip PROM are identical to those for the
standard HN27C256H EPROM.
4.3.1 Writing and Verifying
An efficient, high-speed programming method is provided for writing and verifying the PROM
data. This method achieves high speed without voltage stress on the device and without lowering
the reliability of written data. H'FF data is written in unused address areas.
The basic flow of this high-speed programming method is shown in figure 4-4. Table 4-4 and
table 4-5 give the electrical characteristics in programming mode. Figure 4-5 shows a timing
diagram.
91
Start
Select write or verify mode
V
CC
= 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V
Address = 0
n = 0
n + 1→ n
Yes
n < 25
No
Write with tPW = 1 ms ±5%
No Go
Verify
Go
Address + 1→ address
Write with tOPW = 3n ms
No
Last address?
Yes
Select read mode
VCC = 5.0 V ± 0.5 V, VPP = VCC ± 0.6 V
No Go
Read all
addresses
Error
Go
End
Figure 4-4 High-Speed Programming Flow Chart
92
Table 4-4 DC Characteristics (preliminary)
(Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0.0 V, T = 25°C ±5°C)
CC
PP
SS
a
Test
Item
Symbol Min
Typ Max
Unit Conditions
Input high-
level voltage
EA14 to EA0, OE, CE
EA14 to EA0, OE, CE
VIH
2.4
–0.3
2.4
—
—
—
—
—
—
VCC + 0.3 V
Input low-
level voltage
VIL
0.8
—
V
V
V
Output high- EO7 to EO0
level voltage
VOH
VOL
IOH = –200 µA
IOL = 1.6 mA
Output low-
level voltage
EO7 to EO0
0.45
2
Input leakage EO7 to EO0, EA14 to EA0, |ILI|
—
µA VIN
=
current
OE, CE
5.25 V/0.5 V
VCC current
VPP current
ICC
IPP
—
—
—
—
40
40
mA
mA
Table 4-5 AC Characteristics
(Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0.0 V, T = 25°C ±5°C)
CC
PP
SS
a
Item
Symbol
tAS
Min
2
Typ
—
Max
—
Unit
µs
Test Conditions
Address setup time
OE setup time
Figure 4-5*
tOES
tDS
2
—
—
µs
Data setup time
2
—
—
µs
Address hold time
Data hold time
tAH
0
—
—
µs
tDH
2
—
—
µs
Data output disable time
VPP setup time
tDF
0
—
130
—
ns
tVPS
tPW
2
—
µs
Programming pulse width
0.95
2.85
1.0
—
1.05
ms
CE pulse width for overwrite
programming
tOPW
78.75 ms
VCC setup time
tVCS
tOE
2
0
—
—
—
µs
ns
Data output delay time
500
Notes: * Input pulse level: 0.8 to 2.2 V
Input rise time/fall time ≤ 20 ns
Timing reference levels Input: 1.0 V, 2.0 V
Output: 0.8 V, 2.0 V
93
Write
Verify
Address
Data
tAS
tAH
Output data
tDF
Input data
tDS
tDH
VPP
VPP
VCC
CE
tVPS
VCC
VCC
tVCS
GND
tPW
tOES
tOE
tOPW
OE
Figure 4-5 PROM Write/Verify Timing
4.3.2 Programming Precautions
1. Use the specified programming voltage and timing.
The programming voltage in PROM mode (V ) is 12.5 V. Use of a higher voltage can
PP
permanently damage the chip. Be especially careful with respect to PROM programmer
overshoot.
Setting the PROM programmer to Hitachi specifications for the HN27C256H or to Intel
specifications will result in a correct V of 12.5 V.
PP
2. Make sure the index marks on the PROM programmer socket, socket adapter, and chip are
properly aligned. If they are not, the chip may be destroyed by excessive current flow.
Before programming, be sure the chip is properly mounted in the PROM programmer.
94
3. Avoid touching the socket adapter or chip during programming, since this may cause contact
faults and write errors.
4. Some commercially available EPROM programmers execute a device test before writing,
reading, or verifying. The device test is a leakage test of the EPROM pins or ZTAT
microcontroller pins. (A ZTAT microcontroller is a microcontroller with on-chip EPROM.)
The function of this test is to check whether the device is correctly inserted in the socket, by
confirming that leakage current flow is above a certain minimum level.
In devices like the H8/3714 in which the on-chip EPROM is assigned to high-voltage pins
(PMOS open-drain pins), no leakage current flows in the sink direction. That may cause the
device test to fail and prevent writing, reading, or verifying. If this occurs, switch the device
test off.
Note that in some EPROM programmers, the device test cannot be switched off.
95
4.3.3 Reliability of Written Data
An effective way to assure the data holding characteristics of the programmed chips is to bake
them at 150˚C, then screen them for data errors. This procedure quickly eliminates chips with
PROM memory cells prone to early data retention failure.
Figure 4-8 shows a flow chart of this screening procedure.
Write program and verify written data
Bake chips with power off
*
+8 Hr
°
°
150 C ± 10 C, 48 Hr
–0 Hr
Read and check program
VCC = 4.5 V and 5.5 V
Install
Note: * Baking time is measured from when the oven reaches 150°C.
Figure 4-6 Recommended Screening Procedure
If write errors occur repeatedly while the same PROM programmer is being used, stop
programming and check for problems in the PROM programmer and socket adapter, etc.
Please notify your Hitachi representative of any problems occurring during programming or in
screening after high-temperature baking.
96
Section 5 RAM
5.1 Overview
The H8/3714 has 512 bytes of high-speed static RAM on-chip. The H8/3713 and the H8/3712
each has 384 bytes. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed
two-state access for both byte data and word data.
5.1.1 Block Diagram
Figure 5-1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FD80
H'FD82
H'FD80
H'FD82
H'FD81
H'FD83
H'FF7E
H'FF7E
H'FF7F
Even-numbered
addresses
Odd-numbered
addresses
Figure 5-1 RAM Block Diagram (H8/3714)
5.1.2 Display RAM Area
In the H8/3714, H8/3713 and H8/3712, RAM addresses H'FEC0 to H'FEFF are also used as a
display RAM for the VFD controller/driver. If the VFD controller/driver is not used, this area is
available as an ordinary RAM.
97
98
Section 6 Clock Pulse Generators
6.1 Overview
Clock oscillator circuitry (CPG: Clock Pulse Generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator, system clock divider, and a clock divider (prescaler S) for the
on-chip peripheral modules. The subclock pulse generator consists of a subclock oscillator
circuit, subclock divider, and a further subclock divider (prescaler W) for time-base use.
6.1.1 Block Diagram
Figure 6-1 shows a block diagram of the clock pulse generators.
System clock pulse generator
Prescaler S
φ/2 to φ/8192
fOSC System clock
OSC1
OSC2
System clock
oscillator
φ
divider
(1/2)
Prescaler W
φSUB/32
Subclock
divider
(1/8)
fX
X1
X2
Subclock
oscillator
φSUB
Subclock pulse generator
Figure 6-1 Block Diagram of Clock Pulse Generators
99
6.2 System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input.
1. Connecting a crystal oscillator
•
Circuit configuration
Figure 6-2 shows a typical method of connecting a crystal oscillator.
C1
OSC1
OSC2
Rf
C2
Rf = 1 MΩ ±20%
C1 = C2 = 12 pF ±20%
Figure 6-2 Typical Connection to Crystal Oscillator
Crystal oscillator
•
Figure 6-3 shows the equivalent circuit of the crystal oscillator. An oscillator having the
characteristics given in table 6-1 should be used.
CL
L
RS
OSC1
OSC2
C0
Figure 6-3 Equivalent Circuit of Crystal Oscillator
Table 6-1 Crystal Oscillator Parameters
Frequency (MHz)
2
4
8
Rs max (Ω)
500
7
100
7
50
7
Co max (pF)
100
2. Connecting a ceramic oscillator
Circuit configuration
•
Figure 6-4 shows a typical method of connecting a ceramic oscillator.
OSC1
C1
Ceramic
oscillator
Rf
OSC2
C2
Rf: 1 MΩ ±20%
C1: 30 pF ±20%
C2: 30 pF ±20%
Figure 6-4 Typical Connection to Ceramic Oscillator
3. Notes on board design
When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful
attention to the following points.
Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely
affected by induction currents. (See figure 6-5.)
The board should be designed so that the oscillator and load capacitors are located as close as
possible to pins OSC and OSC .
1
2
101
To be avoided
Signal A Signal B
H8/3714 Series
microcontroller
C2
OSC1
OSC2
C1
Figure 6-5 Board Design of Oscillator Circuit
4. External clock input
• Circuit configuration
When an external clock is used, it is input at pin OSC . Pin OSC should be left open.
1
2
Figure 6-6 shows a typical connection.
OSC1
External clock input
Open
OSC2
Figure 6-6 External Clock Input (Example)
•
External clock
Frequency
Duty cycle
Twice clock frequency (φ)
45% to 55%
102
6.3 Subclock Generator
1. Connecting a 32.768 kHz crystal oscillator
Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz crystal
oscillator, as shown in figure 6-7. Follow the same precautions as noted for the system clock.
C1
X1
X2
C2
C1 = C2 = 15 pF typ
Figure 6-7 Typical Connection to Crystal Oscillator (Subclock)
Figure 6-8 shows the equivalent circuit of the crystal oscillator.
CS
C0
L
RS
C0 = 1.5 pF typ
RS = 14 kΩ typ
f = 32.768 kHz
Figure 6-8 Equivalent Circuit of Crystal Oscillator
2. Pin connection when not using subclock
When the subclock is not used, connect V to pin X and leave pin X open, as shown in
CC
1
2
figure 6-9.
103
VCC
X1
X2
Open
Figure 6-9 Pin Connection When Not Using Subclock
104
Section 7 I/O Ports
7.1 Overview
The H8/3714 Series has five 8-bit I/O ports (of which four are high-voltage ports), one 6-bit I/O
port*, and one 8-bit input port. Table 7-1 indicates the functions of each port.
Ports 1 and 9 are standard input/output ports, consisting of a port control register (PCR) that
controls input and output, and a port data register (PDR) for storing output data. Input or output
can be assigned to individual bits.
Ports 4, 5, 6, and 7 are high-voltage ports, able to handle an applied voltage of V – 40 V. Input
CC
and output are controlled for individual bits by reading from and writing to PDR.
Note: * Pin P1 of port 1 is a high-voltage input-only pin, while pin P1 is a standard input-only
7
6
pin. Pins P1 and P1 are not present.
2
3
Reading a port gives the following results.
•
•
Reading a standard port
— Reading a pin assigned to general-purpose input (PCR = 0) gives the pin level.
— Reading a pin assigned to general-purpose output (PCR = 1) gives the value of the
corresponding PDR bit.
— Reading a pin assigned to an on-chip peripheral function gives the pin level.
Reading a high-voltage port
— Reading a pin assigned to general-purpose input/output gives the pin level.
— Reading a pin assigned to digit output or segment output use gives the value of the
corresponding PDR bit.
105
Table 1 Port Functions
Function
Switching
Register
Port
Description
Pins
Other Functions
Port 0 8-bit standard input port
P07 to P00/
AN7 to AN0
Analog data input channels
7 to 0
PMR0
Port 1 Pin P17: 1-bit high-voltage
input port
P17/Vdisp
Power supply for VFD driver
Mask
option
Pin P16: 1-bit standard input P16/EVENT Timer D event input
port
PMR1
Pins P15, P14, P11, and P10: P15/IRQ5/
External interrupt 5;
Timer E output
PMR1
PMR4
4-bit standard I/O port
TMOE
P14/IRQ4
P11/IRQ1
P10/IRQ0
External interrupts 4, 1, and 0 PMR1
Port 4 8-bit high-voltage I/O port
Port 5 8-bit high-voltage I/O port
Port 6 8-bit high-voltage I/O port
P47 to P40/
FS23 to FS16
VFD segment pins 23 to 16
VFD segment pins 15 to 8
VFSR
VFSR
P57 to P50/
FS15 to FS8
P67 to P60/
VFD digit pins 7 to 0/segment DBR
FD7 to FD0/ pins 0 to 7
FS0 to FS7
VFSR
VFDR
Port 7 8-bit high-voltage I/O port
Port 9 8-bit standard I/O port
P77 to P70/
FD15 to FD8
VFD digit pins 15 to 8
VFDR
P97/UD
Timer C count-up/down
selection
PMR2
PMR3
P96/SO2
P95/SI2/CS
P94/SCK2
P93/SO1
P92/SI1
Serial communication interface
2 data output
Serial communication interface
2 data input/chip select output
Serial communication interface
2 clock I/O
Serial communication interface
1 data output
Serial communication interface
1 data input
P91/SCK1
P90/PWM
Serial communication interface
1 clock I/O
14-bit PWM waveform output pin
Note: Pins P12 and P13, and ports P2, P3, and P8 are not included in these versions.
106
7.1.1 Port Types and Mask Options
The choice of I/O pin options and the resulting states are shown in table 7-2.
Upon reset, the PDR, PCR, and PMR registers are initialized, cancelling the choices of peripheral
functions. When the chip goes to a low-power mode, the on-chip peripheral function input gates
are always on, so unless input levels are fixed there will be an increase in dissipated current.
Table 7-2 Choice of I/O Port Options
For Standard I/O Pins
Class
Pins
With MOS Pull-Up (type B)
No MOS Pull-Up (type C)
I/O pins
P15, P14,
P11, P10,
P97 to P90
With MOS pull-up
No MOS pull-up
Input-only pins
P16
With MOS pull-up
With MOS pull-up
No MOS pull-up
No MOS pull-up
On-chip peripheral
function I/O pins
SCK2, SCK1
(output mode)*
On-chip peripheral
function output pins PWM, TMOE
SO2, SO1,
With MOS pull-up
With MOS pull-up
No MOS pull-up
No MOS pull-up
On-chip peripheral
function input pins
SCK2, SCK1
(input mode)*
SI2, SI1,
IRQ5, IRQ4,
IRQ1, IRQ0
UD, EVENT
Note: If external clock input mode is selected when the serial communication interface is used,
pins SCK2 and SCK1 will be input-only pins.
For High-Voltage Pins
Class
Pins
No MOS Pull-Down (type D) With MOS Pull-Down (type E)
I/O pins
P47 to P40, No MOS pull-down
P57 to P50,
P67 to P60,
With MOS pull-down.
Source of pull-down transistor
connected to Vdisp power
supply.
P77 to P70
Input-only pins
P17
No MOS pull-down
Connected to Vdisp power
supply.
On-chip peripheral FS23 to FS0, No MOS pull-down
function output pins FD15 to FD0
With MOS pull-down.
Source of pull-down transistor
connected to Vdisp power
supply.
107
Table 7-3 shows the mask options with mask ROM versions. A mask ROM version is compatible
with a ZTAT™ version only when C and D options are selected for all pins.
™
Table 7-3 Correspondence between Mask ROM and ZTAT Versions
Type
B
C
D
E
Mask ROM
ZTAT
Option
—
Option
Fixed
Option
Fixed
Option
—
Notes
1. When circuit type E, “with MOS pull-down,” is chosen, the source of the MOS pull-down is
connected to the Vdisp power supply. Accordingly, the mask option making pin P1 /Vdisp a Vdisp
7
power supply pin must also be chosen.
2. Type C, “no MOS pull-up,” is the only option available for port 0.
7.1.2 MOS Pull-Up
Ports 1* and 9, which are standard input/output ports, can be designated by mask options as
having or not having MOS pull-up transistors for their (CMOS) outputs. (This does not apply to
ZTAT™ versions.)
Figure 7-1 shows the MOS pull-up circuit configuration.
When “with MOS pull-up” is selected by mask option, the MOS pull-up will normally be on,
regardless of the port data register (PDR) and port control register (PCR) settings.
(See table 7-4.)
Note: * Pin P1 /V
is a high-voltage pin, so the MOS pull-up option cannot be selected for
7
disp
this pin.
108
STBY*2
VCC
*1
VCC
MOS
pull-up
PDR
PCR
CMOS buffer
VSS
Input data
Notes: 1. Dotted lines indicate mask option.
2. In low-power modes (except sleep mode), the MOS pull-up is switched off
by a STBY signal.
Figure 7-1 MOS Pull-Up Circuit Configuration
Table 7-4 MOS Pull-Up Control
Mask Option
With MOS Pull-Up (type B)
No MOS Pull-Up (type C)
PCR
PDR
0
1
0
1
0
1
0
1
0
1
0
1
CMOS buffer PMOS
Off
Off
Off
On
Off
On
On
On
Off
On
Off
Off
—
Off
Off
—
Off
On
—
On
Off
—
NMOS Off
On
MOS pull-up
109
7.1.3 MOS Pull-Down
Ports 4, 5, 6, and 7, which are high-voltage I/O ports, can be designated by mask option as having
or not having MOS pull-down resistors for their (PMOS open-drain) outputs. (This does not
™
apply to ZTAT versions.)
Figure 7-2 shows the MOS pull-down circuit configuration.
When the “with MOS pull-down” option is chosen, the source of the MOS pull-down is connected
to the V
power supply. Accordingly, the mask option making pin P1 /V
a V
power
disp
7
disp
disp
supply pin must also be chosen.
VCC
STBY
PDR
*
Vdisp
Input control
Input data
Note: * Dotted lines indicate mask option.
Figure 7-2 MOS Pull-Down Circuit Configuration
110
7.2 Port 0
7.2.1 Overview
Port 0 is an 8-bit standard input-only port. Figure 7-3 shows the pin configuration.
P07/AN7 (input)
P06/AN6 (input)
P05/AN5 (input)
P04/AN4 (input)
Port 0
P03/AN3 (input)
P02/AN2 (input)
P01/AN1 (input)
P00/AN0 (input)
Figure 7-3 Port 0 Pin Configuration
7.2.2 Register Configuration and Description
Table 7-5 shows the port 0 register configuration.
Table 7-5 Port 0 Registers
Name
Abbrev.
PMR0
PDR0
R/W
W
Initial Value
Address
H'FFEF
H'FFD0
Port mode register 0
Port data register 0
H'00
—
R
1. Port mode register 0 (PMR0)
Bit
7
AN7
0
6
AN6
0
5
AN5
0
4
AN4
0
3
AN3
0
2
AN2
0
1
AN1
0
0
AN0
0
Initial value
Read/Write
W
W
W
W
W
W
W
W
Each PMR0 bit designates whether the corresponding port 0 pin is to be used for general input or
as an analog input channel to the A/D converter.
Upon reset, PMR0 is initialized to H'00.
111
Bit n
ANn
Explanation
0
1
Pin P0n/ANn is used for general input.
Pin P0n/ANn is an analog input channel.
(initial value)
(n = 0 to 7)
2. Port data register 0 (PDR0)
Bit
7
6
5
4
3
2
1
0
PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00
Initial value
Read/Write
—
R
—
R
—
R
—
R
—
R
—
R
—
R
—
R
When the corresponding bit in PMR0 is 0, the pin state can be read from PDR0. If the
corresponding PMR0 bit is 1, PDR0 is read as 1.
7.2.3 Pin Functions
Table 7-6 gives the port 0 pin functions.
Table 7-6 Port 0 Pin Functions
Pin
Pin Functions and Selection Method
Functions are switched as follows by means of bits AN7 to AN0 in PMR0.
P07/AN7 to P00/AN0
ANn
0
1
Pin function
P0n input pin
ANn input pin
7.2.4 Pin States
Table 7-7 shows the port 0 pin states in each operating mode.
Table 7-7 Port 0 Pin States
Pins
Reset
Sleep
Standby
Watch
Subactive
Active
P07/AN7 to
P00/AN0
High
impedance
Previous
state
High
impedance
High
impedance
High
impedance
Normal
operation
retained
112
7.3 Port 1
7.3.1 Overview
Port 1 consists of four standard I/O pins, one standard input-only pin, and one high-voltage input-
only pin. Figure 7-4 shows the pin configuration.
P17 /Vdisp
(high-voltage input or power supply)
(input/input)
P16 /EVENT
P15 /IRQ5/TMOE (IO/input/output)
Port 1
P14 /IRQ4
P11 /IRQ1
P10 /IRQ0
(IO/input)
(IO/input)
(IO/input)
Note: IO indicates input/output.
Figure 7-4 Port 1 Pin Configuration
7.3.2 Register Configuration and Description
Table 7-8 shows the port 1 register configuration.
Table 7-8 Port 1 Registers
Name
Abbrev.
PMR1
PCR1
PDR1
PMR4
R/W
R/W
W
Initial Value
H'0C
Address
H'FFEB
H'FFE1
H'FFD1
H'FFEE
Port mode register 1
Port control register 1
Port data register 1
Port mode register 4
H'CC
R/W
R/W
Not fixed
H'0F
1. Port mode register 1 (PMR1)
Bit
7
6
5
4
3
—
1
2
—
1
1
0
NOISE
CANCEL
EVENT IRQC5 IRQC4
IRQC1 IRQC0
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
—
—
R/W
R/W
113
PMR1 is an 8-bit read/write register that controls the selection of pin functions for pins
P1 /EVENT, P1 /IRQ , P1 /IRQ , P1 /IRQ , and P1 /IRQ , and turns the IRQ noise
6
5
5
4
4
1
1
0
0
0
cancellation function on and off.
Upon reset, PMR1 is initialized to H'0C.
Note: Before switching pin functions using bits IRQ5 to IRQ0 in PMR1, first disable the
corresponding interrupts by clearing their interrupt enable bits. After the pin functions
have been switched, issue any instruction, then clear the interrupt request flags to 0. For
details see section 3.2.3 1, Port mode register (PMR1).
Bit 7: Noise cancel (NOISE CANCEL)
This bit turns the IRQ noise canceller function on and off. In standby, watch, and subactive
0
modes the noise canceller function is off regardless of the setting of this bit.
Bit 7
NOISE CANCEL
Explanation
0
1
Noise canceller function is off.
(initial value)
Noise canceller function is on. Input is sampled at intervals of 256 states.
If two consecutive input values do not match, noise is assumed.
Bit 6: P1 /EVENT pin function switch (EVENT)
6
This bit selects whether pin P1 /EVENT is used as P1 or as EVENT.
6
6
Bit 6
EVENT
Explanation
P16/EVENT pin functions as P16.*
P16/EVENT pin functions as EVENT (timer D event input).
0
1
(initial value)
Note: * Even when pin P16/EVENT is used as P16, the timer D counter may increment when pin
P16 is read. If timer D is used the counter must be cleared by means of the CLR bit in
timer mode register D (TMD).
Bit 5: P1 /IRQ /TMOE pin function switch (IRQC5)
5
5
This bit selects whether pin P1 /IRQ /TMOE is used as P1 /TMOE or as IRQ .
5
5
5
5
Bit 5
IRQC5
Explanation
0
1
P15/IRQ5/TMOE pin functions as P15/TMOE.
P15/IRQ5/TMOE pin functions for IRQ5 input.
(initial value)
114
Bit 4: P1 /IRQ pin function switch (IRQC4)
4
4
This bit selects whether pin P1 /IRQ is used as P1 or as IRQ .
4
4
4
4
Bit 4
IRQC4
Explanation
0
1
P14/IRQ4 pin functions as P14.
(initial value)
P14/IRQ4 pin functions for IRQ4* input.
Note: * Rising or falling edge sensing can be designated for pin IRQ4.
For details see 3.2.3 (2), IRQ edge select register (IEGR).
Bits 3 and 2: Reserved bits
Bits 3 and 2 are reserved; they always read 1, and cannot be modified.
Bit 1: P1 /IRQ pin function switch (IRQC1)
1
1
This bit selects whether pin P1 /IRQ is used as P1 or as IRQ .
1
1
1
1
Bit 1
IRQC1
Explanation
0
1
P11/IRQ1 pin functions as P11.
(initial value)
P11/IRQ1 pin functions for IRQ1* input.
Note: * Rising or falling edge sensing can be designated for pin IRQ1.
For details see 3.2.3 (2), IRQ edge select register (IEGR).
Bit 0: P1 /IRQ pin function switch (IRQC0)
0
0
This bit selects whether pin P1 /IRQ is used as P1 or as IRQ .
0
0
0
0
Bit 0
IRQC0
Explanation
0
1
P10/IRQ0 pin functions as P10.
(initial value)
P10/IRQ0 pin functions for IRQ0* input.
Note: * Rising or falling edge sensing can be designated for pin IRQ0.
For details see 3.2.3 (2), IRQ edge select register (IEGR).
115
2. Port control register 1 (PCR1)
Bit
7
—
1
6
—
1
5
4
3
—
1
2
—
1
1
0
PCR15 PCR14
PCR11 PCR10
Initial value
Read/Write
0
0
0
0
—
—
W
W
—
—
W
W
PCR1 is an 8-bit register for controlling whether each of port 1 pins P1 , P1 , P1 , and P1
0
5
4
1
functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an input pin. Bits 7, 6, 3, and 2 are reserved
bits that cannot be modified and always read 1.
The settings in PCR1 and in PDR1 are valid when the affected pin is designated in PMR1 as a
general I/O pin.
Upon reset, PCR1 is initialized to H'CC.
3. Port data register 1 (PDR1)
Bit
7
6
5
4
3
—
1
2
—
1
1
0
—
—
—
—
—
—
PDR15 PDR14
PDR11 PDR10
Initial value
Read/Write
0
0
0
0
*
*
R/W
R/W
—
—
R/W
R/W
Note: * Pins P17 and P16 are for input only; reading PDR1 always gives the level of these pins.
PDR1 is an 8-bit register that stores data for pins P1 , P1 , P1 , and P1 . If port 1 is read while
5
4
1
0
PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If
port 1 is read while PCR1 bits are cleared to 0, the pin states are read. Bits 3 and 2 are reserved
bits that cannot be modified and always read 1.
116
4. Port mode register 4 (PMR4)
Bit
7
6
5
4
VRFR
0
3
—
1
2
—
1
1
—
1
0
—
1
TEO
0
TEO ON FREQ
Initial value
Read/Write
0
0
R/W
R/W
R/W
R/W
—
—
—
—
PMR4 is an 8-bit read/write register that switches the P1 /IRQ /TMOE pin function and controls
5
5
TMOE pin waveform output. Bits 3 to 0 are reserved; they always read 1, and cannot be
modified.
Upon reset, PMR4 is initialized to H'0F.
Bit 7: Timer E output select (TEO)
Bit 6: Timer E output on/off (TEO ON)
Bit 5: Fixed frequency select (FREQ)
Bit 4: Variable frequency select (VRFR)
P1 /IRQ /TMOE pin functions are switched as follows, by means of bits 7 to 4 of PMR4 and bit
5
5
IRQC5 of PMR1.
PMR1
PMR4
Bit 5
IRQC5 TEO TEO ON FREQ VRFR Pin Function
Description
Bit 5
Bit 7 Bit 6
Bit 4
Pin State
0
0
0
0
0
0
1
1
0
*
0
1
0
*
*
0
0
*
*
0
P15 pin
P15 pin
Standard I/O port (initial value)
Standard I/O port
TMOE output pin (off) Low level output
TMOE output pin (on) Fixed frequency output:
(φ/2048)
1.95 kHz (φ = 4 MHz)
0.98 kHz (φ = 2 MHz)
0
1
1
1
0
TMOE output pin (on) Fixed frequency output:
(φ/1024)
3.9 kHz (φ = 4 MHz)
1.95 kHz (φ = 2 MHz)
0
1
1
1
*
*
1
TMOE output pin (on) Variable frequency output:
toggled by timer E overflow
*
*
*
IRQ5 input pin
External interrupt input
Note: * Don’t care
117
7.3.3 Pin Functions
Table 7-9 shows the port 1 pin functions.
Table 7-9 Port 1 Pin Functions
Pin
Pin Functions and Selection Method
P17/Vdisp
Selected by mask option
P17 high-voltage input pin
Power supply for VFD driving (Vdisp
)
P16/EVENT
Function is switched as follows by EVENT bit in PMR1
EVENT
0
1
Pin function
P16 input pin
EVENT input pin*
Note: Timer D event input
P15/IRQ5/TMOE,
P14/IRQ4,
Function is switched as follows by bits IRQC5, IRQC4, IRQC1, and IRQC0* in
PMR1 and bit n in PCR1
P11/IRQ1,
PMR1
PCR1n
0
1
—
P10/IRQ0
0
1
Pin function
P1n input pin P1n output pin
IRQn input pin
Notes: 1. Before switching pin functions using bits IRQC5, IRQC4, IRQC1, and
IRQC0 in PMR1, first disable the corresponding interrupts by
clearing their interrupt enable bits. After the pin functions have been
switched, issue any instruction, then clear the interrupt request flags
to 0. For details see section 3.2.3 (1), Port mode register (PMR1).
2. Before entering power-down mode, pins set to external interrupt
input by bits IRQC5, IRQC4, IRQC1, and IRQC0 in PMR1, should be
kept from floating by external connection, or should be switched to
general I/O in PMR1 prior to the state transition.
3. For details on the TMOE function, refer to section 7.3.2 (4), Port
mode register 4 (PMR4). IRQ4, IRQ1, and IRQ0 input can be set for
either rising edge or falling edge detection by register IEGR. For
details, refer to section 3.2.3 (2), IRQ edge select register (IEGR).
IRQ0 and IRQ1 can be used as event input pins for timer B and
timer C, respectively. For details, refer to section 8, Timers.
118
7.3.4 Pin States
Table 7-10 shows the port 1 pin states in each operating mode.
Table 7-10 Port 1 Pin States
Pins
Reset
Sleep
Standby
Watch
Subactive
Active
P17/Vdisp
High
impedance
or Vdisp
High
High
High
impedance
or Vdisp
High
impedance
or Vdisp
Normal
operation
or Vdisp
impedance impedance
or Vdisp
or Vdisp
P16/EVENT, High
Previous
state
High
impedance
High
impedance
High
impedance
Normal
operation
P15/IRQ5/
TMOE,
impedance
or pulled up retained
P14/IRQ4,
P11/IRQ1,
P10/IRQ0
119
7.4 Port 4
7.4.1 Overview
Port 4 is an 8-bit high-voltage I/O port. Figure 7-5 shows the pin configuration.
P47/FS23 (IO/output)
P46/FS22 (IO/output)
P45/FS21 (IO/output)
P44/FS20 (IO/output)
Port 4
P43/FS19 (IO/output)
P42/FS18 (IO/output)
P41/FS17 (IO/output)
P40/FS16 (IO/output)
Note: IO indicates input/output.
Figure 7-5 Port 4 Pin Configuration
7.4.2 Register Configuration and Description
Table 7-11 shows the port 4 register configuration.
Table 7-11 Port 4 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 4
PDR4
R/W
H'00
H'FFD4
1. Port data register 4 (PDR4)
Bit
7
6
5
4
3
2
1
0
PDR47 PDR46 PDR45 PDR44 PDR43 PDR42 PDR41 PDR40
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR4 is an 8-bit register for storing the data of port 4 pins P4 to P4 .
7
0
Upon reset, PDR4 is initialized to H'00.
120
7.4.3 Pin Functions
Table 7-12 shows the port 4 pin functions.
Table 7-12 Port 4 Pin Functions
Pin
Pin Functions and Selection Method
P47/FS23 to
P40/FS16
After designation of the segment pins to be used in bits SR4 to SR0 of the VFD
segment control register (VFSR), bit VFDE in the digit beginning register (DBR)
is set to 1 and VFD controller/driver operation is started. During key scan
intervals, pins designated for segment output can be used by the CPU as
general-purpose ports. Even while the VFD controller/driver is operating, it is
possible to switch segment pins to general-purpose ports by writing 0 in the
VFLAG bit of VFSR.
VFLAG
0
1
Pin function
Pins P47 to P40 are all
Pins designated by bits
general-purpose I/O pins. SR4 to SR0 are segment
*
output pins. Other pins
are for general I/O.
Note: * When a pin functioning as a segment output pin is read, the value of
the corresponding bit in PDR4 is read.
7.4.4 Pin States
Table 7-13 shows the port 4 pin states in each operating mode.
Table 7-13 Port 4 Pin States
Pins
P47/FS23 to High
P40/FS16
Reset
Sleep
Standby
Watch
Subactive
Active
Previous
High
High
High
Normal
impedance or state
impedance or impedance or impedance or operation
pulled down pulled down pulled down
pulled down retained
121
7.5 Port 5
7.5.1 Overview
Port 5 is an 8-bit high-voltage I/O port. Figure 7-6 shows the pin configuration.
P57/FS8 (IO/output)
P56/FS9 (IO/output)
P55/FS10 (IO/output)
P54/FS11 (IO/output)
Port 5
P53/FS12 (IO/output)
P52/FS13 (IO/output)
P51/FS14 (IO/output)
P50/FS15 (IO/output)
Note: IO indicates input/output.
Figure 7-6 Port 5 Pin Configuration
7.5.2 Register Configuration and Description
Table 7-14 shows the port 5 register configuration.
Table 7-14 Port 5 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 5
PDR5
R/W
H'00
H'FFD5
1. Port data register 5 (PDR5)
Bit
7
6
5
4
3
2
1
0
PDR57 PDR56 PDR55 PDR54 PDR53 PDR52 PDR51 PDR50
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR5 is an 8-bit register for storing the data of port 5 pins P5 to P5 .
7
0
Upon reset, PDR5 is initialized to H'00.
122
7.5.3 Pin Functions
Table 7-15 shows the port 5 pin functions.
Table 7-15 Port 5 Pin Functions
Pin
Pin Functions and Selection Method
P57/FS8 to
P50/FS15
After designation of the segment pins to be used in bits SR4 to SR0 of the VFD
segment control register (VFSR), bit VFDE in the digit beginning register (DBR)
is set to 1 and VFD controller/driver operation is started. During key scan
intervals, pins designated for segment output can be used by the CPU as
general-purpose ports. Even while the VFD controller/driver is operating, it is
possible to switch segment pins to general-purpose ports by writing 0 in the
VFLAG bit of VFSR.
VFLAG
0
1
Pin function
Pins P57 to P50 are all
Pins designated by bits
general-purpose I/O pins. SR4 to SR0 are segment
output pins.* Other pins
are for general I/O.
Note: * When a pin functioning as a segment output pin is read, the value of
the corresponding bit in PDR5 is read.
7.5.4 Pin States
Table 7-16 shows the port 5 pin states in each operating mode.
Table 7-16 Port 5 Pin States
Pins
Reset
Sleep
Standby
Watch
Subactive
Active
P57/FS8 to
P50/FS15
High
Previous
High
High
High
Normal
impedance or state
pulled down retained
impedance or impedance or impedance or operation
pulled down pulled down pulled down
123
7.6 Port 6
7.6.1 Overview
Port 6 is an 8-bit high-voltage I/O port. Figure 7-7 shows the pin configuration.
P67/FD7/FS0 (IO/output/output)
P66/FD6/FS1 (IO/output/output)
P65/FD5/FS2 (IO/output/output)
P64/FD4/FS3 (IO/output/output)
Port 6
P63/FD3/FS4 (IO/output/output)
P62/FD2/FS5 (IO/output/output)
P61/FD1/FS6 (IO/output/output)
P60/FD0/FS7 (IO/output/output)
Note: IO indicates input/output.
Figure 7-7 Port 6 Pin Configuration
7.6.2 Register Configuration and Description
Table 7-17 shows the port 6 register configuration.
Table 7-17 Port 6 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 6
PDR6
R/W
H'00
H'FFD6
1. Port data register 6 (PDR6)
Bit
7
6
5
4
3
2
1
0
PDR67 PDR66 PDR65 PDR64 PDR63 PDR62 PDR61 PDR60
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR6 is an 8-bit register for storing the data of port 6 pins P67 to P60.
Upon reset, PDR6 is initialized to H'00.
124
7.6.3 Pin Functions
Table 7-18 shows the port 6 pin functions.
Table 7-18 Port 6 Pin Functions
Pin
Pin Functions and Selection Method
P67/FD7/FS0 to
P60/FD0/FS7
After designation of the digit pins and segment pins to be used in bits DR3 to
DR0 of the VFD digit control register (VFDR), bits SR4 to SR0 of the VFD
segment control register (VFSR), and bits DBR3 to DBR0 of the digit beginning
register (DBR), bit VFDE in DBR is set to 1 and VFD controller/driver operation
is started. During key scan intervals, pins designated for digit or segment
output can be used by the CPU as general-purpose ports. Even while the VFD
controller/driver is operating, it is possible to switch digit pins or segment pins
to general-purpose ports by writing 0 in the VFLAG bit of VFSR.
VFLAG
0
1
Pin function
Pins P67 to P60 are all
Pins are designated as digit
general-purpose I/O pins. output pins,* segment
output pins,* or general
I/O pins by bits DR3 to DR0,
SR4 to SR0, and DBR3 to
DBR0.
Note: * When a pin functioning as a digit output pin or segment output pin is
read, the value of the corresponding bit in PDR6 is read.
7.6.4 Pin States
Table 7-19 shows the port 6 pin states in each operating mode.
Table 7-19 Port 6 Pin States
Pins
Reset
Sleep
Standby
Watch
Subactive
Active
P67/FD7/
FS0 to
P60/FD0/
FS7
High
Previous
High
High
High
Normal
impedance or state
pulled down retained
impedance or impedance or impedance or operation
pulled down pulled down pulled down
125
7.7 Port 7
7.7.1 Overview
Port 7 is an 8-bit high-voltage I/O port. Figure 7-8 shows the pin configuration.
P77 /FD15 (IO/output)
P76 /FD14 (IO/output)
P75 /FD13 (IO/output)
P74 /FD12 (IO/output)
Port 7
P73 /FD11 (IO/output)
P72 /FD10 (IO/output)
P71 /FD9 (IO/output)
P70 /FD8 (IO/output)
Note: IO indicates input/output.
Figure 7-8 Port 7 Pin Configuration
7.7.2 Register Configuration and Description
Table 7-20 shows the port 7 register configuration.
Table 7-20 Port 7 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 7
PDR7
R/W
H'00
H'FFD7
1. Port data register 7 (PDR7)
Bit
7
6
5
4
3
2
1
0
PDR77 PDR76 PDR75 PDR74 PDR73 PDR72 PDR71 PDR70
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR7 is an 8-bit register for storing the data of port 7 pins P7 to P7 .
7
0
Upon reset, PDR7 is initialized to H'00.
126
7.7.3 Pin Functions
Table 7-21 shows the port 7 pin functions.
Table 7-21 Port 7 Pin Functions
Pin
Pin Functions and Selection Method
P77/FD15 to
P70/FD8
After designation of the digit pins to be used, in bits DR3 to DR0 of the VFD
digit control register (VFDR), bit VFDE in the digit beginning register (DBR) is
set to 1 and VFD controller/driver operation is started. Even while the VFD
controller/driver is operating, it is possible to switch digit pins to general-
purpose ports by writing 0 in the VFLAG bit of VFSR.
VFLAG
0
1
Pin function
Pins P77 to P70 are all
Pins designated by bits
general-purpose I/O pins. DR3 to DR0 are digit output
pins.* Other pins are for
general I/O.
Note: * When a pin functioning as a digit output pin is read, the value of the
corresponding bit in PDR7 is read.
7.7.4 Pin States
Table 7-22 shows the port 7 pin states in each operating mode.
Table 7-22 Port 7 Pin States
Pins
P77/FD15 to High
P70/FD8
Reset
Sleep
Standby
Watch
Subactive
Active
Previous
High
High
High
Normal
impedance or state
impedance or impedance or impedance or operation
pulled down pulled down pulled down
pulled down retained
127
7.8 Port 9
7.8.1 Overview
Port 9 is an 8-bit standard I/O port. Figure 7-9 shows the pin configuration.
P97/UD
(IO/input)
P96/SO2
(IO/output)
P95/SI2/CS (IO/input/output)
P94/SCK2 (IO/IO)
Port 9
P93/SO1
P92/SI1
(IO/output)
(IO/input)
P91/SCK1 (IO/IO)
P90/PWM (IO/output)
Note: IO indicates input/output.
Figure 7-9 Port 9 Pin Configuration
7.8.2 Register Configuration and Description
Table 7-23 shows the port 9 register configuration.
Table 7-23 Port 9 Registers
Name
Abbrev.
PMR2
PCR9
R/W
R/W
W
Initial Value
H'00
Address
H'FFEC
H'FFE9
H'FFD9
Port mode register 2
Port control register 9
Port data register 9
H'00
PDR9
R/W
H'00
1. Port mode register 2 (PMR2)
Bit
7
6
5
SI2
0
4
SCK2
0
3
2
SI1
0
1
SCK1
0
0
PWM
0
UP/
DOWN
SO2
0
SO1
0
Initial value
Read/Write
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR2 is an 8-bit read/write register, controlling the selection of port 9 pin functions.
Upon reset, PMR2 is initialized to H'00.
128
Bit 7: P9 /UD pin function switch (UP/DOWN)
7
This bit selects whether pin P9 /UD is used for general-purpose I/O or for timer C up/down
7
control input. Up/down control input (UD) is valid only when bit TMC6 = 1 in timer mode
register C (TMC).
Bit 7
UP/DOWN
Description
0
1
P97/UD pin functions for P97 input/output.
(initial value)
P97/UD pin functions for UD input. If bit TMC6 in TMC is set to 1, then when the UD
input is high, timer C counts down, and when UD is low, timer C counts up.
Bit 6: P9 /SO pin function switch (SO2)
6
2
This bit selects whether pin P9 /SO functions as the P9 I/O pin or the SO output pin.
6
2
6
2
Bit 6
SO2
Description
0
1
P96/SO2 pin functions for P96 input/output.
P96/SO2 pin functions for SO2 output.
(initial value)
Bit 5: P9 /SI /CS pin function switch (SI2)
5
2
This bit selects whether pin P9 /SI /CS functions as the P9 I/O pin or the SI input/CS output
5
2
5
2
pin. For the switching between SI input and CS output see 11.2.5, Port Mode Register 3
2
(PMR3).
Bit 5
SI2
Description
0
P95/SI2/CS pin functions for P95 input/output.
P95/SI2/CS pin functions for SI2 input or CS output.
(initial value)
1
Bit 4: P9 /SCK pin function switch (SCK2)
4
2
This bit selects whether pin P9 /SCK functions as the P9 I/O pin or the SCK I/O pin.
4
2
4
2
Bit 4
SCK2
Description
P94/SCK2 pin functions for P94 input/output.
0
1
(initial value)
P94/SCK2 pin functions for SCK2 input/output. The clock input/output direction and
the divider ratio are set in serial mode register 2 (SMR2).
129
Bit 3: P9 /SO pin function switch (SO1)
3
1
This bit selects whether pin P9 /SO functions as the P9 I/O pin or the SO output pin.
3
1
3
1
Bit 3
SO1
Description
0
1
P93/SO1 pin functions for P93 input/output.
P93/SO1 pin functions for SO1 output.
(initial value)
Bit 2: P9 /SI pin function switch (SI1)
2
1
This bit selects whether pin P9 /SI functions as the P9 I/O pin or the SI input pin.
2
1
2
1
Bit 2
SI1
Description
0
1
P92/SI1 pin functions for P92 input/output.
P92/SI1 pin functions for SI1 input.
(initial value)
Bit 1: P9 /SCK pin function switch (SCK1)
1
1
This bit selects whether pin P9 /SCK functions as the P9 I/O pin or the SCK I/O pin.
1
1
4
1
Bit 1
SCK1
Description
P91/SCK1 pin functions for P91 input/output.
0
1
(initial value)
P91/SCK1 pin functions for SCK1 input/output. The clock input/output direction and
the divider ratio are set in serial mode register 1 (SMR1).
Bit 0: P9 /PWM pin function switch (PWM)
0
This bit selects whether pin P9 /PWM pin functions as the P9 I/O pin or the PWM output pin.
0
0
Bit 0
PWM
Description
0
1
P90/PWM pin functions for P90 input/output.
P90/PWM pin functions for PWM output.
(initial value)
130
2. Port control register 9 (PCR9)
Bit
7
6
5
4
3
2
1
0
PCR97 PCR96 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PCR9 is an 8-bit register for controlling whether each of port 9 pins P9 to P9 functions as an
7
0
input or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR9 and PDR9 are valid when
the affected pin is designated in PMR2 as a general-purpose I/O pin. PCR9 is a write-only
register, which always reads as all 1.
Upon reset, PCR9 is initialized to H'00.
3. Port data register 9 (PDR9)
Bit
7
6
5
4
3
2
1
0
PDR97 PDR96 PDR95 PDR94 PDR93 PDR92 PDR91 PDR90
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR9 is an 8-bit register that stores data for port 9 pins P9 to P9 . If port 9 is read while PCR9
7
0
bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is
read while PCR9 bits are cleared to 0, the pin states are read.
Upon reset, PDR9 is initialized to H'00.
131
7.8.3 Pin Functions
Table 7-24 shows the port 9 pin functions.
Table 7-24 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P97/UD
Functions are switched as follows by means of the UP/DOWN bit* in PMR2
and bit PCR97 in PCR9.
UP/DOWN
PCR97
0
1
—
0
1
Pin function
P97 input pin P97 output pin
UD input pin
Note: * Before entering power-down mode, if this pin is set to UD input by the
UP/DOWN bit in PMR2, it should be kept from floating by external
connection or should be set to general I/O use by clearing the
UP/DOWN bit to 0 prior to the state transition.
P96/SO2*
Functions are switched as follows by means of bit SO2 in PMR2 and bit PCR96
in PCR9.
SO2
0
1
—
PCR96
0
1
Pin function
P96 input pin P96 output pin
SO2 output pin
Note: * The PMOS buffer transistor of pin P96/SO2 can be enabled or
disabled by the SO2PMOS bit in PMR3. For details see 11.2.5, Port
Mode Register 3 (PMR3).
P95/SI2/
Functions are switched as follows by means of bit SI2 in PMR2,* bit CS in
CS
PMR3, and bit PCR95 in PCR9.
SI2
CS
0
1
—
0
1
PCR95
Pin function
0
1
—
—
P95 input pin P95 output pin SI2 input pin CS output pin
Note: * Before entering power-down mode, if this pin is set to SI2 input by bit
SI2 in PMR2, it should be kept from floating by external connection or
should be set to general I/O use by clearing bit SI2 to 0 prior to the
state transition.
132
Table 7-24 Port 9 Pin Functions (cont)
Pin
Pin Functions and Selection Method
P94/SCK2
Functions are switched as follows by means of bit SCK2* in PMR2, bits PS1
and PS0* in serial control register 2 (SCR2), and bit PCR94 in PCR9.
SCK2
PS1, 0
PCR94
0
1
—
Not 11
—
11
—
0
1
Pin function P94 input pin P94 output pin SCK2 output pin SCK2 input pin
Note: * Before entering power-down mode, if this pin is set to SCK2 input by
bit SCK2 in PMR2 and bits PS1 and PS0 in SCR2, it should be kept
from floating by external connection, or else should be set to some
other use by changing bits SCK2 and bits PS1 and PS0 prior to the
state transition.
For the settings of bits PS1 and PS0 in SCR2, see 11.2.3, Serial Control
Register 2 (SCR2).
P93/SO1*
Functions are switched as follows by means of bit SO1 in PMR2 and bit PCR93
in PCR9.
SO1
0
1
—
PCR93
0
1
Pin function
P93 input pin P93 output pin
SO1 output pin
Note: * The PMOS buffer transistor of pin P93/SO1 can be enabled or
disabled by the SO1PMOS bit in PMR3. For details see 10.2.6, Port
Mode Register 3 (PMR3).
P92/SI1
Functions are switched as follows by means of bit SI1* in PMR2 and bit PCR92
in PCR9.
SI1
0
1
—
PCR92
0
1
Pin function
P92 input pin P92 output pin
SI1 input pin
Note: * Before entering power-down mode, if this pin is set to SI1 input by bit
SI1 in PMR2, it should be kept from floating by external connection or
should be set to general I/O use by clearing bit SI1 to 0 prior to the
state transition.
133
Table 7-24 Port 9 Pin Functions (cont)
Pin
Pin Functions and Selection Method
P91/SCK1
Functions are switched as follows by means of bit SCK1 in PMR2,* bits
SMR13 to SMR10 in serial mode register 1 (SMR1)*, and bit PCR91 in PCR9.
SCK1
SMR13 to 10
PCR91
0
1
—
Not 1111
—
1111
—
0
1
Pin function P91 input pin P91 output pin SCK1 output pin SCK1 input pin
Note: * Before entering power-down mode, if this pin is set to SCK1 input by
bit SCK1 in PMR2 and bits SMR13 to SMR10 in SMR1, it should be
kept from floating by external connection, or else should be set to
some other use by changing the SCK1 bit or bits SMR13 to SMR10
prior to the state transition.
For the settings of bits SMR13 to SMR10 in SMR1, see 10.2.1, Serial Mode
Register 1 (SMR1).
P90/PWM
Functions are switched as follows by means of bit PWM in PMR2 and bit
PCR90 in PCR9.
PWM
PCR90
0
1
—
0
1
Pin function
P90 input pin P90 output pin
PWM output pin
7.8.4 Pin States
Table 7-25 shows the port 9 pin states in each operating mode.
Table 7-25 Port 9 Pin States
Pins
Reset
Sleep
Standby
Watch
Subactive
Active
P97/UD,
High
Previous
High
High
High
Normal
P96/SO2,
impedance or state
impedance
impedance
impedance
operation
P95/SI2/CS, pulled up
P94/SCK2,
retained
P93/SO1,
P92/SI1,
P91/SCK1,
P90/PWM
134
Section 8 Timers
8.1 Overview
The H8/3714 Series provides on-chip two prescalers (prescaler S and prescaler W) with different
input clocks, and five timers (timers A through E).
Prescaler S is a 13-bit counter clocked by the system clock (φ = f
/2). Its prescaled outputs are
OSC
used by timers A to C and timer E.
Prescaler W is a 5-bit counter clocked by the subclock (φ
= f /8). Its prescaled output is used
X
SUB
for time-base operation by timer A.
Table 8-1 outlines the functions of timers A through E.
Table 8-1 Timer A to E Functions
Operating Clock
Event
Waveform
Name
Functions
(internal)
Input Pin Output Pin Remarks
Timer A • 8-bit interval timer
φ/8 to φ/8192
(choice of 8 sources)
—
—
—
—
—
• Time base
φSUB/32
(choice of 4 overflow
periods)
Timer B • 8-bit reloadable timer
• Interval timer
P10/IRQ0
P11/IRQ1
—
—
—
φ/8 to φ/8192
(choice of 7 sources)
• Event counter
Counting
direction
can be
Timer C • 8-bit reloadable timer
• Interval timer
φ/8 to φ/8192
(choice of 7 sources)
• Event counter
controlled by
software or
hardware.
• Choice of up- or
down-counting
Timer D • 8-bit event counter
Timer E • 8-bit reloadable timer
• Interval timer
—
P16/EVENT —
P15/IRQ5/
TMOE
—
Can output
square wave
with 50%
—
φ/8 to φ/8192
(choice of 8 sources)
duty cycle
135
8.1.1 Prescaler Operation
1. Prescaler S (PSS)
Prescaler S is a 13-bit counter using the system clock (φ = f
/2) as its input clock. Each
OSC
input clock cycle causes prescaler S to increment once.
Prescaler S is initialized to H'0000 by a reset, and starts counting upon return to active mode.
In standby mode, watch mode, and subactive mode, the system clock (φ) pulse generator
stops, so prescaler S also stops functioning. Its value is reset to H'0000.
The CPU cannot read or write prescaler S data.
The output from prescaler S is shared by timers A to C and E as well as serial communication
interfaces 1 and 2. The frequency division ratio can be set separately for each on-chip
peripheral function.
2. Prescaler W (PSW)
Prescaler W is a 5-bit counter using the subclock (φ
= f /8) as its input clock.
X
SUB
Prescaler W is initialized to H'00 by a reset, and starts counting upon return to active mode.
Even in standby mode, watch mode, or subactive mode, prescaler W continues functioning so
long as clock signals are supplied to pins X and X .
1
2
Prescaler W can be reset by setting bits TMA3 and TMA2 to 1 in timer mode register A
(TMA).
The output from prescaler W can be used as the clock source for timer A, in which case timer
A functions as a time base.
Figure 8-1 shows the clock signals supplied by prescalers S and W to peripheral modules.
136
φ/2 to φ/8192
Timers A to C and E;
System
clock
divider
1/2
System
clock pulse
generator
Prescaler S
fOSC
OSC1
OSC2
φ
serial communication
interfaces 1 and 2
φSUB/32
Subclock
pulse
generator
Subclock
divider
1/8
Timer A
Prescaler W
fX
X1
X2
φSUB
System clock
selection
(LSON bit in
system control
register 1)
CPU, ROM,
RAM, registers,
flags, I/O
Figure 8-1 Clock Supply
137
8.2 Timer A
8.2.1 Overview
Timer A is an 8-bit interval timer. It can be connected to a 32.768 kHz crystal oscillator for use as
a real-time clock time base.
1. Features
Features of timer A are given below.
•
•
•
Choice of eight internal clock sources (φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128,
φ/32, φ/8).
Choice of four overflow periods (2 s, 1 s, 0.5 s, 125 ms) when timer A is used as a time
base (using a 32.768 kHz crystal oscillator).
An interrupt is requested when the counter overflows.
2. Block diagram
Figure 8-2 shows a block diagram of timer A.
32 kHz
crystal
oscillator
Prescaler W
(PSW)
1/8
TMA
TCA
φSUB
φSUB/32
Interval
timer
overflow
φ
φ
φ/8192, /4096, /2048
φ
φ
φ/512, /256, /128,
φ/32, φ/8
Prescaler S
(PSS)
System
clock
1/2
IRRTA
φ
Note: * Can be selected only when the input clock to
TCA is the output from prescaler W (φSUB/32).
Notation:
TMA: Timer mode register A
TCA: Timer counter A
IRRTA: Timer A overflow interrupt request flag (interrupt request register 2)
Figure 8-2 Block Diagram of Timer A
138
3. Register configuration
Table 8-2 shows the register configuration of timer A.
Table 8-2 Timer A Registers
Name
Abbrev.
TMA
R/W
R/W
R
Initial Value
H'F0
Address
H'FFC0
H'FFC1
Timer mode register A
Timer counter A
TCA
H'00
8.2.2 Register Descriptions
1. Timer mode register A (TMA)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
TMA3
0
2
TMA2
0
1
TMA1
0
0
TMA0
0
Initial value
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
TMA is an 8-bit read/write register for selecting the prescaler and input clock.
Upon reset, TMA is initialized to H'F0.
Bits 7 to 4: Reserved bits
Bits 7 to 4 are reserved; they always read 1, and cannot be modified.
Bit 3: Prescaler select (TMA3)
Bit 3 selects either prescaler S or prescaler W as the clock input source for timer A.
Bit 3
TMA3
Description
0
1
Prescaler S (PSS) is clock input source for timer A.
Prescaler W (PSW) is clock input source for timer A.
(initial value)
139
Bits 2 to 0: Clock select (TMA2 to TMA0)
Bits 2 to 0 select the clock input to TCA. The selection is made as follows by the combination of
these bits and bit TMA3.
Bit 3
Bit 2
Bit 1
Bit 0
TMA3 TMA2 TMA1 TMA0
Description
Prescaler divider ratio (interval timer)
or overflow period (time base)
Operation mode
Interval timer mode
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PSS, φ/8192 (initial value)
PSS, φ/4096
PSS, φ/2048
PSS, φ/512
PSS, φ/256
PSS, φ/128
PSS, φ/32
PSS, φ8
Time-base mode
1
PSW, 2 s
PSW, 1 s
PSW, 0.5 s
PSW, 125 ms
PSW and TCA are reset
Note: φ = fOSC/2
140
2. Timer counter A (TCA)
Bit
7
TCA7
0
6
TCA6
0
5
TCA5
0
4
TCA4
0
3
TCA3
0
2
TCA2
0
1
TCA1
0
0
TCA0
0
Initial value
Read/Write
R
R
R
R
R
R
R
R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). The TCA value can be read by the CPU at any time.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 1.
When TCA overflows, the IRRTA bit in interrupt request register 2 (IRR2) is set to 1.
Upon reset, TCA is initialized to H'00.
8.2.3 Timer Operation
Timer A is an 8-bit timer which can be used either as an interval timer or, if a 32.768 kHz crystal
oscillator is connected, as a real-time clock time base.
1. Interval timer operation
When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit
interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval
timing resume immediately after the reset. The clock input to timer A is selected by bits
TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be
selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt request register 2 (IRR2). If IENTA = 1 in
interrupt enable register 2 (IENR2), a CPU interrupt is requested.*
At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A
functions as an interval timer that generates an overflow output at intervals of 256 input clock
pulses.
Note: * For details on interrupts, see 3.2.2, Interrupts.
141
2. Real-time clock time base operation
When bit TMA3 in TMA is set to 1, timer A functions as a time base for a real-time clock by
counting clock signals output by prescaler W.
The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four
periods is available.
3. Count initialization
When bits TMA3 and TMA2 are both set to 1, PSW and TCA are initialized (cleared to 0 and
stopped). From this initialized state, if bit TMA3 is left set to 1 and bit TMA2 is cleared to 0,
timer A begins counting from 0 in time base mode.
From the initialized state, if bit TMA3 is cleared to 0, timer A begins counting from 0 in
interval timer mode. (Bit TMA2 can be either set or cleared.) However, since prescaler S
(PSS) has not been initialized, the time between clearing bit TMA3 to 0 and the first count
will vary.
142
8.3 Timer B
8.3.1 Overview
Timer B is an 8-bit up-counter that increments each time a clock pulse is input. This timer has
two operation modes, interval and auto reload.
1. Features
Features of timer B are given below.
•
Choice of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/128, φ/32, φ/8) or
an external clock (can be used to count external events).
•
An interrupt is requested when the counter overflows.
2. Block diagram
Figure 8-3 shows a block diagram of timer B.
TMB
Prescaler S
(13 bits)
φ
TCB
TLB
IRQ0
IRRTB
Notation:
TMB: Timer mode register B
TCB: Timer counter B
TLB:
Timer load register B
IRRTB: Timer B overflow interrupt request flag (interrupt request register 2)
Figure 8-3 Block Diagram of Timer B
143
3. Pin configuration
Table 8-3 shows the timer B pin configuration.
Table 8-3 Pin Configuration
Name
Abbrev.
I/O
Function
Event input pin
P10/IRQ0
Input
Timer B event input
4. Register configuration
Table 8-4 shows the register configuration of timer B.
Table 8-4 Timer B Registers
Name
Abbrev.
TMB
R/W
R/W
R
Initial Value
H'78
Address
H'FFC2
H'FFC3
H'FFC3
Timer mode register B
Timer counter B
Timer load register B
TCB
H'00
TLB
W
H'00
8.3.2 Register Descriptions
1. Timer mode register B (TMB)
Bit
7
TMB7
0
6
—
1
5
—
1
4
—
1
3
—
1
2
TMB2
0
1
TMB1
0
0
TMB0
0
Initial value
Read/Write
R/W
—
—
—
—
R/W
R/W
R/W
TMB is an 8-bit read/write register for selecting the auto-reload function and input clock.
Upon reset, TMB is initialized to H'78.
Bit 7: Auto-reload function select (TMB7)
Bit 7 selects the auto-reload function of timer B.
Bit 7
TMB7
Description
0
1
Interval timer function selected.
Auto-reload function selected.
(initial value)
144
Bits 6 to 3: Reserved bits
Bits 6 to 3 are reserved; they always read 1, and cannot be modified.
Bits 2 to 0: Clock select (TMB2 to TMB0)
Bits 2 to 0 select the clock input to TCB. For external clock counting, either the rising or falling
edge can be selected.
Bit 2
Bit 1
Bit 0
TMB2
TMB1
TMB0
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Internal clock: φ/8192.
Internal clock: φ/2048.
Internal clock: φ/512.
Internal clock: φ/256.
Internal clock: φ/128.
Internal clock: φ/32.
(initial value)
Internal clock: φ/8.
External clock (P10/IRQ0): rising or falling edge.*
Note: * The edge of the external event signal is selected by bit IEG0 in the IRQ edge select
register (IEGR). For details see 3.2.3 (2), IRQ edge select register (IEGR).
2. Timer counter B (TCB)
Bit
7
TCB7
0
6
TCB6
0
5
TCB5
0
4
TCB4
0
3
TCB3
0
2
TCB2
0
1
TCB1
0
0
TCB0
0
Initial value
Read/Write
R
R
R
R
R
R
R
R
TCB is an 8-bit read-only up-counter, which is incremented by internal or external clock input.
The clock source for input to this counter is selected by bits TMB2 to TMB0 in timer mode
register B (TMB). The TCB value can be read by the CPU at any time.
When TCB overflows from H'FF to H'00 or to the value set in TLB, the IRRTB bit in interrupt
request register 2 (IRR2) is set to 1.
TCB is allocated to the same address as timer load register B (TLB).
Upon reset, TCB is initialized to H'00.
145
3. Timer load register B (TLB)
Bit
7
TLB7
0
6
TLB6
0
5
TLB5
0
4
TLB4
0
3
TLB3
0
2
TLB2
0
1
TLB1
0
0
TLB0
0
Initial value
Read/Write
W
W
W
W
W
W
W
W
TLB is an 8-bit write-only register for setting the reload value of timer counter B (TCB).
When a reload value is set in TLB, the same value is loaded into timer counter B (TCB) as well,
and TCB starts counting up from that value. When TCB overflows during operation in auto-
reload mode, the TLB value is loaded in TCB. Accordingly, overflow periods can be set within
the range of 1 to 256 input clocks.
The same address is allocated to TLB as to TCB.
Upon reset, TLB is initialized to H'00.
8.3.3 Timer Operation
Timer B is an 8-bit multifunction timer. It can be used as an interval timer, an auto-reload timer,
or an event counter. (Event counting requires an input pin setting.)
1. Timer B operation modes
Timer B is an 8-bit up-counter which is incremented each time a clock pulse is input. The
two operation modes, interval and auto-reload, are explained below.
•
Interval timer operation
When bit TMB7 in timer mode register B (TMB) is cleared to 0, timer B functions as an 8-bit
interval timer.
Upon reset, TCB is cleared to H'00 and bit TMB7 is cleared to 0, so up-counting and interval
timing resume immediately after the reset. The clock input to timer B is selected from seven
internal clock signals output by prescaler S, or an external clock input at pin P1 /IRQ . The
0
0
selection is made by bits TMB2 to TMB0 of TMB.
After the count value in TCB reaches H'FF, the next clock signal input causes timer B to
overflow, setting bit IRRTB to 1 in interrupt request register 2 (IRR2). If IENTB = 1 in
interrupt enable register 2 (IENR2), a CPU interrupt is requested.*
At overflow, TCB returns to H'00 and starts counting up again.
During interval timer operation (TMB7 = 0), when a value is set in timer load register B
(TLB), the same value is set in TCB.
Note: * For details on interrupts, see 3.2.2, Interrupts.
146
•
Auto-reload timer operation
Setting bit TMB7 in TMB to 1 causes timer B to function as an 8-bit auto-reload timer.
When a reload value is set in TLB, the same value is loaded into TCB, becoming the value
from which TCB starts its count.
After the count value in TCB reaches H'FF, the next clock signal input causes timer B to
overflow. The TLB value is then loaded into TCB, and the count continues from that value.
The overflow period can be set within a range from 1 to 256 input clocks, depending on the
TLB value.
The clock sources and interrupts in auto-reload mode are the same as for interval mode.
In auto-reload mode (bit TMB7 = 1), setting a new TLB value also initializes TCB.
2. Operation on external clock
Timer B can operate on an external clock input as an event signal at pin P1 /IRQ . External
0
0
clock operation is selected by setting bits TMB2 to TMB0 in timer mode register B to all 1’s
(111). TCB can count either rising or falling edges of the input at pin P1 /IRQ .
0
0
When timer B is used to count external event input, bit IRQC0 in port mode register 1
(PMR1) should be set to 1, and bit IEN0 in interrupt enable register 1 (IENR1) should be
cleared to 0 to disable IRQ interrupt requests.
0
147
8.4 Timer C
8.4.1 Overview
Timer C is an 8-bit up/down counter that increments or decrements each time a clock pulse is
input. This timer has two operation modes, interval and auto reload.
1. Features
Features of timer C are given below.
•
Choice of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/128, φ/32, φ/8) or
an external clock (can be used to count external events).
•
•
An interrupt is requested when the counter overflows.
Can be switched between up- and down-counting by software or hardware control.
2. Block diagram
Figure 8-4 shows a block diagram of timer C.
φ
Prescaler S
TMC
UD
TCC
IRQ1
TLC
IRRTC
Notation:
TMC: Timer mode register C
TCC: Timer counter C
TLC: Timer load register C
IRRTC: Timer C overflow interrupt request flag (interrupt request register 2)
Figure 8-4 Block Diagram of Timer C
148
3. Pin configuration
Table 8-5 shows the timer C pin configuration.
Table 8-5 Pin Configuration
Name
Abbrev.
P11/IRQ1
P97/UD
I/O
Function
Event input pin
Up/down select pin
Input
Input
Timer C event input
Timer C counting direction control
4. Register configuration
Table 8-6 shows the register configuration of timer C.
Table 8-6 Timer C Registers
Name
Abbrev.
TMC
R/W
R/W
R
Initial Value
H'18
Address
H'FFC4
H'FFC5
H'FFC5
Timer mode register C
Timer counter C
Timer load register C
TCC
H'00
TLC
W
H'00
8.4.2 Register Descriptions
1. Timer mode register C (TMC)
Bit
7
TMC7
0
6
TMC6
0
5
TMC5
0
4
—
1
3
—
1
2
TMC2
0
1
TMC1
0
0
TMC0
0
Initial value
Read/Write
R/W
R/W
R/W
—
—
R/W
R/W
R/W
TMC is an 8-bit read/write register for selecting the auto-reload function, counting direction, and
input clock.
Upon reset, TMC is initialized to H'18.
149
Bit 7: Auto-reload function select (TMC7)
Bit 7 selects the auto-reload function of timer C.
Bit 7
TMC7
Description
0
1
Interval timer function selected.
Auto-reload function selected.
(initial value)
Bit 6: Counter up/down control 1 (TMC6)
This bit selects whether the counting direction of timer counter C (TCC) is controlled by hardware
using pin P9 /UD, or by software using bit TMC5.
7
Bit 5: Counter up/down control 2 (TMC5)
This bit selects whether TCC is an up-counter or down-counter. The setting of this bit is valid
when bit TMC6 = 0.
Bits TMC6 and TMC5 operate as follows.
Bit 6
Bit 5
TMC6
TMC5
Description
0
0
1
0
1
*
TCC is an up-counter.
TCC is a down-counter.
(initial value)
TCC up/down control is by input at pin P97/UD. TCC is a down-counter if
UD input is high, and an up-counter if UD input is low.
Note: * Don’t care.
Bits 4 and 3: Reserved bits
Bits 4 and 3 are reserved; they always read 1, and cannot be modified.
Bits 2 to 0: Clock select (TMC2 to TMC0)
150
Bits 2 to 0 select the clock input to TCC. For external clock counting, either the rising or falling
edge can be selected.
Bit 2
Bit 1
Bit 0
TMC2 TMC1 TMC0 Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Internal clock: φ/8192.
Internal clock: φ/2048.
Internal clock: φ/512.
(initial value)
Internal clock: φ/256.
Internal clock: φ/128.
Internal clock: φ/32.
Internal clock: φ/8.
External clock (P11/IRQ1): rising or falling edge.*
Note: * The edge of the external clock is selected by bit IEG1 in the IRQ edge select register
(IEGR). For details see 3.2.3 2, IRQ edge select register (IEGR).
2. Timer counter C (TCC)
Bit
7
TCC7
0
6
TCC6
0
5
TCC5
0
4
TCC4
0
3
TCC3
0
2
TCC2
0
1
TCC1
0
0
TCC0
0
Initial value
Read/Write
R
R
R
R
R
R
R
R
TCC is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or
external clock input. The clock source for input to this counter is selected by bits TMC2 to TMC0
in timer mode register C (TMC). The TCC value can be read by the CPU at any time.
When TCC overflows (from H'FF to H'00 or to the value set in TLC) or underflows (from H'00 to
H'FF or to the value set in TLC), the IRRTC bit in interrupt request register 2 (IRR2) is set to 1.
TCC is allocated to the same address as timer load register C (TLC).
Upon reset, TCC is initialized to H'00.
151
3. Timer load register C (TLC)
Bit
7
TLC7
0
6
TLC6
0
5
TLC5
0
4
TLC4
0
3
TLC3
0
2
TLC2
0
1
TLC1
0
0
TLC0
0
Initial value
Read/Write
W
W
W
W
W
W
W
W
TLC is an 8-bit write-only register for setting the reload value of TCC. When a reload value is set
in TLC, the same value is loaded into timer counter C (TCC) as well, and TCC starts counting up
or down from that value. When TCC overflows or underflows during operation in auto-reload
mode, the TLC value is loaded in TCC. Accordingly, overflow and underflow periods can be set
within the range of 1 to 256 input clocks.
The same address is allocated to TLC as to TCC.
Upon reset, TLC is initialized to H'00.
8.4.3 Timer Operation
Timer C is an 8-bit multifunction timer. It can be used as an interval timer, an auto-reload timer,
or an event counter. (Event counting requires an input pin setting.)
1. Timer C operation modes
Timer C is an 8-bit up-/down-counter which is incremented or decremented each time a clock
pulse is input. The two operation modes, interval and auto-reload, are explained below.
•
Interval timer operation
When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an
8-bit interval timer.
Upon reset, timer counter C (TCC) is initialized to H'00 and TMC to H'18, so up-counting
and interval timing resume immediately after the reset. The clock input to timer C is selected
from seven internal clock signals output by prescaler S, or an external clock input at pin
P1 /IRQ . The selection is made by bits TMC2 to TMC0 in TMC.
1
1
Either software or hardware can control whether TCC counts up or down. The selection is
made by TMC bits TMC6 and TMC5.
152
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C
to overflow (underflow), setting bit IRRTC to 1 in interrupt request register 2 (IRR2). If bit
IENTC = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.*
At overflow or underflow, TCC returns to H'00 or H'FF and starts counting up or down again.
During interval timer operation (TMC7 = 0), when a value is set in timer load register C
(TLC), the same value is set in TCC.
Note: * For details on interrupts, see 3.2.2, Interrupts.
•
Auto-reload timer operation
Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When
a reload value is set in TLC, the same value is loaded into TCC, becoming the value from
which TCC starts its count.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C
to overflow (or underflow). The TLC value is then loaded into TCC, and the count continues
from that value. The overflow (underflow) period can be set within a range from 1 to 256
input clocks, depending on the TLC value.
The clock sources, up/down control, and interrupts in auto-reload mode are the same as for
interval mode.
In auto-reload mode (bit TMC7 = 1), setting a new TLC value also initializes TCC.
2. Operation on external clock
Timer C can operate on an external clock input as an event signal at pin P1 /IRQ . External
1
1
clock operation is selected by setting bits TMC2 to TMC0 in timer mode register C to all 1’s
(111). TCC can count either rising or falling edges of the input at pin P1 /IRQ .
1
1
When timer C is used to count external event input, bit IRQC1 in port mode register 1
(PMR1) should be set to 1, and bit IEN1 in interrupt enable register 1 (IENR1) should be
cleared to 0 to disable IRQ interrupt requests.
1
3. TCC up/down control by hardware
The counting direction of timer C can be controlled by input at pin P9 /UD. When bit TMC6
7
in TMC is set to 1, high-level input at the UD pin selects down-counting, while low-level
input selects up-counting.
When using input at pin UD for this control function, set the UP/DOWN bit in port mode
register 2 (PMR2) to 1.
153
8.5 Timer D
8.5.1 Overview
Timer D is an 8-bit event counter, which is incremented by input of an external event signal.
Either rising or falling edges of the external event signal can be counted.
1. Features
Features of timer D are given below.
•
•
Choice of rising or falling edge for external event counting.
An interrupt is requested when the counter overflows.
2. Block diagram
Figure 8-5 shows a block diagram of timer D.
TMD
TCD
EVENT
Notation:
TMD: Timer mode register D
TCD: Timer counter D
IRRTD
IRRTD: Timer D overflow interrupt request flag (interrupt request register 2)
Figure 8-5 Block Diagram of Timer D
154
3. Pin configuration
Table 8-7 shows the timer D pin configuration.
Table 8-7 Pin Configuration
Name
Abbrev.
I/O
Function
Event input pin
P16/EVENT
Input
Timer D event input
4. Register configuration
Table 8-8 shows the register configuration of timer D.
Table 8-8 Timer D Registers
Name
Abbrev.
TMD
R/W
R/W*
R
Initial Value
H'7E
Address
H'FFC6
H'FFC7
Timer mode register D
Timer counter D
TCD
H'00
Note: * Writing to bit 7 of TMD is possible only when writing 1 to clear the counter.
8.5.2 Register Descriptions
1. Timer mode register D (TMD)
Bit
7
CLR
0
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
EDG
0
Initial value
Read/Write
W
—
—
—
—
—
—
R/W
TMD is an 8-bit read/write register for clearing timer counter D (TCD), and for selecting whether
input at the external event pin is sensed at the rising or falling edge.
Bit 7: Counter clear (CLR)
Bit 7 initializes TCD to H'00.
Bit 7
CLR
Description
0
After 1 is written to this bit to initialize TCD, it is cleared to 0 by
hardware.
(initial value)
1
Initializes TCD to H'00.
155
Bits 6 to 1: Reserved bits
Bits 6 to 1 are reserved; they always read 1, and cannot be modified.
Bit 0: Edge select (EDG)
Bit 0 selects the rising or falling edge of input at external event pin P1 /EVENT.
6
Bit 0
EDG
Description
0
1
TCD counts falling edges of input at pin P16/EVENT.
TCD counts rising edges of input at pin P16/EVENT.
(initial value)
2. Timer counter D (TCD)
Bit
7
TCD7
0
6
TCD6
0
5
TCD5
0
4
TCD4
0
3
TCD3
0
2
TCD2
0
1
TCD1
0
0
TCD0
0
Initial value
Read/Write
R
R
R
R
R
R
R
R
TCD is an 8-bit read-only up-counter, which is incremented by external clock input at pin
P1 /EVENT. The input clock edge is selected by the EDG bit in timer mode register D (TMD).
6
The TCD value can be read by the CPU at any time.
When TCD overflows from H'FF to H'00, the IRRTD bit in interrupt request register 2 (IRR2) is
set to 1.
Upon reset, TCD is initialized to H'00.
156
8.5.3 Timer Operation
1. Operation on external clock
Timer D operates on an external clock input at pin P1 /EVENT, used as an event input pin.
6
The rising or falling edge of this input is selected by the EDG bit in timer mode register D
(TMD).
After the count value in TCD reaches H'FF, the next clock signal input causes timer D to
overflow, setting bit IRRTD in interrupt request register 2 (IRR2) to 1 . If bit IENTD = 1 in
interrupt enable register 2 (IENR2), a CPU interrupt is requested.*
At overflow, TCD returns to H'00 and starts counting up again.
TCD can be cleared by setting the CLR bit to 1 in TMD.
To use external event input, the EVENT bit in port mode register 1 (PMR1) must be set to 1.
Note: * For details on interrupts, see 3.2.2, Interrupts.
157
8.6 Timer E
8.6.1 Overview
Timer E is an 8-bit up-counter that increments each time a clock pulse is input. This timer has
two operation modes, interval and auto reload. In addition, it can output a square wave with a
50% duty cycle, using overflow signals or signals from prescaler S.
1. Features
Features of timer E are given below.
•
Choice of eight internal clock sources (φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32,
φ/8).
•
•
An interrupt is requested when the counter overflows.
Prescaler signals can provide a fixed-frequency output with a 50% duty cycle.
When φ = 4 MHz, output is 1.95 kHz or 3.9 kHz.
When φ = 2 MHz, output is 0.98 kHz or 1.95 kHz.
•
Overflow signals can produce square wave output of any frequency with a 50% duty cycle.
158
2. Block diagram
Figure 8-6 shows a block diagram of timer E.
TME
TLE
φ
Prescaler S
TCE
Notation:
TME: Timer mode register E
TCE: Timer counter E
TLE: Timer load register E
IRRTE
TMOE output
latch
IRRTE: Timer E overflow interrupt request flag (interrupt request register 2)
Figure 8-6 Block Diagram of Timer E
3. Pin configuration
Table 8-9 shows the timer E pin configuration.
Table 8-9 Pin Configuration
Name
Abbrev.
I/O
Function
Timer E waveform output pin
P15/IRQ5/TMOE
Output
Timer E output
159
4. Register configuration
Table 8-10 shows the register configuration of timer E.
Table 8-10 Timer E Registers
Name
Abbrev.
TME
R/W
R/W
R
Initial Value
H'78
Address
H'FFC8
H'FFC9
H'FFC9
H'FFEE
Timer mode register E
Timer counter E
Timer load register E
Port mode register 4
TCE
H'00
TLE
W
H'00
PMR4
R/W
H'0F
8.6.2 Register Descriptions
1. Timer mode register E (TME)
Bit
7
TME7
0
6
—
1
5
—
1
4
—
1
3
—
1
2
TME2
0
1
TME1
0
0
TME0
0
Initial value
Read/Write
R/W
—
—
—
—
R/W
R/W
R/W
TME is an 8-bit read/write register for selecting the auto-reload function and input clock.
Upon reset, TME is initialized to H'78.
Bit 7: Auto-reload function select (TME7)
Bit 7 selects the auto-reload function of timer E.
Bit 7
TME7
Description
0
1
Interval timer function selected.
Auto-reload function selected.
(initial value)
Bits 6 to 3: Reserved bits
Bits 6 to 3 are reserved; they always read 1, and cannot be modified.
160
Bits 2 to 0: Clock select (TME2 to TME0)
Bits 2 to 0 select the clock input to TCE.
Bit 2
Bit 1
Bit 0
TME2 TME1 TME0 Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Internal clock: φ/8192.
Internal clock: φ/4096.
Internal clock: φ/2048.
Internal clock: φ/512.
Internal clock: φ/256.
Internal clock: φ/128.
Internal clock: φ/32.
Internal clock: φ/8.
(initial value)
2. Timer counter E (TCE)
Bit
7
TCE7
0
6
TCE6
0
5
TCE5
0
4
TCE4
0
3
TCE3
0
2
TCE2
0
1
TCE1
0
0
TCE0
0
Initial value
Read/Write
R
R
R
R
R
R
R
R
TCE is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TME2 to TME0 in timer mode register E
(TME). The TCE value can be read by the CPU at any time.
When TCE overflows from H'FF to H'00 or to the value set in TLE, the IRRTE bit in interrupt
request register 2 (IRR2) is set to 1.
TCE is allocated to the same address as timer load register E (TLE).
Upon reset, TCE is initialized to H'00.
161
3. Timer load register E (TLE)
Bit
7
TLE7
0
6
TLE6
0
5
TLE5
0
4
TLE4
0
3
TLE3
0
2
TLE2
0
1
TLE1
0
0
TLE0
0
Initial value
Read/Write
W
W
W
W
W
W
W
W
TLE is an 8-bit write-only register for setting the reload value of TCE.
When a reload value is set in TLE, the same value is loaded into timer counter E (TCE) as well,
and TCE starts counting up from that value. When TCE overflows during operation in auto-reload
mode, the TLE value is loaded in TCE. Accordingly, the overflow period can be set within the
range of 1 to 256 input clocks.
The same address is allocated to TLE as to TCE.
Upon reset, TLE is initialized to H'00.
4. Port mode register 4 (PMR4)
Bit
7
6
5
4
VRFR
0
3
—
1
2
—
1
1
—
1
0
—
1
TEO
0
TEO ON FREQ
Initial value
Read/Write
0
0
R/W
R/W
R/W
R/W
—
—
—
—
PMR4 is an 8-bit read/write register, for switching functions of pin P1 /IRQ /TMOE and for
5
5
controlling waveform output from pin TMOE.
Upon reset, PMR4 is initialized to H'0F.
162
Bit 7: Timer E output select (TEO)
Bit 6: Timer E output on/off (TEO ON)
Bit 5: Fixed frequency select (FREQ)
Bit 4: Variable frequency select (VRFR)
P1 /IRQ /TMOE pin functions are switched as follows, by means of bits 7 to 4 of PMR4 and bit
5
5
IRQC5 of port mode register 1 (PMR1).
PMR1
Bit 5
PMR4
Bit 5
TEO ON FREQ
Description
Bit 7
Bit 6
Bit 4
IRQC5 TEO
VRFR Pin Function
Pin State
0
0
0
0
0
1
0
*
0
0
*
*
0
*
*
P15 pin
P15 pin
Standard I/O port (initial value)
Standard I/O port
TMOE output pin Low-level output
(off)
0
1
1
0
0
TMOE output pin Fixed-frequency output:
(on)
(φ/2048)
1.95 kHz (φ = 4 MHz)
0.98 kHz (φ = 2 MHz)
0
1
1
1
0
TMOE output pin Fixed-frequency output:
(on)
(φ/1024)
3.9 kHz (φ = 4 MHz)
1.95 kHz (φ = 2 MHz)
0
1
1
1
*
*
1
TMOE output pin Variable-frequency output:
(on)
toggled by timer E overflow
*
*
*
IRQ5 input pin
External interrupt input
Note: * Don’t care.
Bits 3 to 0: Reserved bits
Bits 3 to 0 are reserved; they always read 1, and cannot be modified.
163
8.6.3 Timer Operation
Timer E is an 8-bit up-counter that is incremented each time a clock pulse is input. It functions as
an interval or auto-reload timer. It can also output a square wave having a 50% duty cycle. Each
of these operation modes is explained below.
1. Interval timer operation
When bit TME7 in timer mode register E (TME) is cleared to 0, timer E functions as an 8-bit
interval timer.
Upon reset, timer counter E (TCE) is reset to H'00 and bit TME7 is cleared to 0, so up-
counting and interval timing resume immediately after the reset. The clock input to timer E is
selected from eight internal clock signals output by prescaler S. The selection is made by bits
TME2 to TME0 in TME.
After the count value in TCE reaches H'FF, the next clock signal input causes timer E to
overflow, setting bit IRRTE to 1 in interrupt request register 2 (IRR2). If bit IENTE = 1 in
interrupt enable register 2 (IENR2), a CPU interrupt is requested.*
At overflow, TCE returns to H'00, and starts counting up again.
During interval timer operation (TME7 = 0), when a value is set in timer load register E
(TLE), the same value is set in TCE.
Note: * For details on interrupts, see 3.2.2, Interrupts.
2. Auto-reload timer operation
Setting bit TME7 in TME to 1 causes timer E to function as an 8-bit auto-reload timer. When
a reload value is set in TLE, the same value is loaded into TCE, becoming the value from
which TCE starts its count.
After the count value in TCE reaches H'FF, the next clock signal input causes timer E to
overflow. The TLE value is then loaded into TCE, and the count continues from that value.
The overflow period can be set within a range from 1 to 256 input clocks, depending on the
TLE value.
The clock sources and interrupts in auto-reload mode are the same as for interval mode.
In auto-reload mode (bit TME7 = 1), setting a new TLE value also initializes TCE.
164
3. Square wave output
A 50% duty square wave can be output at pin P1 /IRQ /TMOE if this function is selected in
5
5
port mode register 4 (PMR4) and bit IRQC5 in port mode register 1 (PMR1). When bit
VRFR = 0 in PMR4, the square wave has a fixed frequency designated in the FREQ bit. For
the frequencies that can be output, see 8.6.2 (4), Port mode register 4 (PMR4).
When bit VRFR = 1, timer E overflow generates a toggle output alternating between low and
high level (see figure 8-7). The overflow period is selected in timer load register E (TLE),
with timer E operating in auto-reload mode (bit TME7 = 1). The operating clock can be
selected by means of bits TME2 to TME0. These settings can give a waveform output of any
desired frequency within the range shown in table 8-11.
Timer E value = H'FF
TLE value
(auto-reload mode selected)
TMOE output waveform
Timer E interrupt request
Figure 8-7 Square Wave Output Generated by Timer E Overflow
165
Table 8-11 Frequencies of Output Waveforms Generated by Timer E Overflow
Output Waveform (φ = 2 MHz)
1 Count (TLE = H'FF) × 2
256 Counts (TLE = H'00) × 2
Count Time Output Frequency
Internal Clock
Count Time Output Frequency
φ/8 (250 kHz)
8 µs
125 kz
2024 µs
488.3 Hz
122.1 Hz
30.5 Hz
15.3 Hz
φ/32 (62.5 kHz)
32 µs
31.25 kHz
7.8125 kHz
3.9063 kHz
1.9531 kHz
488.3 Hz
244.1 Hz
122.1 Hz
8192 µs
φ/128 (15.62 kHz)
φ/256 (7.8125 kHz)
φ/512 (3.9062 kHz)
φ/2048 (976.5 Hz)
φ/4096 (488.2 Hz)
φ/8192 (244.1 Hz)
128 µs
256 µs
512 µs
2.048 ms
4.096 ms
8.192 ms
32.768 ms
65.536 ms
131.072 ms 7.63 Hz
524.288 ms 1.91 Hz
1048.576 ms 0.95 Hz
2097.152 ms 0.477 Hz
Output Waveform (φ = 4 MHz)
1 Count (TLE = H'FF) × 2
256 Counts (TLE = H'00) × 2
Internal Clock
Count Time Output Frequency
Count Time Output Frequency
φ/8 (500 kHz)
4 µs
250 kz
1024 µs
976.6 Hz
244.1 Hz
61.0 Hz
30.5 Hz
15.3 Hz
φ/32 (125 kHz)
16 µs
62.5 kHz
15.625 kHz
7.8125 kHz
3.9063 kHz
976.6 Hz
488.3 Hz
244.1 Hz
4096 µs
φ/128 (31.25 kHz)
φ/256 (15.625 kHz)
φ/512 (7.8125 kHz)
φ/2048 (1.963 Hz)
φ/4096 (976.52 Hz)
φ/8192 (488.2 Hz)
64 µs
16.384 ms
32.768 ms
65.536 ms
128 µs
256 µs
1.024 ms
2.048 ms
4.096 ms
262.144 ms 3.8 Hz
524.288 ms 1.91 Hz
1048.576 ms 0.95 Hz
166
8.7 Interrupts
Timer A to E interrupts are requested when a timer overflows or underflows. Each timer is
assigned its own vector address. The priority of interrupts is in the order of timer A (high) to
timer E (low). Further details are given in 3.2.2, Interrupts, table 3-2, Interrupt Sources.
When timers A to E overflow, the corresponding bit IRRTA to IRRTE in interrupt request register
2 (IRR2) is set to 1. These interrupt flags are not cleared even if the interrupt is accepted. They
must be cleared to 0 by software in the interrupt handler routine.
Interrupts may be enabled or disabled independently for each timer by means of bits IENTA to
IENTE in interrupt enable register 2 (IENR2).
For further details see 3.2.3, Interrupt Control Registers.
8.8 Application Notes
Even when the EVENT bit in port mode register 1 (PMR1) designates the P1 usage of pin
6
P1 /EVENT, reading the P1 pin may cause timer D to increment. When using timer D, be sure
6
6
to clear timer counter D (TCD) by means of the CLR bit in timer mode register D (TMD).
167
168
Section 9 14-Bit PWM
9.1 Overview
The H8/3714 Series is provided with a 14-bit PWM (pulse width modulator) on-chip, which can
be used as a D/A converter by connecting a low-pass filter.
9.1.1 Features
Features of the 14-bit PWM are as follows.
•
Choice of two conversion periods
A conversion period of 32768/φ, with a minimum modulation width of 2/φ (PWCR0 = 1), or a
conversion period of 16384/φ, with a minimum modulation width of 1/φ (PWCR0 = 0), can be
chosen.
•
Pulse division method for less ripple
9.1.2 Block Diagram
Figure 9-1 shows a block diagram of the 14-bit PWM.
PWDRL
PWDRU
φ/2
PWM waveform
P90/PWM
generator
φ/4
PWCR
PMR2 (bit 0)
Notation:
PWDRL: PWM data register L
PWDRU: PWM data register U
PWCR: PWM control register
PMR2: Port mode register 2
Figure 9-1 Block Diagram of 14-Bit PWM
169
9.1.3 Pin Configuration
Table 9-1 shows the output pin assigned to the 14-bit PWM.
Table 9-1 Pin Configuration
Name
Abbrev.
I/O
Function
PWM waveform output pin
PWM
Output
PWM waveform output
9.1.4 Register Configuration
Table 9-2 shows the register configuration of the 14-bit PWM.
Table 9-2 Register Configuration
Name
Abbrev.
PWCR
R/W
W
Initial Value
H'FE
Address
H'FFCC
H'FFCD
H'FFCE
PWM control register
PWM data register U
PWM data register L
PWDRU
PWDRL
W
H'C0
W
H'00
170
9.2 Register Descriptions
9.2.1 PWM Control Register (PWCR)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
PWCR0
Initial value
Read/Write
0
—
—
—
—
—
—
—
W
PWCR is an 8-bit write-only register for input clock selection.
Upon reset, PWCR is initialized to H'FE.
Bits 7 to 1: Reserved bits
Bits 7 to 1 are reserved; they always read 1, and cannot be modified.
Bit 0: Clock select (PWCR0)
Bit 0 selects the clock supplied to the 14-bit PWM. This bit is a write-only bit; it always
reads 1.
Bit 0
PWCR0
Description
0
The input clock is φ/2 (tφ = 2/φ). The conversion period is 16384/φ,
with a minimum modulation width of 1/φ.
(initial value)
1
The input clock is φ/4 (tφ = 4/φ). The conversion period is 32768/φ, with a minimum
modulation width of 2/φ.
Notation:
tφ: Period of PWM input clock
171
9.2.2 PWM Data Registers U and L (PWDRU, PWDRL)
PWDRU
Bit
7
—
1
6
—
1
5
4
3
2
1
0
PWDRU5PWDRU4PWDRU3PWDRU2 PWDRU1PWDRU0
Initial value
Read/Write
0
0
0
0
0
0
—
—
W
W
W
W
W
W
PWDRL
Bit
7
6
5
4
3
2
1
0
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU
and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total high-
level width of one PWM waveform cycle.
When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the
PWM waveform generator, updating the PWM waveform generation data. The 14-bit data should
always be written in the following sequence, first to PWDRL and then to PWDRU.
1. Write the lower 8 bits to PWDRL.
2. Write the upper 6 bits to PWDRU.
PWDRU and PWDRL are write-only registers. If they are read, all bits read 1.
Upon reset, PWDRU and PWDRL are initialized to H'C000.
172
9.3 Operation
When using the 14-bit PWM, set the registers in the following sequence.
1. Set bit PWM in port mode register 2 (PMR2) to 1 so that pin P9 /PWM is designated for
0
PWM output.
2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either
32768/φ (PWCR0 = 1) or 16384/φ (PWCR0 = 0).
3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write
in the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the
data in these registers will be latched in the PWM waveform generator, updating PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 9-2. The total of the high-
level pulse widths during this period (T ) corresponds to the data in PWDRU and PWDRL.
H
This relation can be represented as follows.
T = (data value in PWDRU and PWDRL + 64) × tφ/2
H
where tφ is the PWM input clock period, either 2/φ (bit PWCR0 = 0) or 4/φ (bit PWCR0 = 1).
If the data value in PWDRU and PWDRL is between H'3FC0 and H'3FFF, the PWM
output level will be high.
When the data value is H'0000, T = 64 × tφ/2 = 32 tφ.
H
Example: Settings in order to obtain a conversion period of 8,192 µs:
When bit PWCR0 = 0, the conversion period is 16384/φ, so φ must be 2 MHz. In
this case t = 128 µs, with 1/φ (resolution) = 0.5 µs.
fn
When bit PWCR0 = 1, the conversion period is 32768/φ, so φ must be 4 MHz. In
this case t = 128 µs, with 2/φ (resolution) = 0.5 µs.
fn
Accordingly, for a conversion period of 8,192 µs, the system clock frequency (φ)
must be 2 MHz or 4 MHz.
173
1 conversion period
tf1
tf2
tf63
tf64
t H1
t H2
t H3
t H63
t H64
TH = tH1 + tH2 + tH3 + . . . + tH64
tf1 = tf2 = tf3 . . . = tf64
Figure 9-2 PWM Output Waveform
174
Section 10 SCI1
10.1 Overview
Serial communication interface 1 (SCI1) performs synchronous serial transfer of 8-bit or 16-bit
data.
10.1.1 Features
SCI1 features are as follows.
•
•
Choice of 8-bit or 16-bit data transfer
Choice of eight internal clock sources (φ/1024, φ/256, φ/64, φ/32, φ/16, φ/8, φ/4, φ/2) or an
external clock
•
Interrupts requested at completion of transfer or when error occurs
10.1.2 Block Diagram
Figure 10-1 shows a block diagram of SCI1.
SMR1
Prescaler S
(13 bits)
φ
Octal/Hexadecimal
counter 1
IRRS1
SO1
(3 or 4 bits)
SPR1
SDRL1
SDRU1
SI1
SCK1
Notation:
SMR1: Serial mode register 1
SPR1: Serial port register 1
SDRL1: Serial data register L1
SDRU1:Serial data register U1
IRRS1: Serial communication interface 1 interrupt request flag (interrupt request register 3)
Figure 10-1 Block Diagram of SCI1
175
10.1.3 Pin Configuration
Table 10-1 shows the SCI1 pin configuration.
Table 10-1 Pin Configuration
Name
Abbrev.
SCK1
SI1
I/O
Function
SCI1 clock pin
SCI1 data input pin
SCI1 data output pin
I/O
SCI1 clock input or output
SCI1 received data input
SCI1 transmit data output
Input
Output
SO1
10.1.4 Register Configuration
Table 10-2 shows the SCI1 register configuration.
Table 10-2 SCI1 Registers
Name
Abbrev.
SMR1
SDRU1
SDRL1
SPR1
R/W
W
Initial Value
H'80
Address
H'FFB0
H'FFB1
H'FFB2
H'FFB3
H'FFEC
H'FFED
Serial mode register 1
Serial data register U1
Serial data register L1
Serial port register 1
Port mode register 2
Port mode register 3
R/W
R/W
R/W
R/W
R/W
Not fixed
Not fixed
Not fixed
H'00
PMR2
PMR3
H'97
176
10.2 Register Descriptions
10.2.1 Serial Mode Register 1 (SMR1)
Bit
7
—
1
6
5
4
3
2
1
0
SMR16 SMR15 SMR14 SMR13 SMR12 SMR11 SMR10
Initial value
Read/Write
0
0
0
0
0
0
0
—
W
W
W
W
W
W
W
SMR1 is an 8-bit write-only register, for selecting the operation mode and the prescaler divider
ratio. Another function is to initialize the internal state of the serial interface, which happens at
each write access to SMR1.
When SMR1 is written to, serial clock supply to serial data registers U1 and L1 (SDRU1, SDRL1)
and to the octal/hexadecimal counter is stopped, and the octal/hexadecimal counter is reset to
H'00. Accordingly, writing to the serial mode register while the serial interface is operating will
abort data transmission or reception, and the serial communication interface 1 interrupt request
flag (IRRS1) will be set.
Upon reset, SMR1 is initialized to H'80.
Bit 7: Reserved bit
Bit 7 is reserved; it always reads 1, and cannot be modified.
Bits 6 to 4: Operation mode select (SMR16 to SMR14)
Bits 6 to 4 select the SCI1 operation mode.
Bit 6
Bit 5
Bit 4
SMR16 SMR15 SMR14
Description
0
1
0
0
Continuous clock output mode
8-bit transfer mode
(initial value)
SMR15, SMR14 set to value other
than 00
0
0
Continuous clock output mode
16-bit transfer mode
SMR15, SMR14 set to value other
than 00
177
Bits 3 to 0: Clock select (SMR13 to SMR10)
Bits 3 to 0 select the clock supplied to SCI1.
Serial Clock Period (µs)
Bit 3
Bit 2
Bit 1
Bit 0
Clock
Source
Prescaler
Divider Ratio φ = 4 MHz
SMR13 SMR12 SMR11 SMR10 Pin SCK1
φ = 2 MHz
0
0
0
0
SCK1 output Prescaler S
φ/1024
256
512
(initial value)
1
0
1
0
1
0
1
0
SCK1 output Prescaler S
SCK1 output Prescaler S
SCK1 output Prescaler S
SCK1 output Prescaler S
SCK1 output Prescaler S
SCK1 output Prescaler S
SCK1 output Prescaler S
φ/256
φ/64
φ/32
φ/16
φ/8
64
16
8
128
32
16
8
1
0
1
0
1
0
4
2
4
φ/4
1
2
φ/2
—
—
1
1
Not used
—
—
—
·
·
·
·
·
·
·
·
·
1
1
1
1
0
1
SCK1 input External clock —
—
—
10.2.2 Serial Data Register U1 (SDRU1)
Bit
7
6
5
4
3
2
1
0
SDRU17 SDRU16 SDRU15 SDRU14 SDRU13 SDRU12 SDRU11 SDRU10
Initial value
Read/Write
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Not fixed
SDRU1 is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit
transfer (SDRL1 is used for the lower 8 bits).
Data written to SDRU1 is output to SDRL1 starting from the least significant bit (LSB), in
synchronization with the falling edge of the serial clock. This data is than replaced by LSB-first
data input at pin SI1, synchronized with the rising edge of the serial clock. In this way data is
shifted in the direction from the most significant bit (MSB) toward the LSB.
SDRU1 must be written or read only after data transmission or reception is complete.
If this register is read or written while a data transfer is in progress, the data contents are not
guaranteed.
The SDRU1 value upon reset is not fixed.
178
10.2.3 Serial Data Register L1 (SDRL1)
Bit
7
6
5
4
3
2
1
0
SDRL17 SDRL16 SDRL15 SDRL14 SDRL13 SDRL12 SDRL11 SDRL10
Initial value
Read/Write
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Not fixed
SDRL1 is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the
data register for the lower 8 bits in 16-bit transfer (SDRU1 is used for the upper 8 bits).
In 8-bit transfer, data written to SDRL1 is output from pin SO1 starting from the least significant
bit (LSB), in synchronization with the falling edge of the serial clock. This data is then replaced
by LSB-first data input at pin SI1, synchronized with the rising edge of the serial clock. In this
way data is shifted in the direction from the most significant bit (MSB) toward the LSB.
In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via
SDRU1.
SDRL1 must be written or read only after data transmission or reception is complete. If this
register is read or written while a data transfer is in progress, the data contents are not guaranteed.
The SDRL1 value upon reset is not fixed.
10.2.4 Serial Port Register 1 (SPR1)
Bit
7
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
SO1 LAST
BIT
Initial value
Read/Write
*
R/W
—
—
—
—
—
—
—
Note: * Not fixed
SPR1 is an 8-bit read/write register, bit 7 of which is connected to the last output stage of
SDRL1.
179
Bit 7: Extended data bit (SO1 LAST BIT)
Bit 7 holds the last bit of transmitted data after transmission ends.
Output from pin SO1 can be altered by software by modifying this bit either before or after
transmission.
If this bit is written during data transmission, the data contents are not guaranteed.
Bit 7
SO1 LAST BIT
Description
0
1
Output from pin SO1 is low.
Output from pin SO1 is high.
(initial value)
Bits 6 to 0: Reserved bits
Bits 6 to 0 are reserved: they always read 1, and cannot be modified.
10.2.5 Port Mode Register 2 (PMR2)
Bit
7
6
5
SI2
0
4
SCK2
0
3
2
SI1
0
1
SCK1
0
0
PWM
0
UP/
DOWN
SO2
0
SO1
0
Initial value
Read/Write
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR2 is an 8-bit read/write register, for switching the port 9 pin functions. Bits 3 to 1, in
combination with SMR1, set the SCI1 operation mode.
Upon reset, PMR2 is initialized to H'00.
Bits 3 to 1 are explained here. For bits 7 to 4 and bit 0, see 7.10.2 (1), Port Mode Register 2
(PMR2).
Bit 3: Pin P9 /SO function switch (SO1)
3
1
Bit 3 selects whether pin P9 /SO functions as a P9 input/output pin or as the SO output pin.
3
1
3
1
Bit 3
SO1
Description
Pin P93/SO1 functions as P93 I/O pin.
0
1
(initial value)
Pin P93/SO1 functions as SO1 output pin. Setting bit SCK1 to 1 and
clearing bit SI1 to 0 puts SCI1 in transmit mode.
180
Bit 2: Pin P9 /SI function switch (SI1)
2
1
Bit 2 selects whether pin P9 /SI functions as a P9 input/output pin or as the SI output pin.
2
1
2
1
Bit 2
SI1
Description
Pin P92/SI1 functions as P92 I/O pin.
0
1
(initial value)
Pin P92/SI1 functions as SI1 output pin. Setting bit SCK1 to 1 and
clearing bit SO1 to 0 puts SCI1 in receive mode.
Bit 1: Pin P9 /SCK function switch (SCK1)
1
1
Bit 1 selects whether pin P9 /SCK functions as a P9 input/output pin or as the SCK
1
1
1
1
input/output pin.
Bit 1
SCK1
Description
Pin P91/SCK1 functions as P91 I/O pin.
Pin P91/SCK1 functions as SCK1 I/O pin. The direction of clock
I/O and the prescaler divider ratio are set in serial mode register 1 (SMR1).
0
1
(initial value)
10.2.6 Port Mode Register 3 (PMR3)
Bit
7
—
1
6
5
CS
0
4
—
1
3
2
—
1
1
—
1
0
—
1
SO2
PMOS
SO1
PMOS
Initial value
Read/Write
0
0
—
R/W
R/W
—
R/W
—
—
—
PMR3 is an 8-bit read/write register, for enabling the PMOS transistors of SCI1 and SCI2 data
output pins (pins SO and SO ), and for controlling SCI2 chip select output (pin SI /CS).
1
2
2
Upon reset, PMR3 is initialized to H'97.
Bit 3 is explained here. For bits 6 and 5, see 11.2.5, Port Mode Register 3 (PMR3).
Bit 3: Pin SO PMOS on/off (SO1PMOS)
1
Bit 3 enables or disables the PMOS buffer transistor of pin P9 /SO .
3
1
Bit 3
S01PMOS
Description
The PMOS transistor of pin P93/SO1 is enabled: CMOS output.
The PMOS transistor of pin P93/SO1 is disabled: NMOS open-drain output.
0
1
(initial value)
181
10.3 Operation
10.3.1 Overview
SCI1 sends and receives data in synchronization with clock pulses.
SCI1 operation modes are set by bits 6 to 4 of serial mode register 1 (SMR1) and bits 3 to 1 of
port mode register 2 (PMR2) in combination, as shown in table 10-3.
Table 10-3 SCI1 Operation Mode Setting
SMR1
PMR2
SMR16 SMR15 SMR14 PMR23 PMR22 PMR21 Operation Mode
*
*
0
*
*
0
0
1
0
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
1
1
1
1
1
Serial communication disabled
Continuous clock output mode
8-bit transmit mode
0
0
SMR15, SMR14
set to value other
than 00
8-bit receive mode
8-bit transmit/receive mode
16-bit transmit mode
SMR15, SMR14
set to value other
than 00
1
16-bit receive mode
16-bit transmit/receive mode
Note: * Don’t care.
SCI1 consists of SMR1, serial data register U1 (SDRU1), serial data register L1 (SDRL1), serial
port register 1 (SPR1), an octal/hexadecimal counter, and a multiplexer. (See figure 10-1.)
Pin SCK and the serial clock are controlled by writing data to SMR1.
1
SDRU1 and SDRL1 are used to write transmit data and to hold received data; these registers can
be written and read by software. Data in these registers is shifted in synchronization with the
serial clock, for input and output at pins SI and SO .
1
1
SCI1 operation starts with a dummy read of SMR1. The octal/hexadecimal counter is cleared to
H'0 by this dummy read, and starts counting anew from the falling edge of the serial clock (pin
SCK ), being incremented by 1 at each rising edge of the serial clock. If 8 or 16 serial clock
1
cycles are input and the counter overflows, or if data transmission or reception is aborted, the
octal/hexadecimal counter is cleared to H'0. At the same time bit IRRS1 in interrupt request
register 3 (IRR3) is set to 1.
For more details on interrupts, see 3.2.2, Interrupts.
182
10.3.2 Data Transfer Format
Figure 10-2 shows the synchronous data transfer format. Data can be sent and received in lengths
of 8 bits or 16 bits. Data is sent and received starting from the least significant bit, in LSB-first
format. Transmit data is output from one falling edge of the serial clock until the next falling
edge. Receive data is latched at the rising edge of the serial clock.
SCK1
LSB
Bit 0
MSB
SO1
Bit 1
Bit 2 Bit 3
Bit n – 1 Bit n
SI1input data
latch timing
n = 7: 8-bit transfer mode
n = 15: 16-bit transfer mode
Figure 10-2 Synchronous Data Transfer Format
10.3.3 Clock
Eight internal clock sources or an external clock may be selected as the serial clock. When an
internal clock is used, pin SCK is the clock output pin.
1
10.3.4 Data Transmit/Receive
1. Initializing SCI1
Before data is sent or received, first SCI1 must be initialized by software. This is done by
writing the desired transfer conditions in serial mode register 1 (SMR1).
2. Transmitting
A transmit operation is carried out as follows.
•
Set bit SO1 in port mode register 2 (PMR2) to 1, making pin P9 /SO the SO output pin.
3 1 1
Also set bit SCK1 in PMR2 to 1, making pin P9 /SCK the SCK I/O pin. If necessary, set
1
1
1
the SO1PMOS bit in PMR3 for NMOS open-drain output at pin SO .
1
183
•
•
Set bit SMR16 in SMR1 to 1 or 0, and set bits SMR15 and SMR14 to a value other than 00,
designating 8- or 16-bit transfer mode. Select the serial clock with bits SMR13 to SMR10.
Writing data to SMR1 initializes the internal state of SCI1.
Write transmit data in serial data register L1 (SDRL1) and serial data register U1
(SDRU1), as follows.
8-bit transfer mode: SDRL1
16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1
•
•
Execute a dummy read of SMR1. SCI1 starts operating, and outputs the transmit data at pin
SO .
1
After data transmission is complete, bit IRRS1 in interrupt request register 3 (IRR3) is
set to 1.
When an internal clock source is used, a serial clock is output from pin SCK in synchronization
1
with the transmit data. After data transmission is complete, the serial clock is not output until the
next dummy read of SMR1. During this time, pin SO continues to output the value of the last bit
1
transmitted.
When an external clock source is used, data is transmitted in synchronization with the serial clock
input at pin SCK . After data transmission is complete, if the serial clock continues to be input,
1
transmission resumes.
Between transmissions, the output value of pin SO can be changed by rewriting bit 7 (SO1 LAST
1
BIT) in serial port register 1 (SPR1).
Executing a dummy read of SMR1 during transmission will cause a transmit error, setting bit
IRRS1 in IRR3 to 1.
3. Receiving
A receive operation is carried out as follows.
•
•
Set bit SI1 in port mode register 2 (PMR2) to 1, making pin P9 /SI the SI input pin. Also
2 1 1
set bit SCK1 in PMR2 to 1, making pin P9 /SCK the SCK I/O pin.
1
1
1
Set bit SMR16 in serial mode register 1 (SMR1) to 1 or 0, and set bits SMR15 and SMR14 to
a value other than 00, designating 8- or 16-bit transfer mode. Select the serial clock with bits
SMR13 to SMR10. Writing data to SMR1 initializes the internal state of SCI1.
•
Execute a dummy read of SMR1. SCI1 starts operating, and receive data is input at pin SI .
1
184
•
•
After data reception is complete, bit IRRS1 in interrupt request register 3 (IRR3) is set to 1.
Read the received data from SDRL1 and SDRU1, as follows.
8-bit transfer mode: SDRL1
16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1
When an internal clock source is used, a dummy read of SMR1 immediately starts a data receive
operation. The serial clock is output from pin SCK .
1
When an external clock source is used, after the dummy read of SMR1, data is received in
synchronization with the serial clock input at pin SCK . After data reception is complete, if the
1
serial clock continues to be input, reception resumes.
Executing a dummy read of SMR1 during reception will cause a receive error, setting bit IRRS1 in
IRR3 to 1.
4. Simultaneous transmit/receive
A simultaneous transmit/receive operation is carried out as follows.
•
•
•
•
Set bits SO1, SI1, and SCK1 in PMR2 to 1, designating the SO output pin, SI pin, and
1 1
SCK pin functions. If necessary, set the SO1PMOS bit in PMR3 for NMOS open-drain
1
output at pin SO .
1
Set bit SMR16 in SMR1 to 1 or 0, and set bits SMR15 and SMR14 to a value other than 00,
designating 8- or 16-bit transfer mode. Select the serial clock with bits SMR13 to SMR10.
Writing data to SMR1 initializes the internal state of SCI1.
Write transmit data in SDRL1 and SDRU1, as follows.
8-bit transfer mode: SDRL1
16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1
Execute a dummy read of SMR1. SCI1 starts operating: transmit data is output at pin SO ,
1
and receive data is input at pin SI .
1
•
•
After data transmission and reception are complete, bit IRRS1 in IRR3 is set to 1.
Read the received data from SDRL1 and SDRU1.
8-bit transfer mode: SDRL1
16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1
185
In simultaneous data transmit/receive, the transmit operation and receive operation described in
10.3.4 sections 2 and 3 take place at the same time. See those sections for further details.
During a transmit/receive operation, a dummy read of SMR1 will result in a transmit/receive error,
setting bit IRRS1 in IRR3 to 1.
10.3.5 SCI1 State Transitions
SCI1 has three internal states, as shown in figure 10-3.
In the serial start pending state, the internal state of the serial communication interface is
initialized. In this state, the serial communication interface does not operate even if a serial clock
signal is input. Executing a dummy read of SMR1 changes this state to the serial clock pending
state.
In the serial clock pending state, when a serial clock signal is input the octal/hexadecimal counter
starts counting up and the serial data register starts shifting, entering the transfer state. If
continuous clock output mode has been selected, however, SCI1 outputs the clock signal
continuously and does not enter the transfer state.
In the transfer state, when 8 or 16 transfer clock cycles are input, or if an SMR1 dummy read is
executed, the octal/hexadecimal counter is reset to H'0, and SCI1 enters the serial clock pending
state. Writing to SMR1 in the transfer state will reset the octal/hexadecimal counter to H'0 and
change to the serial start pending state. In transitions from the transfer state to another state, the
resetting of the octal/hexadecimal counter to H'0 sets bit IRRS1 in IRR3 to 1.
If an internal clock source is selected, a dummy read of SMR1 starts output of the serial clock,
which stops after 8 or 16 clock output cycles.
After writing to SMR1 in the serial clock pending state or transfer state, it is necessary to write to
SMR1 again in order to initialize the initial state of the serial communication interface. Writing to
SMR1 changes the state to the serial start pending state.
186
Serial start (SMR1 dummy read) pending state
octal counter = 000 or
hexadecimal counter = 0000
serial clock disabled.
SMR1 write
SMR1 dummy
read
(serial start)
SMR1 write
(IRRS1 1)
←
8 or 16 serial
clock cycles
(internal clock)
←
(IRRS1 1)
Serial clock
Serial clock pending state
Transfer state
=
octal counter / 000 or
=
hexadecimal counter / 0000
octal counter = 000 or
hexadecimal counter = 0000
SMR1 dummy read (serial start)
←
(IRRS1 1)
8 or 16 serial clock cycles
(external clock)
Figure 10-3 SCI1 State Transitions
10.3.6 Serial Clock Error Detection
In the transfer state, if an extraneous pulse is superimposed on the normal serial clock signal due
to external noise, SCI1 may function incorrectly. Serial clock errors can be detected by means of
the procedure shown in figure 10-4.
In the transfer clock pending state, if more than the normal 8 or 16 serial clock cycles are
mistakenly input, SCI1 changes from the transfer state to the transfer clock pending state and then
back to the transfer state. After bit IRRS1 in interrupt request register 3 (IRR3) is cleared to 0,
writing a value in serial mode register 1 (SMR1) changes the state to serial start pending, and bit
IRRS1 is again set to 1.
187
Transfer complete
←
(IRRS1 1)
Disable interrupts
←
IRRS1
0
SMR1 write
Yes
Serial clock
error processing
IRRS1 = 1?
No
Normal completion
Figure 10-4 Procedure for Detecting Serial Clock Errors
10.3.7 Interrupts
SCI1 can generate interrupts for completion of transfer and for transmit/receive errors. These
interrupts are assigned to the same vector address.
When an SCI1 transfer is complete, or when a transmit/receive error occurs before the transfer is
complete, bit IRRS1 in interrupt request register 3 (IRR3) is set to 1. SCI1 interrupt requests can
be enabled or disabled in bit IENS1 of interrupt enable register 3 (IENR3).
For further details, see 3.2.2, Interrupts.
188
Section 11 SCI2
11.1 Overview
Serial communication interface 2 (SCI2) has a 32-byte data buffer, for synchronous serial transfer
of up to 32 bytes of data in one operation.
11.1.1 Features
SCI2 features are as follows.
•
•
•
Automatic transfer of up to 32 bytes of data
Choice of internal clock sources (φ/8, φ/4, φ/2) or an external clock
Interrupts requested at completion of transfer or when error occurs
11.1.2 Block Diagram
Figure 11-1 shows a block diagram of SCI2.
SCK2
Shift clock
generator circuit
Prescaler S
(13 bits)
φ
Bit counter
SCR2
STAR
Byte counter
Comparator circuit
EDAR
Address decoder and
R/W controller
IRRS2
Data buffer
(32 bytes)
Shift register
SO2
SI2/CS
Internal data bus
Notation:
STAR: Start address register
EDAR: End address register
IRRS2: Serial communication interface 2 interrupt request flag (interrupt request register 3)
Figure 11-1 Block Diagram of SCI2
189
11.1.3 Pin Configuration
Table 11-1 shows the SCI2 pin configuration.
Table 11-1 Pin Configuration
Name
Abbrev.
SCK2
SI2
I/O
Function
SCI2 clock pin
I/O
SCI2 clock input/output
SCI2 receive data input
SCI2 transmit data output
SCI2 chip select output
SCI2 data input pin
SCI2 data output pin
SCI2 chip select output pin
Input
Output
Output
SO2
CS
Note: Functions of pins P94/SCK2, P95/SI2/CS, and P96/SO2 are switched in port mode register 2
(PMR2) and port mode register 3 (PMR3). For PMR2, see 7.10.2 1, Port mode register 2
(PMR2).
11.1.4 Register Configuration
Table 11-2 shows the SCI2 register configuration.
Table 11-2 SCI2 Registers
Name
Abbrev.
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
Not fixed
H'E0
Address
H'FF80 to H'FF9F
H'FFA0
32-byte data buffer
Start address register
End address register
Serial control register 2
Status register
STAR
EDAR
SCR2
STSR
PMR2
PMR3
H'E0
H'FFA1
H'E0
H'FFA2
H'E0/H'E8
H'00
H'FFA3
Port mode register 2
Port mode register 3
H'FFEC
H'97
H'FFED
190
11.2 Register Descriptions
11.2.1 Start Address Register (STAR)
Bit
7
—
1
6
—
1
5
—
1
4
STA4
0
3
STA3
0
2
STA2
0
1
STA1
0
0
STA0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
STAR is an 8-bit read/write register, for designating the transfer start address in the memory area
from H'FF80 to H'FF9F allocated to the 32-byte data buffer.
The 32 bytes from H'00 to H'1F designated by the lower 5 bits of STAR (bits STA4 to STA0)
correspond to addresses H'FF80 to H'FF9F.
Data is sent or received continuously using the area defined in STAR and in the end address
register (EDAR).
Bits 7 to 5 are reserved; they always read 1, and cannot be modified.
Upon reset, STAR is initialized to H'E0.
11.2.2 End Address Register (EDAR)
Bit
7
—
1
6
—
1
5
—
1
4
EDA4
0
3
EDA3
0
2
EDA2
0
1
EDA1
0
0
EDA0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
EDAR is an 8-bit read/write register, for designating the transfer end address in the memory area
from H'FF80 to H'FF9F allocated to the 32-byte data buffer.
The 32 bytes from H'00 to H'1F designated by the lower 5 bits of EDAR (bits EDA4 to EDA0)
correspond to addresses H'FF80 to H'FF9F.
Data is sent or received continuously using the area defined in STAR and EDAR. If the same
value is designated in both STAR and EDAR, only one byte of data is transferred.
Bits 7 to 5 are reserved; they always read 1, and cannot be modified.
Upon reset, EDAR is initialized to H'E0.
191
11.2.3 Serial Control Register 2 (SCR2)
Bit
7
—
1
6
—
1
5
—
1
4
I/O
0
3
GAP2
0
2
GAP1
0
1
0
PS1
0
PS0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
SCR2 is an 8-bit read/write register, for selecting whether SCI2 transmits or receives, for gap
insertion during continuous transfer, and for serial clock selection.
Upon reset, SCR2 is initialized to H'E0.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved; they always read 1, and cannot be modified.
Bit 4: Transmit/receive select (I/O)
Bit 4 selects SCI2 transmit or receive mode.
Bit 4
I/O
Description
0
SCI2 is in receive mode.
SCI2 is in transmit mode.
(initial value)
1
Bits 3 and 2: Gap select (GAP2 to GAP1)
When data is transmitted or received continuously, gaps can be inserted at data divisions by
holding the serial clock high for a length of time designated by bits 3 and 2. Bits 3 and 2 are valid
when an internal clock source is selected as the serial clock (PS1 and 0 ≠ 11).
Data divisions may be placed every 8 bits or 16 bits; this is selected in bit GIT in the status
register (STSR).
Bit 3
Bit 2
GAP2 GAP1 Description
0
0
1
1
0
1
0
1
Serial clock keeps the same duty cycle even at data divisions.
(initial value)
Serial clock high level extended by one clock cycle at data divisions.
Serial clock high level extended by two clock cycles at data divisions.
Serial clock high level extended by eight clock cycles at data divisions.
192
Bits 1 and 0: Serial clock select (PS1 to PS0)
Bits 1 and 0 select one of three internal clock sources or an external clock.
Serial Clock Period
Bit 1 Bit 2
PS1 PS0
Prescaler
Divider Ratio
Pin SCK2
Clock Source
φ = 4 MHz φ = 2 MHz φ = 1 MHz
0
0
1
1
0
1
0
1
SCK2 output Prescaler S
SCK2 output Prescaler S
SCK2 output Prescaler S
φ/2 (initial value) *
1 µs
2 µs
4 µs
—
2 µs
4 µs
8 µs
—
φ/4
φ/8
—
1 µs
2 µs
—
SCK2 input
External clock
Note: * Can be set, but operation is not guaranteed.
11.2.4 Status Register (STSR)
Bit
7
—
1
6
—
1
5
—
1
4
3
OVR
*1
2
WT
0
1
0
SO2 LAST
GIT
0
STF
BIT
Initial value
Read/Write
0
0
—
—
—
R/W
R/W*2
R/W*2
R/W
R/W
Notes: 1. Not fixed
2. Cleared to 0 by write operation to STSR.
STSR is an 8-bit register indicating the SCI2 operation state, error status, etc. Writing to this
register during data transmission may cause misoperation.
Upon reset, STSR is initialized to H'E0 or H'E8.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved; they always read 1, and cannot be modified.
Bit 4: Extended data bit (SO2 LAST BIT)
Bit 4 holds the last bit of transmitted data after transmission ends.
Output from pin SO can be altered by software by modifying this bit either before or after
2
transmission.
Writing to this bit during data transmission may cause misoperation.
193
Bit 4
SO2 LAST BIT
Description
0
1
Output from pin SO2 is low.
Output from pin SO2 is high.
(initial value)
Bit 3: Overrun flag (OVR)
If the amount of data transferred exceeds the buffer size setting, or if an extraneous pulse is
superimposed on the normal serial clock due to external noise, SCI2 overruns and bit 3 is set to 1.
Bit 3
OVR
Description
0
[Clear conditions]
When STSR is written to.
(initial value)
1
[Set conditions]
When overrun occurs.
Bit 2: Waiting flag (WT)
If an attempt is made to execute a read or write instruction to the 32-byte buffer during a serial
data transfer, the instruction is ignored, and bit 2 is set to 1 along with bit IRRS2 in interrupt
request register 3 (IRR3).
Bit 2
WT
Description
0
[Clear conditions]
When STSR is written to.
(initial value)
1
[Set conditions]
When a read/write to the 32-byte buffer is attempted during serial transfer.
Bit 1: Gap interval flag (GIT)
Bit 1 designates whether the extended serial clock high-level interval designated in bits GAP2 and
GAP1 in serial control register 2 (SCR2) occurs every 8 bits or every 16 bits. This setting is valid
only for internal clock operation.
Bit 1
GIT
Description
0
Gap specified by GAP2 and GAP1 is inserted every 16 bits.
Gap specified by GAP2 and GAP1 is inserted every 8 bits.
(initial value)
1
194
Bit 0: Start/busy flag (STF)
Setting bit 0 to 1 starts an SCI2 transfer operation. This bit stays at 1 during the transfer, and is
cleared to 0 after the transfer is complete. It can therefore be used as a busy flag as well.
Clearing this bit to 0 during a transfer aborts the transfer, initializing SCI2. The contents of
the 32-byte data buffer and of registers other than STSR are unchanged when this happens.
Bit 0
STF
Explanation
0
[Read access]
(initial value)
Indicates transfer not in progress.
[Write access]
Stops transfer.
1
[Read access]
Indicates transfer in progress.
[Write access]
Starts transfer.
11.2.5 Port Mode Register 3 (PMR3)
Bit
7
—
1
6
5
CS
0
4
—
1
3
2
—
1
1
—
1
0
—
1
SO2
PMOS
SO1
PMOS
Initial value
Read/Write
0
0
—
R/W
R/W
—
R/W
—
—
—
PMR3 is an 8-bit read/write register, for enabling the PMOS transistors of SCI1 and SCI2 data
output pins (pin P9 /SO and pin P9 /SO ), and for controlling SCI2 chip select output (pin
3
1
6
2
SI /CS).
2
Upon reset, PMR3 is initialized to H'97.
For bit 3, see 10.2.6, Port Mode Register 3 (PMR3).
Bit 7: Reserved bit
Bit 7 is reserved; it always reads 1, and cannot be modified.
195
Bit 6: Pin SO PMOS on/off (SO2PMOS)
2
Bit 6 enables or disables the PMOS buffer transistor of pin P9 /SO .
6
2
Bit 6
SO2PMOS
Description
0
1
PMOS transistor of pin P96/SO2 is enabled: CMOS output.
(initial value)
PMOS transistor of pin P96/SO2 is disabled: NMOS open-drain output.
Bit 5: Chip select output select (CS)
In combination with bit SI2 in port mode register 2 (PMR2), bit 5 selects the CS output function
of pin P9 /SI /CS. The CS output pin function is valid when an internal clock source is selected
5
2
as the serial clock, and only in transmit mode.
PMR2
PMR3
Bit 5
SI2
Bit 5
CS
Description
0
0
1
0
1
Pin P95/SI2/CS functions as P95 I/O pin.
Pin P95/SI2/CS functions as P95 I/O pin.
Pin P95/SI2/CS functions as SI2 input pin.
Pin P95/SI2/CS functions as CS output pin.
(initial value)
1
Bits 4 and 2 to 0: Reserved bits
These bits are reserved; they always read 1, and cannot be modified.
196
11.3 Operation
11.3.1 Overview
SCI2 has a 32-byte data buffer, making possible continuous transfer of up to 32 bytes of data with
one operation. SCI2 transmits and receives data in synchronization with clock pulses.
Selection of transmit or receive mode and of the serial clock is made in serial control register 2
(SCR2).
The start address register (STAR) and end address register (EDAR) designate the area within the
32-byte data buffer for holding transfer data. The address range from H'FF80 to H'FF9F is
allocated to this data buffer. The start and end positions of the transfer data area are indicated in
the lower 5 bits of STAR and EDAR.
After parameters have been set in port mode register 2 (PMR2), port mode register 3 (PMR3),
SCR2, STAR, and EDAR, then when the STF bit of the status register (STSR) is set to 1, SCI2
begins a transfer operation. STF remains set to 1 during the transfer, and is cleared to 0 when the
transfer is complete. The STF bit can therefore be used as a busy flag. Clearing the STF bit to 0
during a transfer stops the transfer operation and initializes SCI2. The contents of the data buffer
and of other registers are unchanged in this case.
During a transfer, the CPU cannot read or write the data buffer. If a write instruction is issued it is
ignored; it has the same effect as a NOP instruction except that it takes more states. Read access
during a transfer yields H'FF.
When the transfer is complete, or if a data buffer read or write is attempted during the transfer, bit
IRRS2 in interrupt request register 3 (IRR3) is set to 1. In case of an overrun error or a data buffer
read or write during the transfer, bit OVR or WT of STSR is set to 1.
Note: If the start address is set to a value higher than the end address, the result is as shown in
figure 11-2. The data transfer wraps around from address H'FF9F to address H'FF80 and
continues to the end address.
197
H'FF80
H'00
End
End address
Start
Start address
H'1F
H'FF9F
Figure 11-2 Operation When Start Address Exceeds End Address
11.3.2 Clock
Three internal clock sources or an external clock may be selected as the serial clock. When an
internal clock is selected, pin SCK becomes the clock output pin.
2
11.3.3 Data Transfer Format
Figure 11-3 shows the SCI2 data transfer format. Data is sent and received starting from the least
significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial
clock until the next falling edge. Receive data is latched at the rising edge of the clock.
When SCI2 operates on an internal clock and is in transmit mode, a gap may be inserted at data
divisions (every 8 bits or 16 bits). During this gap, the serial clock stays at the high level for a
designated number of clock cycles (see figures 11-4 through 11-6).
The CS output remains low during the gap.
Gap insertion and the length of the gap are designated in bits GAP2 and GAP1 in serial control
register 2 (SCR2). Bit GIT in the status register (STSR) designates whether gaps occur at 8-bit or
16-bit intervals.
198
CS
SCK2
SO2
Bit 0
Bit 1
Bit 2 Bit 3
Bit 4
Bit 5
Bit 6 Bit 7
Held
Don’t care
Figure 11-3 Synchronous Data Transfer Format
Does not go to low level
SCK2
output
Bit 14
(Bit 6)
Bit 15
(Bit 7)*
Bit 16
(Bit 8)
Bit 17
(Bit 9)
SO2
SI2 input data
latch timing
Note: * When bit GIT = 1, a gap is inserted at 8-bit intervals.
Figure 11-4 1-Clock Gap Insertion (Bits GAP2 and GAP1 = 01)
Does not go to
low level
SCK2
output
Bit 14
(Bit 6)
Bit 15
(Bit 7)*
Bit 16
(Bit 8)
SO2
SI2 input data
latch timing
Note: * When bit GIT = 1, a gap is inserted at 8-bit intervals.
Figure 11-5 2-Clock Gap Insertion (Bits GAP2 and GAP1 = 10)
199
Serial clock × 8
SCK2
output
Bit 14
(Bit 6)
Bit 15
(Bit 7)*
Bit 16
(Bit 8)
SO2
SI2 input data
latch timing
Note: * When bit GIT = 1, a gap is inserted at 8-bit intervals.
Figure 11-6 8-Clock Gap Insertion (Bits GAP2 and GAP1 = 11)
11.3.4 Data Transmit/Receive
1. SCI2 initialization
Serial communication on SCI2 first of all requires that SCI2 be initialized by software. This
involves clearing bit STF in the status register (STSR) to 0, then selecting pin functions and
transfer modes in port mode register 2 (PMR2), port mode register 3 (PMR3), the start
address register (STAR), the end address register (EDAR), and serial control register 2
(SCR2).
2. Transmitting
A transmit operation is carried out as follows.
•
Set bit SO2 in port mode register 2 (PMR2) to 1, making pin P9 /SO the SO output pin. If
6 2 2
necessary, set the SO2PMOS bit and CS bit in PMR3 for NMOS open-drain output at pin
SO and for chip select output at pin P9 /SI /CS.
2
5
2
•
•
•
•
Write transmit data in the 32-byte data buffer (H'FF80 to H'FF9F).
Set the transfer start address in the lower 5 bits of STAR.
Set the transfer end address in the lower 5 bits of EDAR.
In SCR2, select transmit mode (bit I/O = 1), the serial clock, and gap insertion (internal clock
operation only).
•
Select the data gap interval with bit GIT of STRS, then set bit STF to 1. Setting bit STF starts
the transmit operation.
200
•
After data transmission is complete, bit IRRS2 in interrupt request register 3 (IRR3) is set to
1, and bit STF in STSR is cleared to 0.
If an internal clock source is used, a serial clock is output from pin SCK in synchronization with
2
the transmit data. After data transmission is completed, the serial clock is not output until bit STF
is again set. During this time, pin SO2 continues to output the value of the last bit transmitted.
When an external clock source is used, data is transmitted in synchronization with the serial clock
input at pin SCK . After data transmission is completed, further transmission does not take place
2
even if the serial clock continues to be input; pin SO continues to output the value of the last bit
2
transmitted.
Between transmissions, the output value of pin SO can be changed by rewriting bit SO2 LAST
2
BIT in STSR.
An attempt to read or write the data buffer during transmission will cause bit IRRS2 in IRR3 to be
set to 1. Bit WT in STSR will also be set to 1.
3. Receiving
A receive operation is carried out as follows.
•
•
Set bit SI2 in port mode register 2 (PMR2) to 1, making pin P9 /SI /CS the SI input pin.
5 1 2
Allocate an area to hold the received data in the 32-byte data buffer and set the start address in
the lower 5 bits of the start address register (STAR).
•
•
•
•
Set the transfer end address in the lower 5 bits of the end address register (EDAR).
In serial control register 2 (SCR2), select receive mode (bit I/O = 0) and the serial clock.
Set bit STF of the status register (STSR) to 1, starting the receive operation.
After receiving is completed, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1, and
bit STF is cleared to 0.
•
Read the received data from the data buffer.
If an internal clock source is used, setting bit STF to 1 in STSR immediately starts a data receive
operation. The serial clock is output from pin SCK .
2
201
When an external clock source is used, after bit STF is set, data is received in synchronization
with the clock input at pin SCK . After receiving is completed, no further receive operations take
2
place until bit STF is again set, even if the serial clock continues to be input.
An attempt to read or write the data buffer during receiving will cause bit IRRS2 in IRR3 and bit
WT in STSR to be set to 1. Bit OVR in STSR is set to 1 if an overrun error occurs.
When SCI2 operates on an internal clock and is in transmit mode, a gap may be inserted at data
divisions (every 8 bits or 16 bits). During this gap, serial clock stays at the high level for a
designated number of clock cycles (see figures 11-4 through 11-6).
Gap insertion and the length of the gap are designated in bits GAP2 and GAP1 of SCR2. Bit GIT
of STSR designates whether gaps occur at 8-bit or 16-bit intervals.
11.4 Interrupts
SCI2 can generate interrupts when a transfer is completed and when the data buffer is read or
written during a transfer. These interrupts are assigned to the same vector address.
When the above conditions occur, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1.
SCI2 interrupt requests can be enabled or disabled in bit IENS2 of interrupt enable register 3
(IENR3). For further details, see 3.2.2, Interrupts.
When an overrun error occurs, or when a read or write of the data buffer is attempted during a
transfer, the OVR or WT bit in the status register (STSR) is set to 1. These bits can be used to
determine the cause of the error.
11.5 Application Notes
1. Do not write to any register during a transfer (while bit STF of STSR is set to 1), since this
can cause misoperation.
2. When receiving, set bit SI2 in port mode register 2 (PMR2) to 1 and clear bit CS in port mode
register 3 (PMR3) to 0 to select the SI pin function. If bit CS = 1 and bit SI2 = 1, selecting
2
the CS pin function, incorrect data will be received.
202
Section 12 VFD Controller/Driver
12.1 Overview
The H8/3714 Series is equipped with an on-chip vacuum fluorescent display (VFD) controller/
driver and high-voltage, high-current pins, for direct VFD driving.
12.1.1 Features
The VFD controller/driver has the following features.
•
Maximum of 24 segment pins and 16 digit pins (20 segment pins, eight digit pins, and eight
switched segment/digit pins).
•
•
•
•
•
Brightness can be adjusted in eight steps (dimmer function).
Automatic shifting of displayed digit.
Digit pins and segment pins can be switched over to use as general-purpose high-voltage pins.
Optional key scan interval.
Interrupt generated when key scan interval starts.
12.1.2 Block Diagram
Figure 12-1 shows a block diagram of the VFD controller/driver.
Internal data bus
VFDR
DBR
VFSR
Display timing
generator circuit
IRRKS
VFD display RAM
Segment pins
Digit pins
Notation:
VFDR: VFD digit control register
DBR: Digit beginning register
VFSR: VFD segment control register
IRRKS: Key scan interrupt request flag (bit 6 of interrupt request register 3)
Figure 12-1 Block Diagram of VFD Controller/Driver
203
12.1.3 Pin Configuration
Table 12-1 shows the VFD controller/driver pin configuration.
Table 12-1 Pin Configuration
Name
Abbrev.
I/O
Function
Digit/segment pins
FD0/FS7 to FD7/FS0
Output
Digit or segment pins for vacuum
fluorescent display (function selected
in DBR for each bit)
Digit pins
FD8 to FD15
FS8 to FS23
Output
Output
Digit pins for vacuum fluorescent
display
Segment pins
Segment pins for vacuum fluorescent
display
12.1.4 Register Configuration
Table 12-2 shows the VFD controller/driver register configuration.
Table 12-2 Register Configuration
Name
Abbrev.
—
R/W
R/W
R/W
R/W
R/W
Initial Value
Not fixed
H'20
Address
VFD display RAM
H'FEC0 to H'FEFF
H'FFB9
VFD segment control register
VFD digit control register
Digit beginning register
VFSR
VFDR
DBR
H'00
H'FFBA
H'20
H'FFBB
204
12.2 Register Descriptions
12.2.1 VFD Digit Control Register (VFDR)
Bit
7
FLMO
0
6
5
4
3
2
1
0
DM2
0
DM1
0
DM0
0
DR3
0
DR2
0
DR1
0
DR0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VFDR is an 8-bit read/write register for control of digit output.
Upon reset, VFDR is initialized to H'00.
Bit 7: VFD mode bit (FLMO)
Bit 7 designates the time per digit (T ) and the dimmer resolution (T
). T is also the
digit
digit
dimmer
time per key scan.
Digit/Key Scan Time (Tdigit
)
Dimmer Resolution (Tdimmer)
Bit 7
FLMO
Period
φ = 4 MHz
φ = 2 MHz
Period
φ = 4 MHz
φ = 2 MHz
0
1536/φ
384 µs
768 µs
96/φ
24 µs
48 µs
(initial value)
(initial value)
1
768/φ
192 µs
384 µs
48/φ
12 µs
24 µs
The frame period (T
) is calculated using the equation below.
frame
T
= T
× (D + K)
digit
frame
D: Number of digit pins used
K: 1 if key scan is used; 0 if not used
205
Bits 6 to 4: Digit waveform select (DM2 to DM0)
Bits 6 to 4 select the digit waveform.
Bit 6
DM2
Bit 5
DM1
Bit 4
DM0
Digit Signal Waveform
0
0
1
0
1
0
1
0
1
0
1
0
1
(initial value)
1
*1
*1
*2
Tdigit
*2
Tdimmer
Notes: 1. Segment signal transition timing
2. For Tdimmer and Tdigit, see under FLMO bit.
206
Bits 3 to 0: Digit pin select (DR3 to DR0)
Bits 3 to 0, in combination with bits 3 to 0 of the digit beginning register (DBR), designate the
digit pins used.
Bit 3
DR3
Bit 2
DR2
Bit 1
DR1
Bit 0
DR0
Pins Valid as Digit Pins
FD0 to FD15
FD0 to FD14
FD0 to FD13
FD0 to FD12
FD0 to FD11
FD0 to FD10
FD0 to FD9
FD0 to FD8
FD0 to FD7
FD0 to FD6
FD0 to FD5
FD0 to FD4
FD0 to FD3
FD0 to FD2
FD0 to FD1
FD0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(initial value)
Note: For the switching between digit and segment use of pins FD0/FS7 to FD7/FS0, which can
function as either digit or segment pins, see 12.2.3, Digit Beginning Register (DBR).
FDm
FDm+1
FDm+2
to
FDn–2
FDn–1
FDn
Segment
data
Figure 12-2 Order of Digit Output
207
12.2.2 VFD Segment Control Register (VFSR)
Bit
7
VFLAG
0
6
5
—
1
4
3
2
1
0
KSE
0
SR4
0
SR3
0
SR2
0
SR1
0
SR0
0
Initial value
Read/Write
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
VFSR is an 8-bit read/write register for control of segment output.
Upon reset, VFSR is initialized to H'20.
Bit 7: VFD/port switching flag (VFLAG)
Bit 7 designates whether pins Pnn/FDnn and Pnn/FSnn are used as VFD pins (FDnn, FSnn) or as
general-purpose ports (Pnn).
Bit 7
VFLAG
Description
0
All of pins Pnn/FDnn and all of pins Pnn/FSnn function as
general-purpose ports.
(initial value)
1
Pnn/FDnn and Pnn/FSnn function as VFD pins according to the designations in bits
DR3 to DR0 in the VFD digit control register (VFDR), bits SR4 to SR0 in VFSR, and
bits DBR3 to DBR0 in the digit beginning register (DBR).
Note: Even when this flag is set to 1, during a key scan interval the segment pins function as
general-purpose ports; for this reason, when this flag is read during a key scan interval it
reads 0.
Bit 6: Key scan enable (KSE)
Bit 6 enables or disables the addition of a key scan interval (T ) to the VFD operation frame
digit
specified by the combination of bits DR3 to DR0 in the VFD digit control register, bits SR4 to
SR0 in the VFD segment control register, and bits DBR3 to DBR0 in the digit beginning register.
Bit 6
KSE
Description
0
1
No key scan interval.
(initial value)
A key scan interval can be added. See also under bit 7 (VFLAG) above.
Bit 5: Reserved bit
Bit 5 is reserved; it always reads 1, and cannot be modified.
208
Bits 4 to 0: Segment pin select (SR4 to SR0)
Bits 4 to 0, in combination with bits 3 to 0 of the digit beginning register (DBR), designate the
segment pins used.
Bit4
SR4
Bit 3
SR3
Bit 2
SR2
Bit 1
SR1
Bit 0
SR0
Pins Valid as Segment Pins
FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(initial value)
FS0 to FS1
FS0 to FS2
FS0 to FS3
FS0 to FS4
FS0 to FS5
FS0 to FS6
FS0 to FS7
FS0 to FS8
FS0 to FS9
FS0 to FS10
FS0 to FS11
FS0 to FS12
FS0 to FS13
FS0 to FS14
FS0 to FS15
FS0 to FS16
FS0 to FS17
FS0 to FS18
FS0 to FS19
FS0 to FS20
FS0 to FS21
FS0 to FS22
FS0 to FS23
Note: For the switching between digit and segment use of pins FD0/FS7 to FD7/FS0, which can
function as either digit or segment pins, see 12.2.3, Digit Beginning Register (DBR).
209
12.2.3 Digit Beginning Register (DBR)
Bit
7
VFDE
0
6
DISP
0
5
—
1
4
—
3
DBR3
0
2
DBR2
0
1
DBR1
0
0
DBR0
0
Initial value
Read/Write
0
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
DBR is an 8-bit read/write register for on/off control of the VFD controller/driver and for
switching functions of pins that can be either digit or segment pins.
Bit 7: VFD enable (VFDE)
Bit 7 switches the VFD controller/driver on and off.
Bit 7
VFDE
Description
0
1
VFD controller/driver is in reset state.
VFD controller/driver is operative.
(initial value)
Note: This setting is unrelated to whether pins Pnn/FDnn and Pnn/FSnn are used as VFD pins or
as general-purpose ports.
Bit 6: Display bit (DISP)
Bit 6 switches the display on and off.
Bit 6
DISP
Description
0
All segment pins (FS) are in the non-illuminating state (pulled down).
(initial value)
Register and RAM values are unchanged. Digit pins (FD) continue operating.
1
Display RAM data is output to segment pins (FS).
Bit 5: Reserved bit
Bit 5 is reserved; it always reads 1, and cannot be modified.
Bit 4: Reserved bit
Bit 4 is reserved, but it can be written and read.
210
Bits 3 to 0: Digit/segment pin function switch (DBR3 to DBR0)
Bits 3 to 0 designate the first digit pin and the first segment pin of those pins that can function
both ways. Bits DR3 to DR0 of the VFD digit control register (VFDR) and bits SR4 to SR0 of
VFSR must be set so that the first digit and segment pins are operational. Otherwise these pins
will not function.
Bit 3
Bit 2
Bit 1
Bit 0
DBR3 DBR2 DBR1 DBR0 Functions of FD0/FS7 to FD7/FS0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
*
0
0
1
1
0
0
1
1
*
0
1
0
1
0
1
0
1
*
FD0 to FD7
(initial value)
FD1 to FD7, FS7
FD2 to FD7, FS7 to FS6
FD3 to FD7, FS7 to FS5
FD4 to FD7, FS7 to FS4
FD5 to FD7, FS7 to FS3
FD6 to FD7, FS7 to FS2
FD7, FS7 to FS1
FS7 to FS0
Notes: Digit pins (FD) and segment pins (FS) are controlled by both VFDR and VFSR. During a
key scan interval, digit pins (FD) and segment pins (FS) function as general-purpose ports.
* Don’t care.
211
12.3 Operation
12.3.1 Overview
The VFD controller/driver may use up to 24 segment pins (FS) and up to 16 digit pins (FD). Of
these, 8 pins may be used as either segment or digit pins; their function is switched in the digit
beginning register (DBR). The 32 pins assigned to the VFD controller are high-voltage, high-
current pins capable of directly driving a VFD.
12.3.2 Control Section
The control section consists of the VFD digit control register (VFDR), VFD segment control
register (VFSR), digit beginning register (DBR), display timing generator circuit, and VFD
display RAM (see figure 12-1).
Display timing is determined by the number of digits per frame. When the key scan feature is
activated, the frame is extended by one digit; during that interval only, segment pins and digit pins
may be used as general purpose ports by the CPU. These pins are in the non-illuminating state
(pulled down) during the key scan interval.
12.3.3 RAM Bit Correspondence to Digits/Segments
VFD display data is set in the VFD display RAM at addresses H'FEC0 through H'FEFF.
Table 12-3 shows the correspondence between digit/segment pins and the VFD display RAM bits.
212
213
12.3.4 Procedure for Starting Operation
The procedure for starting operation of the VFD controller/driver is given below for a case in
which digit pins FD to FD and segment pins FS to FS are used. It is assumed that data has
3
15
5
23
already been written to the VFD display RAM area.
•
•
•
Select the digit/key-scan time and dimmer resolution with bit FLMO of the VFD digit control
register (VFDR), and select the digit waveform with bits DM2 to DM0. Clear bits DR3 to
DR0 to 0000, making pins FD to FD operational.
0
15
Set the VFLAG bit of the VFD segment control register (VFSR) to 1, making the selected
pins valid as VFD pins. Set bit KSE to enable or disable the key scan interval. Set bits SR4
to SR0 to 11011, making pins FS to FS operational.
0
23
Set bits DBR3 to DBR0 in the digit beginning register (DBR) to 0011, designating pin FD as
3
the first digit pin and pin FS as the first segment pin. Set bit DISP to 1, turning the display
5
on, and set bit VFDE to 1, starting VFD controller/driver operation.
12.4 Interrupts
When the key scan interval starts, bit IRRKS in interrupt request register 3 (IRR3) is set to 1.
These VFD interrupt requests can be enabled or disabled by means of bit IENKS of interrupt
enable register 3 (IENR3). For further details, see 3.2.2, Interrupts.
12.5 Occurrence of Flicker when VFD Registers are Rewritten
The VFD controller/driver is initialized whenever one of its registers (VFDR, VFSR, DBR) is
rewritten. If this initialization takes place while a digit is being displayed, the contents displayed
just prior to initialization will in some cases remain as an after-image in other digits. (This
depends in part on the performance of the vacuum fluorescent display, but a momentary glow may
be visible.) Frequent rewriting of the registers can make these after-images bright enough to
appear as a false display. This problem can be avoided by employing the following programming
sequence when VFD controller/driver registers are rewritten.
Step
1.
Description
DISP = 0
2.
VFLAG = 0
3.
Rewrite register (FLMO, DM0 to DM3, etc.)
4.
Wait for at least T
(display time of one digit). (Execute other routines.) If
digit
the wait time is too long, the entire display may flicker. If the key scan feature
is activated, this wait time does not have to be specially programmed.
5.
6.
VFLAG = 1
DISP = 1
214
Section 13 A/D Converter
13.1 Overview
The H8/3714 Series includes on-chip a resistance-ladder type successive-approximation A/D
converter, which can convert up to eight channels of analog input.
13.1.1 Features
The A/D converter has the following features.
•
•
•
•
•
8-bit resolution
Eight input channels
Conversion time: 14.8 µs per channel (min, at f = 8.38 MHz)
osc
Built-in sample-and-hold function
Interrupt requested on completion of A/D conversion
215
13.1.2 Block Diagram
Figure 13-1 shows a block diagram of the A/D converter.
PMR0 (8b)
AMR (4b)
MPX
Port
Port
P00/AN0
P01/AN1
Port
Port
Port
P02/AN2
P03/AN3
P04/AN4
P05/AN5
P06/AN6
P07/AN7
ADSR
Port
Port
Port
+
–
Control logic
Control circuitry
(successive
approximation,
Interrupt
interrupt request, etc.)
Reference voltage
VREF
AVCC
R255
R254
Chopper-type comparator
R253
R252
R251
ADRR
Successive approximation finds the input
voltage by changing a reference voltage
(VREF).
R1
RESET
LPM (low-power mode)
AVSS
One of 256 switches is selected by binary search.
The reference voltage value resulting from eight
comparisons is set in ADDR.
(The eighth value is equal to the analog input
voltage.)
The internal ladder resistance is 35 kΩ to 40 kΩ typ (approximately).
Upon reset and in low-power operation modes (sleep, watch, subactive,
or standby modes), the ladder resistance is disconnected from AVSS
by a switching transistor. The AVCC current at this time is a leakage current
Alcc of 1 µA or less (approximate value).
Notation:
PMR0: Port mode register 0
AMR: A/D mode register
ADSR: A/D start register
ADRR: A/D result register
IRRAD: A/D conversion end interrupt request flag (interrupt request register 3)
RESET: Signal set to 1 upon reset
LPM:
Signal set to 1 in low-power modes
Figure 13-1 Block Diagram of A/D Converter
216
13.1.3 Pin Configuration
Table 13-1 shows the A/D converter pin configuration.
Table 13-1 Pin Configuration
Name
Abbrev. I/O
Function
Analog power supply pin AVCC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Analog power supply and reference voltage
Analog ground and reference voltage
Analog input channel 0
Analog input channel 1
Analog input channel 2
Analog input channel 3
Analog input channel 4
Analog input channel 5
Analog input channel 6
Analog input channel 7
Analog ground pin
Analog input pin 0
Analog input pin 1
Analog input pin 2
Analog input pin 3
Analog input pin 4
Analog input pin 5
Analog input pin 6
Analog input pin 7
AVSS
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
13.1.4 Register Configuration
Table 13-2 shows the A/D converter register configuration.
Table 13-2 Register Configuration
Name
Abbrev.
AMR
R/W
R/W
R/W
R
Initial Value
H'78
Address
H'FFBC
H'FFBE
H'FFBD
H'FFEF
A/D mode register
A/D start register
A/D result register
Port mode register 0
ADSR
ADRR
PMR0
H'7F
Not fixed
H'00
W
217
13.2 Register Descriptions
13.2.1 A/D Result Register (ADRR)
Bit
7
6
5
4
3
2
1
0
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
Initial value
Read/Write
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
Note: * Not fixed
The A/D result register (ADRR) is an 8-bit read-only register for holding the result of analog-to-
digital conversion.
ADRR can be read by the CPU at any time, but the ADRR value during A/D conversion is not
fixed.
After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data
is held in ADRR until the next conversion operation starts.
ADRR is not cleared on reset.
13.2.2 A/D Mode Register (AMR)
Bit
7
AMR7
0
6
—
1
5
—
1
4
—
1
3
—
1
2
AMR2
0
1
AMR1
0
0
AMR0
0
Initial value
Read/Write
R/W
—
—
—
—
R/W
R/W
R/W
AMR is an 8-bit read/write register for selecting the A/D conversion speed and analog input pin.
Writing to AMR should be done with the A/D start flag (ADSF) cleared to 0 in the A/D start
register (ADSR).
Upon reset, AMR is initialized to H'78.
218
Bit 7: Clock select (AMR7)
*1
Bit 7 sets the A/D conversion speed.
Bit 7
AMR7
Conversion Period*2
φ = 2 MHz
31 µs
φ = 4 MHz
0
1
62/φ
31/φ
14.8 µs
(initial value)
*1
15.5 µs
—
Notes: 1. Operation is not guaranteed if the conversion time is less than 14.8 µs. Set bit 7 for a
value of at least 14.8 µs.
2. A/D conversion starts after a value of 1 is written to ADSF. The conversion period starts
when the start flag is set and ends when it is reset upon completion of conversion. The
actual time during which sample and hold are repeated is called the conversion interval
(see figure 13-2).
State
Instruction
MOV B.
execution
WRITE
Start flag
Conversion interval
Conversion period (31 or 62 states)
Interrupt request flag
IRQ sampling
(CPU)
Note: IRQ sampling: When conversion is complete, the start flag is reset and the interrupt request flag
is set. An interrupt is recognized by the CPU in the last instruction execution state,
and interrupt exception handling is executed after that instruction is completed.
Figure 13-2 Internal Operation of A/D Converter
219
Bits 6 to 3: Reserved bits
Bits 6 to 3 are reserved; they always read 1, and cannot be modified.
Bits 2 to 0: Channel select (AMR2 to AMR0)
Bits 2 to 0 select the analog input channel.
Settings are also required in port mode register 0 (PMR0). See 13.2.4, Port Mode Register 0
(PMR0).
Bit 2
Bit 1
Bit 0
AMR2
AMR1
AMR0
Analog Input Channel
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
(initial value)
220
13.2.3 A/D Start Register (ADSR)
Bit
7
ADSF
0
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
R/W
—
—
—
—
—
—
—
The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D
conversion.
A/D conversion is started by writing 1 to the A/D start flag (ADSF). When conversion is
complete, the converted data is set in the A/D result register (ADRR), and at the same time ADSF
is cleared to 0.
Bit 7: A/D start flag (ADSF)
Bit 7 is for controlling and confirming the start and end of A/D conversion.
Bit 7
ADSF
Description
0
[Read access]
(initial value)
Indicates that A/D conversion has been completed or stopped.
[Write access]
Stops A/D conversion.
1
[Read access]
Indicates A/D conversion in progress.
[Write access]
Starts A/D conversion.
Bits 6 to 0: Reserved bits
Bits 6 to 0 are reserved; they always read 1, and cannot be modified.
221
13.2.4 Port Mode Register 0 (PMR0)
Bit
7
AN7
0
6
AN6
0
5
AN5
0
4
AN4
0
3
AN3
0
2
AN2
0
1
AN1
0
0
AN0
0
Initial value
Read/Write
W
W
W
W
W
W
W
W
PMR0 is an 8-bit write-only register for designating whether each of the port 0 pins is used as a
general-purpose input pin or as an analog input channel to the A/D converter. Designation is
made separately for each pin.
Upon reset, PMR0 is initialized to H'00.
Bit n
ANn
Description
0
1
Pin P0n/ANn is used for general-purpose input.
Pin P0n/ANn is an analog input channel.
(initial value)
(n = 0 to 7)
13.3 Operation
The A/D converter operates by successive approximations, and yields its conversion result as 8-bit
data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 3 (IRR3) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 3 (IENR3) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid misoperation.
13.4 Interrupts
When A/D conversion is complete (ADSF changes from 1 to 0), bit IRRAD in interrupt request
register 3 (IRR3) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 3 (IENR3).
For further details see 3.2.2, Interrupts.
222
13.5 Typical Use
An example of how the A/D converter can be used is given below, using channel 1 (AN ) as the
1
analog input channel. Figure 13-3 shows the operation timing for this example.
1. Bits AMR2 to AMR0 of the A/D mode register (AMR) are set to 001, and bits AN7 to AN0
of port mode register 0 (PMR0) are set to 00000010, making AN the analog input channel.
1
Interrupt request is cleared by setting bit IRRAD to 0, A/D interrupts are enabled by setting
bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1.
2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion results are
sent to the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D
converter goes to the idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 13-4 and 13-5 show flow charts of procedures for using the A/D converter.
223
Figure 13-3 Typical A/D Converter Operation Timing
224
START
Set A/D conversion speed
and input channels
Disable A/D conversion
end interrupt
Start A/D conversion
Read ADSR
No
ADSF = 0?
Yes
Read ADRR data
Perform
Yes
A/D conversion?
No
END
Figure 13-4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software)
225
START
Set A/D converter speed
and input channels
Clear bit IRRAD to 0
Enable A/D conversion
end interrupt
Start A/D conversion
Yes
A/D conversion
end interrupt?
No
Clear bit IRRAD
to 0 in IRR3
Read ADRR data
Perform
Yes
A/D conversion?
No
END
Figure 13-5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used)
226
13.6 Application Notes
1. Data in the A/D result register (ADRR) should be read only when the A/D start flag (ADSF)
in the A/D start register (ADSR) is cleared to 0.
2. Changing a digital input signal at a nearby pin during A/D conversion may adversely affect
conversion accuracy.
3. The pin selected as an analog input channel in the A/D mode register (AMR) must also be
designated as an analog input channel in port mode register 0 (PMR0).
227
228
Section 14 Electrical Specifications
14.1 Absolute Maximum Ratings
Table 14-1 gives the absolute maximum ratings.
Table 14-1 Absolute Maximum Ratings
Item
Symbol
VCC
VPP
AVCC
AVin
VT
Rating
Unit
V
Notes
1, 2
Supply voltage
–0.3 to +7.0
Programming voltage
Analog supply voltage
Analog input voltage
Pin voltage (standard pins)
Pin voltage (high-voltage pins)
Operating temperature
Storage temperature
–0.3 to +14.0
–0.3 to +7.0
V
1, 2, 3
1, 2
V
–0.3 to AVCC +0.3
–0.3 to VCC +0.3
VCC –45 to VCC +0.3
–20 to +75
V
1, 2
V
1, 2, 4
1, 2, 5
1, 2
VT
V
Top
°C
°C
Tstg
–55 to +125
1, 2
Notes: 1. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.
2. All voltages are referenced to VSS
3. Applies to the ZTAT™ version.
4. Applies to standard-voltage pins.
5. Applies to high-voltage pins.
.
229
14.2 HD6473714 Electrical Characteristics
14.2.1 HD6473714 DC Characteristics
Table 14-2 gives the allowable current values of the HD6473714. Table 14-3 gives the DC
characteristics.
Table 14-2 Allowable Output Current Values
Conditions: V = 4.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C
CC
SS
a
Item
Symbol
IO
Rating
2
Unit
mA
mA
mA
mA
mA
Notes
1, 2
2, 3
3, 4
5
Allowable input current (sink)
Allowable output current (source)
Allowable output current (source)
Total allowable input current (sink)
–IO
2
–IO
20
∑IO
50
Total allowable output current (source)
–∑IO
150
6
Notes: 1. Allowable input current means the maximum current that can flow from each I/O pin to
VSS
.
2. Applies to standard-voltage pins.
3. Allowable output current means the maximum current that can flow from VCC to each I/O
pin.
4. Applies to high-voltage pins.
5. Total allowable input current means the sum of current that can flow at one time from all
I/O pins to VSS
.
6. Total allowable output current means the sum of current that can flow from VCC to all I/O
pins.
230
Table 14-3 DC Characteristics
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Typ
Applicable
Symbol Pins
Item
Test Conditions
Min
Max
Unit Notes
Input high VIH
voltage
RES
IRQ0, IRQ1,
0.8 VCC
—
VCC +0.3
V
IRQ4, IRQ5
VCC = 2.7 to 5.5 V
0.9 VCC
—
VCC +0.3
SCK1, SCK2 incl. subactive mode
SI1, SI2
EVENT, UD
VCC = 2.7 to 5.5 V
incl. subactive mode
0.7 VCC
—
VCC +0.3
V
V
OSC1
VCC –0.5
VCC –0.3
—
—
VCC +0.3
VCC +0.3
VCC = 2.7 to 5.5 V
incl. subactive mode
P00 to P07
P10, P11,
P14 to P16
P90 to P97
VCC = 2.7 to 5.5 V
incl. subactive mode
0.7 VCC
—
VCC +0.3
V
V
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P17
VCC = 2.7 to 5.5 V
incl. subactive mode
0.7 VCC
—
VCC +0.3
Input low
voltage
VIL
RES,
–0.3
–0.3
—
—
0.2 VCC
0.1 VCC
V
SCK1, SCK2
IRQ0, IRQ1,
IRQ4, IRQ5
SI1, SI2
VCC = 2.7 to 5.5 V
incl. subactive mode
EVENT, UD
VCC = 2.7 to 5.5 V
incl. subactive mode
–0.3
—
0.3 VCC
V
V
OSC1
–0.3
–0.3
—
—
0.5
0.3
VCC = 2.7 to 5.5 V
incl. subactive mode
P00 to P07
P10, P11,
P14 to P16
P90 to P97
VCC = 2.7 to 5.5 V
incl. subactive mode
–0.3
—
0.3 VCC
V
V
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P17
VCC = 2.7 to 5.5 V
incl. subactive mode
VCC –40
—
0.3 VCC
Note: Connect the TEST pin to VSS
.
231
Table 14-3 DC Characteristics (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Typ
Applicable
Pins
Item
Symbol
Test Conditions
–IOH = 1.0 mA
–IOH = 0.5 mA
Min
Max
—
Unit Notes
Output high
voltage
P10, P11,
P14, P15
P90 to P97
PWM, SO1,
SO2, SCK1,
SCK2
VOH
VCC –1.0
VCC –0.5
VCC –0.5
—
—
—
V
—
VCC = 2.7 to 5.5 V
–IOH = 0.3 mA
—
P40 to P47
P50 to P57
P60 to P67
P70 to P77
–IOH = 15 mA
–IOH = 10 mA
–IOH = 4 mA
VCC –3.0
VCC –2.0
VCC –1.0
—
—
—
—
—
—
—
V
VCC = 2.7 to 5.5 V
–IOH = 4 mA
VCC –1.0 —
V
V
Reference
value
P10, P11,
P14, P15
Output low VOL
voltage
VCC = 4.0 to 5.5 V
IOL = 1.6 mA
—
—
—
0.4
P90 to P97
PWM, SO1,
SO2, SCK1,
SCK2
VCC = 2.7 to 5.5 V
IOL = 0.5 mA
0.4
—
V
V
Reference
value
P40 to P47
P50 to P57
P60 to P67
P70 to P77
Pull-down
—
—
—
—
VCC –37
resistance
150 kΩ; pull-down
voltage VCC –40 V
Input
|IIL|
RES
VIN = 0.0 to VCC
40
µA
leakage
current
232
Table 14-3 DC Characteristics (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Applicable
Pins
Item
Symbol
Test Conditions
Min
Typ
Max
Unit Notes
I/O leakage |IIL|
current
TEST
SCK1, SCK2
SI1, SI2
VIN = 0.0 to VCC
—
—
1
µA
IRQ0, IRQ1,
IRQ4, IRQ5
EVENT, UD
OSC1
P00 to P07
P10, P11
P14 to P16
P90 to P97
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P17
VIN = VCC –40
to VCC
—
—
—
—
20
20
µA
pF
Input
CIN
Input pins
other than
power supply
pins and I/O
pins
f = 1 MHz, VIN = 0 V
Ta = 25°C
capaci-
tance
P16/EVENT
—
—
—
—
35
70
RES
233
Table 14-3 DC Characteristics (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Applicable
Pins
Item
Symbol
Test Conditions
Min
Typ
Max
Unit Notes
Power
Reference
value
1
IOPE
VCC
VCC = 5 V,
fOSC = 8 MHz
—
17
—
mA
mA
mA
dissipation
when CPU
operating in
active mode
VCC = 5 V,
fOSC = 4 MHz
—
—
—
—
—
—
—
—
9
—
—
9
VCC = 3 V,
fOSC = 4 MHz
6
Power
IRES
VCC
VCC
VCC
VCC = 5 V,
fOSC = 8 MHz
6
1
1
dissipation
during reset
in active
mode
VCC = 5 V,
fOSC = 4 MHz
3
5
VCC = 3 V,
fOSC = 4 MHz
1.5
2.5
1.5
1.0
—
3.5
2.0
—
Power
dissipation in
sleep mode
ISLEEP
VCC = 5 V,
fOSC = 8 MHz
VCC = 5 V,
fOSC = 4 MHz
VCC = 3 V,
fOSC = 4 MHz
Power
VCC = 2.7 V
32 kHz crystal
oscillator used
ISUB
—
—
6
20
—
µA
µA
dissipation in
subactive
mode
11
2
VCC = 5.0 V
32 kHz crystal
oscillator used
—
—
16
22
—
—
µA
µA
Reference
value
2
Power
dissipation in
watch mode
VCC = 2.7 V
32 kHz crystal
oscillator used
IWATCH
VCC
—
—
3.2
3.8
6
µA
µA
—
2
VCC = 5.0 V
32 kHz crystal
oscillator used
—
10
—
µA
Reference
value
—
—
12
—
—
µA
µA
2
Power
ISTBY
VCC
32 kHz crystal
oscillator not used
X1 = VCC
10
dissipation
in standby
mode
234
Table 14-3 DC Characteristics (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Applicable
Pins
Item
Symbol
Test Conditions
Min
Typ
Max
Unit Notes
RAM data
retention
voltage in
standby
mode
VSTBY
VCC
32 kHz crystal
oscillator not used
X1 = VCC
2
—
—
V
Notes: 1. Does not include current flowing to output buffer.
2. Reference value when bypass capacitor of 47 µF is connected between VCC and VSS
.
235
14.2.2 HD6473714 AC Characteristics
Table 14-4 gives the control signal timing of the HD6473714. Table 14-5 gives the serial interface
timing.
Table 14-4 Control Signal Timing
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V
,
CC
disp
CC
CC
V
= 0.0 V, T = –20 to +75°C
a
SS
Rating
Applicable
Pins
Reference
Diagram
Item
Symbol
Test Conditions
Min
Typ
—
Max
8.4
Unit
Clock pulse
generator
frequency
OSC1,
OSC2,
fOSC
2
2
MHz
VCC = 2.7 to 5.5 V
—
4.2
OSC1,
OSC2,
Figure
14-1
Clock cycle time
tCYC
119
238
—
—
500
500
ns
VCC = 2.7 to 5.5 V
Instruction cycle
time
φ
238
476
—
—
1000 ns
1000
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
—
Subclock pulse
generator
frequency
fx
X1, X2
X1, X2
32.768
—
kHz
Subclock cycle
time
tsubcyc
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
—
—
30.5
—
—
µs
µs
Subactive
instruction cycle
time
φSUB
244.14
Oscillator settling
time (crystal
oscillator)
OSC1,
OSC2,
trc
—
—
—
—
40
60
ms
ms
VCC = 2.7 to 5.5 V
Oscillator settling
time (ceramic
oscillator)
OSC1,
OSC2,
trc
—
—
—
—
20
40
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
Oscillator
settling time
trc
X1, X2
OSC1
—
—
2
s
External clock
pulse width (high)
Figure
14-1
tCPH
40
100
40
100
—
—
—
—
—
—
—
—
—
—
—
—
—
20
20
20
20
ns
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
External clock
pulse width (low)
tCPL
tCPr
tCPf
OSC1
OSC1
OSC1
ns
ns
ns
External clock
rise time
—
External clock fall
time
—
—
236
Table 14-4 Control Signal Timing (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
a
SS
Rating
Applicable
Pins
Reference
Diagram
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
RES pin pulse
width (low)
tREL
RES
VCC = 2.7 to 5.5 V
10
—
—
φ
Figure
14-2
IRQ pin pulse
width (high)
tIH
IRQ0, IRQ1, VCC = 2.7 to 5.5 V
IRQ4, IRQ5
2
—
—
—
—
—
—
—
—
—
—
φ
φSUB
Figure
14-3
IRQ pin pulse
width (low)
tIL
IRQ0, IRQ1, VCC = 2.7 to 5.5 V
IRQ4, IRQ5
2
φ
φSUB
EVENT pin
pulse width (high)
tEVH
tEVL
EVENT
EVENT
UD
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
2
φ
φ
φ
Figure
14-4
EVENT pin
pulse width (low)
2
UD pin minimum tUDH
high/low width tUDL
2
Figure
14-5
Table 14-5 Serial Interface Timing
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
a
SS
Rating
Applicable
Pins
Reference
Diagram
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Output serial
clock cycle time
tscyc
SCK1,
SCK2
VCC = 2.7 to 5.5 V
2
—
—
φ
Figure
14-6
Output serial
clock pulse width
(high)
tSCKH
SCK1,
SCK2
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
0.4
—
—
—
—
tscyc
Output serial
clock pulse
width (low)
tSCKL
SCK1,
SCK2
0.4
tscyc
Output serial
clock rise time
SCK1,
SCK2
tSCKr
—
—
—
—
1
—
—
—
—
—
60
80
60
80
—
ns
ns
VCC = 2.7 to 5.5 V
Output serial
clock fall time
SCK1,
SCK2
tSCKf
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
SCK1,
SCK2
Input serial
clock cycle time
tscyc
φ
SCK1,
SCK2
Input serial
clock pulse
width (high)
tSCKH
VCC = 2.7 to 5.5 V
0.4
—
—
tscyc
237
Table 14-5 Serial Interface Timing (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
a
SS
Rating
Applicable
Pins
Reference
Diagram
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
SCK1,
SCK2
Input serial
clock pulse
width (low)
tSCKL
VCC = 2.7 to 5.5 V
0.4
—
—
tscyc
Figure
14-6
Input serial
clock rise time
SCK1,
SCK2
tSCKr
tSCKf
tdSO
tsSI
—
—
—
—
—
—
—
—
—
—
—
—
60
80
60
80
200
350
—
ns
ns
ns
ns
ns
µs
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
—
Input serial
clock fall time
SCK1,
SCK2
—
—
Serial output
data delay time
SO1, SO2
SI1, SI2
SI1, SI2
SCK2
—
—
Serial input data
setup time
230
470
230
470
0.2
—
Serial input data
hold time
thSI
—
—
Transfer pending tSCK2
time
When pin SCK2 is
input pin
40
Figure
14-7
When pin SCK2 is
input pin
VCC = 2.7 to 5.5 V
0.4
—
3
—
—
—
40
1
When pin SCK2 is
output pin
VCC = 2.7 to 5.5 V
tscyc
Transfer end
acknowledge
time
tCS
CS
VCC = 2.7 to 5.5 V
4
φ
238
14.2.3 HD6473714 A/D Converter Characteristics
Table 14-6 gives the HD6473714 A/D converter characteristics.
Table 14-6 A/D Converter Characteristics
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V
,
CC
disp
CC
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Typ
VCC –0.3 VCC
Applicable
Symbol Pins
Item
Test Conditions
Min
Max
Unit Notes
Analog
supply
voltage
AVCC
AVCC
VCC +0.3
V
Analog
input voltage
AVIN
AN0 to AN7
AVCC
AVSS
—
AVCC
V
Analog
supply
current
AICC
AVCC = 5 V
—
—
—
—
200
10
µA
µA
AISTOP
Reset and power-
down mode
Analog input CAIN
capacitance
AN0 to AN7
AN0 to AN7
—
—
—
—
30
10
pF
Allowable
RAIN
kΩ
signal source
impedance
Resolution
—
—
—
—
8
Bit
Absolute
accuracy
VCC = AVCC = 5 V
—
±2.5
—
LSB
VCC = AVCC
4.0 to 5.5 V
=
±2.5
Reference
value
Conversion
time
31
15.5
14.8
µs
239
14.3 HD6433712, HD6433713 and HD6433714 Electrical Characteristics
14.3.1 HD6433712, HD6433713 and HD6433714 DC Characteristics
Table 14-7 gives the allowable current values of the HD6433712, HD6433713 and HD6433714.
Table 14-8 gives the DC characteristics.
Table 14-7 Allowable Output Current Values
Conditions: V = 4.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C
CC
SS
a
Item
Symbol
IO
Rating
2
Unit
mA
mA
mA
mA
mA
mA
Notes
1, 2
2, 3
3, 4
5
Allowable input current (sink)
Allowable output current (source)
Allowable output current (source)
Total allowable input current (sink)
–IO
2
–IO
20
∑IO
50
Total allowable output current (source)
Total allowable output current to Vdisp
–∑IO
–∑IO
150
30
6
7
Notes: 1. Allowable input current means the maximum current that can flow from each I/O pin to
VSS
.
2. Applies to standard-voltage pins.
3. Allowable output current means the maximum current that can flow from VCC to each I/O
pin.
4. Applies to high-voltage pins.
5. Total allowable input current means the sum of current that can flow at one time from all
I/O pins to VSS
.
6. Total allowable output current means the sum of current that can flow from VCC to all I/O
pins.
7. Total allowable output current to Vdisp is the sum of current that can flow from all I/O pins
to Vdisp
.
240
Table 14-8 DC Characteristics
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Typ
Applicable
Symbol Pins
Item
Test Conditions
Min
Max
Unit Notes
Input high VIH
voltage
RES
IRQ0, IRQ1,
0.8 VCC
—
VCC +0.3
V
IRQ4, IRQ5
VCC = 2.5 to 5.5 V
0.9 VCC
—
VCC +0.3
SCK1, SCK2 incl. subactive mode
SI1, SI2
EVENT, UD
VCC = 2.5 to 5.5 V
incl. subactive mode
0.7 VCC
—
VCC +0.3
V
V
OSC1
VCC –0.5
VCC –0.3
—
—
VCC +0.3
VCC +0.3
VCC = 2.5 to 5.5 V
incl. subactive mode
P00 to P07
P10, P11
P14 to P16
P90 to P97
VCC = 2.5 to 5.5 V
incl. subactive mode
0.7 VCC
—
VCC +0.3
V
V
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P17
VCC = 2.5 to 5.5 V
incl. subactive mode
0.7 VCC
—
VCC +0.3
Input low
voltage
VIL
RES,
–0.3
–0.3
—
—
0.2 VCC
0.1 VCC
V
SCK1, SCK2
IRQ0, IRQ1,
IRQ4, IRQ5
SI1, SI2
VCC = 2.5 to 5.5 V
incl. subactive mode
EVENT, UD
VCC = 2.5 to 5.5 V
incl. subactive mode
–0.3
—
0.3 VCC
V
V
OSC1
–0.3
–0.3
—
—
0.5
0.3
VCC = 2.5 to 5.5 V
incl. subactive mode
P00 to P07
P10, P11
P14 to P16
P90 to P97
VCC = 2.5 to 5.5 V
incl. subactive mode
–0.3
—
0.3 VCC
V
V
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P17
VCC = 2.5 to 5.5 V
incl. subactive mode
VCC –40
—
0.3 VCC
Note: Connect the TEST pin to VSS
.
241
Table 14-8 DC Characteristics (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Applicable
Pins
Item
Symbol
Test Conditions
–IOH = 1.0 mA
–IOH = 0.5 mA
Min
Typ
—
Max
—
Unit Notes
Output high
voltage
P10, P11
P14, P15
P90 to P97
PWM, SO1,
SO2, SCK1,
SCK2
VOH
VCC –1.0
VCC –0.5
VCC –0.5
V
—
—
VCC = 2.7 to 5.5 V
–IOH = 0.3 mA
—
—
P40 to P47
P50 to P57
P60 to P67
P70 to P77
–IOH = 15 mA
–IOH = 10 mA
–IOH = 4 mA
VCC –3.0
VCC –2.0
VCC –1.0
—
—
—
—
—
—
—
V
VCC = 2.7 to 5.5 V
–IOH = 4 mA
VCC –1.0 —
V
V
Reference
value
Output low VOL
voltage
P10, P11
P14, P15
P90 to P97
PWM, SO1,
SO2, SCK1,
SCK2
VCC = 4.0 to 5.5 V
IOL = 1.6 mA
—
—
—
0.4
VCC = 2.7 to 5.5 V
IOL = 0.5 mA
0.4
—
V
V
Reference
value
P40 to P47
P50 to P57
P60 to P67
P70 to P77
Vdisp = VCC –40 V
—
—
—
—
VCC –37
VCC –37
With
MOS
pull-down
Pull-down
resistance
150 kΩ; pull-down
voltage VCC –40 V
Input
leakage
current
|IIL|
RES
Mask ROM version:
VIN = 0.0 to VCC
—
—
1
µA
242
Table 14-8 DC Characteristics (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Typ
—
Applicable
Symbol Pins
Item
Test Conditions
Min
Max
Unit Notes
I/O leakage |IIL|
current
TEST
SCK1, SCK2
SI1, SI2
VIN = 0.0 to VCC
—
1
µA
IRQ0, IRQ1
IRQ4, IRQ5
EVENT, UD
OSC1
P00 to P07
P10, P11
P14 to P16
P90 to P97
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P17
VIN = VCC –40
to VCC
—
—
20
µA
Not
including
pins with
MOS
pull-down
Pull-up
MOS
current
–Ip
P10, P11
P14 to P16
P90 to P97
VCC = 5 V, VIN = 0 V 50
—
300
—
µA
µA
VCC = 2.7 V,
VIN = 0 V
—
25
Reference
value
Pull-down Id
MOS
current
P40 to P47
P50 to P57
P60 to P67
P70 to P77
Vdisp = VCC –36
VIN = VCC
120
—
—
800
—
Vdisp = VCC –18
VIN = VCC
280
—
Reference
value
Input
capaci-
tance
CIN
Input pins
other than
power supply
pins and I/O
pins
f = 1 MHz, VIN = 0 V
Ta = 25°C
—
15
pF
P17
—
—
30
243
Table 14-8 DC Characteristics (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Typ
Applicable
Pins
Item
Symbol
Test Conditions
Min
Max
Unit Notes
IOPE
VCC
VCC = 5 V,
fOSC = 8 MHZ
—
15
—
mA
mA
mA
µA
Power
Reference
value
1
dissipation
when CPU
operating in
active mode
VCC = 5 V,
fOSC = 4 MHz
—
—
—
—
—
—
—
—
—
8
—
—
8
VCC = 3 V,
fOSC = 4 MHz
5
IRES
VCC
VCC
VCC
VCC = 5 V,
fOSC = 8 MHz
5
1
1
Power
dissipation
during reset
in active
mode
VCC = 5 V,
fOSC = 4 MHz
2.5
1.3
2
4
VCC = 3 V,
fOSC = 4 MHz
—
3
ISLEEP
VCC = 5 V,
fOSC = 8 MHz
Power
dissipation in
sleep mode
VCC = 5 V,
fOSC = 4 MHz
1
1.5
—
20
VCC = 3 V,
fOSC = 4 MHz
0.6
5
ISUB
Power
VCC = 2.5 V
dissipation in
subactive
mode
32 kHz crystal
oscillator used
—
—
9
—
—
µA
µA
2
13
Reference
value
VCC = 5.0 V
32 kHz crystal
oscillator used
—
20
—
µA
2
IWATCH
VCC
—
—
2.2
2.8
5
µA
µA
Power
dissipation in
watch mode
VCC = 2.5 V
32 kHz crystal
oscillator used
—
2
—
6
—
µA
Reference
value
VCC = 5.0 V
32 kHz crystal
oscillator used
—
—
8
—
5
µA
µA
2
Power
ISTBY
VCC
32 kHz crystal
oscillator not used
X1 = VCC
—
dissipation
in standby
mode
244
Table 14-8 DC Characteristics (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Typ
Applicable
Symbol Pins
Item
Test Conditions
Min
Max
Unit Notes
RAM data
retention
voltage in
standby
mode
VSTBY
VCC
32 kHz crystal
oscillator not used
X1 = VCC
2
—
—
V
Notes: 1. Does not include current flowing to pull-up MOS or output buffer.
2. Reference value when bypass capacitor of 47 µF is connected between VCC and VSS
.
245
14.3.2 HD6433712, HD6433713 and HD6433714 AC Characteristics
Table 14-9 gives the control signal timing of the HD6433712, HD6433713 and HD6433714.
Table 14-10 gives the serial interface timing.
Table 14-9 Control Signal Timing
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V
,
CC
disp
CC
CC
V
= 0.0 V, T = –20 to +75°C
a
SS
Rating
Applicable
Pins
Reference
Diagram
Item
Symbol
Test Conditions
Min
Typ
—
Max
8.4
Unit
fOSC
2
2
MHz
Clock pulse
generator
frequency
OSC1,
OSC2,
VCC = 2.7 to 5.5 V
—
4.2
Clock cycle time
tCYC
119
238
—
—
500
500
ns
Figure
14-1
OSC1,
OSC2,
VCC = 2.7 to 5.5 V
φ
238
476
—
—
1000 ns
1000
Instruction cycle
time
VCC = 2.7 to 5.5 V
VCC = 2.5 to 5.5 V
—
Subclock pulse
generator
frequency
fx
X1, X2
X1, X2
32.768
—
kHz
Subclock cycle
time
tsubcyc
VCC = 2.5 to 5.5 V
VCC = 2.5 to 5.5 V
—
—
30.5
—
—
µs
µs
Subactive
instruction cycle
time
φSUB
244.14
trc
—
—
—
—
40
60
ms
ms
Oscillator settling
time (crystal
oscillator)
OSC1,
OSC2,
VCC = 2.7 to 5.5 V
trc
—
—
—
—
20
40
Oscillator settling
time (ceramic
oscillator)
OSC1,
OSC2,
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
Oscillator
settling time
trc
X1, X2
OSC1
—
—
2
s
tCPH
40
100
40
100
—
—
—
—
—
—
—
—
—
—
—
—
—
20
20
20
20
ns
External clock
pulse width (high)
Figure
14-1
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
tCPL
tCPr
tCPf
OSC1
OSC1
OSC1
ns
ns
ns
External clock
pulse width (low)
External clock
rise time
—
—
External clock fall
time
—
246
Table 14-9 Control Signal Timing (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
a
SS
Rating
Applicable
Symbol Pins
Reference
Diagram
Item
Test Conditions
Min
Typ
Max
Unit
RES pin pulse
width (low)
tREL RES
VCC = 2.7 to 5.5 V
10
—
—
φ
Figure
14-2
IRQ pin pulse
width (high)
tIH
IRQ0, IRQ1 VCC = 2.7 to 5.5 V
IRQ4, IRQ5
2
—
—
—
—
—
—
—
—
—
—
φ
φSUB
Figure
14-3
IRQ pin pulse
width (low)
tIL
IRQ0, IRQ1 VCC = 2.7 to 5.5 V
IRQ4, IRQ5
2
φ
φSUB
EVENT pin
pulse width (high)
tEVH
tEVL
EVENT
EVENT
UD
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
2
φ
φ
φ
Figure
14-4
EVENT pin
pulse width (low)
2
UD pin minimum tUDH
high/low width tUDL
2
Figure
14-5
Table 14-10 Serial Interface Timing
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
a
SS
Rating
Applicable
Symbol Pins
Reference
Diagram
Item
Test Conditions
Min
Typ
Max
Unit
Output serial
clock cycle timing
tscyc
SCK1,
SCK2
VCC = 2.7 to 5.5 V
2
—
—
φ
Figure
14-6
Output serial
clock pulse width
(high)
tSCKH
SCK1,
SCK2
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
0.4
—
—
—
—
tscyc
Output serial
clock pulse
width (low)
tSCKL
SCK1,
SCK2
0.4
tscyc
Output serial
clock rise time
tSCKr
SCK1,
SCK2
—
—
—
—
1
—
—
—
—
—
60
80
60
80
—
ns
ns
VCC = 2.7 to 5.5 V
Output serial
clock fall time
tSCKf
SCK1,
SCK2
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
Input serial
clock cycle timing
tscyc
SCK1,
SCK2
φ
Input serial
clock pulse
width (high)
tSCKH
SCK1,
SCK2
VCC = 2.7 to 5.5 V
0.4
—
—
tscyc
247
Table 14-10 Serial Interface Timing (cont)
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V ,
CC
CC
disp
CC
V
= 0.0 V, T = –20 to +75°C
a
SS
Rating
Applicable
Symbol Pins
Reference
Diagram
Item
Test Conditions
Min
Typ
Max
Unit
Input serial
clock pulse
width (low)
tSCKL
SCK1,
SCK2
VCC = 2.7 to 5.5 V
0.4
—
—
tscyc
Figure
14-6
Input serial
clock rise time
tSCKr
tSCKf
tdSO
tsSI
SCK1,
SCK2
—
—
—
—
—
—
—
—
—
—
—
—
60
80
60
80
200
350
—
ns
ns
ns
ns
ns
µs
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
VCC = 2.7 to 5.5 V
—
Input serial
clock fall time
SCK1,
SCK2
—
—
Serial output
data delay time
SO1, SO2
SI1, SI2
SI1, SI2
SCK2
—
—
Serial input data
setup time
230
470
230
470
0.2
—
Serial input data
hold time
thSI
—
—
Transfer pending tSCK2
time
When pin SCK2 is
input pin
40
Figure
14-7
When pin SCK2 is
input pin
VCC = 2.7 to 5.5 V
0.4
—
3
—
—
—
40
1
When pin SCK2 is
output pin
VCC = 2.7 to 5.5 V
tscyc
Transfer end
acknowledge
time
tCS
CS
VCC = 2.7 to 5.5 V
4
φ
248
14.3.3 HD6433712, HD6433713 and HD6433714 A/D Converter Characteristics
Table 14-11 gives the HD6433712, HD6433713 and HD6433714 A/D converter characteristics.
Table 14-11 A/D Converter Characteristics
Conditions: Unless otherwise indicated, V = 4.0 to 5.5 V, V
= V – 40 to V
,
CC
disp
CC
CC
V
= 0.0 V, T = –20 to +75°C
SS
a
Rating
Typ
VCC –0.3 VCC
Applicable
Symbol Pins
Item
Test Conditions
Min
Max
Unit Notes
Analog
supply
voltage
AVCC
AVCC
VCC +0.3
V
Analog
input voltage
AVIN
AN0 to AN7
AVCC
AVSS
—
AVCC
V
Analog
supply
current
AICC
AVCC = 5 V
—
—
—
—
200
10
µA
µA
AISTOP
Reset and power-
down mode
Analog input CAIN
capacitance
AN0 to AN7
AN0 to AN7
—
—
—
—
30
10
pF
Allowable
RAIN
kΩ
signal source
impedance
Resolution
—
—
—
—
8
Bit
Absolute
accuracy
VCC = AVCC = 5 V
—
±2.5
—
LSB
VCC = AVCC
4.0 to 5.5 V
=
±2.5
Reference
value
Conversion
time
31
15.5
14.8
µs
249
14.4 Operational Timing
This section provides operational timing diagrams (figures 14-1 to 14-8).
φ
tcyc
VIH
VIL
OSC1
tCPH
tCPL
tCPf
tCPr
Figure 14-1 System Clock Input Timing
RES
VIL
tREL
Figure 14-2 RES Pin Pulse Width (Low)
VIH
VIL
IRQ0, IRQ1,
IRQ4, IRQ5
tIL
tIH
Figure 14-3 IRQ Pin Input Timing
VIH
VIL
EVENT
tEVL
tEVH
Figure 14-4 EVENT Pin Minimum Pulse Widths
250
VIH
UD
VIL
tUDH
tUDL
Figure 14-5 UD Pin Minimum High/Low Width
tscyc
V
IH or VOH
*
SCK1
SCK2
VIL or VOL
*
tSCKH
tSCKf
tSCKL
tdso
tSCKr
SO1
SO2
VOH
*
VOL*
tssi thsi
SI1
SI2
Note: * Output timing reference levels:
Output high level: VOH: 2.0 V
Output low level:
VOL: 0.8 V
See figure 14-8 for the load conditions.
Figure 14-6 SCI I/O Timing
251
VOH*
CS
VOL*
tSCK2
tCS
VIH or VOH
*
SCK2
VIL or VOL
*
Note: * Output timing reference levels:
Output high level: VOH: 2.0 V
Output low level:
VOL: 0.8 V
See figure 14-8 for the load conditions.
Figure 14-7 Serial Communication Interface 2 Chip Select Timing
VCC
2.4 kΩ
Output pin
30 pF
12 kΩ
Figure 14-8 Output Load Conditions
252
14.5 Differences in Electrical Characteristics between HD6473714 and
HD6433712/HD6433713/HD6433714
Table 14-12 shows the difference in electrical characteristics between the HD6473714 and
HD6433712/HD6433713/HD6433714.
Table 14-12 Differences in Electrical Characteristics between HD6473714 and
HD6433712/HD6433713/HD6433714
Mask ROM Version ZTAT™ Version
Applicable
Pins
Item
Symbol
Test Conditions
Min
Typ
Max Min Typ Max Unit
Operation
range in
subactive
mode
VCC
2.5
—
5.5
2.7
—
5.5
V
Input leakage |IIL|
current
RES
—
—
1
—
—
40
µA
pF
Input
CIN
P16/EVENT
P17/Vdisp
RES
—
—
—
—
—
—
—
15
15
30
15
—
—
—
—
—
—
—
—
17
35
20
70
—
capacitance
Power
IOPE
VCC
VCC = 5 V,
fOSC = 8 MHz
mA
mA
dissipation
when CPU
operating in
active mode
VCC = 5 V,
fOSC = 4 MHz
—
—
—
—
—
—
—
—
8
—
—
8
—
—
—
—
—
—
—
—
9
—
—
9
VCC = 3 V,
fOSC = 4 MHz
5
6
Power
IRES
VCC
VCC = 5 V,
fOSC = 8 MHz
5
6
dissipation
during reset
in active
mode
VCC = 5 V,
fOSC = 4 MHz
2.5
1.3
2
4
3
5
VCC = 3 V,
fOSC = 4 MHz
—
3
1.5
—
Power
ISLEEP
VCC
VCC = 5 V,
fOSC = 8 MHz
2.5 3.5
dissipation in
sleep mode
VCC = 5 V,
fOSC = 4 MHz
1
1.5
—
1.5
1
2
VCC = 3 V,
0.6
—
fOSC = 4 MHz
253
Table 14-12 Differences in Electrical Characteristics between HD6473714 and
HD6433713/HD6433714 (cont)
Mask ROM Version ZTAT™ Version
Applicable
Pins
Item
Symbol
Test Conditions
Min
Typ
Max Min Typ Max Unit
Power
ISUB
VCC
VCC = 2.5 V
(no bypass capacitor)
—
5
20
µA
µA
µA
dissipation
in subactive
mode
VCC = 2.5 V
(47 µF bypass
capacitor)
—
9
—
VCC = 2.7 V
(no bypass capacitor)
—
—
6
20
—
VCC = 2.7 V
(47 µF bypass
capacitor)
11
VCC = 5 V
(no bypass capacitor)
—
—
13
20
—
—
—
—
16
22
—
—
VCC = 5 V
(47 µF bypass
capacitor)
Power
IWATCH
VCC
VCC = 2.5 V
(no bypass capacitor)
—
—
2.2
2.8
5
dissipation
in watch
mode
VCC = 2.5 V
(47 µF bypass
capacitor)
—
VCC = 2.7 V
(no bypass capacitor)
—
—
3.2
3.8
6
VCC = 2.7 V
(47 µF bypass
capacitor)
—
VCC = 5 V
(no bypass capacitor)
—
—
6
8
—
—
—
—
10
12
—
—
VCC = 5 V
(47 µF bypass
capacitor)
Power
ISTBY
VCC
—
—
5
—
—
10
dissipation
in standby
mode
254
Appendix A CPU Instruction Set
A.1 Instruction Notation
Operation Notation
Rd8/16
General register (destination) (8 or 16 bits)
Rs8/16
General register (source) (8 or 16 bits)
General register (8 or 16 bits)
Condition code register
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Program counter
Rn8/16
CCR
N
Z
V
C
PC
SP
Stack pointer
#xx: 3/8/16
Immediate data (3, 8, or 16 bits)
Displacement (8 or 16 bits)
Absolute address (8 or 16 bits)
Addition
d: 8/16
@aa: 8/16
+
–
×
÷
Subtraction
Multiplication
Division
AND logical
OR logical
Exclusive OR logical
Move
→
—
Logical complement
Condition Code Notation
Symbol
↕
*
Modified according to the instruction result
Not fixed (value not guaranteed)
Always cleared to 0
0
—
Not affected by the instruction execution result
255
A.2 Operation Code Map
Table A-1 is an operation code map. It shows the operation codes contained in the first byte of the
instruction code (bits 15 to 8 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
256
A.3 Number of States Required for Execution
Table A-2 Instruction Set
Addressing Mode/
Instruction Length (bytes)
Condition Code
Mnemonic
Operation
I
H N Z V C
MOV.B #xx:8, Rd
MOV.B Rs, Rd
B
B
B
B
B
#xx:8 → Rd8
2
2
2
4
2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 6
Rs8 → Rd8
MOV.B @Rs, Rd
MOV.B @(d:16, Rs), Rd
MOV.B @Rs+, Rd
@Rs16 → Rd8
@(d:16, Rs16)→ Rd8
@Rs16 → Rd8
Rs16+1 → Rs16
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
B
B
B
B
B
@aa:8 → Rd8
2
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 6
@aa:16 → Rd8
Rs8 → @Rd16
4
2
4
2
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @—Rd
Rs8 → @(d:16, Rd16)
Rd16–1 → Rd16
Rs8 → @Rd16
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
B
B
Rs8 → @aa:8
2
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 6
Rs8 → @aa:16
#xx:16 → Rd
4
W
W
W
W
W
4
2
2
4
2
Rs16 → Rd16
MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd
MOV.W @Rs+, Rd
@Rs16 → Rd16
@(d:16, Rs16) → Rd16
@Rs16 → Rd16
Rs16+2 → Rs16
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
W
W
W
W
@aa:16 → Rd16
4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 6
Rs16 → @Rd16
2
4
2
MOV.W Rs, @(d:16, Rd)
MOV.W Rs, @—Rd
Rs16 → @(d:16, Rd16)
Rd16–2 → Rd16
Rs16 → @Rd16
MOV.W Rs, @aa:16
POP Rd
W
W
Rs16 → @aa:16
4
2
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 6
@SP → Rd16
SP+2 → SP
PUSH Rs
W
SP–2 → SP
2
— — ↕ ↕ 0 — 6
Rs16 → @SP
258
Table A-2 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
Mnemonic
Operation
I H N Z V C
EEPMOV
—
if R4L≠0 then
Repeat @R5 → @R6
R5+1 → R5
4 — — — — — — ➃
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W Rs, Rd
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
ADDS.W #1, Rd
ADDS.W #2, Rd
INC.B Rd
B
B
Rd8+#xx:8 → Rd8
Rd8+Rs8 → Rd8
Rd16+Rs16 → Rd16
Rd8+#xx:8 +C → Rd8
Rd8+Rs8 +C → Rd8
Rd16+1 → Rd16
Rd16+2 → Rd16
Rd8+1 → Rd8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
—
—
—
—
↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ 2
➀ ↕ ↕ ↕ ↕ 2
W
B
↕ ↕ ➁ ↕ ↕ 2
↕ ↕ ➁ ↕ ↕ 2
B
W
W
B
— — — — — — 2
— — — — — — 2
— — ↕ ↕ ↕ — 2
DAA.B Rd
B
Rd8 decimal adjust → Rd8
Rd8–Rs8 → Rd8
Rd16–Rs16 → Rd16
Rd8–#xx:8–C → Rd8
Rd8–Rs8–C → Rd8
Rd16–1 → Rd16
Rd16–2 → Rd16
Rd8–1 → Rd8
—
—
—
—
—
*
↕ ↕ * ➂ 2
↕ ↕ ↕ ↕ ↕ 2
➀ ↕ ↕ ↕ ↕ 2
SUB.B Rs, Rd
SUB.W Rs, Rd
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
SUBS.W #1, Rd
SUBS.W #2, Rd
DEC.B Rd
B
W
B
↕ ↕ ➁ ↕ ↕ 2
↕ ↕ ➁ ↕ ↕ 2
B
W
W
B
— — — — — — 2
— — — — — — 2
— — ↕ ↕ ↕ — 2
DAS.B Rd
B
Rd8 decimal adjust → Rd8
0–Rd → Rd
—
—
—
—
*
↕ ↕ * — 2
NEG.B Rd
B
↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ 2
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W Rs, Rd
B
Rd8–#xx:8
B
Rd8–Rs8
W
Rd16–Rs16
— ➀ ↕ ↕ ↕ ↕ 2
259
Table A-2 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
Mnemonic
Operation
I
H N Z V C
MULXU.B Rs, Rd
DIVXU.B Rs, Rd
B
B
Rd8 × Rs8 → Rd16
2
2
— — — — — — 14
Rd16÷Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
— — ➄ ➅ — — 14
AND.B #xx:8, Rd
AND.B Rs, Rd
OR.B #xx:8, Rd
OR.B Rs, Rd
XOR.B #xx:8, Rd
XOR.B Rs, Rd
NOT.B Rd
B
B
B
B
B
B
B
B
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
Rd → Rd
2
2
2
2
2
2
2
2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ ↕ ↕ 2
SHAL.B Rd
C
0
b7
b0
SHAR.B Rd
SHLL.B Rd
SHLR.B Rd
ROTXL.B Rd
ROTXR.B Rd
B
B
B
B
B
2
2
2
2
2
— — ↕ ↕ 0 ↕ 2
— — ↕ ↕ 0 ↕ 2
— — 0 ↕ 0 ↕ 2
— — ↕ ↕ 0 ↕ 2
— — ↕ ↕ 0 ↕ 2
C
b7
b0
C
0
b7
b0
0
C
b7
b0
C
b7
b0
b7
b0
C
260
Table A-2 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
Mnemonic
Operation
I H N Z V C
ROTL.B Rd
B
B
2
2
— — ↕ ↕ 0 ↕ 2
C
b7
b0
ROTR.B Rd
— — ↕ ↕ 0 ↕ 2
C
b7
b0
BSET #xx:3, Rd
BSET #xx:3, @Rd
BSET #xx:3, @aa:8
BSET Rn, Rd
B
B
B
B
B
B
B
B
B
B
B
B
B
(#xx:3 of Rd8) ← 1
2
4
4
2
4
4
2
4
4
2
4
4
2
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — — 2
(#xx:3 of @Rd16) ← 1
(#xx:3 of @aa:8) ← 1
(Rn8 of Rd8) ← 1
BSET Rn, @Rd
BSET Rn, @aa:8
BCLR #xx:3, Rd
BCLR #xx:3, @Rd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
(Rn8 of @Rd16) ← 1
(Rn8 of @aa:8) ← 1
(#xx:3 of Rd8) ← 0
(#xx:3 of @Rd16) ← 0
(#xx:3 of @aa:8) ← 0
(Rn8 of Rd8) ← 0
BCLR Rn, @Rd
BCLR Rn, @aa:8
BNOT #xx:3, Rd
(Rn8 of @Rd16) ← 0
(Rn8 of @aa:8) ← 0
(#xx:3 of Rd8) ←
(#xx:3 of Rd8)
BNOT #xx:3, @Rd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
B
B
B
B
B
(#xx:3 of @Rd16) ←
(#xx:3 of @Rd16)
4
— — — — — — 8
— — — — — — 8
— — — — — — 2
— — — — — — 8
— — — — — — 8
(#xx:3 of @aa:8) ←
(#xx:3 of @aa:8)
4
(Rn8 of Rd8) ←
(Rn8 of Rd8)
2
4
4
BNOT Rn, @Rd
BNOT Rn, @aa:8
(Rn8 of @Rd16) ←
(Rn8 of @Rd16)
(Rn8 of @aa:8) ←
(Rn8 of @aa:8)
261
Table A-2 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
Mnemonic
Operation
I
H N Z V C
BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
(#xx:3 of Rd8) → Z
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
— — — ↕ — — 2
— — — ↕ — — 6
— — — ↕ — — 6
— — — ↕ — — 2
— — — ↕ — — 6
— — — ↕ — — 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
(#xx:3 of @Rd16) → Z
(#xx:3 of @aa:8) → Z
(Rn8 of Rd8) → Z
BTST Rn, @Rd
BTST Rn, @aa:8
BLD #xx:3, Rd
(Rn8 of @Rd16) → Z
(Rn8 of @aa:8) → Z
(#xx:3 of Rd8) → C
BLD #xx:3, @Rd
BLD #xx:3, @aa:8
BILD #xx:3, Rd
(#xx:3 of @Rd16) → C
(#xx:3 of @aa:8) → C
(#xx:3 of Rd8) → C
BILD #xx:3, @Rd
BILD #xx:3, @aa:8
BST #xx:3, Rd
(#xx:3 of @Rd16) → C
(#xx:3 of @aa:8) → C
C → (#xx:3 of Rd8)
BST #xx:3, @Rd
BST #xx:3, @aa:8
BIST #xx:3, Rd
C → (#xx:3 of @Rd16)
C → (#xx:3 of @aa:8)
C → (#xx:3 of Rd8)
BIST #xx:3, @Rd
BIST #xx:3, @aa:8
BAND #xx:3, Rd
BAND #xx:3, @Rd
BAND #xx:3, @aa:8
BIAND #xx:3, Rd
BIAND #xx:3, @Rd
BIAND #xx:3, @aa:8
BOR #xx:3, Rd
C → (#xx:3 of @Rd16)
C → (#xx:3 of @aa:8)
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
BOR #xx:3, @Rd
BOR #xx:3, @aa:8
BIOR #xx:3, Rd
BIOR #xx:3, @Rd
262
Table A-2 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
Branching
Condition
Mnemonic
Operation
I H N Z V C
BIOR #xx:3, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
BIXOR #xx:3, Rd
BIXOR #xx:3, @Rd
BIXOR #xx:3, @aa:8
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
B
C (#xx:3 of @aa:8) → C
4
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 6
— — — — — — 8
— — — — — — 6
B
C
C
C
C
C
C
(#xx:3 of Rd8) → C
2
4
4
2
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
B
(#xx:3 of @Rd16) → C
(#xx:3 of @aa:8) → C
(#xx:3 of Rd8) → C
B
B
B
(#xx:3 of @Rd16) → C
(#xx:3 of @aa:8) → C
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PC ← PC+d:8
PC ← PC+2
If
C
C
Z = 0
Z = 1
condition
is true
then
PC ←
PC+d:8
else next;
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
C = 0
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
N
N
Z
V = 0
BLT d:8
V = 1
BGT d:8
(N V) = 0
(N V) = 1
BLE d:8
Z
JMP @Rn
PC ← Rn16
PC ← aa:16
JMP @aa:16
JMP @@aa:8
BSR d:8
PC ← @aa:8
SP–2 → SP
PC → @SP
PC ← PC+d:8
263
Table A-2 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
Mnemonic
Operation
I
H N Z V C
JSR @Rn
—
—
SP–2 → SP
PC → @SP
PC ← Rn16
2
4
2
— — — — — — 6
— — — — — — 8
— — — — — — 8
2 — — — — — — 8
JSR @aa:16
JSR @@aa:8
SP–2 → SP
PC → @SP
PC ← aa:16
SP–2 → SP
PC → @SP
PC ← @aa:8
RTS
RTE
—
—
PC ← @SP
SP+2 → SP
CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
2 ↕ ↕ ↕ ↕ ↕ ↕ 10
SLEEP
—
B
Transit to sleep mode.
#xx:8 → CCR
2 — — — — — — 2
↕ ↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ ↕ 2
— — — — — — 2
↕ ↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ ↕ 2
2 — — — — — — 2
LDC #xx:8, CCR
LDC Rs, CCR
STC CCR, Rd
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
2
2
2
2
2
2
B
Rs8 → CCR
B
CCR → Rd8
B
CCR #xx:8 → CCR
CCR #xx:8 → CCR
CCR #xx:8 → CCR
PC ← PC+2
B
B
—
Notes: ➀ Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
➁ If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0.
➂ Set to 1 if decimal adjustment produces a carry; otherwise cleared to 0.
➃ The number of states required for execution is 4n+9 (n = value of R4L).
➄ Set to 1 if the divisor is negative; otherwise cleared to 0.
➅ Set to 1 if the divisor is zero; otherwise cleared to 0.
264
Appendix B On-Chip Registers
B.1 On-Chip Registers (1)
Addr.
(Last Register
Byte) Name
Bit Names
Module
Name
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
Bit 3
STA3
EDA3
GAP2
OVR
Bit 2
STA2
EDA2
GAP1
WT
Bit 1
STA1
EDA1
PS1
Bit 0
STA0
EDA0
PS0
H'A0 STAR
H'A1 EDAR
H'A2 SCR2
H'A3 STSR
STA4
EDA4
I/O
SCI2
—
—
—
—
—
—
—
—
—
SO2
LAST
BIT
GIT
STF
H'A4
to
—
Not used
—
H'AF
H'B0 SMR1
H'B1 SDRU1
H'B2 SDRL1
H'B3 SPR1
—
SMR16 SMR15 SMR14 SMR13 SMR12 SMR11 SMR10 SCI1
SDRU17 SDRU16 SDRU15 SDRU14 SDRU13 SDRU12 SDRU11 SDRU10
SDRL17 SDRL16 SDRL15 SDRL14 SDRL13 SDRL12 SDRL11 SDRL10
SO1
LAST
BIT
—
—
—
—
—
—
—
H'B4
H'B5
H'B6
H'B7
H'B8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VFD
con-
troller/
driver
H'B9 VFSR
H'BA VFDR
H'BB DBR
H'BC AMR
H'BD ADRR
H'BE ADSR
VFLAG KSE
—
SR4
DM0
—
SR3
DR3
DBR3
—
SR2
DR2
DBR2
AMR2
ADR2
—
SR1
DR1
DBR1
AMR1
ADR1
—
SR0
DR0
DBR0
AMR0
ADR0
—
FLMO
VFDE
AMR7
ADR7
ADSF
—
DM2
DISP
—
DM1
—
A/D
con-
verter
—
—
ADR6
—
ADR5
—
ADR4
—
ADR3
—
H'BF
—
—
—
—
—
—
—
—
Notation: SCI1: Serial communication interface 1
SCI2: Serial communication interface 2
265
B.1 On-Chip Registers (1) (cont)
Addr.
(Last Register
Bit Names
Module
Name
Byte) Name
H'C0 TMA
H'C1 TCA
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
Bit 3
TMA3
TCA3
—
Bit 2
Bit 1
Bit 0
—
TMA2
TCA2
TMB2
TMA1
TCA1
TMB1
TMA0
TCA0
TMB0
Timer A
TCA7
TMB7
TCA6
—
TCA5
—
TCA4
—
H'C2 TMB
H'C3 TLB/TCB
Timer B
TLB7/
TCB7
TLB6/
TCB6
TLB5/
TCB5
TLB4/
TCB4
TLB3/
TCB3
TLB2/
TCB2
TLB1/
TCB1
TLB0/
TCB0
H'C4 TMC
TMC7
TMC6
TMC5
—
—
TMC2
TMC1
TMC0
Timer C
H'C5 TLC/TCC TLC7/
TCC7
TLC6/
TCC6
TLC5/
TCC5
TLC4/
TCC4
TLC3/
TCC3
TLC2/
TCC2
TLC1/
TCC1
TLC0/
TCC0
H'C6 TMD
H'C7 TCD
CLR
—
—
—
—
—
—
EDG
Timer D
Timer E
TCD7
TME7
TCD6
—
TCD5
—
TCD4
—
TCD3
—
TCD2
TME2
TCD1
TME1
TCD0
TME0
H'C8 TME
H'C9 TLE/TCE
TLE7/
TCE7
TLE6/
TCE6
TLE5/
TCE5
TLE4/
TCE4
TLE3/
TCE3
TLE2/
TCE2
TLE1/
TCE1
TLE0/
TCE0
H'CA
H'CB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
14-bit
PWM
H'CC PWCR
H'CD PWDRU
H'CE PWDRL
PWCR0
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
H'CF
—
—
—
—
—
—
—
—
—
I/O
ports
H'D0 PDR0
H'D1 PDR1
PDR07
—
PDR06
—
PDR05
PDR15
—
PDR04
PDR14
—
PDR03
—
PDR02
—
PDR01
PDR11
—
PDR00
PDR10
—
H'D2
H'D3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H'D4 PDR4
H'D5 PDR5
H'D6 PDR6
H'D7 PDR7
PDR47
PDR57
PDR67
PDR77
—
PDR46
PDR56
PDR66
PDR76
—
PDR45
PDR55
PDR65
PDR75
—
PDR44
PDR54
PDR64
PDR74
—
PDR43
PDR53
PDR63
PDR73
—
PDR42
PDR52
PDR62
PDR72
—
PDR41
PDR51
PDR61
PDR71
—
PDR40
PDR50
PDR60
PDR70
—
H'D8
—
H'D9 PDR9
PDR97
—
PDR96
—
PDR95
—
PDR94
—
PDR93
—
PDR92
—
PDR91
—
PDR90
—
H'DA
H'DB
H'DC
H'DD
H'DE
H'DF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
266
B.1 On-Chip Registers (1) (cont)
Addr.
(Last Register
Byte) Name
H'E0
H'E1 PCR1
Bit Names
Bit 4 Bit 3
Module
Name
Bit 7
—
Bit 6
—
Bit 5
—
Bit 2
—
Bit 1
—
Bit 0
—
I/O
—
—
—
ports
—
—
PCR15
—
PCR14
—
—
—
PCR11
—
PCR10
—
H'E2
H'E3
H'E4
H'E5
H'E6
H'E7
H'E8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H'E9 PCR9
H'EA
PCR97
—
PCR96
—
PCR95
—
PCR94
—
PCR93
—
PCR92
—
PCR91
—
PCR90
—
—
H'EB PMR1
H'EC PMR2
H'ED PMR3
NOISE
CANCEL
EVENT IRQC5
IRQC4
—
—
IRQC1
IRQC0
UP/
DOWN
SO2
SI2
CS
SCK2
—
SO1
SI1
—
SCK1
—
PWM
—
—
SO2
SO1
PMOS
PMOS
H'EE PMR4
H'EF PMR0
H'F0 SYSCR1
H'F1 SYSCR2
H'F2 IEGR
H'F3 IENR1
H'F4 IENR2
H'F5 IENR3
H'F6 IRR1
TEO
AN7
SSBY
—
TEO ON FREQ
VRFR
AN4
STS0
—
—
—
—
—
AN6
STS2
—
AN5
STS1
—
AN3
LSON
DTON
—
AN2
—
AN1
—
AN0
—
System
control
—
—
—
—
—
—
IEG4
IEN4
IENTE
—
—
IEG1
IEN1
IENTB
IENS2
IRRI1
IRRTB
IRRS2
—
IEG0
IEN0
IENTA
IENS1
IRRI0
IRRTA
IRRS1
—
—
—
IEN5
IENDT
—
—
—
—
—
IENTD
—
IENTC
—
IENAD
—
IENKS
—
IRRI5
IRRDT
—
IRRI4
IRRTE
—
—
—
H'F7 IRR2
—
—
IRRTD
—
IRRTC
—
H'F8 IRR3
IRRAD
—
IRRKS
—
H'F9
H'FA
H'FB
H'FC
H'FD
H'FE
H'FF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
267
B.2 On-Chip Registers (2)
Register
acronym
Register
name
Address to which
register is mapped
Name of on-chip
peripheral
module
DBR—Digit Beginning Register
H'BB
VFD Controller
Bit
numbers
Bit
7
VFDE
0
6
DISP
0
5
—
0
4
—
3
DBR3
0
2
DBR2
0
1
0
Initial bit
values
DBR1
0
DBR0
0
Initial value
Read/Write
0
Bit names
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
and positions.
Dashes (—)
indicate
Segment Pin Select
reserved bits.
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
*
0 0 FD0 to FD7
0 1 FD1 to FD7, FS7
Possible types of access
1 0 FD2 to FD7, FS7 to FS6
1 1 FD3 to FD7, FS7 to FS5
0 0 FD4 to FD7, FS7 to FS4
0 1 FD5 to FD7, FS7 to FS3
1 0 FD6 to FD7, FS7 to FS2
1 1 FD to FD7, FS7 to FS1
R
Read only
Write only
Full name
of bit
W
R/W Read and write
Bit settings
and
FS7to FS0
*
*
descriptions
Note: * Don’t care.
Display Bit
0
All segment pins are in non-illuminating
state (pull-down state).
Digit pins continue operating.
Register and RAM values are unchanged.
1
Display RAM contents are output to
segment pins.
268
STAR—Start Address Register
H'A0
SCI2
Bit
7
—
1
6
—
1
5
—
1
4
STA4
0
3
STA3
0
2
1
STA1
0
0
STA0
0
STA2
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Designates transfer starting address
in range from H'FF80 to H'FF9F.
EDAR—End Address Register
H'A1
SCI2
Bit
7
—
1
6
—
1
5
—
1
4
EDA4
0
3
EDA3
0
2
EDA2
0
1
EDA1
0
0
EDA0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Designates transfer end address
in range from H'FF80 to H'FF9F.
SCR2—Serial Control Register
H'A2
SCI2
Bit
7
—
1
6
—
1
5
—
1
4
I/O
0
3
GAP2
0
2
GAP1
0
1
0
PS1
0
PS0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Transmit/Receive Select
Gap Select
0 Receive mode
1 Transmit mode
0 0 No gap insertion
0 1 1-clock gap insertion
1 0 2-clock gap insertion
1 1 8-clock gap insertion
Serial Clock Select
φ
0 0 /2, SCK2 is output pin
φ
0 1 /4, SCK2 is output pin
φ
1 0 /8, SCK2 is output pin
1 1 External clock, SCK2 is input pin
269
STSR—Status Register
H'A3
SCI2
Bit
7
—
1
6
—
1
5
—
1
4
3
2
1
GIT
0
0
SO2 LAST
OVR
WT
0
STF
0
BIT
Initial value
Read/Write
0
Not fixed
R/W*
—
—
—
R/W
R/W*
R/W
R/W
Extended Data Bit
0 Pin SO2 output low
1 Pin SO2 output high
Waiting Flag
[Clear condition] When STSR is written
0
1
[Set condition] When 32-byte data
buffer is read or written during transfer
Overrun Flag
Gap Interval Flag
0 [Clear condition] When STSR is written
1 [Set condition] When overrun occurs
0 Insert gap every 16 bits
1 Insert gap every 8 bits
Start/Busy Flag
0 [Read] Transfer stopped
[Write] Transfer aborted
[Read] Transfer in progress
[Write] Starts transfer
1
Note: * Cleared to 0 by a write access to STSR.
270
SMR1—Serial Mode Register 1
H'B0
SCI1
Bit
7
—
1
6
5
4
3
2
1
0
SMR16 SMR15 SMR14 SMR13 SMR12 SMR11 SMR10
Initial value
Read/Write
0
0
0
0
0
0
0
—
W
W
W
W
W
W
W
Operation Mode Select
Clock Select
φ
0 0 0 0 /1024, SCK1is output pin
0
0
0
Clock continuous output mode
8-bit transfer mode
φ
1
/256, SCK1is output pin
Not 00
φ
1 0 /64, SCK1is output pin
1
0
0
Clock continuous output mode
16-bit transfer mode
φ
1
/32, SCK1is output pin
Not 00
φ
1 0 0 /16, SCK1is output pin
φ
1
/8, SCK1is output pin
φ
1 0 /4, SCK1is output pin
φ
1
/2, SCK1is output pin
1 0 0 0
Not used
Not used
Not used
Not used
Not used
Not used
Not used
1
1 0
1
1 0 0
1
1 0
1
External clock, SCK1 is input pin
SDRU1—Serial Data Register U1
H'B1
SCI1
Bit
7
6
5
4
3
2
1
0
SDRU17 SDRU16 SDRU15 SDRU14 SDRU13 SDRU12 SDRU11 SDRU10
Initial value
Read/Write
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Used to set transmit data and store received data.
8-bit transfer mode: not used
16-bit transfer mode: upper 8-bits of data register
Note: * Not fixed
271
SDRL1—Serial Data Register L1
H'B2
SCI1
Bit
7
6
5
4
3
2
1
0
SDRL17 SDRL16 SDRL15 SDRL14 SDRL13 SDRL12 SDRL11 SDRL10
Initial value
Read/Write
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Used to set transmit data and store received data.
8-bit transfer mode: data register
16-bit transfer mode: lower 8-bits of data register
Note: * Not fixed
SPR1—Serial Port Register 1
H'B3
SCI1
Bit
7
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
SO1 LAST
BIT
Initial value
Read/Write
*
R/W
—
—
—
—
—
—
—
Extended Data Bit
0 Pin SO1output low
0 Pin SO1output high
Note: * Not fixed
272
VFSR—VFD Segment Control Register
H'B9
VFD Controller/Driver
Bit
7
VFLAG
0
6
5
—
1
4
3
2
1
0
KSE
0
SR4
0
SR3
0
SR2
0
SR1
0
SR0
0
Initial value
Read/Write
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
Segment Pin Select
0 0 0 0 0 FS0
1 0 0 0 0 FS0 to FS16
Key Scan Enable
0 0 0 0 1 FS0 to FS1 1 0 0 0 1 FS0 to FS17
0 0 0 1 0 FS0 to FS2 1 0 0 1 0 FS0 to FS18
0 0 0 1 1 FS0 to FS3 1 0 0 1 1 FS0 to FS19
0 0 1 0 0 FS0 to FS4 1 0 1 0 0 FS0 to FS20
0 0 1 0 1 FS0 to FS5 1 0 1 0 1 FS0 to FS21
0 0 1 1 0 FS0 to FS6 1 0 1 1 0 FS0 to FS22
0 0 1 1 1 FS0 to FS7 1 0 1 1 1 FS0 to FS23
0 1 0 0 0 FS0 to FS8 1 1 0 0 0
0 No key scan interval
1 Key scan interval added
0 1 0 0 1 FS0 to FS9 1 1 0 0 1
0 1 0 1 0 FS0 to FS10 1 1 0 1 0
0 1 0 1 1 FS0 to FS11 1 1 0 1 1
0 1 1 0 0 FS0 to FS12 1 1 1 0 0
0 1 1 0 1 FS0 to FS13 1 1 1 0 1
0 1 1 1 0 FS0 to FS14 1 1 1 1 0
0 1 1 1 1 FS0 to FS15 1 1 1 1 1
VFD/Port Switching Flag
0 All pins doubling as general-purpose ports and VFD pins are used
as general-purpose ports.
1 Pins designated as digit or segment pins function as VFD pins.
273
VFDR—VFD Digit Control Register
H'BA
VFD Controller/Driver
Bit
7
FLMO
0
6
5
4
3
2
1
0
DM2
0
DM1
0
DM0
0
DR3
0
DR2
0
DR1
0
DR0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Digit Pin Select
0 0 0 0 FD0 to FD15 1 0 0 0 FD0 to FD7
0 0 0 1 FD0 to FD14 1 0 0 1 FD0 to FD6
0 0 1 0 FD0 to FD13 1 0 1 0 FD0 to FD5
0 0 1 1 FD0 to FD12 1 0 1 1 FD0 to FD4
0 1 0 0 FD0 to FD11 1 1 0 0 FD0 to FD3
0 1 0 1 FD0 to FD10 1 1 0 1 FD0 to FD2
0 1 1 0 FD0 to FD9 1 1 1 0 FD0 to FD1
0 1 1 1 FD0 to FD8 1 1 1 1 FD0
Digit Waveform Select
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Tdigit
Tdimmer
VFD Mode Bit
φ
φ
0 T digit = 1536/ , Tdimmer = 96/
φ
φ
1 T digit = 768/ , Tdimmer = 48/
274
DBR—Digit Beginning Register
H'BB
VFD Controller/Driver
Bit
7
VFDE
0
6
DISP
0
5
—
1
4
—
3
DBR3
0
2
1
DBR1
0
0
DBR0
0
DBR2
0
Initial value
Read/Write
0
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
Digit/Segment Pin Function Select
0 0 0 0 FD0 to FD7
0 0 0 1 FD1 to FD7, FS7
0 0 1 0 FD2 to FD7, FS7 to FS6
0 0 1 1 FD3 to FD7, FS7 to FS5
0 1 0 0 FD4 to FD7, FS7 to FS4
0 1 0 1 FD5 to FD7, FS7 to FS3
0 1 1 0 FD6 to FD7, FS7 to FS2
0 1 1 1
FD7, FS7 to FS1
FS7to FS0
1
* * *
Note: * Don’t care.
Display Bit
0 All segment pins are in non-illuminating
state (pulled down).
Digit pins continue operating.
Register and RAM values are unchanged.
1 Display RAM contents are output to
segment pins.
VFD Enable
0 VFD controller/driver is in reset state.
1 VFD controller/driver is in active state.
275
AMR—A/D Mode Register
H'BC
A/D Converter
Bit
7
AMR7
0
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
AMR2
0
AMR1
0
AMR0
0
Initial value
Read/Write
R/W
—
—
—
—
R/W
R/W
R/W
Channel Select
Clock Select
φ
φ
0 0 0 Analog input pin is AN0
1 Analog input pin is AN1
1 0 Analog input pin is AN2
1 Analog input pin is AN3
1 0 0 Analog input pin is AN4
1 Analog input pin is AN5
1 0 Analog input pin is AN6
1 Analog input pin is AN7
0 Conversion period is 62/
1 Conversion period is 31/
ADRR—A/D Result Register
H'BD
A/D Converter
Bit
7
ADR7
*
6
ADR6
*
5
ADR5
*
4
ADR4
*
3
ADR3
*
2
ADR2
*
1
0
ADR1
ADR0
Initial value
Read/Write
*
*
R
R
R
R
R
R
R
R
A/D Conversion Result
Note: * Not fixed
276
ADSR—A/D Start Register
H'BE
A/D Converter
Bit
7
ADSF
0
6
—
1
5
—
1
4
—
1
3
—
1
2
1
—
1
0
—
1
—
1
Initial value
Read/Write
R/W
—
—
—
—
—
—
—
A/D Start Flag
0 [Read] A/D conversion stopped or complete
[Write] A/D conversion aborted
[Read] A/D conversion in progress
[Write] Starts A/D conversion
1
TMA—Timer Mode Register A
H'C0
Timer A
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
TMA3
0
2
1
0
TMA2
0
TMA1
0
TMA0
0
Initial value
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Clock Select
0 0 0 0 Input source PSS, /8192
φ
φ
1 Input source PSS, /4096
φ
1 0 Input source PSS, /2048
φ
1 Input source PSS, /512
φ
1 0 0 Input source PSS, /256
φ
1 Input source PSS, /128
φ
1 0 Input source PSS, /32
φ
1 Input source PSS, /8
1 0 0 0
Input source PSW, 2 s
Input source PSW, 1 s
Input source PSW, 0.5 s
Input source PSW, 125 ms
PSW and TCA reset
1
1 0
1
1 0 0
1
1 0
1
277
TCA—Timer Counter A
H'C1
Timer A
Bit
7
TCA7
0
6
TCA6
0
5
TCA5
0
4
TCA4
0
3
TCA3
0
2
1
TCA1
0
0
TCA2
TCA0
Initial value
Read/Write
0
0
R
R
R
R
R
R
R
R
Count Value
TMB—Timer Mode Register B
H'C2
Timer B
Bit
7
TMB7
0
6
—
1
5
—
1
4
—
1
3
—
1
2
TMB2
0
1
TMB1
0
0
TMB0
Initial value
Read/Write
0
R/W
—
—
—
—
R/W
R/W
R/W
Clock Select
0 0 0 Internal clock, /8192
φ
φ
1 Internal clock, /2048
φ
1 0 Internal clock, /512
φ
1 Internal clock, /256
φ
1 0 0 Internal clock, /128
φ
1 Internal clock, /32
φ
1 0 Internal clock, /8
1 External clock, choice of rising or falling edge
Auto Reload Function Select
0 Free-running timer
1 Auto-reload timer
278
TCB—Timer Counter B
H'C3
Timer B
Bit
7
TCB7
0
6
TCB6
0
5
TCB5
0
4
TCB4
0
3
TCB3
0
2
1
TCB1
0
0
TCB2
TCB0
Initial value
Read/Write
0
0
R
R
R
R
R
R
R
R
Count Value
TLB—Timer Load Register B
H'C3
Timer B
Bit
7
TLB7
0
6
TLB6
0
5
TLB5
0
4
TLB4
0
3
TLB3
0
2
TLB2
0
1
TLB1
0
0
TLB0
Initial value
Read/Write
0
W
W
W
W
W
W
W
W
Reload Value Setting
279
TMC—Timer Mode Register C
H'C4
Timer C
Bit
7
TMC7
0
6
TMC6
0
5
TMC5
0
4
—
1
3
—
1
2
1
TMC1
0
0
TMC2
0
TMC0
Initial value
Read/Write
0
R/W
R/W
R/W
—
—
R/W
R/W
R/W
Clock Select
0 0 0 Internal clock, /8192
φ
φ
1 Internal clock, /2048
φ
1 0 Internal clock, /512
φ
1 Internal clock, /256
φ
1 0 0 Internal clock, /128
φ
1 Internal clock, /32
φ
1 0 Internal clock, /8
1 External clock, choice of rising or falling edge
Count-Up/Down Control
0 0 Up-counter
1
Down-counter
1
Hardware control via pin P97/UD. High is down, low is up.
*
Note: * Don’t care.
Auto-Reload Function Select
0 Free-running timer
1 Auto-reload timer
TCC—Timer Counter C
H'C5
Timer C
Bit
7
TCC7
0
6
TCC6
0
5
TCC5
0
4
TCC4
0
3
TCC3
0
2
1
TCC1
0
0
TCC2
TCC0
Initial value
Read/Write
0
0
R
R
R
R
R
R
R
R
Count Value
280
TLC—Timer Load Register C
H'C5
Timer C
Bit
7
TLC7
0
6
TLC6
0
5
TLC5
0
4
TLC4
0
3
TLC3
0
2
1
TLC1
0
0
TLC2
0
TLC0
Initial value
Read/Write
0
W
W
W
W
W
W
W
W
Reload Value Setting
TMD—Timer Mode Register D
H'C6
Timer D
Bit
7
CLR
0
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
EDG
Initial value
Read/Write
0
W
—
—
—
—
—
—
R/W
Edge Select
0 Incremented at falling edge of EVENT pin input
1 Incremented at rising edge of EVENT pin input
Counter Clear
0 After this bit is set to 1 and TCD is initialized, it is automatically cleared by hardware.
1 TCD is initialized to H'00.
TCD—Timer Counter D
H'C7
Timer D
Bit
7
TCD7
0
6
TCD6
0
5
TCD5
0
4
TCD4
0
3
TCD3
0
2
1
TCD1
0
0
TCD0
0
TCD2
Initial value
Read/Write
0
R
R
R
R
R
R
R
R
Count Value
281
TME—Timer Mode Register E
H'C8
Timer E
Bit
7
TME7
0
6
—
1
5
—
1
4
—
1
3
—
1
2
1
TME1
0
0
TME2
0
TME0
Initial value
Read/Write
0
R/W
—
—
—
—
R/W
R/W
R/W
Clock Select
0 0 0 Internal clock, /8192
Auto-Reload Function Select
φ
0 Free-running timer
1 Auto-reload timer
φ
1 Internal clock, /4096
φ
1 0 Internal clock, /2048
φ
1 Internal clock, /512
φ
1 0 0 Internal clock, /256
φ
1 Internal clock, /128
φ
1 0 Internal clock, /32
φ
1 Internal clock, /8
TCE—Timer Counter E
H'C9
Timer E
Bit
7
TCE7
0
6
TCE6
0
5
TCE5
0
4
TCE4
0
3
TCE3
0
2
TCE2
0
1
TCE1
0
0
TCE0
0
Initial value
Read/Write
R
R
R
R
R
R
R
R
Count Value
TLE—Timer Load Register E
H'C9
Timer E
Bit
7
TLE7
0
6
TLE6
0
5
TLE5
0
4
TLE4
0
3
TLE3
0
2
TLE2
0
1
TLE1
0
0
TLE0
0
Initial value
Read/Write
W
W
W
W
W
W
W
W
Reload Value Setting
282
PWCR—PWM Control Register
H'CC
14-bit PWM
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
—
1
0
—
1
PWCR0
Initial value
Read/Write
0
—
—
—
—
—
—
—
W
Clock Select
φ
0 The input clock is /2. The conversion period is
φ
φ
16384/ , with a minimum modulation width of 1/ .
φ
1 The input clock is /4. The conversion period is
φ
φ
32768/ , with a minimum modulation width of 2/ .
PWDRU—PWM Data Register U
H'CD
14-bit PWM
Bit
7
—
1
6
—
1
5
4
3
2
1
0
PWDRU5PWDRU4PWDRU3PWDRU2 PWDRU1PWDRU0
Initial value
Read/Write
0
0
0
0
0
0
—
—
W
W
W
W
W
W
Upper 6 Bits of Data for PWM Waveform Generation
PWDRL—PWM Data Register L
H'CE
14-bit PWM
Bit
7
6
5
4
3
2
1
0
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Lower 8 Bits of Data for PWM Waveform Generation
283
PDR0—Port Data Register 0
H'D0
I/O Ports
Bit
7
6
5
4
3
2
1
0
PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00
Initial value
Read/Write
—
R
—
R
—
R
—
R
—
R
—
R
—
R
—
R
PDR1—Port Data Register 1
H'D1
I/O Ports
Bit
7
6
5
4
3
—
1
2
1
0
—
—
—
—
—
—
PDR15 PDR14
—
1
PDR11 PDR10
Initial value
Read/Write
0
0
0
0
*
*
R/W
R/W
—
—
R/W
R/W
Note: * Pins P16 and P17 are input-only pins; whenever they are read, the pin level is read out.
PDR4—Port Data Register 4
H'D4
I/O Ports
Bit
7
6
5
4
3
2
1
0
PDR47 PDR46 PDR45 PDR44 PDR43 PDR42 PDR41 PDR40
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR5—Port Data Register 5
H'D5
I/O Ports
Bit
7
6
5
4
3
2
1
0
PDR57 PDR56 PDR55 PDR54 PDR53 PDR52 PDR51 PDR50
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR6—Port Data Register 6
H'D6
I/O Ports
Bit
7
6
5
4
3
2
1
0
PDR67 PDR66 PDR65 PDR64 PDR63 PDR62 PDR61 PDR60
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
284
PDR7—Port Data Register 7
H'D7
I/O Ports
Bit
7
6
5
4
3
2
1
0
PDR77 PDR76 PDR75 PDR74 PDR73 PDR72 PDR71 PDR70
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR9—Port Data Register 9
H'D9
I/O Ports
Bit
7
6
5
4
3
2
1
0
PDR97 PDR96 PDR95 PDR94 PDR93 PDR92 PDR91 PDR90
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCR1—Port Control Register 1
H'E1
I/O Ports
Bit
7
—
1
6
—
1
5
4
3
—
1
2
—
1
1
0
PCR15 PCR14
PCR11 PCR10
Initial value
Read/Write
0
0
0
0
—
—
W
W
—
—
W
W
Port 1 I/O Select
0 Input port
1 Output port
PCR9—Port Control Register 9
H'E9
I/O Ports
Bit
7
6
5
4
3
2
1
0
PCR97 PCR96 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 9 I/O Select
0 Input port
1 Output port
285
PMR1—Port Mode Register 1
H'EB
I/O Ports
Bit
7
6
5
4
3
—
1
2
—
1
1
0
NOISE
CANCEL
EVENT IRQC5 IRQC4
IRQC1 IRQC0
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
—
—
R/W
R/W
P1 /IRQ0Pin Function
Switch
P1 /EVENT Pin Function
Switch
0
6
0 P10 pin function
1 IRQ0pin function
0 P16 pin function
1 EVENT pin function
P11/IRQ1 Pin Function
Switch
Noise Cancel
0 IRQ0pin noise cancel
function off
0 P11 pin function
1 IRQ1pin function
1 IRQ0pin noise cancel
function on
P1 /IRQ4 Pin Function Switch
4
0 P14 pin function
1 IRQ4pin function
P1 /IRQ5 /TMOE Pin Function Switch
5
0 P15/TMOE pin function*
1 IRQ5pin function
Note: * For the switching between P15 and TMOE pin functions see under PMR4.
286
PMR2—Port Mode Register 2
H'EC
I/O Ports
Bit
7
6
5
SI2
0
4
SCK2
0
3
2
1
SCK1
0
0
PWM
0
UP/
DOWN
SO2
0
SO1
0
SI1
0
Initial value
Read/Write
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P90/PWM Pin Function
Switch
P96/SO2Pin Function
Switch
0 P90 pin function
1 PWM pin function
0 P96 pin function
1 SO2 pin function
P91/SCK1Pin Function
Switch
P97/UD Pin Function Switch
0 P91 pin function
0 P97 pin function
1 UD pin function
1 SCK1pin function
P92/SI1pin function switch
0 P92 pin function
1 SI1pin function
P93/SO1Pin Function Switch
0 P93 pin function
1 SO1 pin function
P94/SCK2 Pin Function Switch
0 P94 pin function
1 SCK2pin function
P95/SI1/CS Pin Function Switch
0 P95 pin function
1 SI 1/CS pin function*
Note: * For the switching between SI1 and CS pin functions see under PMR3.
287
PMR3—Port Mode Register 3
H'ED
I/O Ports
Bit
7
—
1
6
5
CS
0
4
—
1
3
2
1
—
1
0
—
1
SO2
PMOS
SO1
PMOS
—
1
Initial value
Read/Write
0
0
—
R/W
R/W
—
R/W
—
—
—
SO1Pin PMOS On/Off
0 SO1 pin PMOS buffer on. CMOS output.
1 SO1 pin PMOS off. NMOS open-drain output.
Chip Select Output Select
PMR2 PMR3
SI2
CS P95/SI2/CS pin function switch
0
0
1
0
1
P95 pin function
1
SI2 pin function
CS pin function
SO2Pin PMOS On/Off
0 SO2 pin PMOS buffer on. CMOS output.
1 SO2 pin PMOS off. NMOS open-drain output.
288
PMR4—Port Mode Register 4
H'EE
I/O Ports
Bit
7
6
5
4
VRFR
0
3
—
1
2
1
—
1
0
—
1
TEO
0
TEO ON FREQ
—
1
Initial value
Read/Write
0
0
R/W
R/W
R/W
R/W
—
—
—
—
Timer E Output Control
PMR1 PMR4
IRQC5 TEO TEO ON FREQ VRFR
P15 /IRQ5/TMOE Pin
Function Switch
Pin Status
0
0
0
0
0
0
1
1
1
1
*
0
1
1
1
*
*
0
1
*
*
*
0
0
1
P15 pin function
Standard I/O port
TMOE pin function (off) Low-level output
TMOE pin function (on) Fixed-frequency output: /2048
φ
φ
TMOE pin function (on) Fixed-frequency output: /1024
TMOE pin function (on) Variable-frequency output:
output toggles at each timer E
overflow
1
*
*
*
*
IRQ5 pin function
External interrupt input
Note: * Don’t care.
PMR0—Port Mode Register 0
H'EF
I/O Ports
Bit
7
AN7
0
6
AN6
0
5
4
AN4
0
3
2
1
AN1
0
0
AN0
0
AN5
0
AN3
0
AN2
0
Initial value
Read/Write
W
W
W
W
W
W
W
W
Analog Input Select
0 General-purpose input port
1 Analog input channel
289
SYSCR1—System Control Register 1
H'F0
System Control
Bit
7
6
STS2
0
5
STS1
0
4
STS0
0
3
LSON
0
2
—
0
1
—
0
0
—
0
SSBY
Initial value
Read/Write
0
R/W*1
R/W
R/W
R/W
R/W
R/W
—
—
*2
Low-Speed On Flag
0 CPU runs on system clock ( )
φ
φ
1 CPU runs on subclock (
)
SUB
Standby Timer Select
0 0 0
0 0 1
0 1 0
0 1 1
1 *3 *3
Wait time = 8192 states
Wait time = 16384 states
Wait time = 32768 states
Wait time = 65536 states
Wait time = 131072 states
Standby
0 Sleep mode entered after SLEEP instruction is executed.
1 Standby mode entered after SLEEP instruction is executed.
Notes: 1. Write is enabled in active mode only.
2. This relates to the transitions between operation modes, so functioning depends on the
combination of this bit with other control bits and interrupts. For details see 3.3, System
Modes.
3. Don’t care.
SYSCR2—System Control Register 2
H'F1
System Control
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
DTON
0
2
—
1
1
—
0
0
—
0
Initial value
Read/Write
—
—
—
—
W*
—
R/W
R/W
Direct Transfer On Flag
0 In subactive mode, watch mode is entered when a SLEEP
instruction is executed.
1 In subactive mode, if LSON bit = 0, active mode is entered
via watch mode when a SLEEP instruction is executed.
Note: * Write is enabled in subactive mode only.
290
IEGR—IRQ Edge Select Register
H'F2
System Control
Bit
7
—
1
6
—
1
5
—
1
4
IEG4
0
3
—
1
2
—
1
1
0
IEG1
0
IEG0
0
Initial value
Read/Write
—
—
—
R/W
—
—
R/W
R/W
IRQ4Input Edge Select
IRQ0Input Edge Select
0 Rising edge detected.
1 Falling edge detected.
0 Rising edge detected.
1 Falling edge detected.
IRQ1Input Edge Select
0 Rising edge detected.
1 Falling edge detected.
IENR1—Interrupt Enable Register 1
H'F3
System Control
Bit
7
—
1
6
—
1
5
IEN5
0
4
IEN4
0
3
—
2
—
1
0
IEN1
0
IEN0
0
Initial value
Read/Write
0
0
—
—
R/W
R/W
R/W
R/W
R/W
R/W
IRQ5 Interrupt Enable
IRQ0 Interrupt Enable
0 Interrupts disabled.
1 Interrupts enabled.
0 Interrupts disabled.
1 Interrupts enabled.
IRQ4 Interrupt Enable
IRQ1 Interrupt Enable
0 Interrupts disabled.
1 Interrupts enabled.
0 Interrupts disabled.
1 Interrupts enabled.
291
IENR2—Interrupt Enable Register 2
H'F4
System Control
Bit
7
—
6
—
5
4
3
2
1
0
IENDT IENTE IENTD IENTC
IENTB IENTA
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTON Interrupt Enable
Timer A Interrupt Enable
0 Interrupts disabled.
1 Interrupts enabled.
0 Interrupts disabled.
1 Interrupts enabled.
Timer E Interrupt Enable
Timer B Interrupt Enable
0 Interrupts disabled.
1 Interrupts enabled.
0 Interrupts disabled.
1 Interrupts enabled.
Timer D Interrupt Enable
Timer C Interrupt Enable
0 Interrupts disabled.
1 Interrupts enabled.
0 Interrupts disabled.
1 Interrupts enabled.
IENR3—Interrupt Enable Register 3
H'F5
System Control
Bit
7
IENAD
0
6
IENKS
0
5
—
1
4
—
1
3
—
1
2
—
1
1
0
IENS2 IENS1
Initial value
Read/Write
0
0
R/W
R/W
—
—
—
—
R/W
R/W
Key Scan Interrupt Enable
SCI1 Interrupt Enable
0 Interrupts disabled.
1 Interrupts enabled.
0 Interrupts disabled.
1 Interrupts enabled.
A/D Conversion Complete Interrupt Enable
SCI2 Interrupt Enable
0 Interrupts disabled.
1 Interrupts enabled.
0 Interrupts disabled.
1 Interrupts enabled.
292
IRR1—Interrupt Request Register 1
H'F6
System Control
Bit
7
—
1
6
—
1
5
4
3
—
0
2
—
0
1
0
IRRI5
0
IRRI4
0
IRRI1
0
IRRI0
0
Initial value
Read/Write
—
—
R/W*
R/W*
—
—
R/W*
R/W*
IRQ5 Interrupt Request
IRQ0 Interrupt Request
0 No interrupt request
0 No interrupt request
1 Interrupt request raised
1 Interrupt request raised
IRQ4 Interrupt Request
IRQ1 Interrupt Request
0 No interrupt request
0 No interrupt request
1 Interrupt request raised
1 Interrupt request raised
Note: * Only 0 can be written, to clear the flag.
293
IRR2—Interrupt Request Register 2
H'F7
System Control
Bit
7
—
0
6
—
0
5
4
3
2
1
0
IRRDT IRRTE IRRTD IRRTC IRRTB IRRTA
Initial value
Read/Write
0
0
0
0
0
0
—
—
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
DTON Interrupt Request
Timer A Interrupt Request
0 No interrupt request
1 Interrupt request
0 No interrupt request
1 Interrupt request
Timer E Interrupt Request
Timer B Interrupt Request
0 No interrupt request
1 Interrupt request
0 No interrupt request
1 Interrupt request
Timer D Interrupt Request
Timer C Interrupt Request
0 No interrupt request
1 Interrupt request
0 No interrupt request
1 Interrupt request
Note: * Only 0 can be written, to clear the flag.
IRR3—Interrupt Request Register 3
H'F8
System Control
Bit
7
6
5
—
1
4
—
1
3
—
1
2
—
1
1
0
IRRAD IRRKS
IRRS2 IRRS1
Initial value
Read/Write
0
0
0
0
R/W*
R/W*
—
—
—
—
R/W*
R/W*
Key Scan Interrupt Request
SCI1 Interrupt Request
0 No interrupt request
1 Interrupt request
0 No interrupt request
1 Interrupt request
A/D Conversion Complete Interrupt Request
SCI2 Interrupt Request
0 No interrupt request
1 Interrupt request
0 No interrupt request
1 Interrupt request
Note: * Only 0 can be written, to clear the flag.
294
Appendix C I/O Port Block Diagrams
C.1 Port 0 Block Diagram
PMR0
(bit n)
Internal
data bus
P0n
A/D converter
VIN
SEL
PMR0: Port mode register 0
n = 0 to 7
Figure C-1 Port 0 Block Diagram
295
C.2 Port 1 Block Diagram
STBY
VCC
VCC
Option
PDR1
(bit n)
P1n
PMR1
(bit n)
Internal
data bus
PCR1
(bit n)
VSS
IRQ
P10: IRQ0
P11: IRQ1
P14: IRQ4
PDR1: Port data register 1
PMR1: Port mode register 1
PCR1: Port control register 1
n = 0, 1, 4
Figure C-2 (a) Port 1 Block Diagram (Pins P1 , P1 , and P1 )
0
1
4
296
STBY
Timer E
VCC
VCC
TMOE
TEO
Option
PDR1
(bit 5)
P15
PMR1
(bit 5)
Internal
data bus
PCR1
(bit 5)
VSS
IRQ5
PDR1: Port data register 1
PMR1: Port mode register 1
PCR1: Port control register 1
TEO: Port mode register 4, bit 7
TMOE: Square wave output
Figure C-2 (b) Port 1 Block Diagram (Pin P1 )
5
297
STBY
Option
PDR1
(bit 6)
Internal
data bus
P16
Timer D
EVENT
EDG
(edge select)
PMR1: Port mode register 1
Figure C-2 (c) Port 1 Block Diagram (Pin P1 )
6
Internal
data bus
Option
P17
VSS
Vdisp
Figure C-2 (d) Port 1 Block Diagram (Pin P1 )
7
298
C.3 Port 4 Block Diagram
VFD controller/
driver
STBY
SR4 to SR0
Decoder
SGDL
VFLAG
LTCLK
VCC
RAM
DATA
P4n
PDR4
(bit n)
Internal
data bus
Option
Vdisp
PDR4: Port data register 4
SGDL: Segment data latch
LTCLK: Segment data latch clock
SR4 to SR0: VFD segment control register bits 4 to 0
VFLAG: VFD segment control register bit 7
n = 0 to 7
Figure C-3 Port 4 Block Diagram
299
C.4 Port 5 Block Diagram
VFD controller/
driver
STBY
SR4 to SR0
Decoder
SGDL
VFLAG
LTCLK
VCC
RAM
DATA
P5n
PDR5
(bit n)
Internal
data bus
Option
Vdisp
PDR5: Port data register 5
SGDL: Segment data latch
LTCLK: Segment data latch clock
SR4 to SR0: VFD segment control register bits 4 to 0
VFLAG: VFD segment control register bit 7
n = 0 to 7
Figure C-4 Port 5 Block Diagram
300
C.5 Port 6 Block Diagram
VFD controller/
driver
FD
STBY
DBR3 to DBR0
DR3 to DR0
Decoder
SGDL
VCC
SR4 to SR0
VFLAG
LTCLK
RAM
DATA
P6n
PDR6
(bit n)
Option
Internal
data bus
Vdisp
PDR6: Port data register 6
SGDL: Segment data latch
LTCLK: Segment data latch clock
FD: Digit output waveform
DBR3 to DBR0: Digit beginning register bits 3 to 0
DR3 to DR0: VFD digit control register bits 3 to 0
SR4 to SR0: VFD segment control register bits 4 to 0
VFLAG: VFD segment control register bit 7
n = 0 to 7
Figure C-5 Port 6 Block Diagram
301
C.6 Port 7 Block Diagram
VFD controller/
driver
STBY
FD
DR3 to DR0
VFLAG
Decoder
VCC
PDR7
(bit n)
P7n
Internal
data bus
Option
Vdisp
PDR7: Port data register 7
FD: Digit output waveform
DR3 to DR0: VFD digit control register bits 3 to 0
VFLAG: VFD segment control register bit 7
n = 0 to 7
Figure C-6 Port 7 Block Diagram
302
C.7 Port 9 Block Diagram
STBY
VCC
VCC
PWM
PWM
Option
P90
PDR9
(bit 0)
PMR2
(bit 0)
Internal
data bus
PCR9
(bit 0)
VSS
PDR9: Port data register 9
PMR2: Port mode register 2
PCR9: Port control register 9
Figure C-7 (a) Port 9 Block Diagram (Pin P9 )
0
303
STBY
SCI
EXCK
VCC
VCC
SCKO
SCKi
Option
PDR9
(bit n)
P9n
PMR2
(bit n)
Internal
data bus
PCR9
(bit n)
VSS
PDR9: Port data register 9
PMR2: Port mode register 2
PCR9: Port control register 9
n = 1 and 4
Figure C-7 (b) Port 9 Block Diagram (Pins P9 and P9 )
1
4
304
STBY
VCC
VCC
Option
PDR9
(bit 2)
P92
PMR2
(bit 2)
Internal
data bus
PCR9
(bit 2)
VSS
SCI
SI
PDR9: Port data register 9
PMR2: Port mode register 2
PCR9: Port control register 9
Figure C-7 (c) Port 9 Block Diagram (Pin P9 )
2
305
STBY
PMR3
P93: bit 3
P96: bit 6
VCC
VCC
SCI
SO
Option
PDR9
(bit n)
P9n
PMR2
(bit n)
Internal
data bus
PCR9
(bit n)
VSS
PDR9: Port data register 9
PMR2: Port mode register 2
PCR9: Port control register 9
n = 3 and 6
Figure C-7 (d) Port 9 Block Diagram (Pins P9 and P9 )
3
6
306
STBY
PMR3
(bit 5)
VCC
VCC
SCI
CS
SI
Option
PDR9
(bit 5)
P95
PMR2
(bit 5)
Internal
data bus
PCR9
(bit 5)
VSS
PDR9: Port data register 9
PMR2: Port mode register 2
PCR9: Port control register 9
Figure C-7 (e) Port 9 Block Diagram (Pin P9 )
5
307
STBY
VCC
VCC
Option
PDR9
(bit 7)
P97
PMR2
(bit 7)
Internal
data bus
PCR9
(bit 7)
VSS
Timer C
UD
PDR9: Port data register 9
PMR2: Port mode register 2
PCR9: Port control register 9
Figure C-7 (f) Port 9 Block Diagram (Pin P9 )
7
308
Appendix D Port States in Each Processing State
Table D-1 Port States
Mode
Watch
Port Pins
Reset
Sleep
Standby
Subactive Active
P07 to P00 Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Standard
input port
P17
P16
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
High-voltage
input port
Hi-Z or pulled up Hi-Z or
pulled up
Hi-Z
Hi-Z
Standard
input port
P15, P14,
P11, P10
Hi-Z or pulled up prev. state Hi-Z
Hi-Z
Hi-Z
Standard I/O
port
P47 to P40 Hi-Z or
pulled down
prev. state Hi-Z or
Hi-Z or
Hi-Z or
High-voltage
pulled down pulled down pulled down I/O port
prev. state Hi-Z or Hi-Z or Hi-Z or High-voltage
pulled down pulled down pulled down I/O port
prev. state Hi-Z or Hi-Z or Hi-Z or High-voltage
pulled down pulled down pulled down I/O port
prev. state Hi-Z or Hi-Z or Hi-Z or High-voltage
pulled down pulled down pulled down I/O port
P57 to P50 Hi-Z or
pulled down
P67 to P60 Hi-Z or
pulled down
P77 to P70 Hi-Z or
pulled down
P97 to P90 Hi-Z or pulled up prev. state Hi-Z
Hi-Z
Hi-Z
Standard I/O
port
Notation:
Hi-Z: High-impedance state
Prev. state: Input pins are in high-impedance state. Output pins hold their previous output.
Hi-Z or pulled up: Standard ports for which the pull-up MOS mask option is chosen are pulled
up; ports without the pull-up MOS option are in the high-impedance state.
Hi-Z or pulled down: High-voltage ports for which the pull-down MOS mask option is chosen are
pulled down; ports without the pull-down MOS option are in the high-
impedance state.
309
Notes: 1. When MOS pull-up is chosen as a mask option with standard ports, the pull-ups are
always on in active mode and sleep mode, regardless of the port control register (PCR)
and port data register (PDR) settings. The pull-ups are off in power-down modes other
than sleep mode.
2. The input gates of pins selected for peripheral function input remain on even in power-
down modes. Their input levels must be held fixed in order to avoid increased power
dissipation.
3. The states indicated above for P17 apply when this pin is designated as a high-voltage
input pin by mask option.
310
Appendix E List of Mask Options
HD6433712, HD6433713 and HD6433714
Please indicate the selected specifications by
marking the appropriate box (with an × or √
mark). The shaded boxes cannot be selected.
Date of order
Company
Address
, 19
Name
ROM code name
Part no.
(1) I/O Options
HD6433712
HD6433714
HD6433713
B: With MOS pull-up
D: No MOS pull-down
C: No MOS pull-up
E: With MOS pull-down
I/O option
Pin
I/O option
I/O
Pin
I/O
I/O
I/O
I/O
I/O
I
C
B
D
E
B C D E
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P10/IRQ0
P11/IRQ1
P14/IRQ4
P15/IRQ5/TMOE
P16/EVENT
P40/FS16
P41/FS17
P42/FS18
P43/FS19
P44/FS20
P45/FS21
P46/FS22
P47/FS23
P50/FS15
P51/FS14
P52/FS13
P53/FS12
P54/FS11
P55/FS10
P56/FS9
P60/FD0/FS7
P61/FD1/FS6
P62/FD2/FS5
P63/FD3/FS4
P64/FD4/FS3
P65/FD5/FS2
P66/FD6/FS1
P67/FD7/FS0
P70/FD8
P71/FD9
P72/FD10
P73/FD11
P74/FD12
P75/FD13
P76/FD14
P77/FD15
P90/PWM
P91/SCK1
P92/SI1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
P93/SO1
P57/FS8
P17/Vdisp
P94/SCK2
P95/SI2/CS
P96/SO2
Fill in (2) below
P97/UD
(2) P1 /V
(4) Oscillator at OSC and OSC
1 2
7
disp
P17: No MOS pull-down (D)
Vdisp
Crystal oscillator
Ceramic oscillator
External clock
fOSC
fOSC
fOSC
=
=
=
MHz
MHz
MHz
Note: If E (MOS pull-down) is selected as an option
for one or more high-voltage pins, Vdisp must
be selected for the P17/Vdisp pin.
(3) Package
(5) Oscillator at X and X
1 2
FP-64A
DP-64S
Used
fx = 32.768 kHz
X1 = VCC
Not used
Notes: 1. The wide temperature range specification and I specification are special specifications. There is no
J specification for these products. Please contact your local Hitachi representative for details.
2. ROM data submitted in an EPROM must be written starting from address H'0000 in accordance with the
memory map of the particular microcontroller. For data outside the ROM area on the memory map use
H'FF.
311
Appendix F Rise Time and Fall Time of High-Voltage Pins
With the mask ROM versions there is a choice of high-voltage pin output configurations. Either
PMOS open-drain (D) or MOS pull-down (E) may be selected. (Only PMOS open-drain is
available as the output configuration of high-voltage pins on ZTAT™ versions.)
The rise time t and fall time t of high-voltage pin output are as follows.
r
f
.
It is possible to estimate t and t from the time constant τ = C R (time up to 63% of rise or fall).
r
f
t : The time constant is determined by the PMOS on-resistance and load capacitance. The DC
r
on-resistance is approximately 200 Ω (based on V = V – 3 V at –I = 15 mA,
OH
CC
OH
3/0.015 = 200). The AC on-resistance however, includes the non-saturation state when the
PMOS transistor turns on (it is not a constant-current source), resulting in a longer time
constant. Assuming a load capacitance of 30 pF at high-voltage pins, the minimum value is
approximately 20 ns.
t : The time constant is determined by the pull-down resistance and load capacitance (including
f
wiring capacitance, etc.). As an example, assuming a pull-down resistance of 5 kΩ and load
capacitance of 30 pF, the following is derived.
3
–12
–9
t ≥ 5 × 10 × 30 × 10 = 150 × 10 (150 ns)
f
MOS pull-down resistance varies from 45 kΩ to 300 kΩ, so all due care must be taken in
timing design.
VCC
63%
63%
tr
tf
H8/3714 Series
microcontroller
Vdisp
or VSS
Note: If pull-down resistance is made too small in an attempt to speed up the fall time, –I will
OH
increase, limiting the output high-level voltage (V ). Pull-down resistance must be set to
OH
a suitable value taking into consideration both operation speed and the output high level.
312
Appendix G Package Dimensions
Figures G-1 and G-2 show the external dimensions of the FP-64A and DP-64S packages,
respectively, for the H8/3712, H8/3713 and H8/3714.
Unit: mm
Figure G-1 External Dimensions (FP-64A)
Unit: mm
Figure G-2 External Dimensions (DP-64S)
313
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