HD66753TB0_技术文档

HD66753

(168 x 132-dot Graphics LCD Controller/Driver with

Bit-operation Functions)

ADE-207-347(Z)

Rev. 1.0

Jan. 31. 2003

Description

The HD66753, dot-matrix graphics LCD controller and driver LSI, displays 168-by-132-dot graphics for

four monochrome grayscales. When 12-by-13-dot size fonts are used, up to 13 lines x 11 characters (143

characters) can be simultaneously displayed. Since the HD66753 incorporates bit-operation functions and a

16-bit high-speed bus interface, it enables efficient data transfer and high-speed rewriting of data in the

graphics RAM.

The HD66753 has various functions for reducing the power consumption of an LCD system, such as low-

voltage operation of 1.7 V/min., a step-up circuit to generate a maximum of seven-times the LCD drive

voltage from the input-supplied voltage, and voltage followers to decrease the direct current flow in the

LCD drive bleeder-resistors. Combining these hardware functions with software functions, such as a

partial display with low-duty drive and standby and sleep modes, allows precise power control. The

HD66753 is suitable for any mid-sized or small portable battery-driven product requiring long-term driving

capabilities, such as digital cellular phones supporting a WWW browser.

Features

•

168 × 132-dot graphics display LCD controller/driver for four monochrome grayscales

16-/8-bit high-speed bus interface

Clock-synchronized serial interface (transfer rate: 10 MHz max.)

I2C bus interface (transfer rate: 1.3 MHz max.)

Bit-operation functions for graphics processing:

 Write-data mask function in bit units

 Bit rotation function

 Bit logic-operation function

•

Low-power operation supports:

 Vcc = 1.7 to 3.6 V (low voltage)

 V_LPS= 5 to 19.5 V (liquid crystal drive voltage)

 Internal three-, five-, six-, or seven-times step-up circuit for liquid crystal drive voltage to be

selected by software

 128-step contrast adjuster and voltage followers to decrease direct current flow in the LCD drive

bleeder-resistors

HD66753

 Power-save functions such as the standby mode and sleep mode

 Programmable drive duty ratios and bias values displayed on LCD

Internal LCD-drive-voltage regulator circuits

•

168-segment × 132-common liquid crystal display driver

n-raster-row AC liquid-crystal drive (C-pattern waveform drive)

Duty ratio and drive bias (selectable by program)

Window cursor display supported by hardware

Black-and-white reversed display

Internal oscillation and hardware reset

Shift change of segment and common driver

Table 1

Progammable Display Sizes and Duty Ratios

Graphics Display

Duty Optimum Bit-map

12 x 13-dot 12 x 14-dot 16 x 16-dot 16 x 17-dot 8 x 10-dot

Ratio Drive Bias Display Area Font Width Font Width Font Width Font Width Font Width

1/96 1/10 168 x 96 dots 12 lines x 8 12 lines x 8 10 lines x 6 10 lines x 5 21 lines x 9

characters characters characters characters characters

168 x 104 dots 12 lines x 8 12 lines x 8 10 lines x 6 10 lines x 6 21 lines x 10

characters characters characters characters characters

168 x 112 dots 12 lines x 9 12 lines x 9 10 lines x 7 10 lines x 6 21 lines x 11

characters characters characters characters characters

168 x 120 dots 12 lines x 10 12 lines x 10 10 lines x 7 10 lines x 7 21 lines x 12

characters characters characters characters characters

168 x 128 dots 12 lines x 10 12 lines x 10 10 lines x 8 10 lines x 7 21 lines x 12

characters characters characters characters characters

168 x 132 dots 12 lines x 11 12 lines x 11 10 lines x 8 10 lines x 7 21 lines x 13

characters characters characters characters characters

1/104 1/11

1/112 1/11

1/120 1/11

1/128 1/11

1/132 1/11

Note: When 12 x 13-dot fonts are used for display, the spaces between characters on the last line are not

displayed.

Rev. 1.0, Jan. 2003, page 2 of 102

HD66753

Total Current Consumption Characteristics (Vcc = 3 V, TYP Conditions, LCD

Drive Power Current Included)

Total Power Consumption

Normal Display Operation

Character

R-C

Display Dot Duty Oscillation Frame

Internal

(60 µA)

(70 µA)

(80 µA)

LCD

Power

Sleep Standby

Mode Mode

Size

Ratio Frequency Frequency Logic

Total*

96 x 168 dots 1/96

100 kHz

69 Hz

71 Hz

69 Hz

(20 µA)

(25 µA)

Five-times (12 µA) 0.1 µA

(160 µA)

104 x 168 dots 1/104 100 kHz

112 x 168 dots 1/112 100 kHz

120 x 168 dots 1/120 100 kHz

128 x 168 dots 1/128 100 kHz

132 x 168 dots 1/132 100 kHz

Five-times (12 µA)

(160 µA)

Six-times (12 µA)

(220 µA)

Six-times (12 µA)

(220 µA)

Six-times (12 µA)

(230 µA)

Six-times (12 µA)

(230 µA)

Note: When a three-, five-, six-, or seven-times step-up is used:

the total current consumption = internal logic current + LCD power current x 3 (three-times step-up),

the total current consumption = internal logic current + LCD power current x 5 (five-times step-up),

the total current consumption = internal logic current + LCD power current x 6 (six-times step-up),

and

the total current consumption = internal logic current + LCD power current x 7 (seven-times step-up)

Type Name

Types

External Dimensions

Bending TCP

MPU Interface

COM Driver Arrangement

Display

HD66753TB0

HCD66753BP

HWD66753BP

8-bit or 16-bit

parallel or clock-

synchronized serial

interface

Both sides of COM

(Output from left and right

sides of the chip)

Four

monochrome

grayscales

Au-bump chip

Au-bump wafer

Rev. 1.0, Jan. 2003, page 3 of 102

HD66753

LCD Family Comparison

Items

HD66724

HD66725

HD66726

Character display sizes

Graphic display sizes

Grayscale display

12 characters x 3 lines

16 characters x 3 lines

16 characters x 5 lines

72 x 26 dots

96 x 26 dots

96 x 42 dots

—

Multiplexing icons

144

192

Annunciator

1/2 duty: 144

1/2 duty: 192

Key scan control

8 x 4

LED control ports

—

General output ports

Operating power voltages

Liquid crystal drive voltages

Serial bus

3

1.8 V to 5.5 V

3 V to 6.5 V

1.8 V to 5.5 V

3 V to 6.5 V

1.8 V to 5.5 V

4.5 V to 11 V

Clock-synchronized serial

4 bits, 8 bits

Clock-synchronized serial

4 bits, 8 bits

1/2, 10, 18, 26

1/4 to 1/6.5

Clock-synchronized serial

4 bits, 8 bits

1/2, 10, 18, 26

1/4 to 1/6.5

Parallel bus

Liquid crystal drive duty ratios

Liquid crystal drive biases

Liquid crystal drive waveforms

Liquid crystal voltage step-up

1/2, 10, 18, 26, 34, 42

1/2 to 1/8

B

Single, two-, or three-times

Single, two-, three-, or four-

times

Bleeder-resistor for liquid crystal drive

Liquid crystal drive operational amplifier

Liquid crystal contrast adjuster

Horizontal smooth scroll

Vertical smooth scroll

Double-height display

DDRAM

Incorporated (external)

Incorporated

Incorporated (32 steps)

3-dot unit

Line unit

Incorporated (external)

Incorporated

Incorporated (32 steps)

3-dot unit

Line unit

Incorporated (external)

Incorporated

Incorporated (32 steps)

—

Line unit

Yes

80 x 8

20,736

480 x 8

96 x 8

240 + 192

64

CGROM

20,736

CGRAM

384 x 8

SEGRAM

72 x 8

96 x 8

No. of CGROM fonts

No. of CGRAM fonts

Font sizes

240 + 192

64

240 + 192

64

6 x 8

Bit map areas

72 x 26

96 x 26

96 x 42

R-C oscillation resistor/

oscillation frequency

External resistor,

incorporated (32 kHz)

External resistor,

incorporated (32 kHz)

External resistor

(50 kHz)

Reset function

External

Low power control

Partial display off,

Oscillation off,

Partial display off,

Oscillation off,

Partial display off,

Oscillation off,

Liquid crystal power off,

Key wake-up interrupt

Liquid crystal power off,

Key wake-up interrupt

Liquid crystal power off,

Key wake-up interrupt

SEG/COM direction switching

QFP package

TQFP package

TCP package

Bare chip

SEG, COM

—

SEG, COM

—

SEG, COM

—

TCP-146

—

TCP-170

—

TCP-188

Yes

Bumped chip

Yes

Chip sizes

10.34 x 2.51

80 µm

10.97 x 2.51

80 µm

13.13 x 2.51

100 µm

Pad intervals

Rev. 1.0, Jan. 2003, page 4 of 102

HD66753

LCD Family Comparison (cont)

Items

HD66728

HD66729

HD66740

Character display sizes

Graphic display sizes

Grayscale display

Multiplexing icons

Annunciator

16 characters x 10 lines

—

112 x 80 dots

105 x 68 dots

112 x 80 dots

—

Key scan control

8 x 4

—

LED control ports

General output ports

Operating power voltages

Liquid crystal drive voltages

Serial bus

—

3

—

1.8 V to 5.5 V

4.5 V to 15 V

Clock-synchronized serial

4 bits, 8 bits

1.8 V to 5.5 V

4.0 V to 13 V

Clock-synchronized serial

4 bits, 8 bits

1.8 V to 3.6 V

4.5 V to 15 V

Clock-synchronized serial

4 bits, 8 bits

Parallel bus

Liquid crystal drive duty ratios

1/8, 16, 24, 32, 40, 48, 56,

64, 72, 80

1/8, 16, 24, 32, 40, 48, 56,

64, 68

1/8, 16, 24, 32, 40, 48, 56,

64, 72, 80

Liquid crystal drive biases

1/4 to 1/10

1/4 to 1/9

B, C

1/4 to 1/10

Liquid crystal drive waveforms

Liquid crystal voltage step-up

B, C

Three-, four-, or five-times

Two-, three-, four-, or five-

times

Three-, four-, or five-times

Bleeder-resistor for liquid crystal drive

Liquid crystal drive operational amplifier

Liquid crystal contrast adjuster

Horizontal smooth scroll

Vertical smooth scroll

Double-height display

DDRAM

Incorporated (external)

Incorporated

Incorporated (64 steps)

—

Line unit

Yes

Line unit

Yes

160 x 8

20,736

1,120 x 8

—

CGROM

—

CGRAM

1,050 x 8

1,120 x 8

SEGRAM

—

No. of CGROM fonts

No. of CGRAM fonts

Font sizes

240 + 192

64

—

6 x 8

—

Bit map areas

112 x 80

105 x 68

112 x 80

R-C oscillation resistor/

oscillation frequency

External resistor

(70–90 kHz)

External resistor

(75 kHz)

External resistor

(70–90 kHz)

Reset function

External

Low power control

Partial display off,

Oscillation off,

Partial display off,

Oscillation off,

Partial display off,

Oscillation off,

Liquid crystal power off,

Key wake-up interrupt

Liquid crystal power off

SEG/COM direction switching

QFP package

TQFP package

TCP package

Bare chip

SEG, COM

—

SEG, COM

—

SEG, COM

—

TCP-241

—

TCP-213

—

TCP-236

—

Bumped chip

Yes

Chip sizes

13.67 x 2.78

70 µm

12.23 x 2.52

70 µm

9.40 x 2.18

50 µm

Pad intervals

Rev. 1.0, Jan. 2003, page 5 of 102

HD66753

LCD Family Comparison (cont)

Items

HD66741

HD66751S

—

HD66750S

—

Character display sizes

Graphic display sizes

Grayscale display

—

128 x 80 dots

—

128 x 128 dots

Four monochrome

grayscales (5 levels)

Multiplexing icons

Annunciator

—

Key scan control

—

LED control ports

General output ports

Operating power voltages

Liquid crystal drive voltages

Serial bus

—

3

—

1.8 V to 5.5 V

4.5 V to 15 V

Clock-synchronized serial

4 bits, 8 bits

1.7 V to 3.6 V

5.0 V to 16.5V

—

1.7 V to 3.6 V

5.0 V to 16.5V

Clock-synchronized serial

8 bits, 16 bits

Parallel bus

8 bits, 16 bits

Liquid crystal drive duty ratios

1/8, 16, 24, 32, 40, 48, 56,

64, 72, 80

1/16, 24, 72, 80, 88, 96, 104, 1/16, 24, 72, 80, 88, 96, 104,

112, 120, 128

1/4 to 1/11

B, C

112, 120, 128

1/4 to 1/11

B, C

Liquid crystal drive biases

1/4 to 1/10

Liquid crystal drive waveforms

Liquid crystal voltage step-up

B, C

Three-, four-, or five-times

Two-, five-, six-, or seven-

times

Two-, five-, six-, or seven-

times

Bleeder-resistor for liquid crystal drive

Liquid crystal drive operational amplifier

Liquid crystal contrast adjuster

Horizontal smooth scroll

Vertical smooth scroll

Double-height display

DDRAM

Incorporated (external)

Incorporated

Incorporated (64 steps)

—

Line unit

Yes

—

CGROM

—

CGRAM

1,280 x 8

4,096 x 8

SEGRAM

—

No. of CGROM fonts

No. of CGRAM fonts

Font sizes

—

Bit map areas

128 x 80

128 x 128

R-C oscillation resistor/

oscillation frequency

External resistor

(70–90 kHz)

External resistor

(70 kHz)

External resistor

(70 kHz)

Reset function

External

Low power control

Partial display off,

Oscillation off,

Partial display off,

Oscillation off,

Partial display off,

Oscillation off,

Liquid crystal power off

SEG/COM direction switching

QFP package

TQFP package

TCP package

Bare chip

SEG, COM

—

SEG, COM

—

SEG, COM

—

TCP-254

—

TCP-308

—

TCP-308

—

Bumped chip

Yes

Chip sizes

14.30 x 2.78

70 µm

8.42 x 3.18

50 µm

8.44 x 2.95

50 µm

Pad intervals

Rev. 1.0, Jan. 2003, page 6 of 102

HD66753

LCD Family Comparison (cont)

Items

HD66752

HD66753

—

Character display sizes

Graphic display sizes

Grayscale display

—

168 x 132 dots

Four monochrome

grayscales (7 levels)

Multiplexing icons

Annunciator

—

Key scan control

—

LED control ports

General output ports

Operating power voltages

Liquid crystal drive voltages

Serial bus

—

2.0 V to 3.6 V

5.0 V to 15.5V

—

1.7 V to 3.6 V

5 V to 19.5V

Clock-synchronized serial

8 bits, 16 bits

Parallel bus

8 bits, 16 bits

Liquid crystal drive duty ratios

1/80, 88, 96, 104, 112, 120, 1/80, 88, 96, 104, 112, 120,

128, 132

1/4 to 1/11

B, C

128, 132

1/4 to 1/11

B, C

Liquid crystal drive biases

Liquid crystal drive waveforms

Liquid crystal voltage step-up

Two-, five-, six-, or seven-

times

Two-, five-, six-, or seven-

times

Bleeder-resistor for liquid crystal drive

Liquid crystal drive operational amplifier

Liquid crystal contrast adjuster

Horizontal smooth scroll

Vertical smooth scroll

Double-height display

DDRAM

Incorporated (external)

Incorporated

Incorporated (128 steps)

—

Line unit

Yes

—

CGROM

—

CGRAM

5,544 x 8

SEGRAM

—

No. of CGROM fonts

No. of CGRAM fonts

Font sizes

—

Bit map areas

168 x 132, 132 x 168

R-C oscillation resistor/

oscillation frequency

External resistor

(70 kHz)

External resistor

(70 kHz)

Reset function

External

Low power control

2-screen division partial

drive, Partial display off,

Oscillation off,

2-screen division partial

drive, Partial display off,

Oscillation off,

Liquid crystal power off

SEG/COM direction switching

QFP package

TQFP package

TCP package

Bare chip

SEG, COM

—

TCP-352

—

Bumped chip

Yes

Chip sizes

12.68 x 4.31

60 µm

15.90 x 2.02

50 µm

Pad intervals

Rev. 1.0, Jan. 2003, page 7 of 102

HD66753

HD66753 Block Diagram

OSC1 OSC2

CPG

Vcc

RESET*

TEST

Timing generator

Instruction

decoder

Instruction register (IR)

IM2-1

16

132-bit

COM1/132-COM132/1

IM0ID

CS*

Address counter (AC)

bidirectional

common shift

register

Common

driver

System

RS

E/WR*/SCL

interface

·Synchronized

serial

16

Bit operation

·16-bit bus

·8-bit bus

RW/RD*/SDA

SEG1/168-SEG168/1

16

12

DB0-DB15

16

168-bit

latch circuit

Read data

latch

16

Segment driver

Vci

C1+

16

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

C6+

C6-

Graphic RAM

(CGRAM)

5,544 bytes

LCD drive voltage

selector

Three-, five-, six-,

and seven-times

step-up

Four-grayscale control circuit

Window cursor control

VLOUT

VSW1

VSW2

VREG

V1REF

LCD drive voltage

regulator

Drive bias controller

Contrast

adjuster

VTEST

+ -

VR

+ -

R

0

R

VLREF

OPOFF

V1OUT

V2OUT

V3OUT

V4OUT

V5OUT

GND

Rev. 1.0, Jan. 2003, page 8 of 102

HD66753

HD66753 Pad Arrangement

Chip size: 15.90 m m

x 2.02 m m

µ

Chip thickness: 400

m (typ.)

Pad coordinates: pad centers

Coordinate origin: chip center

No. 1

No. 417

Au bum p size:

Dummy8

GNDDU M3

DB15

DB14

DB13

DB12

DB11

DB10

DB9

Dummy1

µ

(m in 100- m

(1) 80

m

x

80

m

pitch)

Dummy1, Dummy2 to GNDDUM2, Dummy8,

GNDDUM3, DB15 to V4OUT, V5OUT,

Dum my9, Dummy10 to Dum my19, Dummy20

COM1/132

COM2/131

µ

(m in 60- m

(2) 45

m

x

80

m

pitch)

COM 14/119

COM 15/118

COM 16/117

COM 65/68

COM 66/67

COM1/132 to C OM 14/119,

COM17/116 to COM 30/103

Type code

µ

(3) 35 um x 80 um (min 50- ‚

SEG1/168 to SEG168/1,

COM15/118, COM16/117,

COM65/68 to C OM 112/21,

COM31/102 to COM 132/1

Au bum p pitch: see the pad coordinates

µ

Height of the Au bump: 15

m (typ.)

DB8

Numbers in the figure correspond to pad no.

DB7

Alignment m ark

COM 111/22

COM 112/21

SEG168/1

SEG167/2

(1) Alignment: two points

@@ Coordinates (X, Y)

DB6

i±7642, 613j

DB5

µ

190

m

95

DB4

DB3

DB2

DB1

DB0

GNDDU M4

RESET*

CS*

45 30 40 30 45

(2-b) Coordinates (X, Y)

=

i7668, 406j

RS

20

µ

50

m

E/WR*/SCL

RW/RD*/SDA

GND

OSC2

OSC1

Vcc

(3-a) Coordinates (X, Y)

=

i-7548, 406j

5

10 25

25 10

5

HD66753

(Top view)

Y

Vcc

µ

70

80

m

X

Vcc

Vci

(3-b) Coordinates (X, Y)

10 25

=

i7548, 406j

25 10

Vci

VREG

C6+

C6-

µ

70

m

C5+

C5-

Update histo ry

C5-

C4+

C4-

Rev 0 .0 : new ly created

Rev 0 .1 : pad coo rd in ate no. updated,

@@@@@ type co de a dde d

Rev 0 .2 : pin nam e m odified in Au b um p

@@@@@

size (3)

C4-

C3+

C3-

C2+

C2-

C1+

C1-

SEG2/167

SEG1/168

COM 132/1

COM 131/2

C1-

VLOUT

VLPS

V1REF

VLREF

V1OUT

V2OUT

V3OUT

V4OUT

V5OUT

COM 114/19

COM 113/20

COM 64/69

COM 63/70

COM 31/102

COM 30/103

COM 18/115

COM 17/116

Dummy9

Dummy20

No. 116

No. 101

Rev. 1.0, Jan. 2003, page 9 of 102

HD66753

HD66753 Pad Coordinates

No. Pad Name

X

Y

No. Pad Name

-848 38 Vcc

X

Y

1

2

3

4

5

6

7

8

9

Dummy8

GNDDUM3

DB15

-7788

-7610

-7395

-7071

-6747

-6423

-6099

-5775

-5451

-5126

-4802

-4478

-4154

-3830

-3506

-3181

-2857

-2533

-2319

-2105

-1781

-1456

-1132

-808

1233

1333

1433

1576

1676

1776

1876

1976

2076

2176

2319

2419

2519

2619

2719

2819

2920

3020

3120

3220

3320

3420

3520

3620

3720

3820

3921

4021

4121

4221

4321

4421

4521

4621

4721

4821

4922

-848

-848 39 Vcc

-848 40 Vcc

-848 41 Vci

-848 42 Vci

-848 43 Vci

-848 44 Vci

-848 45 Vci

-848 46 Vci

-848 47 VREG

-848 48 C6+

-848 49 C6+

-848 50 C6+

-848 51 C6-

-848 52 C6-

-848 53 C6-

-848 54 C5+

-848 55 C5+

-848 56 C5+

-848 57 C5-

-848 58 C5-

-848 59 C5-

-848 60 C4+

-848 61 C4+

-848 62 C4+

-848 63 C4-

-848 64 C4-

-848 65 C4-

-848 66 C3+

-848 67 C3+

-848 68 C3+

-848 69 C3-

-848 70 C3-

-848 71 C3-

-848 72 C2+

-848 73 C2+

-848 74 C2+

DB14

DB13

DB12

DB11

DB10

DB9

10 DB8

11 DB7

12 DB6

13 DB5

14 DB4

15 DB3

16 DB2

17 DB1

18 DB0

19 GNDDUM4

20 RESET*

21 CS*

22 RS

23 E/WR*/SCL

24 RW/RD*/SDA

25 GND

26 GND

27 GND

28 GND

29 GND

30 GND

31 GND

32 GND

33 OSC2

34 OSC1

35 Vcc

-594

-494

-394

-294

-193

-93

7

107

358

682

932

36 Vcc

1032

1132

37 Vcc

Rev. 1.0, Jan. 2003, page 10 of 102

HD66753

HD66753 Pad Coordinates (cont)

No. Pad Name

75 C2-

X

Y

No. Pad Name

-848 112 Dummy16

-848 113 Dummy17

-848 114 Dummy18

-848 115 Dummy19

-848 116 Dummy20

-848 117 COM17/116

-848 118 COM18/115

-848 119 COM19/114

-848 120 COM20/113

-848 121 COM21/112

-848 122 COM22/111

-848 123 COM23/110

-848 124 COM24/109

-848 125 COM25/108

-848 126 COM26/107

-848 127 COM27/106

-848 128 COM28/105

-848 129 COM29/104

-848 130 COM30/103

-848 131 COM31/102

-848 132 COM32/101

-848 133 COM33/100

-848 134 COM34/99

-848 135 COM35/98

-848 136 COM36/97

-848 137 COM37/96

-848 138 COM38/95

-635 139 COM39/94

-535 140 COM40/93

-435 141 COM41/92

-335 142 COM42/91

-235 143 COM43/90

-135 144 COM44/89

-34 145 COM45/88

66 146 COM46/87

X

Y

5022

5122

5222

5322

5422

5522

5622

5722

5823

5965

6065

6166

6266

6366

6466

6566

6666

6766

6866

7009

7109

7209

7309

7409

7510

7610

7788

7628

7568

7508

7448

7388

7328

7268

7207

7147

7087

7027

6967

6907

6847

6792

6742

6691

6641

6591

6541

6491

6441

6391

6341

6290

6240

6190

6140

6090

6040

5990

5940

366

466

566

666

880

76 C2-

77 C2-

78 C1+

79 C1+

80 C1+

81 C1-

82 C1-

83 C1-

84 VLOUT

85 VLOUT

86 VLOUT

87 VLOUT

88 VLOUT

89 VLPS

90 VLPS

91 VLPS

92 VLPS

93 VLPS

94 V1REF

95 VLREF

96 V1OUT

97 V2OUT

98 V3OUT

99 V4OUT

100 V5OUT

101 Dummy9

102 Dummy10

103 Dummy11

104 Dummy12

105 Dummy13

106 VTEST

107 GNDDUM5

108 VSW1

109 VSW2

110 Dummy14

111 Dummy15

166 147 COM47/86

266 148 COM48/85

Rev. 1.0, Jan. 2003, page 11 of 102

HD66753

HD66753 Pad Coordinates (cont)

No. Pad Name

149 COM49/84

150 COM50/83

151 COM51/82

152 COM52/81

153 COM53/80

154 COM54/79

155 COM55/78

156 COM56/77

157 COM57/76

158 COM58/75

159 COM59/74

160 COM60/73

161 COM61/72

162 COM62/71

163 COM63/70

164 COM64/69

165 COM113/20

166 COM114/19

167 COM115/18

168 COM116/17

169 COM117/16

170 COM118/15

171 COM119/14

172 COM120/13

173 COM121/12

174 COM122/11

175 COM123/10

176 COM124/9

177 COM125/8

178 COM126/7

179 COM127/6

180 COM128/5

181 COM129/4

182 COM130/3

183 COM131/2

184 COM132/1

185 SEG1/168

X

Y

No. Pad Name

880 186 SEG2/167

880 187 SEG3/166

880 188 SEG4/165

880 189 SEG5/164

880 190 SEG6/163

880 191 SEG7/162

880 192 SEG8/161

880 193 SEG9/160

880 194 SEG10/159

880 195 SEG11/158

880 196 SEG12/157

880 197 SEG13/156

880 198 SEG14/155

880 199 SEG15/154

880 200 SEG16/153

880 201 SEG17/152

880 202 SEG18/151

880 203 SEG19/150

880 204 SEG20/149

880 205 SEG21/148

880 206 SEG22/147

880 207 SEG23/146

880 208 SEG24/145

880 209 SEG25/144

880 210 SEG26/143

880 211 SEG27/142

880 212 SEG28/141

880 213 SEG29/140

880 214 SEG30/139

880 215 SEG31/138

880 216 SEG32/137

880 217 SEG33/136

880 218 SEG34/135

880 219 SEG35/134

880 220 SEG36/133

880 221 SEG37/132

880 222 SEG38/131

X

Y

5889

5839

5789

5739

5689

5639

5589

5539

5488

5438

5388

5338

5288

5238

5188

5138

5087

5037

4987

4937

4887

4837

4787

4737

4686

4636

4586

4536

4486

4436

4386

4336

4285

4235

4185

4135

4085

4035

3985

3935

3885

3834

3784

3734

3684

3634

3584

3534

3484

3433

3383

3333

3283

3233

3183

3133

3083

3032

2982

2932

2882

2832

2782

2732

2682

2631

2581

2531

2481

2431

2381

2331

2281

2230

880

Rev. 1.0, Jan. 2003, page 12 of 102

HD66753

HD66753 Pad Coordinates (cont)

No. Pad Name

223 SEG39/130

224 SEG40/129

225 SEG41/128

226 SEG42/127

227 SEG43/126

228 SEG44/125

229 SEG45/124

230 SEG46/123

231 SEG47/122

232 SEG48/121

233 SEG49/120

234 SEG50/119

235 SEG51/118

236 SEG52/117

237 SEG53/116

238 SEG54/115

239 SEG55/114

240 SEG56/113

241 SEG57/112

242 SEG58/111

243 SEG59/110

244 SEG60/109

245 SEG61/108

246 SEG62/107

247 SEG63/106

248 SEG64/105

249 SEG65/104

250 SEG66/103

251 SEG67/102

252 SEG68/101

253 SEG69/100

254 SEG70/99

255 SEG71/98

256 SEG72/97

257 SEG73/96

258 SEG74/95

259 SEG75/94

X

Y

No. Pad Name

880 260 SEG76/93

880 261 SEG77/92

880 262 SEG78/91

880 263 SEG79/90

880 264 SEG80/89

880 265 SEG81/88

880 266 SEG82/87

880 267 SEG83/86

880 268 SEG84/85

880 269 SEG85/84

880 270 SEG86/83

880 271 SEG87/82

880 272 SEG88/81

880 273 SEG89/80

880 274 SEG90/79

880 275 SEG91/78

880 276 SEG92/77

880 277 SEG93/76

880 278 SEG94/75

880 279 SEG95/74

880 280 SEG96/73

880 281 SEG97/72

880 282 SEG98/71

880 283 SEG99/70

880 284 SEG100/69

880 285 SEG101/68

880 286 SEG102/67

880 287 SEG103/66

880 288 SEG104/65

880 289 SEG105/64

880 290 SEG106/63

880 291 SEG107/62

880 292 SEG108/61

880 293 SEG109/60

880 294 SEG110/59

880 295 SEG111/58

880 296 SEG112/57

X

Y

2180

2130

2080

2030

1980

1930

1880

1829

1779

1729

1679

1629

1579

1529

1479

1428

1378

1328

1278

1228

1178

1128

1078

1028

977

326

276

880

226

175

125

75

25

-25

-75

-125

-175

-226

-276

-326

-376

-426

-476

-526

-576

-627

-677

-727

-777

-827

-877

-927

-977

-1028

-1078

-1128

-1178

-1228

-1278

-1328

-1378

-1428

-1479

927

877

827

777

727

677

627

576

526

476

426

376

Rev. 1.0, Jan. 2003, page 13 of 102

HD66753

HD66753 Pad Coordinates (cont)

No. Pad Name

297 SEG113/56

298 SEG114/55

299 SEG115/54

300 SEG116/53

301 SEG117/52

302 SEG118/51

303 SEG119/50

304 SEG120/49

305 SEG121/48

306 SEG122/47

307 SEG123/46

308 SEG124/45

309 SEG125/44

310 SEG126/43

311 SEG127/42

312 SEG128/41

313 SEG129/40

314 SEG130/39

315 SEG131/38

316 SEG132/37

317 SEG133/36

318 SEG134/35

319 SEG135/34

320 SEG136/33

321 SEG137/32

322 SEG138/31

323 SEG139/30

324 SEG140/29

325 SEG141/28

326 SEG142/27

327 SEG143/26

328 SEG144/25

329 SEG145/24

330 SEG146/23

331 SEG147/22

332 SEG148/21

333 SEG149/20

X

Y

No. Pad Name

880 334 SEG150/19

880 335 SEG151/18

880 336 SEG152/17

880 337 SEG153/16

880 338 SEG154/15

880 339 SEG155/14

880 340 SEG156/13

880 341 SEG157/12

880 342 SEG158/11

880 343 SEG159/10

880 344 SEG160/9

880 345 SEG161/8

880 346 SEG162/7

880 347 SEG163/6

880 348 SEG164/5

880 349 SEG165/4

880 350 SEG166/3

880 351 SEG167/2

880 352 SEG168/1

880 353 COM112/21

880 354 COM111/22

880 355 COM110/23

880 356 COM109/24

880 357 COM108/25

880 358 COM107/26

880 359 COM106/27

880 360 COM105/28

880 361 COM104/29

880 362 COM103/30

880 363 COM102/31

880 364 COM101/32

880 365 COM100/33

880 366 COM99/34

880 367 COM98/35

880 368 COM97/36

880 369 COM96/37

880 370 COM95/38

X

Y

-1529

-1579

-1629

-1679

-1729

-1779

-1829

-1880

-1930

-1980

-2030

-2080

-2130

-2180

-2230

-2281

-2331

-2381

-2431

-2481

-2531

-2581

-2631

-2682

-2732

-2782

-2832

-2882

-2932

-2982

-3032

-3083

-3133

-3183

-3233

-3283

-3333

-3383

-3433

-3484

-3534

-3584

-3634

-3684

-3734

-3784

-3834

-3885

-3935

-3985

-4035

-4085

-4135

-4185

-4235

-4285

-4336

-4386

-4436

-4486

-4536

-4586

-4636

-4686

-4737

-4787

-4837

-4887

-4937

-4987

-5037

-5087

-5138

-5188

880

Rev. 1.0, Jan. 2003, page 14 of 102

HD66753

HD66753 Pad Coordinates (cont)

No. Pad Name

371 COM94/39

372 COM93/40

373 COM92/41

374 COM91/42

375 COM90/43

376 COM89/44

377 COM88/45

378 COM87/46

379 COM86/47

380 COM85/48

381 COM84/49

382 COM83/50

383 COM82/51

384 COM81/52

385 COM80/53

386 COM79/54

387 COM78/55

388 COM77/56

389 COM76/57

390 COM75/58

391 COM74/59

392 COM73/60

393 COM72/61

394 COM71/62

395 COM70/63

396 COM69/64

397 COM68/65

398 COM67/66

399 COM66/67

400 COM65/68

401 COM16/117

X

Y

No. Pad Name

880 402 COM15/118

880 403 COM14/119

880 404 COM13/120

880 405 COM12/121

880 406 COM11/122

880 407 COM10/123

880 408 COM9/124

880 409 COM8/125

880 410 COM7/126

880 411 COM6/127

880 412 COM5/128

880 413 COM4/129

880 414 COM3/130

880 415 COM2/131

880 416 COM1/132

880 417 Dummy1

880 418 Dummy2

880 419 Dummy3

880 420 Dummy4

880 421 Dummy5

880 422 Dummy6

880 423 Dummy7

880 424 IM2

X

Y

-5238

-5288

-5338

-5388

-5438

-5488

-5539

-5589

-5639

-5689

-5739

-5789

-5839

-5889

-5940

-5990

-6040

-6090

-6140

-6190

-6240

-6290

-6341

-6391

-6441

-6491

-6541

-6591

-6641

-6691

-6742

-6792

-6847

-6907

-6967

-7027

-7087

-7147

-7207

-7268

-7328

-7388

-7448

-7508

-7568

-7628

-7788

880

666

566

466

366

266

166

66

880 425 GNDDUM1

880 426 IM1

-34

-135

-235

-335

-435

-535

-635

880 427 IM0ID

880 428 VccDUM1

880 429 OPOFF

880 430 TEST

880 431 GNDDUM2

880

Rev. 1.0, Jan. 2003, page 15 of 102

HD66753

Alignment Mark

X

Y

Cross

-7642

7642

-7668

7668

-7548

7548

613

406

Circle (positive)

Circle (negative)

L type (positive)

L type (negative)

Rev. 1.0, Jan. 2003, page 16 of 102

HD66753

TCP External Dimensions (HD66753TB0L/R)

Bending slit

3.8 mm

Dummy

COM1/132

COM2/131

0.14P x (66-1)

9.10 mm

=

NC

IM2

IM1

IM0/ID

OPOFF

TEST

COM15/118

COM16/117

COM65/68

COM66/67

COM

64

DB15

DB14

DB13

DB12

DB11

DB10

DB9

0.14-mm

pitch

COM111/22

COM112/21

0.14 mm

0.65-mm

pitch

SEG168/1

SEG167/2

DB8

RESET*

CS*

RS

35.74 mm

E/WR*/SCL

RW/RD*/SDA

GND

0.10-mm

pitch

OSC2

OSC1

Vcc

Vci

LCD drive

VREG

I/O, Power supply

C6+

C6-

C5+

C5-

C4+

C4-

0.10P x (168-1)

=

16.7 mm

0.65P x (50-1)

=31.85 mm

C3+

C3-

C2+

C2-

C1+

C1-

VLOUT

SEG2/167

SEG1/168

VLPS

V1REF

VLREF

V1OUT

V2OUT

V3OUT

V4OUT

V5OUT

VTEST

VSW1

VSW2

NC

0.14 mm

COM132/1

COM131/2

0.14-mm

pitch

COM114/19

COM113/20

COM64/69

COM63/70

COM

68

0.14P x (70-1)

9.66 mm

=

COM18/111

COM17/112

Dummy

Rev. 1.0, Jan. 2003, page 17 of 102

HD66753

Pin Functions

Table 2

Pin Functional Description

Number of

Pins

Signals

I/O

Connected to Functions

GND or V_CCSelects the MPU interface mode:

IM2, IM1,

IM0/ID

3

I

IM2

GND

Vcc

IM1

GND

Vcc

GND

Vcc

IM0

GND 68-system 16-bit bus interface

Vcc 68-system 8-bit bus interface

GND 80-system 16-bit bus interface

MPU interface mode

Vcc

ID

80-system 8-bit bus interface

Clock-synchronized serial interface

I2C bus interface

Vcc

ID

When a serial interface is selected, the IM0 pin is

used for setting the device code ID.

CS*

1

I

MPU

Selects the HD66753:

Low: HD66753 is selected and can be accessed

High: HD66753 is not selected and cannot be

accessed

Must be fixed at GND level when not in use.

RS

1

I

MPU

Selects the register.

Low: Index/status

High: Control

Must be fixed at Vcc or GND level for a clock-

synchronized interface.

E/WR*/SCL

For a 68-system bus interface, serves as an enable

signal to activate data read/write operation.

For an 80-system bus interface, serves as a write

strobe signal and writes data at the low level.

For a clock-synchronized interface, serves as a

synchronized clock signal.

RW/RD*/

SDA

1

I/O

MPU

For a 68-system bus interface, serves as a signal to

select data read/write operation.

Low: Write

High: Read

For an 80-system bus interface, serves as a read

strobe signal and reads data at the low level.

For a clock-synchronized interface, serves as a

bidirectional serial transfer data to receive and send

the data.

DB0–DB15 16

I/O

MPU

Serves as a 16-bit bidirectional data bus.

For an 8-bit bus interface, data transfer uses DB15-

DB8; fix unused DB7-DB0 to the Vcc or GND level.

For a clock-synchronized interface, fix DB15-DB0 to

the Vcc or GND level.

Rev. 1.0, Jan. 2003, page 18 of 102

HD66753

Table 2

Pin Functional Description (cont)

Number

Signals

of Pins

I/O

Connected to Functions

LCD Output signals for common drive: All the unused pins

output unselected waveforms. In the display-off

COM1/132 132

–

O

COM132/1

period (D = 0), sleep mode (SLP = 1), or standby

mode (STB = 1), all pins output GND level.

The CMS bit can change the shift direction of the

common signal. For example, if CMS = 0, COM1/132

is COM1, and COM132/1 is COM132. If CMS = 1,

COM1/132 is COM132, and COM132/1 is COM1.

SEG1/168– 168

SEG168/1

O

LCD

Output signals for segment drive. In the display-off

period (D = 0), sleep mode (SLP = 1), or standby

mode (STB = 1), all pins output GND level.

The SGS bit can change the shift direction of the

segment signal. For example, if SGS = 0, SEG1/168

is SEG1. If SGS = 1, SEG1/168 is SEG168.

V1OUT–

V5OUT

5

Stabilization

capacitance

Built-in op-amp output. This should be stabilized by

connecting a capacitor.

V_LPS

1

2

—

Power supply

Power supply for LCD drive. V_LPS= 19.5 V max.

V_CC: +1.7 V to + 3.6 V; GND (logic): 0 V

V_CC, GND

OSC1,

OSC2

I or O Oscillation-

For R-C oscillation using an external resistor,

resistor or clock connect an external resistor. For external clock

supply, input clock pulses to OSC1.

Vci

1

I

Power supply

Inputs a reference voltage and supplies power to the

step-up circuit; generates the liquid crystal display

drive voltage from the operating voltage. The step-

up output voltage must not be larger than the

absolute maximum ratings.

Must be left disconnected when the step-up circuit is

not used.

VLOUT

1

O

V_LPSpin/step-up Potential difference between Vci and GND is two- to

capacitance

seven-times-stepped up and then output. Magnitude

of step-up is selected by instruction.

C1+, C1–

C2+, C2–

C3+, C3–

C4+, C4–

C5+, C5–

C6+, C6–

2

—

Step-up

capacitance

External capacitance should be connected here

when using the five-times or more step-up.

Step-up

capacitance

External capacitance should be connected here for

step-up.

Step-up

capacitance

External capacitance should be connected here for

step-up.

Step-up

capacitance

External capacitance should be connected here

when using the five-times or more step-up.

Step-up

capacitance

External capacitance should be connected here for

step-up.

Step-up

capacitance

External capacitance should be connected here for

step-up.

Rev. 1.0, Jan. 2003, page 19 of 102

HD66753

Table 2

Pin Functional Description (cont)

Number of

Pins

Signals

I/O

Connected to Functions

RESET*

1

I

MPU or

Reset pin. Initializes the LSI when low. Must be reset

external R-C

circuit

after power-on.

OPOFF

VSW1

VSW2

VREG

1

I

GND

—

Test pin. Must be fixed at GND level.

Test pin. Must be left disconnected.

I

—

I

Input pin

Input pin for the reference voltage of the LCD-drive-

voltage regulator circuit. Connect Vci or external

power supply.

V1REF

VLREF

1

O

I

Stabilization

Output pin for the LCD-drive-voltage regulator circuit.

capacitance or Must be left disconnected when not in use.

open

Input pin

Connected to the top electrode of the internal

bleeder-resistor. Use this pin to supply the LCD

voltage externally.

VccDUM

1

5

O

Input pins

Outputs the internal V_CClevel; shorting this pin sets

the adjacent input pin to the V_CClevel.

GNDDUM

Outputs the internal GND level; shorting this pin sets

the adjacent input pin to the GND level.

Dummy

TEST

4

1

—

I

—

Dummy pad. Must be left disconnected.

Test pin. Must be fixed at GND level.

Test pin. Must be left disconnected.

GND

—

VTEST

—

Rev. 1.0, Jan. 2003, page 20 of 102

HD66753

Block Function Description

System Interface

The HD66753 has five high-speed system interfaces: an 80-system 16-bit/8-bit bus, a 68-system 16-bit/8-

bit bus, and a clock-synchronized serial interface. The interface mode is selected by the IM2-0 pins.

The HD66753 has three 16-bit registers: an index register (IR), a write data register (WDR), and a read data

register (RDR). The IR stores index information from the control registers and the CGRAM. The WDR

temporarily stores data to be written into control registers and the CGRAM, and the RDR temporarily

stores data read from the CGRAM. Data written into the CGRAM from the MPU is first written into the

WDR and then is automatically written into the CGRAM by internal operation. Data is read through the

RDR when reading from the CGRAM, and the first read data is invalid and the second and the following

data are normal (for the serial interface, the 5-byte data is invalid). When a logic operation is performed

inside of the HD66753 by using the display data set in the CGRAM and the data written from the MPU, the

data read through the RDR is used. Accordingly, the MPU does not need to read data twice nor to fetch the

read data into the MPU. This enables high-speed processing.

Execution time for instruction excluding oscillation start is 0 clock cycle and instructions can be written in

succession.

Table 3

Register Selection

R/W Bits

RS Bits

Operations

0

1

0

1

0

1

Writes indexes into IR

Status read

Writes into control registers and CGRAM through WDR

Reads from CGRAM through RDR

Bit Operation

The HD66753 supports the following functions: a bit rotation function that writes the data written from the

MPU into the CGRAM by moving the display position in bit units, a write data mask function that selects

and writes data into the CGRAM in bit units, and a logic operation function that performs logic operations

on the display data set in the CGRAM and writes into the CGRAM. With the 16-bit bus interface, these

functions can greatly reduce the processing loads of the MPU graphics software and can rewrite the display

data in the CGRAM at high speed. For details, see the Graphics Operation Function section.

Address Counter (AC)

The address counter (AC) assigns addresses to the CGRAM. When an address set instruction is written into

the IR, the address information is sent from the IR to the AC.

After writing into the CGRAM, the AC is automatically incremented by 1 (or decremented by 1). After

reading from the data, the RDM bit automatically updates or does not update the AC.

Rev. 1.0, Jan. 2003, page 21 of 102

HD66753

Graphic RAM (CGRAM)

The graphic RAM (CGRAM) stores bit-pattern data of 168 x 132 dots. It has two bits/pixel and 5,544-byte

capacity.

Grayscale Control Circuit

The grayscale control circuit performs four-grayscale control with the frame rate control (FRC) method for

four-monochrome grayscale display. For details, see the Four Grayscale Display Function section.

Timing Generator

The timing generator generates timing signals for the operation of internal circuits such as the CGRAM.

The RAM read timing for display and internal operation timing by MPU access are generated separately to

avoid interference with one another.

Oscillation Circuit (OSC)

The HD66753 can provide R-C oscillation simply through the addition of an external oscillation-resistor

between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display

size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be

supplied externally. Since R-C oscillation stops during the standby mode, current consumption can be

reduced. For details, see the Oscillation Circuit section.

Liquid Crystal Display Driver Circuit

The liquid crystal display driver circuit consists of 132 common signal drivers (COM1 to COM132) and

168 segment signal drivers (SEG1 to SEG168). When the number of lines are selected by a program, the

required common signal drivers automatically output drive waveforms, while the other common signal

drivers continue to output unselected waveforms.

Display pattern data is latched when 168-bit data has arrived. The latched data then enables the segment

signal drivers to generate drive waveform outputs. The shift direction of 168-bit data can be changed by the

SGS bit. The shift direction for the common driver can also be changed by the CMS bit by selecting an

appropriate direction for the device mounting configuration.

When multiplexing drive is not used, or during the standby or sleep mode, all the above common and

segment signal drivers output the GND level, halting the display.

Step-up Circuit (DC-DC Converter)

The step-up generates three-, five-, six-, or seven-times voltage input to the Vci pin. With this, both the

internal logic units and LCD drivers can be controlled with a single power supply. Step-up output level

from three-times to seven-times step-up can be selected by software. For details, see the Liquid Crystal

Display Voltage Generator section.

Rev. 1.0, Jan. 2003, page 22 of 102

HD66753

V-Pin Voltage Follower

A voltage follower for each voltage level (V1 to V5) reduces current consumption by the LCD drive power

supply circuit. No external resistors are required because of the internal bleeder-resistor, which generates

different levels of LCD drive voltage. This internal bleeder-resistor can be software-specified from 1/4 bias

to 1/11 bias, according to the liquid crystal display drive duty value. The voltage followers can be turned

off while multiplexing drive is not being used. For details, see the Power Supply for Liquid Crystal Display

Drive section.

Contrast Adjuster

The contrast adjuster can be used to adjust LCD contrast in 128 steps by varying the LCD drive voltage by

software. This can be used to select an appropriate LCD brightness or to compensate for temperature.

LCD-Drive Power-Supply Regulator Circuit

The LCD-drive power-supply regulator circuit generates an LCD-drive voltage from the reference voltage

that does not depend on the LCD load current. Change of the LCD-drive voltage is controlled for the LCD

load current. For details, see the Liquid Crystal Display Voltage Generator section.

Rev. 1.0, Jan. 2003, page 23 of 102

HD66753

CGRAM Address Map

Table 4

Relationships between the CGRAM Address and the Display Screen Position

Table 5

Relationships between the CGRAM Data and the Display Contents

Upper Bit

Lower Bit

LCD

0

1

0

1

0

1

Non-selection display (unlit)

1/4-, 1/3- or 2/4-level grayscale display (selected by the GSL1-0 bits)

2/4-, 2/3-, or 3/4-level grayscale display (selected by the GSH1-0 bits)

Selection display (lit)

Note: Upper bits: DB15, DB13, DB11, DB9, DB7, DB5, DB3, DB1

Lower bits: DB14, DB12, DB10, DB8, DB6, DB4, DB2, DB0

Rev. 1.0, Jan. 2003, page 24 of 102

HD66753

Instructions

Outline

The HD66753 uses the 16-bit bus architecture. Before the internal operation of the HD66753 starts, control

information is temporarily stored in the registers described below to allow high-speed interfacing with a

high-performance microcomputer. The internal operation of the HD66753 is determined by signals sent

from the microcomputer. These signals, which include the register selection signal (RS), the read/write

signal (R/W), and the data bus signals (DB15 to DB0), make up the HD66753 instructions. There are seven

categories of instructions that:

•

Specify the index

Read the status

Control the display

Control power management

Process the graphics data

Set internal CGRAM addresses

Transfer data to and from the internal CGRAM

Normally, instructions that write data are used the most. However, an auto-update of internal CGRAM

addresses after each data write can lighten the microcomputer program load.

Because instructions are executed in 0 cycles, they can be written in succession.

Rev. 1.0, Jan. 2003, page 25 of 102

HD66753

Instruction Descriptions

Index (IR)

The index instruction specifies the RAM control and control register indexes (R00 to R12). It sets the

register number in the range of 00000 to 10010 in binary form.

R/W

0

RS

0

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

*

ID4 ID3 ID2 ID1 ID0

Figure 1 Index Instruction

Status Read (SR)

The status read instruction reads the internal status of the HD66753.

L7–0: Indicate the driving raster-row position where the liquid crystal display is being driven.

C6–0: Read the contrast setting values (CT6–0).

R/W

1

RS

0

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

L7

L6

L5

L4

L3

L2

L1

L0

0

C6

C5

C4 C3

C2

C1 C0

Figure 2 Status Read Instruction

Start Oscillation (R00)

The start oscillation instruction restarts the oscillator from the halt state in the standby mode. After issuing

this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (See the

Standby Mode section.)

If this register is read forcibly as R/W = 1, 0753H is read.

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

*

1

0

1

0

1

0

1

0

1

0

Figure 3 Start Oscillation Instruction

Rev. 1.0, Jan. 2003, page 26 of 102

HD66753

Driver Output Control (R01)

CMS: Selects the output shift direction of a common driver. When CMS = 0, COM1/132 shifts to COM1,

and COM132/1 to COM132. When CMS = 1, COM1/132 shifts to COM132, and COM132/1 to COM1.

SGS: Selects the output shift direction of a segment driver. When SGS = 0, SEG1/168 shifts to SEG1, and

SEG168/1 to SEG168. When SGS = 1, SEG1/168 shifts to SEG128, and SEG168/1 to SEG1.

NL4-0: Specify the LCD drive duty ratio. The duty ratio can be adjusted for every eight raster-rows.

CGRAM address mapping does not depend on the setting value of the drive duty ratio.

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

*

CMS SGS

*

NL4 NL3 NL2 NL1 NL0

Figure 4 Driver Output Control Instruction

NL Bits and Drive Duty

Table 6

NL4 NL3 NL2 NL1 NL0 Display Size

LCD Drive Duty

1/8 Duty

Common Driver Used

COM1–COM8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

168 x 8 dots

168 x 16 dots

168 x 24 dots

168 x 32 dots

168 x 40 dots

168 x 48 dots

168 x 56 dots

168 x 64 dots

168 x 72 dots

168 x 80 dots

168 x 88 dots

168 x 96 dots

168 x 104 dots

168 x 112 dots

168 x 120 dots

168 x 128 dots

168 x 132 dots

1/16 Duty

1/24 Duty

1/32 Duty

1/40 Duty

1/48 Duty

1/56 Duty

1/64 Duty

1/72 Duty

1/80 Duty

1/88 Duty

1/96 Duty

1/104 Duty

1/112 Duty

1/120 Duty

1/128 Duty

1/132 Duty

COM1–COM16

COM1–COM24

COM1–COM32

COM1–COM40

COM1–COM48

COM1–COM56

COM1–COM64

COM1–COM72

COM1–COM80

COM1–COM88

COM1–COM96

COM1–COM104

COM1–COM112

COM1–COM120

COM1–COM128

COM1–COM132

Rev. 1.0, Jan. 2003, page 27 of 102

HD66753

LCD-Driving-Waveform Control (R02)

B/C: When B/C = 0, a B-pattern waveform is generated and alternates in every frame for LCD drive.

When B/C = 1, a C-pattern waveform is generated and alternates in each raster-row specified by bits EOR

and NW4–NW0 in the LCD-driving-waveform control register. For details, see the n-raster-row Reversed

AC Drive section.

EOR: When the C-pattern waveform is set (B/C = 1) and EOR = 1, the odd/even frame-select signals and

the n-raster-row reversed signals are EORed for alternating drive. EOR is used when the LCD is not

alternated by combining the set values of the LCD drive duty ratio and the n raster-row. For details, see the

n-raster-row Reversed AC Drive section.

NW4–0: Specify the number of raster-rows n that will alternate at the C-pattern waveform setting (B/C =

1). NW4–NW0 alternate for every set value + 1 raster-row, and the first to the 32nd raster-rows can be

selected.

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

*

B/C EOR NW4 NW3 NW2 NW1 NW0

Figure 5 LCD-Driving-Waveform Control Instruction

Power Control (R03)

BS2–0: The LCD drive bias value is set within the range of a 1/4 to 1/11 bias. The LCD drive bias value

can be selected according to its drive duty ratio and voltage. For details, see the Liquid Crystal Display

Drive Bias Selector section.

BT1-0: The output factor of VLOUT between two-times, three-times, four-times, five-times, six-times, and

seven-times step-up is switched. The LCD drive voltage level can be selected according to its drive duty

ratio and bias. Lower amplification of the step-up circuit consumes less current.

PS1-0: Using the internal or external power supply is selected as the reference voltage for the LCD drive

voltage generator.

DC1-0: The operating frequency in the step-up circuit is selected. When the step-up operating frequency is

high, the driving ability of the step-up circuit and the display quality become high, but the current

consumption is increased. Adjust the frequency considering the display quality and the current

consumption.

AP1-0: The amount of fixed current from the fixed current source in the operational amplifier for V pins

(V1 to V5) is adjusted. When the amount of fixed current is large, the LCD driving ability and the display

quality become high, but the current consumption is increased. Adjust the fixed current considering the

display quality and the current consumption.

During no display, when AP1–0 = 00, the current consumption can be reduced by ending the operational

amplifier and step-up circuit operation.

Rev. 1.0, Jan. 2003, page 28 of 102

HD66753

Table 7

BS Bits and LCD Drive Bias Value

BS2

0

BS1

BS0

0

LCD Drive Bias Value

0

1

0

1

1/11 bias drive

1/10 bias drive

1/9 bias drive

1/8 bias drive

1/7 bias drive

1/6 bias drive

1/5 bias drive

1/4 bias drive

0

1

0

1

0

1

0

1

Table 8

BT Bits and Output Level

BT1

0

BT0

0

VLOUT Output Level

Three-times step-up

Five-times step-up

Six-times step-up

0

1

0

1

Seven-times step-up

Table 9

DC Bits and Operating Clock Frequency

DC1

DC0

Operating Clock Frequency in the Step-up Circuit

0

1

0

1

0

1

32-divided clock

16-divided clock

8-divided clock

Setting inhibited

Table 10

AP Bits and Amount of Fixed Current

AP1

AP0

Amount of Fixed Current in the Operational Amplifier

0

1

0

1

0

1

Operational amplifier and booster do not operate.

Small

Middle

Large

Rev. 1.0, Jan. 2003, page 29 of 102

HD66753

Table 11

PS Bits and Reference Power Supply

Switching the Reference Power Supply for the LCD Voltage Generator

VLREF

V1REF-VLREF

PS1

PS0

VREG Pin

V1REF Pin

VLREF Pin

Regulator

Switch

0

Input

Output from

regulator

Input (internal short

between V1REF

and VLREF)

Used

On

0

1

0

1

Input

Open

Output from

regulator

Input

Used

Halt

Off

Open

Input (from external

power supply)

Setting inhibited

SLP: When SLP = 1, the HD66753 enters the sleep mode, where the internal display operations are halted

except for the R-C oscillator, thus reducing current consumption. For details, see the Sleep Mode section.

Only the following instructions can be executed during the sleep mode.

Power control (BS2–0, BT1–0, DC1–0, AP1–0, SLP, and STB bits)

During the sleep mode, the other CGRAM data and instructions cannot be updated although they are

retained.

STB: When STB = 1, the HD66753 enters the standby mode, where display operation completely stops,

halting all the internal operations including the internal R-C oscillator. Further, no external clock pulses

are supplied. For details, see the Standby Mode section.

Only the following instructions can be executed during the standby mode.

a. Standby mode cancel (STB = 0)

b. Start oscillation

c. Power control (BS2–0, BT1–0, DC1–0, AP1–0, SLP, and STB bits)

During the standby mode, the CGRAM data and instructions may be lost. To prevent this, they must be set

again after the standby mode is canceled.

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

*

BS2 BS1 BS0 BT1 BT0 PS1 PS0 DC1 DC0 AP1 AP0 SLP STB

Figure 6 Power Control Instruction

Rev. 1.0, Jan. 2003, page 30 of 102

HD66753

Contrast Control (R04)

CT6–0: These bits control the LCD drive voltage (potential difference between V1 and GND) to adjust

128-step contrast. For details, see the Contrast Adjuster section.

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

*

VR2 VR1 VR0

*

CT6 CT5 CT4 CT3 CT2 CT1 CT0

Figure 7 Contrast Control Instruction

HD66753

V

LREF

VR

+

-

V1

V2

V3

R

+

-

+

-

R0

+

-

V4

V5

R

+

-

GND

Figure 8 Contrast Adjuster

CT Bits and Variable Resistor Value of Contrast Adjuster

Table 12

CT Set Value

Variable

CT6

0

CT5

CT4

0

CT3

0

CT2

0

CT1

0

CT0

0

Resistor (VR)

0

6.40 x R

6.35 x R

6.30 x R

6.25 x R

6.20 x R

•

0

1

0

1

0

1

0

1

0

•

1

0

1

0

1

0

1

1.20 x R

0.15 x R

0.10 x R

0.05 x R

1

Rev. 1.0, Jan. 2003, page 31 of 102

HD66753

VR2–0: These bits adjust the output voltage (V1REF) for the LCD-drive reference voltage generator

within the 2.8- to 6.5-times ranges of Vreg (Vci or VREG pin input voltage).

Table 13

VR Bits and V1REF Voltages

VR2

0

VR1

VR0

0

V1REF Voltage Setting

0

1

0

1

Vreg x 2.8

Vreg x 3.5

Vreg x 4.0

Vreg x 4.5

Vreg x 5.0

Vreg x 5.5

Vreg x 6.0

Vreg x 6.5

0

1

0

1

0

1

0

1

Entry Mode (R05)

Rotation (R06)

The write data sent from the microcomputer is modified in the HD66753 and written to the CGRAM. The

display data in the CGRAM can be quickly rewritten to reduce the load of the microcomputer software

processing. For details, see the Graphics Operation Function section.

I/D: When I/D = 1, the address counter (AC) is automatically incremented by 1 after the data is written to

the CGRAM. When I/D = 0, the AC is automatically decremented by 1 after the data is written to the

CGRAM.

AM1–0: Set the automatic update method of the AC after the data is written to the CGRAM. When AM1–

0 = 00, the data is continuously written in parallel. When AM1–0 = 01, the data is continuously written

vertically. When AM1–0 = 10, the data is continuously written vertically with two-word width (32-bit

length).

LG1–0: Write again the data read from the CGRAM and the data written from the microcomputer to the

CGRAM by a logical operation. When LG1–0 = 00, replace (no logical operation) is done. ORed when

LG1–0 = 01, ANDed when LG1–0 = 10, and EORed when LG1–0 = 11.

RT2–0: Write the data sent from the microcomputer to the CGRAM by rotating in a bit unit. RT3–0

specify rotation. For example, when RT2–0 = 001, the data is rotated in the upper side by two bits. When

RT2–0 = 111, the data is rotated in the upper side by 14 bits. The upper bit overflown in the most

significant bit (MSB) side is rotated in the least significant bit (LSB) side.

Rev. 1.0, Jan. 2003, page 32 of 102

HD66753

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

*

I/D AM1 AM0 LG1 LG0

0

1

*

RT2 RT1 RT0

Figure 9 Entry Mode and Rotation Instructions

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Write data sent

from the

0

1

0

1

0

1

microcomputer

(DB15-0)

Rotation

(RT2-0 = 001)

1

0

1

0

1

0

Logical operation LG1-0 = 00: Replace

LG1-0 = 01: ORed

Logical operation

(LG1-0)

LG1-0 = 10: ANDed

LG1-0 = 11: EORed

Write data mask*

(WM15-0)

Write data mask (WM15-0)

CGRAM

Note: The write data mask (WM15-0) is set by the register in the RAM Write Data Mask section.

Figure 10 Logical Operation and Rotation for the CGRAM

Display Control (R07)

SPT: When SPT = 01, the 2-division LCD drive is performed. For details, see the Division Screen Drive

section.

GSH1-0: When GS = 0, the grayscale level at a brightly-colored display (when DB = 10) is selected. For

details, see the 4-Grayscale Display Function section.

GSL1-0: The grayscale level at a weakly-colored display (when DB = 01) is selected.

Rev. 1.0, Jan. 2003, page 33 of 102

HD66753

Table 14

GSH Bits and Output Level

GSH1

GSH0

Grayscale Output Level (DB = 10)

0

1

0

1

0

1

3/4 level grayscale control

2/3 level grayscale control

2/4 level grayscale control

Lit (No grayscale control)

Table 15

GSL Bits and Output Level

GSL1

GSL0

Grayscale Output Level (DB = 01)

0

1

0

1

0

1

1/4 level grayscale control

1/3 level grayscale control

2/4 level grayscale control

Lit (No grayscale control)

REV: Displays all character and graphics display sections with black-and-white reversal when REV = 1.

For details, see the Reversed Display Function section.

D: Display is on when D = 1 and off when D = 0. When off, the display data remains in the CGRAM, and

can be displayed instantly by setting D = 1. When D is 0, the display is off with the SEG1 to SEG168

outputs and COM1 to COM132 outputs set to the GND level. Because of this, the HD66753 can control the

charging current for the LCD with AC driving.

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

GS GS GS GS

DB1 DB0

*

SPT

*

REV

D

H1 H0

L1

L0

Figure 11 Display Control Instruction

Cursor Control (R08)

C: When C = 1, the window cursor display is started. The display mode is selected by the CM1–0 bits, and

the display area is specified in a dot unit by the horizontal cursor position register (HS6–0 and HE6–0 bits)

and vertical cursor position register (VS6–0 and VE6–0 bits). For details, see the Window Cursor Display

section.

CM1–0: The display mode of the window cursor is selected. These bits can display a white-blink cursor,

black-blink cursor, black-and-white reversed cursor, and black-and-white-reversed blink cursor.

Rev. 1.0, Jan. 2003, page 34 of 102

HD66753

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5

DB4 DB3 DB2 DB1 DB0

*

C

CM1 CM0

Figure 12 Cursor Control Instruction

Table 16

CM Bits and Window Cursor Display Mode

CM1 CM0 Window Cursor Display Mode

0

1

0

1

0

1

White-blink cursor (alternately blinking between the normal display and an all-white

display (all unlit))

Black-blink cursor (alternately blinking between the normal display and an all-black

display (all lit))

Black-and-white reversed cursor (black-and-white-reversed normal display (no

blinking))

Black-and-white-reversed blink cursor (alternately blinking the black-and-white-

reversed normal display)

Horizontal Cursor Position (R0B)

Vertical Cursor Position (R0C)

HS7-0: Specify the start position for horizontally displaying the window cursor in a dot unit. The cursor is

displayed from the 'set value + 1' dot. Ensure that HS7–0 ≤ HE7–0.

HE7-0: Specify the end position for horizontally displaying the window cursor in a dot unit. The cursor is

displayed to the 'set value + 1' dot. Ensure that HS7–0 ≤ HE7–0.

VS7-0: Specify the start position for vertically displaying the window cursor in a dot unit. The cursor is

displayed from the 'set value + 1' dot. Ensure that VS7–0 ≤ VE7–0.

VE7-0: Specify the end position for vertically displaying the window cursor in a dot unit. The cursor is

displayed to the 'set value + 1' dot. Ensure that VS7–0 ≤ VE7–0.

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

HE7 HE6 HE5 HE4 HE3 HE2 HE1 HE0 HS7 HS6 HS5 HS4 HS3 HS2 HS1 HS0

0

1

VE7 VE6 VE5 VE4 VE3 VE2 VE1 VE0 VS7 VS6 VS5 VS4 VS3 VS2 VS1 VS0

Figure 13 Horizontal Cursor Position and Vertical Cursor Position Instructions

Rev. 1.0, Jan. 2003, page 35 of 102

HD66753

HS1+1

HE1+1

VS1+1

VE1+1

Window

cursor

Figure 14 Window Cursor Position

1st Screen Driving Position (R0D)

2nd Screen Driving Position (R0E)

SS17-10: Specify the driving start position for the first screen in a line unit. The LCD driving starts from

the 'set value + 1' common driver.

SE17-10: Specify the driving end position for the first screen in a line unit. The LCD driving is performed

to the 'set value + 1' common driver. For instance, when SS17-10 = 07H and SE17-10 = 10H are set, the

LCD driving is performed from COM8 to COM17, and non-selection driving is performed for COM1 to

COM7, COM18, and others. Ensure that SS17–10 ≤ SE17–10 ≤ 83H. For details, see the Screen Division

Driving Function section.

SS27-20: Specify the driving start position for the second screen in a line unit. The LCD driving starts

from the 'set value + 1' common driver. The second screen is driven when SPT = 1.

SE27-20: Specify the driving end position for the second screen in a line unit. The LCD driving is

performed to the 'set value + 1' common driver. For instance, when SPT = 1, SS27-20 = 20H, and SE27-20

= 5FH are set, the LCD driving is performed from COM33 to COM96 and the non-selected driving is

performed from COM1 to COM7 and COM18 and followings. Ensure that SS17–10 ≤ SE17–10 < SS27–

20 ≤ SE27–20 ≤ 83H. For details, see the Screen Division Driving Function section.

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10

SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20

0

1

Figure 15 1st Screen Driving Position and 2nd Screen Driving Position

Rev. 1.0, Jan. 2003, page 36 of 102

HD66753

RAM Write Data Mask (R10)

WM15-0: In writing to the CGRAM, these bits mask writing in a bit unit. When WM15 = 1, this bit masks

the write data of DB15 and does not write to the CGRAM. Similarly, the WM14–0 bits mask the write

data of DB14–0 in a bit unit. However, when AM = 10, the write data is masked with the set values of

WM15–0 for the odd-times CGRAM write. It is also masked automatically with the reversed set values of

WM15–0 for the even-times CGRAM write. For details, see the Graphics Operation Function section.

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Figure 16 RAM Write Data Mask Instruction

RAM Address Set (R11)

AD12-0: Initially set CGRAM addresses to the address counter (AC). Once the CGRAM data is written,

the AC is automatically updated according to the AM1–0 and I/D bit settings. This allows consecutive

accesses without resetting addresses. Once the CGRAM data is read, the AC is not automatically updated.

CGRAM address setting is not allowed in the sleep mode or standby mode.

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AD AD AD

*

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

12

11

10

Figure 17 RAM Address Set Instruction

Table 17

AD Bits and CGRAM Settings

AD12–AD0

CGRAM Setting

"0000"H–"0014"H

"0020"H–"0034"H

"0040"H–"0054"H

"0060"H–"0074"H

"0080"H–"0094"H

"00A0"H–"00B4"H

:

Bitmap data for COM1

Bitmap data for COM2

Bitmap data for COM3

Bitmap data for COM4

Bitmap data for COM5

Bitmap data for COM6

:

"0FC0"H–"0FD4"H

"0FE0"H–"0FF4"H

"1000"H–"1014"H

"1020"H–"1034"H

"1040"H–"1054"H

"1060"H–"1074"H

Bitmap data for COM127

Bitmap data for COM128

Bitmap data for COM129

Bitmap data for COM130

Bitmap data for COM131

Bitmap data for COM132

Rev. 1.0, Jan. 2003, page 37 of 102

HD66753

Write Data to CGRAM (R12)

WD15-0 : Write 16-bit data to the CGRAM. After a write, the address is automatically updated according

to the AM1–0 and I/D bit settings. During the sleep and standby modes, the CGRAM cannot be accessed.

R/W

0

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Figure 18 Write Data to CGRAM Instruction

Read Data from CGRAM (R12)

RD15-0 : Read 16-bit data from the CGRAM. When the data is read to the microcomputer, the first-word

read immediately after the CGRAM address setting is latched from the CGRAM to the internal read-data

latch. The data on the data bus (DB15–0) becomes invalid and the second-word read is normal.

When bit processing, such as a logical operation, is performed within the HD66753, only one read can be

processed since the latched data in the first word is used.

For the clock-synchronized serial interface, the 5-byte data is invalid. For details, see the Serial Data

Transfer section.

R/W

1

RS

1

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6

DB5 DB4 DB3 DB2 DB1 DB0

RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Figure 19 Read Data from CGRAM Instruction

Rev. 1.0, Jan. 2003, page 38 of 102

HD66753

Sets the I/D and AM1-0 bits

Address: N set

Sets the I/D and AM1-0 bits

Address: N set

Dummy read (invalid data)

CGRAM -> Read-data latch

Dummy read (invalid data)

CGRAM -> Read-data latch

First word

Read (data of address n)

Read-data latch -> DB15-0

Read (data of address n)

DB15-0 -> CGRAM

Second word

Address: M set

Automatic address update: N + α

Dummy read (invalid data)

CGRAM -> Read-data latch

Dummy read (invalid data)

CGRAM -> Read-data latch

First word

Read (data of address)

Write (data of address N + α)

Second word

Read-data latch -> DB15-0

DB15-0 -> CGRAM

i) Data read to the microcomputer

ii) Logical operation processing in the HD66753

Figure 20 CGRAM Read Sequence

Rev. 1.0, Jan. 2003, page 39 of 102

HD66753

Table 18 Instruction List

Upper Code

Lower Code

Reg. Register

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB

No.

Name

R/W RS 15 14 13 12 11 10

9

8

7

*

6

5

4

3

2

1

0

IR

Index

0

1

0

1

*

ID4 ID3 ID2 ID1 ID0

SR Status read

L7 L6 L5 L4 L3 L2 L1 L0

0

*

C6 C5 C4 C3 C2 C1 C0

R00 Start

oscillation

*

1

Device code

read

1

0

1

0

*

0

*

0

*

0

*

0

*

1

*

1

0

1

*

0

*

1

0

1

R01 Driver output

control

CMS SGS *

NL4 NL3 NL2 NL1 NL0

R02 LCD-driving-

waveform

*

B/C EOR NW NW NW NW NW

4

3

2

1

0

control

R03 Power control

0

1

*

BS2 BS1 BS0 BT1 BT0 PS1 PS0 DC DC AP1 AP0 SLP STB

1

0

R04 Contrast

control

*

VR2 VR1 VR0 *

CT6 CT5 CT4 CT3 CT2 CT1 CT0

R05 Entry mode

*

I/D AM AM LG1 LG0

1

0

R06 Rotation

1

*

RT2 RT1 RT0

R07 Display control 0

SPT *

GSH GSH GSL GSL REV D

1

0

1

0

R08 Cursor control

0

1

*

C

CM CM

1

0

R09 NOOP

R0A NOOP

0

1

*

R0B Horizontal

cursor position

HE7 HE6 HE5 HE4 HE3 HE2 HE1 HE0 HS7 HS6 HS5 HS4 HS3 HS2 HS1 HS0

R0C Vertical cursor 0

position

1

VE7 VE6 VE5 VE4 VE3 VE2 VE1 VE0 VS7 VS6 VS5 VS4 VS3 VS2 VS1 VS0

R0D 1st screen

driving position

0

1

SE SE SE SE SE SE SE SE SS SS SS SS SS SS SS SS

17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10

R0E 2nd screen

driving position

SE SE SE SE SE SE SE SE SS SS SS SS SS SS SS SS

27 26 25 24 23 22 21 20 27 26 25 24 23 22 21 20

R10 RAM write

data mask

WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

R11 RAM address

set

*

AD12-8

(upper))

AD7-0 (lower)

R12 RAM data

write

Write data (upper)

Write data (lower)

Read data (lower)

RAM data

read

Read data (upper)

Note: '*' means 'doesn't matter'.

Rev. 1.0, Jan. 2003, page 40 of 102

HD66753

Table 18 Instruction List (cont)

Reg. Register Name

Execution

Cycle

No.

Description

IR

Index

Sets the index register value.

0

SR Status read

Reads the driving raster-row position (L7-0) and contrast setting (C6-0). 0

Starts the oscillation mode. 10 ms

R00 Start

oscillation

Device code Reads 0753H.

read

0

R01 Driver output Sets the common driver shift direction (CMS), segment driver shift

control direction (SGS), and driving duty ratio (NL4-0).

R02 LCD-driving- Sets the LCD drive AC waveform (B/C), and EOR output (EOR) or the

waveform

control

number of n-raster-rows (NW4-0) at C-pattern AC drive.

R03 Power control Sets the sleep mode (SLP), standby mode (STB), LCD power on (AP1-

0), boosting cycle (DC1-0), boosting output multiplying factor (BT1-0),

0

reference power supply (PS1-0), and LCD drive bias value (BS2-0).

R04 Contrast

control

Sets the contrast adjustment (CT6-0) and regulator adjustment (VR2-0). 0

R05 Entry mode

Specifies the logical operation (LG1-0), AC counter mode (AM1-0), and

increment/decrement mode (I/D).

0

R06 Rotation

Specifies the amount of write-data rotation (RT2-0).

0

R07 Display

control

Specifies display on (D), black-and-white reversed display (REV),

grayscale mode (GS), double-height display on (DHE), and partial scroll

(PS1-0).

R08 Cursor control Specifies cursor display on (C) and cursor display mode (CM1-0).

0

R09 NOOP

R0A NOOP

No operation

R0B Horizontal

cursor

Sets horizontal cursor start (HS6-0) and end (HE6-0).

position

R0C Vertical cursor Sets vertical cursor start (VS6-0) and end (VE6-0).

position

0

R0D 1st screen

driving

Sets 1st screen driving start (SS17-10) and end (SE17-10).

Sets 2nd screen driving start (SS27-20) and end (SE27-20).

Specifies write data mask (WM15-0) at RAM write.

position

R0E 2nd screen

driving

0

position

R10 RAM write

data mask

0

R11 RAM address Initially sets the RAM address to the address counter (AC).

set

R12 RAM data

write

Writes data to the RAM.

RAM data

read

Reads data from the RAM.

Rev. 1.0, Jan. 2003, page 41 of 102

HD66753

Reset Function

The HD66753 is internally initialized by RESET input. Because the busy flag (BF) indicates a busy state

(BF = 1) during the reset period, no instruction or CGRAM data access from the MPU is accepted. The

reset input must be held for at least 1 ms. Do not access the CGRAM or initially set the instructions until

the R-C oscillation frequency is stable after power has been supplied (10 ms).

Instruction Set Initialization:

1. Start oscillation executed

2. Driver output control (NL4–0 = 10000, SGS = 0, CMS = 0)

3. B-pattern waveform AC drive (B/C = 0, ECR = 0, NW4–0 = 00000)

4. Power control (PS1–0 = 00, DC1–0 = 00, AP1–0 = 00: LCD power off, SLP = 0: Sleep mode off, STB

= 0: Standby mode off)

5. 1/11 bias drive (BS2–0 = 000), Three-times step-up (BT1–0 = 00), Weak contrast (CT6–0 = 0000000),

2.8-times output voltage for LCD-drive reference voltage generator (VR2–0 = 000)

6. Entry mode set (I/D = 1: Increment by 1, AM1–0 = 00: Horizontal move, LG1–0 = 00: Replace mode)

7. Rotation (RT2–0 = 000: No shift)

8. Display control (SPT = 0: GSH1-0 = GSL1-0 = 00, REV = 0, GS = 0, D = 0: Display off)

9. Cursor control (C = 0: Cursor display off, CM1–0 = 00)

10. 1st screen division (SS17–10 = 00000000, SE17–10 = 00000000)

11. 2nd screen division (SS27–20 = 00000000, SE27–20 = 00000000)

12. Window cursor display position (HS7–0 = HE7–0 = VS7–0 = VE7–0 = 00000000)

13. RAM write data mask (WM15–0 = 0000H: No mask)

14. RAM address set (AD12–0 = 000H)

CGRAM Data Initialization:

This is not automatically initialized by reset input but must be initialized by software while display is off

(D = 0).

Output Pin Initialization:

1. LCD driver output pins (SEG/COM): Outputs GND level

2. Step-up circuit output pins (VLOUT): Outputs Vcc level

3. Oscillator output pin (OSC2): Outputs oscillation signal

Rev. 1.0, Jan. 2003, page 42 of 102

HD66753

Parallel Data Transfer

16-bit Bus Interface

Setting the IM2/1/0 (interface mode) to the GND/GND/GND level allows 68-system E-clock-synchronized

16-bit parallel data transfer. Setting the IM2/1/0 to the GND/Vcc/GND level allows 80-system 16-bit

parallel data transfer. When the number of buses or the mounting area is limited, use an 8-bit bus interface.

CSn*

A1

CS*

RS

H8/2245

HD66753

HWR*

(RD*)

WR*

(RD*)

DB15 - DB0

D15 - D0

16

Figure 21 Interface to 16-bit Microcomputer

8-bit Bus Interface

Setting the IM2/1/0 (interface mode) to the GND/GND/Vcc level allows 68-system E-clock-synchronized

8-bit parallel data transfer using pins DB15–DB8. Setting the IM2/1/0 to the GND/Vcc/Vcc level allows

80-system 8-bit parallel data transfer. The 16-bit instructions and RAM data are divided into eight

upper/lower bits and the transfer starts from the upper eight bits. Fix unused pins DB7–DB0 to the Vcc or

GND level. Note that the upper bytes must also be written when the index register is written to.

CSn*

A1

CS*

RS

H8/2245

HD66753

HWR*

(RD*)

WR*

(RD*)

D15 - D8

DB15 - DB8

DB7 - 0

8

GND

Figure 22 Interface to 8-bit Microcomputer

Note: Transfer synchronization function for an 8-bit bus interface

The HD66753 supports the transfer synchronization function which resets the upper/lower counter

to count upper/lower 8-bit data transfer in the 8-bit bus interface. Noise causing transfer mismatch

between the eight upper and lower bits can be corrected by a reset triggered by consecutively

writing a 00H instruction four times. The next transfer starts from the upper eight bits. Executing

synchronization function periodically can recover any runaway in the display system.

Rev. 1.0, Jan. 2003, page 43 of 102

HD66753

RS

R/W

E

00H

(1)

00H

(2)

00H

(3)

00H

(4)

Upper/

lower

DB15-DB8

Upper

Lower

(8-bit transfer synchronization)

Figure 23 8-bit Transfer Synchronization

Rev. 1.0, Jan. 2003, page 44 of 102

HD66753

Serial Data Transfer

Setting the IM1 and IM2 pins (interface mode pins) to the Vcc or GND level allows standard clock-

synchronized serial data transfer, using the chip select line (CS*), serial data line (SDA), and serial transfer

clock line (SCL). For a serial interface, the IM0/ID pin function uses an ID pin.

The HD66753 initiates serial data transfer by transferring the start byte at the falling edge of CS* input. It

ends serial data transfer at the rising edge of CS* input.

The HD66753 is selected when the 6-bit chip address in the start byte transferred from the transmitting

device matches the 6-bit device identification code assigned to the HD66753. The HD66753, when

selected, receives the subsequent data string. The least significant bit of the identification code can be

determined by the ID pin. The five upper bits must be 01110. Two different chip addresses must be

assigned to a single HD66753 because the seventh bit of the start byte is used as a register select bit (RS):

that is, when RS = 0, an index register can be written to or the status can be read from, and when RS = 1, an

instruction can be written to or the data can be written to or read from RAM. Read or write is selected

according to the eighth bit of the start byte (R/W bit) as shown in table 19.

After receiving the start byte, the HD66753 receives or transmits the subsequent data byte-by-byte. The

data is transferred with the MSB first. Since all the instructions in the HD66753 are configured by 16 bits,

they are internally executed after two bytes have been transferred with the MSB first (DB15-0). The

HD66753 internally receives the first byte as upper eight bits of instructions, and the second byte as lower

eight bits.

Five bytes of RAM read data after the start byte are invalid. The HD66753 starts to read correct RAM data

from the sixth byte.

Table 19

Start Byte Format

Transfer Bit

S

1

2

3

4

5

6

7

8

Start byte format

Transfer start

Device ID code

RS

R/W

0

1

0

ID

Note: ID bit is selected by the IM0/ID pin.

Table 20

RS and R/W Bit Functions

RS

0

R/W

Function

0

1

0

1

Writes index register

Reads status

0

1

Writes instructions and RAM data

Reads RAM data

1

Rev. 1.0, Jan. 2003, page 45 of 102

HD66753

a) Basic Data-transfer Timing through Clock-synchronized Serial Bus Interface

Transfer end

Transfer start

CS*

(Input)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SCL

(Input)

MSB

LSB

SDA

(Input)

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB

15 14 13 12 11 10

DB

0

"0" "1" "1" "1" "0" ID RS RW

9

8

7

6

5

4

3

2

1

Device ID code

Start byte

RS RW

Instruction register set,

instruction, RAM data write

b) Consecutive Data-transfer Timing through Clock-synchronized Serial Bus Interface

CS*

(Input)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

17 18 19 20 21 22 23 24

25 26 27 28 29 30 31 32

SCL

(Input)

SDA

(Input)

Upper 8 bits of

instruction 1

Lower 8 bits of

instruction 1

Upper 8 bits of

instruction 2

Start byte

Execution time for

instruction 1

Start

End

Note: The first byte after the start byte should be upper 8 bits.

c) RAM Data Read-transfer Timing

CS*

(Input)

SCL

(Input)

Start byte

RS="1",

R/W="1"

SDA

(Input)

Upper 8 bits of

RAM read

Lower 8 bits of

RAM read

Dummy read 1

Dummy read 2 Dummy read 3

Dummy read 4

Dummy read 5

Start

End

Note: Five bytes of the RAM read data after the start byte are invalid. The HD66753 starts to read

the correct RAM data from the sixth byte.

d) Status Read/Instruction Read Timing

CS*

(Input)

SCL

(Input)

Start byte

RS="1",

R/W="1"

Start

SDA

(Input)

Upper 8 bits of

status read

Lower 8 bits of

status read

Dummy read 1

End

Note: One byte of the read after the start byte is invalid. The HD66753 starts to read

the correct data from the second byte.

Figure 24 Clock-synchronized Serial Interface Timing Sequence

Rev. 1.0, Jan. 2003, page 46 of 102

HD66753

Graphics Operation Function

The HD66753 can greatly reduce the load of the microcomputer graphics software processing through the

16-bit bus architecture and graphics-bit operation function. This function supports the following:

1. A write data mask function that selectively rewrites some of the bits in the 16-bit write data.

2. A bit rotation function that shifts and writes the data sent from the microcomputer in a bit unit.

3. A logical operation function that writes the data sent from the microcomputer and the original RAM

data by a logical operation.

Since the display data in the graphics RAM (CGRAM) can be quickly rewritten, the load of the

microcomputer processing can be reduced in the large display screen when a font pattern, such as kanji

characters, is developed for any position (BiTBLT processing).

The graphics bit operation can be controlled by combining the entry mode register, the bit set value of the

RAM-write-data mask register, and the read/write from the microcomputer.

Table 21

Graphics Operation

Bit Setting

Operation Mode

I/D

AM

LG

Operation and Usage

Write mode 1

0/1

00

Horizontal data replacement, horizontal-border

drawing

Write mode 2

0/1

01

10

00

01

10

00

Vertical data replacement, font development, vertical-

border drawing

Write mode 3

00

Vertical data replacement with two-word width, kanji-

font development

Read/write mode 1

Read/write mode 2

Read/write mode 3

01 10 11

Horizontal data replacement with logical operation,

horizontal-border drawing

Vertical data replacement with logical operation,

vertical-border drawing

Horizontal data replacement with two-word-width

logical operation

Rev. 1.0, Jan. 2003, page 47 of 102

HD66753

Microcomputer

16

HD66753

Write-data latch

16

Read-

data

atch

+1/-1

+16

Rotation bit

(RT2-0 )

3

2

Bit rotation

16

00: through

Address

counter

(AC)

Logical

operation

01: OR

Logical operation

10: AND

11: EOR

bit

16

(LG1-0)

16

Write-mask register

(WM15-0)

Write bit mask

16

11

Graphics RAM

(CGRAM)

Figure 25 Data Processing Flow of the Graphics Bit Operation

Rev. 1.0, Jan. 2003, page 48 of 102

HD66753

1. Write mode 1: AM1–0 = 00, LG1–0 = 00

This mode is used when the data is horizontally written at high speed. It can also be used to initialize

the graphics RAM (CGRAM) or to draw borders. The rotation function (RT2–0) or write-data mask

function (WM15–0) are also enabled in these operations. After writing, the address counter (AC)

automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and automatically jumps to the

counter edge one-raster-row below after it has reached the left edge of the graphics RAM.

Operation Examples:

1) I/D = 1, AM1-0 = 00, LG1-0 = 00, RT2-0 = 000

2) WM15-0 = 0000H

3) AC = 0000H

WM0

WM15

DB15

Write data mask:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DB0

Write data (1) :

Write data (2) :

Write data (3) :

1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1

1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0

0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1

0000H

0001H

0002H

1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1

Write data (2)

Write data (3)

Write data (1)

CGRAM

Figure 26 Writing Operation of Write Mode 1

Rev. 1.0, Jan. 2003, page 49 of 102

HD66753

2. Write mode 2: AM1–0 = 01, LG1–0 = 00

This mode is used when the data is vertically written at high speed. It can also be used to initialize the

graphics RAM (CGRAM), develop the font pattern in the vertical direction, or draw borders. The

rotation function (RT2–0) or write-data mask function (WM15–0) are also enabled in these operations.

After writing, the address counter (AC) automatically increments by 20, and automatically jumps to the

upper-right edge (I/D = 1) or upper-left edge (I/D = 0) following the I/D bit after it has reached the

lower edge of the graphics RAM.

Operation Examples:

1) I/D = 1, AM1-0 = 01, LG1-0 = 00, RT2-0 = 010

2) WM15-0 = F007H

3) AC = 0000H

WM0

WM15

Write data mask: 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1

DB0

DB15

4-bit rotation

Write data (1) : 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1

0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 0

1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0

1 1 1 1 0 1 1 1 0 1 0 0 0 0 0 1

Write data (2) : 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0

Write data (3) :

0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1

0000H

0020H

* * * 1 1 0 0 1 1 0 0 1 * * * *

* * * 0 1 1 0 0 0 0 1 1 * * * *

Write data (1)

Write data (2)

0040H

:

1060H

1 0 1 1 1 0 1 0 0

* * *

* * * * Write data (3)

CGRAM

Notes: 1. The bit area data in the RAM indicated by "*" is not changed.

2. After writing to address 1060H, the AC jumps to 0001H.

Figure 27 Writing Operation of Write Mode 2

Rev. 1.0, Jan. 2003, page 50 of 102

HD66753

3. Write mode 3: AM1–0 = 10, LG1–0 = 00

This mode is used when the data is written at high speed by vertically shifting bits. It can also be used

to write the 16-bit data for two words into the graphics RAM (CGRAM), develop the font pattern, or

transfer the BiTBLT as a bit unit. The rotation function (RT2–0) or write-data mask function (WM15–

0) are also enabled in these operation. However, although the write-data mask function masks the bit

position set with the write-data mask register (WM15–0) at the odd-times (such as the first or third)

write, the function masks the bit position that reversed the setting value of the write-data mask register

(WM15–0) at the even-times (such as the second or fourth) write. After the odd-times writing, the

address counter (AC) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0). After the

even-times writing, the AC automatically increments or decrements by –1 + 20 (I/D = 1) or +1 + 20

(I/D = 0). The AC automatically jumps to the upper edge after it has reached the lower edge of the

graphics RAM.

Operation Examples:

1) I/D = 1, AM1-0 = 10, LG1-0 = 00, RT2-0 = 010

2) WM15-0 = 000FH

3) AC = 0000H

WM0

WM15

DB15

Write data mask:

1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

DB0

4-bit rotation

Write data (1) :

Write data (2) :

Write data (3) :

Write data (4) :

Write data (5) :

Write data (6) :

1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0

1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1

1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0

1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1

1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0

0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1

0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0

0000H

0001H

0000H * * * * 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 * * * * * * * * * * * *

0020H * * * * 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 * * * * * * * * * * * *

Write data (1), (2)

Write data (3), (4)

0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0

0040H * * * *

* * * * * * * * * * * * Write data (5), (6)

CGRAM

1060H

Notes: 1. The bit area data in the RAM indicated by "*" is not changed.

2. After writing to address 1061H, the AC jumps to 0001H.

Figure 28 Writing Operation of Write Mode 3

Rev. 1.0, Jan. 2003, page 51 of 102

HD66753

4. Read/Write mode 1: AM1–0 = 00, LG1–0 = 01/10/11

This mode is used when the data is horizontally written at high speed by performing a logical operation

with the original data. It reads the display data (original data), which has already been written in the

graphics RAM (CGRAM), performs a logical operation with the write data sent from the

microcomputer, and rewrites the data to the CGRAM. This mode can read the data during the same bus

cycle as for the write operation since the read operation of the original data does not latch the read data

into the microcomputer and temporarily holds it in the read-data latch. (However, the bus cycle must be

the same as the read cycle.) The rotation function (RT2–0) or write-data mask function (WM15–0) are

also enabled in these operations. After writing, the address counter (AC) automatically increments by 1

(I/D = 1) or decrements by 1 (I/D = 0), and automatically jumps to the counter edge one-raster-row

below after it has reached the left or right edges of the graphics RAM.

Operation Examples:

1) I/D = 1, AM1-0 = 00, LG1-0 = 01 (OR), RT2-0 = 000

2) WM15-0 = 0000H

3) AC = 0000H

WM0

WM15

DB15

Write data mask:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DB0

Read data (1):

Write data (1):

1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1

Logical operation

(OR)

1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1

1 0 1 1 1 1 0 1 0 1 1 0 0 0 1 1

Read data (2):

Write data (2):

0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0

Logical operation

(OR)

1 1 0 0 1 1 1 1 1 0 0 0 1 1 0 0

Read data (3):

Write data (3):

0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 0

0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1

Logical operation

(OR)

0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1

0000H

0001H

0002H

1 0 1 1 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1

Read data (1) + Write data (1) Read data (2) + Write data (2) Read data (3) + Write data (3)

CGRAM

Figure 29 Writing Operation of Read/Write Mode 1

Rev. 1.0, Jan. 2003, page 52 of 102

HD66753

5. Read/Write mode 2: AM1–0 = 01, LG1–0 = 01/10/11

This mode is used when the data is vertically written at high speed by performing a logical operation

with the original data. It reads the display data (original data), which has already been written in the

graphics RAM (CGRAM), performs a logical operation with the write data sent from the

microcomputer, and rewrites the data to the CGRAM. This mode can read the data during the same bus

cycle as for the write operation since the read operation of the original data does not latch the read data

into the microcomputer and temporarily holds it in the read-data latch. The rotation function (RT2–0)

or write-data mask function (WM15–0) are also enabled in these operations. After writing, the address

counter (AC) automatically increments by 20, and automatically jumps to the upper-right edge (I/D = 1)

or upper-left edge (I/D = 0) following the I/D bit after it has reached the lower edge of the graphics

RAM.

Operation Examples:

1) I/D = 1, AM1-0 = 01, LG1-0 = 01 (OR), RT2-0 = 010

2) WM15-0 = FC03H

3) AC = 0000H

WM0

WM15

DB15

Write data mask:

1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1

DB0

1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1

Read data (1):

Write data (1):

4-bit rotation

1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1

0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0

Logical operation (OR)

1 0 0 1 1 0 1 1 1 1 0 0 0 1 1 1

1 1 0 0 1 1 0 0 0 0 1 1 1 0 0 0

0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0

Read data (2):

Write data (2):

4-bit rotation

Logical operation (OR)

1 1 0 0 1 1 1 1 0 0 1 1 1 0 0 0

1 1 1 1 0 1 1 1 0 1 0 0 0 0 0 1

Read data (3):

Write data (3):

0 0 0 0 1 1 1 0 1 1 1 0 0 1 1 0

0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1

Logical operation (OR)

1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1

0000H

0000H * * 0 1 1 0 1 1 1 1 * * * * * *

0001H

Read data (1) + Write data (1)

0020H

0040H

0 0 1 1 1 1 0 0

1 1 1 1 1 1 1 1

* *

* * * * * * Read data (2) + Write data (2)

Read data (3) + Write data (3)

* * * * * *

CGRAM

1060H

Notes: 1. The bit area data in the RAM indicated by "*" is not changed.

2. After writing to address 1060H, the AC jumps to 0001H.

Figure 30 Writing Operation of Read/Write Mode 2

Rev. 1.0, Jan. 2003, page 53 of 102

HD66753

6. Read/Write mode 3: AM1–0 = 10, LG1–0 = 01/10/11

This mode is used when the data is written with high speed by vertically shifting bits and by performing

logical operation with the original data. It can be also used to write the 16-bit data for two words into

the graphics RAM (CGRAM), develop the font pattern, or transfer the BiTBLT as a bit unit. This mode

can read the data during the same bus cycle as for the write operation since the read operation of the

original data does not latch the read data into the microcomputer and temporarily holds it in the read-

data latch. The rotation function (RT2–0) or write-data mask function (WM15–0) are also enabled in

these operations. However, although the write-data mask function masks the bit position set with the

write-data mask register (WM15–0) at the odd-times (such as the first or third) write, the function

masks the bit position which reversed the setting value of the write-data mask register (WM15–0) at the

even-times (such as the second or fourth) write. After the odd-times writing, the address counter (AC)

automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0). After the even-times writing, the

AC automatically increments or decrements by –1 + 20 (I/D = 1) or +1 + 20 (I/D = 0). The AC

automatically jumps to the upper edge after it has reached the lower edge of the graphics RAM.

Rev. 1.0, Jan. 2003, page 54 of 102

HD66753

Operation Examples:

1) I/D = 1, AM1-0 = 10, LG1-0 = 01, RT2-0 = 010

2) WM15-0 = 000FH

3) AC = 0000H

WM0

WM15

DB15

Write data mask:

1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

DB0

Read data (1):

Write data (1):

0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0

4-bit rotation

1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0

1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1

Logical operation (OR)

1 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1

Read data (2):

Write data (2):

0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1

1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0

1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1

Logical operation (OR)

1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1

Read data (3):

Write data (3):

0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0

0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1

1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0

Logical operation (OR)

1 1 1 1 0 0 1 1 0 1 1 1 0 1 1 0

Read data (4):

Write data (4):

1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1

0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1

4-bit rotation

1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0

Logical operation (OR)

1 1 1 1 0 0 0 0 0 1 1 1 0 1 0 1

0000H

0001H

1 0

1 1 * * * * * * * * * * * *

0000H

* * * * 1 1 1 1 1 1 0 0 1 1 0 1

0 0 1 1 0 1 1 1 0 1 1 0

Write data (1), (2)

0020H

* * * *

1 1 1 1 * * * * * * * * * * * * Write data (3), (4)

CGRAM

1060H

Notes: 1. The bit area data in the RAM indicated by "*" is not changed.

2. After writing to address 1060H, the AC jumps to 0001H.

Figure 31 Writing Operation of Read/Write Mode 3

Rev. 1.0, Jan. 2003, page 55 of 102

HD66753

Oscillation Circuit

The HD66753 can either be supplied with operating pulses externally (external clock mode) or oscillate

using an internal R-C oscillator with an external oscillator-resistor (external resistor oscillation mode).

Note that in R-C oscillation, the oscillation frequency is changed according to the internal capacitance

value, the external resistance value, or operating power-supply voltage.

1) External clock mode

Clock

2) External resistor oscillation mode

OSC1

The oscillator frequency can be

adjusted by oscillator resistor (Rf).

If Rf is increased or power supply

voltage is decreased, the

oscillation frequency decreases.

For the relationship between Rf

resistor value and oscillation

frequency, see the Electric

OSC1

(100 kHz)

Rf

OSC2

Dumping

resistance

HD66753

(2 kΩ)

Characteristics Notes section.

Figure 32 Oscillation Circuits

Table 22

Relationship between Liquid Crystal Drive Duty Ratio and Frame Frequency

Recommended

Drive Bias Value

Frame

Frequency

LCD Duty

1/24

NL4–0 Set Value

02H

One-frame Clock

1392

1/6

72 Hz

71 Hz

72 Hz

71 Hz

69 Hz

71 Hz

69 Hz

71 Hz

69 Hz

1/32

03H

1/6

1408

1/40

04H

1/7

1400

1/48

05H

1/8

1392

1/56

06H

1/8

1400

1/64

07H

1/9

1408

1/72

08H

1/9

1440

1/80

09H

1/10

1/11

1440

1/88

0AH

1408

1/96

0BH

1440

1/104

1/112

1/120

1/128

1/132

0CH

1456

0DH

1456

0EH

1440

0FH

1408

10H

1452

Note: The frame frequency above is for 100-kHz operation and proportions the oscillation frequency (fosc).

Rev. 1.0, Jan. 2003, page 56 of 102

HD66753

1

2

3

4

131 132

1

2

3

131 132

V1

V2

COM1

COM2

V5

GND

V1

V2

V5

GND

V1

V2

COM131

COM132

V5

GND

V1

V2

V5

GND

1 frame

Figure 33 LCD Drive Output Waveform (B-pattern AC Drive with 1/132 Multiplexing Duty Ratio)

Rev. 1.0, Jan. 2003, page 57 of 102

HD66753

n-raster-row Reversed AC Drive

The HD66753 supports not only the LCD reversed AC drive in a one-frame unit (B-pattern waveform) but

also the n-raster-row reversed AC drive which alternates in an n-raster-row unit from one to 32 raster-rows

(C-pattern waveform). When a problem affecting display quality occurs, such as crosstalk at high-duty

driving of more than 1/64 duty, the n-raster-row reversed AC drive (C-pattern waveform) can improve the

quality. Determine the number of raster-rows n (NW bit set value + 1) for alternating after confirmation of

the display quality with the actual LCD panel. However, if the number of AC raster-rows is reduced, the

LCD alternating frequency becomes high. Because of this, the charge or discharge current is increased in

the LCD cells.

1 frame

1

2

3

4

5

6

7

8

9 10 11 12 13

79 80 1

2

3

4

5

6

7

8

9 10 11 12 13

79 80 1 2 3

B-pattern

waveform drive

· 1/80 duty

C-pattern

waveform drive

· 1/80 duty

· 11-raster-row

reversal

· Without EORs

C-pattern

waveform drive

· 1/80 duty

· 11-raster-row

reversal

· With EORs

Note: Specify the number of AC drive raster-rows and the necessity of EOR so that the DC bias is not generated for

the liquid crystal.

Figure 34 Example of an AC Signal under n-raster-row Reversed AC Drive

Rev. 1.0, Jan. 2003, page 58 of 102

HD66753

Liquid Crystal Display Voltage Generator

When External Power Supply and Internal Operational Amplifiers are Used

To supply LCD drive voltage directly from the external power supply without using the internal step-up

circuit, circuits should be connected as shown in figure 35. Here, contrast can be adjusted by software

through the CT bits of the contrast adjustment register. Since the VLREF input is the reference voltage to

determine the LCD drive voltage, fluctuation of the voltage must be minimized.

The HD66753 incorporates a voltage-follower operational amplifier for each V1 to V5 to reduce current

flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive

voltages. Thus, potential difference between V_LPSand V1 must be 0.1 V or higher, and that between V4 and

GND must be 1.4 V or higher. Place a capacitor of about 0.47 µF (B characteristics) between each internal

operational amplifier (V1OUT to V5OUT outputs) and GND and stabilize the output level of the

operational amplifier. Adjust the capacitance value of the stabilized capacitor after the LCD panel has been

mounted and the screen quality has been confirmed.

Rev. 1.0, Jan. 2003, page 59 of 102

HD66753

V_LPS

PS1-0 = "10"

SEG1-SEG168

V_LREF

V1OUT

V2OUT

HD66753

(+)

*2 0.1 µF

(B characteristics)

GND

VR

R

+

V1

-

+

-

V2

R

+

-

V3

V3OUT

V4OUT

LCD

driver

R

0

+

-

V4

V5

COM1-COM132

R

*2 0.47 µF (*)

(B characteristics)

+

-

V5OUT

GND

R

GND

Vci

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

Step-up

circuit

C6+

C6-

VLOUT

Notes: 1. Adjust the capacitance value of the capacitor after the LCD panel has been mounted.

2. Use the capacitors with breakdown voltages equal to or higher than the VLPS voltage

for connecting to V1OUT through V5OUT. Determine the capacitor breakdown voltages

by checking VLPS voltage fluctuation.

Figure 35 External Power Supply Circuit for LCD Drive Voltage Generation

Rev. 1.0, Jan. 2003, page 60 of 102

HD66753

When an Internal Booster and Internal Operational Amplifiers are Used

To supply LCD drive voltage using the internal step-up circuit, circuits should be connected as shown in

figure 36. Generate a higher voltage (VLPS) of the internal operational amplifier than the output voltage

(V1REF) of the LCD drive voltage regulator. Here, contrast can be adjusted through the CT bits of the

contrast control instruction.

The HD66753 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current

flowing through the internal bleeder-resistors, which generate different liquid-crystal drive voltages. Thus,

potential difference between V_LPSand V1 must be 0.1 V or higher, and that between V4 and GND must be

1.4 V or higher. Place a capacitor of about 0.47 µF (B characteristics) between each internal operational

amplifier (V1OUT to V5OUT outputs) and GND and stabilize the output level of the operational amplifier.

Adjust the capacitance value of the stabilized capacitor after the LCD panel has been mounted and the

screen quality has been confirmed.

Rev. 1.0, Jan. 2003, page 61 of 102

HD66753

V

LPS

PS1-0 = "00"

V

REG

LCD drive

voltage regulator

HD66753

V

1REF

ON

(+)

*5

0.1 µF

V

LREF

VR

(B characteristics)

+

-

V1

V2

GND

V1OUT

R

+

-

V2OUT

V3OUT

V4OUT

SEG1-SEG168

COM1-COM132

+

-

V3

LCD

driver

R

0

+

-

V4

V5

*5, *8, *9

0.47 µF (*)

(B characteristics)

R

+

-

V5OUT

GND

Vci

C1+

C1-

(+)

*7 1-2 µF

(B characteristics)

C2+

C2-

(+)

*7 1-2 µF

(B characteristics)

C3+

C3-

(+)

*6 1-2 µF

(B characteristics)

C4+

C4-

Step-up

circuit

(+)

*7 1-2 µF

(B characteristics)

C5+

C5-

C6+

C6-

*7 1-2 µF (+)

(B characteristics)

*6 1-2 µF (+)

(B characteristics)

(+)

*8 1-2 µF

(B characteristics)

VLOUT

GND

Notes: 1. The reference voltage input (Vci) must be adjusted so that the output voltage after boosting will not

exceed the absolute maximum rating for the liquid-crystal power supply voltage (20.5 V).

2. Vci is both a reference voltage and power supply for the step-up circuit; obtain sufficient current.

3. Polarized capacitors must be connected correctly.

4. Circuits for temperature compensation should be based on the sample circuits in figures 37 and 38.

5. Adjust the capacitance value of the stabilized capacitor after the LCD panel has been mounted.

6. The breakdown voltages of the capacitors connected to C3+/C3- and C6+/C6- should be three times or

higher than the Vci voltage.

7. The breakdown voltages of the capacitors connected to C1+/C1-, C2+/C2-, C4+/C4-, and C5+/C5-

should be equal to or higher than the Vci voltage.

8. The breakdown voltages of the capacitors connected to VLOUT and V1OUT through V5OUT should be

n times or higher than the Vci voltage (n: step-up magnification).

9. Determine thebreakdown voltages of the capacitors used in 6 to 8 above by checking Vci voltage

fluctuation.

Figure 36 Internal Step-up Circuit for LCD Drive Voltage Generation

Rev. 1.0, Jan. 2003, page 62 of 102

HD66753

Temperature can be compensated either through the CT bits by software, by controlling the reference

voltage for the LCD drive voltage regulator (VREG pin) using a thermistor, or by controlling the reference

output voltage of the LCD drive voltage regulator (V1REF pin).

Vcc

PS1-0 = "00"

V

REG

Thermistor

Tr

LCD drive

voltage regulator

HD66753

GND

1REF

ON

*5

0.1 µF

V

LREF

(+)

(B characteristics)

VR

+

-

V1

V2

GND

V1OUT

V2OUT

R

+

-

SEG1-SEG168

COM1-COM132

+

-

V3

V3OUT

V4OUT

LCD

driver

R

0

+

-

V4

R

+

-

V5

V5OUT

GND

Figure 37 Temperature Compensation Circuits (1)

Rev. 1.0, Jan. 2003, page 63 of 102

HD66753

PS1-0 = "01"

V

REG

LCD drive

voltage regulator

HD66753

V

1REF

0.1 µF

OFF

Thermistor

Tr

V

LREF

VR

R

+

-

V1

V2

V1OUT

V2OUT

GND

(or Vcc)

+

-

SEG1-SEG168

COM1-COM132

R

+

-

V3

V3OUT

V4OUT

LCD

driver

R

0

+

-

V4

R

+

-

V5

V5OUT

GND

Figure 38 Temperature Compensation Circuits (2)

Rev. 1.0, Jan. 2003, page 64 of 102

HD66753

Picture quality provision in case of high-load display

The HD66753 is an on-chip LCD driver that has an LCD power supply for high duty. Screen quality is

affected by the load current of the high-duty LCD panel used. When the bias (1/11 bias, 1/10 bias, 1/9 bias,

etc.) is high and the displayed pattern is completely or almost completely white, the white sections may

appear dark.

If this happens, execute the following countermeasures to improve screen quality.

(1) After the change in the V4OUT/V3OUT level is verified, insert about 1 MΩ between V4OUT and

GND or VLPS and V3OUT and then adjust the screen quality (see the following figures). By inserting

resistance, the current consumption increases as much as the boosting factor of the resistance current.

Adjust the resistance after checking the screen quality and the increase in current consumption.

(2) Decrease the drive bias and use the new bias level after verifying that the potential differences between

V4OUT and GND or VLPS and V3OUT are sufficient.

VLPS

Driver

V4OUT

Fixed

current

source

C

Vbn

Rv4

GND

Figure 39 Countermeasure for V4OUT Output

VLPS

Fixed

current

Rv3

Vbp

source

V3OUT

C

Driver

GND

Figure 40 Countermeasure for V3OUT Output

Note: The actual LCD drive voltage VLREF used must not exceed 16.5 V.

Rev. 1.0, Jan. 2003, page 65 of 102

HD66753

Switching the Step-up Factor

Instruction bits (BT1/0 bits) can optionally select the step-up factor of the internal step-up circuit.

According to the display status, power consumption can be reduced by changing the LCD drive duty and

the LCD drive bias, and by controlling the step-up factor for the minimum requirements. For details, see

the Partial-display-on Function section.

According to the maximum step-up factor, external capacitors need to be connected. For example, when

the maximum step-up is six times or five times, capacitors between C6+ and C6– or between C5+ and C5–

are needed as in the case of the seven-times step-up. When the step-up is three-times, capacitors between

C1+ and C1– or between C4+ and C4– are not needed.

Place a capacitor with a breakdown voltage of three times or more the Vci-GND voltage between C6+ and

C6– and between C3+ and C3–, a capacitor with a breakdown voltage larger than the Vci-GND voltage

between C1+ and C1–, C2+ and C2–, C4+ and C4–, and C5+ and C5–, and a capacitor with a breakdown

voltage of n times or more the Vci-GND voltage to VLOUT (n: step-up factor) (see figure 37).

Note: Determine the capacitor breakdown voltages by checking Vci voltage fluctuation.

Table 23

VLOUT Output Status

BT1

0

BT0

0

VLOUT Output Status

Three-times step-up output

Five-times step-up output

Six-times step-up output

Seven-times step-up output

0

1

0

1

Rev. 1.0, Jan. 2003, page 66 of 102

HD66753

i) Maximum seven-times step-up

ii) Maximum six-times step-up

Vci

(+)

1 µF

(+)

(B Charac-

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

C6+

C6-

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

(B Charac-

teristics)

(+)

1 µF

(B Charac-

teristics)

(B Charac-

teristics)

(+)

1 µF

(B Charac-

teristics)

(B Charac-

teristics)

(+)

1 µF

(B Charac-

teristics)

(B Charac-

teristics)

(+)

1 µF

C5+

C5-

C6+

C6-

(B Charac-

teristics)

(B Charac-

teristics)

(+)

1 µF

(B Charac-

teristics)

(B Charac-

teristics)

VLOUT

(+)

1 µF

(B Charac-

teristics)

(+)

1 µF

(B Charac-

teristics)

GND

iv) Maximum three-times step-up

iii) Maximum five-times step-up

Vci

(+)

1 µF

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

C6+

C6-

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

C6+

C6-

(B Charac-

teristics)

(+)

1 µF

(B Charac-

teristics)

(B Charac-

teristics)

(+)

1 µF

(B Charac-

teristics)

(B Charac-

teristics)

(+)

1 µF

(B Charac-

teristics)

(+)

1 µF

(B Charac-

teristics)

(B Charac-

teristics)

(+)

1 µF

(B Charac-

teristics)

(B Charac-

teristics)

VLOUT

1 µF

(B Charac-

teristics)

(+)

1 µF

(B Charac-

teristics)

(+)

GND

Figure 41 Step-up Circuit Output Factor Switching

Rev. 1.0, Jan. 2003, page 67 of 102

HD66753

Example of Power-supply Voltage Generator for More Than Seven-times Step-up Output

The HD66753 incorporates a step-up circuit for up to seven-times step-up. However, the LCD drive

voltage (VLREF) will not be enough for seven-times step-up from Vcc when the power-supply voltage of

Vcc is low or when the LCD drive voltage is high for the high-contrast LCD display. In this case, the

reference voltage (Vci) for step-up can be set higher than the power-supply voltage of Vcc.

When the step-up factor is high, the current driving ability is lowered and insufficient display quality may

result. In this case, the step-up ability can be improved by decreasing the step-up factor as shown in the

step-up circuit in figure 42.

Set the Vci input voltage for the step-up circuit to 3.6 V or less. Control the Vci voltage so that the step-up

output voltage (VLOUT) should be less than the absolute maximum ratings (20.5 V).

HD66753

2.0 V

2.2 V

Regulator

(1)

Vci

Logic circuit

Vcc

1 µF

(B Charac-

teristics)

(+)

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

Battery

3.6 V

Regulator

(2)

Vci

1 µF

(B Charac-

teristics)

1 µF

(B Charac-

teristics)

Step-up circuit

GND

1 µF

(B Charac-

teristics)

VLPS (= 15.4V)

1 µF

(B Charac-

teristics)

C5+

C5-

2.2 V x 7 = 15.4 V

VLOUT

1 µF

(B Charac-

teristics)

C6+

C6-

SEG1-SEG 168

COM1-COM132

LCD driver

GND

VLPS

(+)

1 µF

(B Charac-

teristics)

GND

Vci (= 2.2 V)

Vcc (= 2.0 V)

GND

GND (= 0 V)

Note: In practice, the LCD drive current lowers

the voltage in the step-up output voltage.

Figure 42 Usage Example of Step-up Circuit at Vci > Vcc

Rev. 1.0, Jan. 2003, page 68 of 102

HD66753

Precautions when Switching Boosting Circuit

The boosting factor of the HD66753 can be switched between 3, 5, 6, and 7 times by instruction. When the

factor is switched, there is a transition period before the voltage from VLOUT stabilizes. When VLOUT is

used as the VLPS, the boosting factor is changed by switching the BT bit, and the supply voltage for the

VLPS is changed, a direct current may be applied to the LCD display if the display is on during the

transition period.

When the output voltage of the VLOUT pin is changed, the display must be switched off and on after the

output voltage stabilizes.

Table 24

Instructions Accompanying Change in Boosting Factor (example)

Display Contents

Instructions

All display drive in 1/128 duty to 1/48 duty drive

(1) Display control (R7)

(2) Power control (R1)

(3) 10-ms wait

0x0000

0x1914

(4) Contrast control (R4)

(5) Driver output control (R1)

(6) Display control (R7)

0x0006

0x0245

0x0005

Rev. 1.0, Jan. 2003, page 69 of 102

HD66753

Contrast Adjuster

Software can adjust 128-step contrast for an LCD by varying the liquid-crystal drive voltage (potential

difference between V_LREFand V1) through the CT bits of the contrast adjustment register (electron volume

function). The value of a variable resistor between V_LREFand V1 (VR) can be precisely adjusted in a 0.05 x

R unit within a range from 0.05 x R through 6.40 x R, where R is a reference resistance obtained by

dividing the total resistance.

The HD66753 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current

flowing through the internal bleeder resistors, which generate different liquid-crystal drive voltages. Thus,

CT5-0 bits must be adjusted so that potential difference between V_LPSand V1 is 0.1 V or higher and that

between V4 and GND is 1.4 V or higher when liquid-crystal drives, particularly when the VR is small.

HD66753

V

LREF

CT

VR

+

-

V1

R

+

-

V2

V3

+

-

R0

+

-

V4

V5

R

+

-

GND

Figure 43 Contrast Adjuster

Rev. 1.0, Jan. 2003, page 70 of 102

HD66753

Table 25

Contrast Adjustment Bits (CT) and Variable Resistor Values

CT Set Value

Variable Resistor

Valu e (VR)

Potential Difference

between V1 and GND

Display Color

CT3 CT2 CT1 CT0

CT6 CT5 CT4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

6.40 x R

6.35 x R

6.30 x R

6.25 x R

6.20 x R

6.15 x R

6.10 x R

6.05 x R

6.00 x R

5.95 x R

5.90 x R

5.85 x R

5.80 x R

(Small)

(Weak)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3.25 x R

3.20 x R

3.15 x R

3.10 x R

3.05 x R

3.00 x R

2.95 x R

2.90 x R

2.85 x R

2.80 x R

2.75 x R

0

1

0

1

0

1

0

1

0.20 x R

0.15 x R

0.10 x R

0.05 x R

(Large)

(Bright)

Rev. 1.0, Jan. 2003, page 71 of 102

HD66753

Table 26

Contrast Adjustment per Bias Drive Voltage

Bias

LCD Drive Voltage: VDR

Contrast Adjustment Range

- LCD drive voltage

adjustment range

:

0.775 x (VLREF-GND) ≤ VDR

≤

0.995 x (VLREF-GND)

1/11

bias

drive

2 x R

11 x R

11 x R + VR

- Limit of potential

difference between V4 and GND

x (VLREF-GND)

≥ 1.4 [V]

x (VLREF-GND)

11 x R + VR

VR

- Limit if potential

difference between VLPS and V1

≥ 0.1 [V]

:

11 x R + VR

- LCD drive voltage

adjustment range

: 0.757 x (VLREF-GND) ≤VDR

≤

0.995 x (VLREF-GND)

1/10

bias

drive

2 x R

10 x R

- Limit of potential

difference between V4 and GND

x (VLREF-GND)

≥ 1.4 [V]

x (VLREF-GND)

:

10 x R + VR

VR

10 x R + VR

- Limit if potential

difference between VLPS and V1

≥

0.1 [V]

10 x R + VR

- LCD drive voltage

adjustment range

: 0.737 x (V_LREF-GND) ≤VDR

≤

0.994 x (VLREF-GND)

1/9

bias

drive

9 x R

9 x R + VR

2 x R

9 x R + VR

VR

9 x R + VR

- Limit of potential

difference between V4 and GND

x (VLREF-GND)

≥ 1.4 [V]

≥ 0.1 [V]

:

x (VLREF-GND)

- Limit if potential

difference between VLPS and V1

x (VLREF-GND)

- LCD drive voltage

adjustment range

: 0.714 x (VLREF-GND) ≤ VDR

≤

0.993 x (VLREF-GND)

1/8

bias

drive

2 x R

8 x R + VR

VR

8 x R

- Limit of potential

difference between V4 and GND

x (VLREF-GND)

≥ 1.4 [V]

:

8 x R + VR

- Limit if potential

difference between VLPS and V1

≥ 0.1 [V]

8 x R + VR

- LCD drive voltage

adjustment range

:

0.686 x (VLREF-GND) ≤ VDR

≤

0.993 x (VLREF-GND)

1/7

bias

drive

2 x R

7 x R + VR

VR

7 x R + VR

7 x R

7 x R + VR

- Limit of potential

difference between V4 and GND

x (VLREF-GND)

≥ 1.4 [V]

:

- Limit if potential

difference between VLPS and V1

x (VLREF-GND)

≥

0.1 [V]

- LCD drive voltage

adjustment range

: 0.652 x (VLREF-GND) ≤ VDR

≤

0.992 x (VLREF-GND)

1/6

bias

drive

2 x R

6 x R + VR

VR

6 x R

- Limit of potential

difference between V4 and GND

x (VLREF-GND)

≥ 1.4 [V]

≥ 0.1 [V]

:

6 x R + VR

- Limit if potential

difference between VLPS and V1

6 x R + VR

- LCD drive voltage

adjustment range

:

0.610 x (VLREF-GND ) ≤ VDR

≤

0.990 x (VLREF-GND)

1/5

bias

drive

2 x R

5 x R + VR

5 x R

5 x R + VR

- Limit of potential

difference between V4 and GND

x (VLREF-GND )

≥ 1.4 [V]

:

x (VLREF-GND)

VR

- Limit if potential

difference between VLPS and V1

x (VLREF-GND )

5 x R + VR

≥ 0.1 [V]

- LCD drive voltage

adjustment range

:

0.556 x (VLREF-GND) ≤ VDR

≤

0.988 x (VLREF-GND)

1/4

bias

drive

4 x R

2 x R

4 x R + VR

VR

- Limit of potential

difference between V4 and GND

x (VLREF-GND)

≥ 1.4 [V]

4 x R + VR

- Limit if potential

difference between VLPS and V1

≥ 0.1 [V]

:

4 x R + VR

Rev. 1.0, Jan. 2003, page 72 of 102

HD66753

Liquid-crystal-display Drive-bias Selector

An optimum liquid-crystal-display bias value can be selected using the BS2-0 bits, according to the liquid

crystal drive duty ratio setting (NL4-0 bits). The liquid-crystal-display drive duty ratio and bias value can

be displayed while switching software applications to match the LCD panel display status. The optimum

bias value calculated using the following expression is a logical optimum value. Driving by using a lower

value than the optimum bias value provides lower logical contrast and lower liquid-crystal-display voltage

(the potential difference between V1 and GND), which results in better image quality. When the liquid-

crystal-display voltage is insufficient even if a seven-times step-up circuit is used, when the step-up driving

ability is lowered by setting a high factor for the step-up circuit, or when the output voltage is lowered

because the battery life has been reached, the display can be made easier to see by lowering the liquid-

crystal-display bias.

The liquid crystal display can be adjusted by using the contrast adjustment register (CT6-0 bits) and

selecting the step-up output level (BT1/0 bits).

1

Optimum bias value for 1/N duty ratio drive voltage =

N + 1

Table 27

Optimum Drive Bias Values

LCD drive

duty ratio

1/132 1/128 1/120 1/112 1/104 1/96 1/88 1/80 1/72 1/64 1/32 1/24 1/16

(NL4-0 set

value)

10H

1/11

0FH

1/11

0EH

1/11

0DH

1/11

0CH

1/11

0BH 0AH 09H 08H 07H 03H 02H 01H

Optimum

drive bias

value

1/10 1/10 1/10 1/9

1/9

1/6

1/5

(BS2-0 set

value)

000

001

010

101

110

Rev. 1.0, Jan. 2003, page 73 of 102

HD66753

VLREF

VR

V1

V2

V3

V4

R

V2

V3

7R

R

5R

R

3R

R

6R

R

4R

R

V4

V5

R

GND

ii) 1/ 10 bias

GND

iii) 1/ 9 bias

GND

i) 1/ 11 bias

iv) 1/ 8 bias

(BS2Ð0 = 011)

v) 1/7 bias

(BS2Ð0 = 100)

(BS2Ð0 = 000)

(BS2Ð0 = 001)

(BS2Ð0 = 010)

VLREF

VR

V1

VR

R

V1

V2

R

V2

V3

2R

R

V3,V4

V5

V4

V5

Note: R = Reference resistor

R

GND

v) 1/6 bias

(BS2Ð0 = 101)

v) 1/5 bias

(BS2Ð0 = 110)

vi) 1/ 4 bias

(BS2Ð0 = 111)

Figure 44 Liquid Crystal Display Drive Bias Circuit

Rev. 1.0, Jan. 2003, page 74 of 102

HD66753

Four-grayscale Display Function

The HD66753 supports the four-grayscale monochrome display function. The four-grayscale monochrome

display is used for the display data of the two-bit pixel set sent to the CGRAM. There are four grayscale

levels: always unlit, weak middle level, bright middle level, and always lit. In the middle-level grayscale

display, the GSL1-0 and GSH1-0 bits can select the grayscale level, respectively.

The frame rate control (FRC) method, which is used for grayscale control, can reduce charge/discharge

current in the LCD glass during grayscale display.

Table 28

Relationships between the CGRAM Data and the Display Contents

Upper Bit

Lower Bit

Liquid Crystal Display

0

1

Non-selected (unlit)

GSL1-0 = 00: 1/4-level grayscale (one frame lit during a four-frame

period)

GSL1-0 = 01: 1/3-level grayscale (one frame lit during a three-frame

period)

GSL1-0 = 10: 2/4-level grayscale (two frames lit during a four-frame

period)

GSL1-0 = 11: Lit (no grayscale control)

1

0

GSH1-0 = 00: 3/4-level grayscale (three frames lit during a four-

frame period)

GSH1-0 = 01: 2/3-level grayscale (two frames lit during a three-

frame period)

GSH1-0 = 10: 2/4-level grayscale (two frames lit during a four-frame

period)

GSH1-0 = 11: Lit (no grayscale control)

Selected (lit)

1

Note: Upper bits: DB15, DB13, DB11, DB9, DB7, DB5, DB3, and DB1

Lower bits: DB14, DB12, DB10, DB8, DB6, DB4, DB2, and DB0

Rev. 1.0, Jan. 2003, page 75 of 102

HD66753

LSB

DB0

MSB LSB

DB15 DB0

MSB

DB15

0 0 1 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1

CGRAM

Grayscale

control circuit

LCD panel display

Figure 45 Four-grayscale Monochrome Display

Rev. 1.0, Jan. 2003, page 76 of 102

HD66753

Window Cursor Display Function

The HD66753 displays the window cursor by specifying a window area. The horizontal display position of

the window cursor is specified with the horizontal cursor position register (HS6-0 to HE6-0), and the

vertical display position is specified with the vertical cursor position register (VS6-0 or VE6-0). In these

display position setting registers, ensure that HS6-0 ≤ HE6-0 and VS6-0 ≤ VE6-0. If these relationships are

not satisfied, normal display cannot be attained. In addition, if the setting is VS6-0 = VE6-0 = 00H, a

cursor is displayed on a raster-row at the most-upper edge of the screen.

This window cursor can automatically display the hardware-supported block cursor, highlight window, or

menu bar. The CM1-0 bits select the following four displays in each window cursor:

1. White-blink cursor (CM1-0 = 00): Alternately blinks between the normal display and an all-white

(unlit) display

2. Black-blink cursor (CM1-0 = 01): Alternately blinks between the normal display and an all-black (all

lit) display

3. Black-and-white reversed cursor (CM1-0 = 10): Normal black-and-white-reversed display (without

blinking)

4. Black-and-white reversed blinking cursor (CM1-0 = 11): Alternately blinks between the normal display

and a black-and-white-reversed display

The above blinking display is switched in a 32-frame unit. To set a range of the window cursor, specify the

display area.

Figure 46 White Blink Cursor Display

Rev. 1.0, Jan. 2003, page 77 of 102

HD66753

Figure 47 Black Blink Cursor Display

Figure 48 Black-and-white Reversed Cursor Display

Figure 49 Black-and-white Reversed Blink Cursor Display

Rev. 1.0, Jan. 2003, page 78 of 102

HD66753

Reversed Display Function

The HD66753 can display graphics display sections by black-and-white reversal. Black-and-white reversal

can be easily displayed when the REV bit in the display control register is set to 1.

Figure 50 Reversed Display

Rev. 1.0, Jan. 2003, page 79 of 102

HD66753

Screen-division Driving Function

The HD66753 can select and drive two screens at any position with the screen-driving position registers

(R0D and R0E). Any two screens required for display are selectively driven and a duty ratio is lowered by

LCD-driving duty setting (NL4-0), thus reducing LCD-driving voltage and power consumption.

For the 1st division screen, start line (SS17-10) and end line (SE17-10) are specified by the 1st screen-

driving position register (R0D). For the 2nd division screen, start line (SS27-20) and end line (SE27-20)

are specified by the 2nd screen-driving position register (R0E). The 2nd screen control is effective when

the SPT bit is 1. The total count of selection-driving lines for the 1st and 2nd screens must correspond to

the LCD-driving duty set value.

Figure 51 Display Example in 2-screen Division Driving

Rev. 1.0, Jan. 2003, page 80 of 102

HD66753

Restrictions on the 1st/2nd Screen Driving Position Register Settings

The following restrictions must be satisfied when setting the start line (SS17-10) and end line (SE17-10) of

the 1st screen driving position register (R0D) and the start line (SS27-20) and end line (SE27-20) of the

2nd screen driving position register (R0D) for the HD66753. Note that incorrect display may occur if the

restrictions are not satisfied.

Table 29 Restrictions on the 1st/2nd Screen Driving Position Register Settings

1st Screen Driving (STP = 0)

2nd Screen Driving (STP = 1)

Register setting

SS17-10 ≤ SE17-0 ≤ 83H

SS17-10 ≤ SE17-10 < SS17-10 ≤

SE17-0 ≤ 83H

Display operation

Time-sharing driving for COM pins

(SS1+1) to (SE1+1)

Time-sharing driving for COM pins

(SS1+1) to (SE1+1) and (SS2+1) to

(SE2+1)

Non-selection level driving for others

Notes: 1. When the total line count in screen division driving settings is less than the duty setting, non-

selection level driving is performed without the screen division driving setting range.

2. When the total line count in screen division driving settings is larger than the duty setting, the

start line, the duty-setting line, and the lines between them are displayed and non-selection level

driving is performed for other lines.

3. For the 1st screen driving, the SS27-20 and SE27-20 settings are ignored.

Rev. 1.0, Jan. 2003, page 81 of 102

HD66753

Sleep Mode

Setting the sleep mode bit (SLP) to 1 puts the HD66753 in the sleep mode, where the device stops all

internal display operations, thus reducing current consumption. Specifically, LCD operation is completely

halted. Here, all the SEG (SEG1 to SEG168) and COM (COM1 to COM132) pins output the GND level,

resulting in no display. If the AP1-0 bits in the power control register are set to 00 in the sleep mode, the

LCD drive power supply can be turned off, reducing the total current consumption of the LCD module.

Table 30 Comparison of Sleep Mode and Standby Mode

Function

Sleep Mode (SLP = 1)

Turned off

Standby Mode (STB = 1)

Turned off

LCD control

R-C oscillation circuit

Operates normally

Operation stopped

Standby Mode

Setting the standby mode bit (STB) to 1 puts the HD66753 in the standby mode, where the device stops

completely, halting all internal operations including the R-C oscillation circuit, thus further reducing

current consumption compared to that in the sleep mode. Specifically, all the SEG (SEG1 to SEG168) and

COM (COM1 to COM132) pins for the time-sharing drive output the GND level, resulting in no display. If

the AP1-0 bits are set to 00 in the standby mode, the LCD drive power supply can be turned off.

During the standby mode, no instructions can be accepted other than the start-oscillation instruction. To

cancel the standby mode, issue the start-oscillation instruction to stabilize R-C oscillation before setting the

STB bit to 0.

Turn off the LCD power supply: AP1 to 0 = 00

Set standby mode: STB = 1

Standby mode

Issue the start-oscillation instruction

Wait at least 10 ms

Cancel standby mode: STB = 0

Turn on the LCD power supply: AP1 to 0 = 01 / 10 / 11

Figure 52 Procedure for Setting and Canceling Standby Mode

Rev. 1.0, Jan. 2003, page 82 of 102

HD66753

Absolute Maximum Ratings

Item

Symbol

Unit

V

Value

Notes*

1, 2

1, 3

1

Power supply voltage (1) V_CC

–0.3 to +4.6

–0.3 to +20.5

–0.3 to V_CC+ 0.3

–40 to +85

–55 to +110

Power supply voltage (2) V_LPS– GND

V

Input voltage

Vt

V

Operating temperature

Storage temperature

Topr

Tstg

°C

1, 4

1, 5

Notes: 1. If the LSI is used above these absolute maximum ratings, it may become permanently damaged.

Using the LSI within the following electrical characteristics limits is strongly recommended for

normal operation. If these electrical characteristic conditions are also exceeded, the LSI will

malfunction and cause poor reliability.

2. VCC > GND must be maintained.

3. VLPS > GND must be maintained.

4. For bare die and wafer products, specified up to 85•C.

5. This temperature specifications apply to the TCP package.

Rev. 1.0, Jan. 2003, page 83 of 102

HD66753

DC Characteristics (V_CC= 1.7 to 3.6 V, Ta = –40 to +85°C*¹)

Item

Symbol Min

Typ

—

Max

Unit Test Condition

Notes

2, 3

2

Input high voltage

Input low voltage

V_IH

V_IL

0.7 V_CC

V_CC

V

–0.3

—

0.15 V_CC

—

V

V_CC= 1.7 to 2.4 V

V_CC= 2.4 to 3.6 V

I_OH= –0.1 mA

–0.3

—

Output high voltage (1) V_OH1

(DB0-15 and SDA pins)

0.75 V_CC

—

Output low voltage (1) V_OL1

(DB0-15 and SDA pins)

—

3

0.2 V_CC

0.15 V_CC

10

V

V_CC= 1.7 to 2.4 V,

2

4

I

_OL= 0.1 mA

V_CC= 2.4 to 3.6 V,

I_OL= 0.1 mA

Driver ON resistance

(COM pins)

R_COM

R_SEG

kΩ ±Id = 0.05 mA,

V_LPS= 10 V

Driver ON resistance

(SEG pins)

3

10

kΩ ±Id = 0.05 mA,

V_LPS= 10 V

I/O leakage current

I_Li

–1

—

1

µA Vin = 0 to V_CC

5

Current consumption

during normal operation

(V_CC– GND)

I_OP

100

150

µA R-C oscillation,

6, 7

V_CC= 3 V, Ta = 25 °C, f_OSC

= 100 kHz (1/132 duty),

RAM write: checker

pattern

Current consumption

during standby mode

(V_CC– GND)

I_ST

—

0.1

40

5

µA V_CC= 3 V, Ta = 25°C

6, 7

LCD drive power supply I_LPS

current (V_LPS– GND)

60

µA

V = 3 V, V = 15 V, 1/11 7

bias,

Ta = 25 °C, f_OSC= 100

kHz, amount of fixed

current in the operational

amplifier: small

LCD drive voltage

(V_LPS– GND)

V_LPS

V_REG

5.0

—

19.5

2.5

—

V

8

VREG input voltage

(VREG pin)

1.3

13.0

VREG external input

(PS1-0 = 10), Ta = 25 °C

V1REF output voltage V_1REF

(V1REF pin)

—

VREG = 1.3 V,

Ta = 25 °C, 11 times of

VREG (VR2-0 = 111),

V1REF ≤ VLPS – 0.5 V

Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.

Rev. 1.0, Jan. 2003, page 84 of 102

HD66753

Step-up Circuit Characteristics

Item

Symbol Min

Typ

Max

Unit Test Condition

Notes

Three-times

step-up output

voltage (VLOUT

pin)

V_UP3

7.6

8.0

8.1

V

V_CC= Vci = 2.7 V,

I_O= 30 µA, C = 1 µF,

f_OSC= 100 kHz, Ta = 25°C

11

Five-times step-

up output voltage

(VLOUT pin)

V_UP5

13.0

15.7

18.4

13.3

16.0

18.7

13.5

16.2

18.9

V

V_CC= Vci = 2.7 V,

I_O= 30 µA, C = 1 µF,

f_OSC= 100 kHz, Ta = 25°C

11

Six-times step-up V_UP6

output voltage

(VLOUT pin)

V_CC= Vci = 2.7 V,

I_O= 30 µA, C = 1 µF,

f_OSC= 100 kHz, Ta = 25°C

Seven-times

step-up output

voltage (VLOUT

pin)

V_UP7

V_CC= Vci = 2.7 V,

I_O= 30 µA, C = 1 µF,

f_OSC= 100 kHz, Ta = 25°C

Use range of

step-up output

voltages

V_UP3

V_UP5

V_UP6

V_UP7

Vcc

—

19.5

V

For three- to seven-times

step-up

11

Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.

Rev. 1.0, Jan. 2003, page 85 of 102

HD66753

AC Characteristics (V_CC= 1.7 to 3.6 V, Ta = –40 to +85°C*¹)

Clock Characteristics (V_CC= 1.7 to 3.6 V)

Item

Symbol

Min

Typ

Max

Unit

Test Condition

Notes

External clock

frequency

fcp

50

75

150

kHz

9

External clock duty

ratio

Duty

trcp

tfcp

f_OSC

45

—

80

50

—

55

%

9

External clock rise

time

0.2

120

µs

9

External clock fall

time

—

µs

9

R-C oscillation clock

100

kHz

Rf = 220 kΩ,

V_CC= 3 V

10

Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.

68-system Bus Interface Timing Characteristics

(Vcc = 1.7 to 2.4 V)

Item

Symbol Min

Typ

—

Max

—

Unit

Test Condition

Enable cycle time

Write t_CYCE

600

800

120

350

300

400

—

ns

Figure 60

Read t_CYCE

Write PW_EH

Read PW_EH

Write PW_EL

Read PW_EL

t_Er, t_Ef

—

Enable high-level pulse width

Enable low-level pulse width

—

ns

Figure 60

—

Enable rise/fall time

25

—

ns

Figure 60

Setup time (RS, R/W to E, CS*)

Address hold time

t_ASE

50

t_AHE

20

—

Write data setup time

Write data hold time

Read data delay time

Read data hold time

t_DSWE

60

—

t_HE

20

—

t_DDRE

—

300

—

t_DHRE

5

Rev. 1.0, Jan. 2003, page 86 of 102

HD66753

(Vcc = 2.4 to 3.6 V)

Item

Symbol Min

Typ

—

Max

—

Unit

ns

Test Condition

Enable cycle time

Write t_CYCE

380

500

70

Figure 60

Read t_CYCE

Write PW_EH

Read PW_EH

Write PW_EL

Read PW_EL

t_Er, t_Ef

—

Enable high-level pulse width

Enable low-level pulse width

—

ns

250

150

200

—

Enable rise/fall time

25

—

ns

Figure 60

Setup time (RS, R/W to E, CS*)

Address hold time

t_ASE

50

t_AHE

20

—

Write data setup time

Write data hold time

Read data delay time

Read data hold time

t_DSWE

60

—

t_HE

20

—

t_DDRE

—

200

—

t_DHRE

5

Rev. 1.0, Jan. 2003, page 87 of 102

HD66753

80-system Bus Interface Timing Characteristics

(Vcc = 1.7 to 2.4 V)

Item

Symbol Min

Typ

—

Max

—

Unit

ns

Test Condition

Figure 61

Bus cycle time

Write t_CYCW

Read t_CYCR

PW_LW

600

800

120

350

300

400

—

Write low-level pulse width

Read low-level pulse width

Write high-level pulse width

Read high-level pulse width

Write/Read rise/fall time

Setup time (RS to CS*, WR*, RD*)

Address hold time

—

PW_LR

—

PW_HW

—

PW_HR

—

t_WRr

t_AS

,

25

—

WRf

50

t_AH

20

—

Write data setup time

t_DSW

t_H

t_DDR

t_DHR

60

—

Write data hold time

20

—

Read data delay time

—

300

—

Read data hold time

5

(Vcc = 2.4 to 3.6 V)

Item

Symbol Min

Typ

—

Max

—

Unit

ns

Test Condition

Figure 61

Bus cycle time

Write t_CYCW

Read t_CYCR

PW_LW

380

500

70

—

Write low-level pulse width

Read low-level pulse width

Write high-level pulse width

Read high-level pulse width

Write/Read rise/fall time

Setup time (RS to CS*, WR*, RD*)

Address hold time

—

PW_LR

PW_HW

PW_HR

t_{WRr, WRf}

t_AS

250

150

200

—

25

—

50

t_AH

20

—

Write data setup time

t_DSW

60

—

Write data hold time

t_H

20

—

Read data delay time

t_DDR

—

200

—

Read data hold time

t_DHR

5

Rev. 1.0, Jan. 2003, page 88 of 102

HD66753

Clock-synchronized Serial Interface Timing Characteristics

(Vcc = 1.7 to 2.4 V)

Item

Symbol Min

Typ

—

Max

Unit

Test Condition

Figure 62

Serial clock cycle time

Write (receive) t_SCYC

Read (send) t_SCYC

Serial clock high-level width Write (receive) t_SCH

Read (send) t_SCH

Write (receive) t_SCL

100

250

40

120

40

120

—

2000 ns

—

20

—

200

—

ns

Serial clock low-level width

Read (send)

t_SCL

Serial clock rise/fall time

Chip-select setup time

t_scf, t_scr

t_CSU

t_CH

20

60

30

—

Chip-select hold time

Serial input data setup time

Serial input data hold time

Serial output data delay time

Serial output data hold time

t_SISU

t_SIH

t_SCD

t_SCH

5

(Vcc = 2.4 to 3.6 V)

Item

Symbol Min

Typ

—

Max

Unit

Test Condition

Figure 62

Serial clock cycle time

Write (receive) t_SCYC

Read (send) t_SCYC

Serial clock high-level width Write (receive) t_SCH

Read (send) t_SCH

Write (receive) t_SCL

100

250

40

120

40

120

—

2000 ns

—

20

—

200

—

ns

Serial clock low-level width

Read (send)

t_SCL

Serial clock rise/fall time

Chip-select setup time

t_scf, t_scr

t_CSU

t_CH

20

60

30

—

Chip-select hold time

Serial input data setup time

Serial input data hold time

Serial output data delay time

Serial output data hold time

t_SISU

t_SIH

t_SCD

t_SCH

5

Reset Timing Characteristics (V_CC= 1.7 to 3.6 V)

Item

Symbol

t_RES

Min

1

Typ

Max

—

Unit

Test Condition

Figure 63

Reset low-level width

Reset rise time

—

ms

T_rRES

—

10

µs

Figure 63

Rev. 1.0, Jan. 2003, page 89 of 102

HD66753

Electrical Characteristics Notes

1. For bare die products, specified up to +85°C.

2. The following three circuits are I/O pin configurations (figure 53).

Pins: RESET*, CS*, E/WR/SCL,RS,

OSC1, OPOFF, IM2-1, IM0/ID, TEST

Pin: OSC2

Vcc

PMOS

NMOS

PMOS

NMOS

GND

Pins: DB15 to DB0, RW/RD/SDA

Vcc

PMOS

NMOS

PMOS

(Input circuit)

Vcc

(Tri-state output circuit)

Output enable

Output data

PMOS

NMOS

GND

Figure 53 I/O Pin Configuration

Rev. 1.0, Jan. 2003, page 90 of 102

HD66753

3. The TEST pin must be grounded and the IM1/0 and OPOFF pins must be grounded or connected to

Vcc.

4. Applies to the resistor value (RCOM) between power supply pins V1OUT, V2OUT, V5OUT, GND and

common signal pins, and resistor value (RSEG) between power supply pins V1OUT, V3OUT, V4OUT,

GND and segment signal pins.

5. This excludes the current flowing through output drive MOSs.

6. This excludes the current flowing through the input/output units. The input level must be fixed high or

low because through current increases if the CMOS input is left floating.

7. The following shows the relationship between the operation frequency (fosc) and current consumption

(Icc) (figure 54).

Vcc = 3.0 V

Vcc = 3.0 V, fosc = 100 kHz

100

80

60

Display on (typ.)

40

typ.

60

20

0

40

0

Sleep (typ.)

Standby (typ.)

80 100 120

20

40 60

11.0

13.0

15.0

17.0

R-C oscillation frequencies: fosc (kHz)

LCD drive voltage: VLCD (V)

Figure 54 Relationship between the Operation Frequency and Current Consumption

8. Each COM and SEG output voltage is within ±0.15 V of the LCD voltage (Vcc, V1, V2, V3, V4, V5)

when there is no load.

9. Applies to the external clock input (figure 55).

Th

Tl

2 kΩ

0.7Vcc

0.5Vcc

0.3Vcc

Oscillator

OSC1

OSC2

Th

Duty =

x 100%

Th + Tl

Open

t

rcp

fcp

Figure 55 External Clock Supply

Rev. 1.0, Jan. 2003, page 91 of 102

HD66753

10. Applies to the internal oscillator operations using external oscillation resistor Rf (figure 56 and table

31).

OSC1

Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance,

the wiring length to these pins should be minimized.

OSC2

Rf

Figure 56 Internal Oscillation

Table 31 External Resistance Value and R-C Oscillation Frequency (Referential Data)

External

Resistance (Rf)

200 kΩ

R-C Oscillation Frequency: fosc

Vcc = 1.8 V

89 kHz

70 kHz

65 kHz

60 kHz

55 kHz

52 kHz

48 kHz

44 kHz

Vcc = 2.2 V

103 kHz

80 kHz

73 kHz

68 kHz

62 kHz

58 kHz

53 kHz

48 kHz

Vcc = 3.0 V

115 kHz

88 kHz

80 kHz

74 kHz

68 kHz

64 kHz

58 kHz

52 kHz

Vcc = 3.6 V

121 kHz

92 kHz

83 kHz

77 kHz

71 kHz

66 kHz

60 kHz

54 kHz

270 kΩ

300 kΩ

330 kΩ

360 kΩ

390 kΩ

430 kΩ

470 kΩ

11. The step-up characteristics test circuit is shown in figure 57.

(5 to 7-times step-up)

Vcc

Vci

+

C1+

1 µF

C1-

C2+

C2-

+

C3+

C3-

C4+

C4-

1 µF

+

C5+

C5-

C6+

C6-

VLOUT

V

+

LCD

GND

1 µF

Figure 57 Step-up Characteristics Test Circuit

Rev. 1.0, Jan. 2003, page 92 of 102

HD66753

(i) Relation between the obtained voltage and input voltage

Six-times step-up

Seven-times step-up

typ.

18.0

15.0

12.0

9.0

13.0

8.0

1.5

2.0

2.5

3.0

1.5

2.0

2.5

3.0

Vci (V)

Vci = Vcc, fosc = 100 kHz, Ta = 25˚C, DC1 to 0= 00

Vci = Vcc, fosc = 100 kHz, Ta = 25˚C, DC1 to 0 = 00

(ii) Relation between the obtained voltage and temperature

Six-times step-up

20.0

Seven-times step-up

typ.

21.0

18.0

typ.

100

16.0

14.0

19.0

17.0

-60

-20 0 20

˚C

Ta ( )

60

-60

-20

0

20

60

100

˚C

)

Ta (

Vci = Vcc = 2.7 V, fosc = 100 kHz, Io = 30 µA,

DC1 to 0= 00

Vci = Vcc = 2.7 V, fosc = 100 kHz, Io = 30 µA,

DC1 to 0 = 00

Figure 58 Step-up

Rev. 1.0, Jan. 2003, page 93 of 102

HD66753

(iii) Relation between the obtained voltage and capacity

Six-times step-up

18.0

Seven-times step-up

20.0

typ.

17.0

19.0

18.0

17.0

16.0

15.0

14.0

16.0

0.5

1.0

C (µF)

1.5

0.5

1.0

C (µF)

1.5

Vci = Vcc = 2.7 V, fosc = 100 kHz, Io = 30 µA,

DC1 to 0 = 00

Vci = Vcc = 2.7 V, fosc = 100 kHz, Io = 30 µA,

DC1 to 0 = 00

(iv) Relation between the obtained voltage and current

Seven-times step-up

Six-times step-up

16.4

19.2

16.2

19.0

18.8

18.6

18.4

18.2

18.0

typ.

16.0

15.8

15.6

15.4

15.2

0

10 20 30 40

Io (µA)

50

0

10 20 30 40

Io (µA)

50

Vci = Vcc = 2.7 V, fosc = 100 kHz, Ta = 25˚C,

DC1 to 0 = 00

Vci = Vcc = 2.7 V, fosc = 100 kHz, Ta = 25˚C,

DC1 to 0 = 00

Figure 58 Step-up (cont)

AC Characteristics Test Load Circuits

Data bus: DB15 to DB0

Test Point

50 pF

Figure 59 Load Circuit

Rev. 1.0, Jan. 2003, page 94 of 102

HD66753

Timing Characteristics

68-system Bus Operation

RS

R/W

VIH

VIL

VIH

VIL

t _ASE

t _AHE

CS*

E

VIL

*

PW_EH

PW_EL

VIH

VIL

VIH

VIL

t_Ef

t_Er

t _CYCE

t _HE

t _DSWE

DB0

to DB15

VIH

Write data

VIL

t_DDRE

t _DHRE

DB0

to DB15

VOH1

VOL1

VOH1

VOL1

Read data

Note: PWEH is specified in the overlapped period when CS* is low and E is high.

Figure 60 68-system Bus Timing

Rev. 1.0, Jan. 2003, page 95 of 102

HD66753

80-system Bus Operation

VIH

VIL

VIH

VIL

RS

t _AS

t _AH

VIH

CS*

VIL

PWHW PWHR

PWLW, PWLR

VIH

VIL

VIH

VIL

WR*

RD*

VIH

t_WRf

t_WRr

t _CYCW,t _CYCR

t _DSW

t _H

DB0

to DB15

VIH

VIL

VIH

VIL

Write data

t_DDR

t _DHR

DB0

to DB15

VOH1

VOL1

VOH1

VOL1

Read data

Note: PWLW and PWLR are specified in the overlapped period when CS* is low and WR* or RD* is low.

Figure 61 80-system Bus Timing

Rev. 1.0, Jan. 2003, page 96 of 102

HD66753

Clock-synchronized Serial Operation

Start: S

End: P

VIH

CS*

VIL

tSCYC

tscf

tCSU

tscr

tSCH

tSCL

VIL

tCH

VIH

VIL

SCL

VIL

tSISU

tSIH

VIH

VIL

VIH

VIL

SDA

Input data

tSOD

tSOH

VOH1

VOL1

VOH1

VOL1

SDA

Output data

Figure 62 Clock-synchronized Serial Interface Timing

Reset Operation

t _rRES

t _RES

VIH

VIL

RESET*

VIL

Figure 63 Reset Timing

Rev. 1.0, Jan. 2003, page 97 of 102

HD66753

Power-on/off Sequence

To prevent pulse lighting of LCD screens at power-on/off, the power-on/off sequence is activated as shown

below. However, since the sequence depends on LCD materials to be used, confirm the conditions by

using your own system.

Power-on Sequence

Turn on power voltages Vcc and Vci, RESET = "Low"

Wait for 1 ms or longer (power-on time)

Wait for 10 ms or longer (oscillation stabilization time)

Issue LCD power instruction

Wait for 10-150 ms or longer

Note: Depends on the external

(op-amplifier output

stabilization time)

Issue use-state instruction

capacitance of V1OUT to V5OUT.

Turned on display: D = 1

Figure 64 Power-on Sequence

Rev. 1.0, Jan. 2003, page 98 of 102

HD66753

Vcc

Power voltage: Vcc

Power-on reset time: 1 ms

GND

Vcc

RESET

GND

Oscillation state

Oscillation stabilization time: 10 ms

Vcc

Signal-input

instruction issued

GND

Note: CR oscillation starts by power-on and input reset.

The standby mode is cleared by input reset.

Figure 65 Power-on Timing

Rev. 1.0, Jan. 2003, page 99 of 102

HD66753

Power-off Sequence

Normal state

Turn off display: D = 0

Issue LCD power instruction

Turn off power voltages Vcc and Vci

To the power-on sequence

Abnormal state

Turn off power voltages Vcc and Vci

RESET = "Low"

Driver SEG/COM output: GND

To the power-on sequence

Figure 66 Power-off Sequence

Rev. 1.0, Jan. 2003, page 100 of 102

HD66753

Vcc

Power is turned off.

Power voltage: Vcc

GND

RESET is input as soon as possible.

Vcc

RESET

GND

V1OUT

Driver

SEG/COM

output

GND

Note: When hardware reset is input during the power-off period, the D bit is

cleared to 0 and SEG/COM output is forcibly lowered to the GND level.

Figure 67 Power-off Timing

Rev. 1.0, Jan. 2003, page 101 of 102

HD66753

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

copyright, trademark, or other intellectual property rights for information contained in this document.

Hitachi bears no responsibility for problems that may arise with third party’s rights, including

intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used

beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable

failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-

safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other

consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

Sales Offices

Hitachi, Ltd.

Semiconductor & Integrated Circuits

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Tel: (03) 3270-2111 Fax: (03) 3270-5109

URL

http://www.hitachisemiconductor.com/

For further information write to:

Hitachi Semiconductor

(America) Inc.

Hitachi Europe Ltd.

Hitachi Asia Ltd.

Hitachi Asia (Hong Kong) Ltd.

Group III (Electronic Components)

7/F., North Tower

Electronic Components Group

Hitachi Tower

179 East Tasman Drive Whitebrook Park

16 Collyer Quay #20-00

Singapore 049318

Tel : <65>-6538-6533/6538-8577

Fax : <65>-6538-6933/6538-3877

URL : http://semiconductor.hitachi.com.sg

San Jose,CA 95134

Lower Cookham Road

World Finance Centre,

Tel: <1> (408) 433-1990 Maidenhead

Fax: <1>(408) 433-0223 Berkshire SL6 8YA, United Kingdom

Tel: <44> (1628) 585000

Harbour City, Canton Road

Tsim Sha Tsui, Kowloon Hong Kong

Tel : <852>-2735-9218

Fax : <852>-2730-0281

URL : http://semiconductor.hitachi.com.hk

Fax: <44> (1628) 778322

Hitachi Asia Ltd.

(Taipei Branch Office)

4/F, No. 167, Tun Hwa North Road

Hung-Kuo Building

Taipei (105), Taiwan

Hitachi Europe GmbH

Electronic Components Group

Dornacher Str 3

D-85622 Feldkirchen

Postfach 201, D-85619 Feldkirchen

Germany

Tel : <886>-(2)-2718-3666

Fax : <886>-(2)-2718-8180

Telex : 23222 HAS-TP

Tel: <49> (89) 9 9180-0

Fax: <49> (89) 9 29 30 00

URL : http://semiconductor.hitachi.com.tw

Colophon 7.0

Rev. 1.0, Jan. 2003, page 102 of 102


型号：	HD66753TB0
厂家：	RENESAS TECHNOLOGY CORP
描述：	132X168 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC352, BENDING TCP-352 时钟驱动 CD 外围集成电路
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中文：	中文翻译
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